lowlevel_init.S 3.5 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
  4. * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
  5. *
  6. * Modified for the at91rm9200dk board by
  7. * (C) Copyright 2004
  8. * Gary Jennejohn, DENX Software Engineering, <garyj@denx.de>
  9. */
  10. #include <config.h>
  11. #if !CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT)
  12. #include <asm/arch/hardware.h>
  13. #include <asm/arch/at91_mc.h>
  14. #include <asm/arch/at91_pmc.h>
  15. #include <asm/arch/at91_pio.h>
  16. #define ARM920T_CONTROL 0xC0000000 /* @ set bit 31 (iA) and 30 (nF) */
  17. _MTEXT_BASE:
  18. #undef START_FROM_MEM
  19. #ifdef START_FROM_MEM
  20. .word CONFIG_TEXT_BASE-PHYS_FLASH_1
  21. #else
  22. .word CONFIG_TEXT_BASE
  23. #endif
  24. .globl lowlevel_init
  25. lowlevel_init:
  26. ldr r1, =AT91_ASM_PMC_MOR
  27. /* Main oscillator Enable register */
  28. #ifdef CONFIG_SYS_USE_MAIN_OSCILLATOR
  29. ldr r0, =0x0000FF01 /* Enable main oscillator */
  30. #else
  31. ldr r0, =0x0000FF00 /* Disable main oscillator */
  32. #endif
  33. str r0, [r1] /*AT91C_CKGR_MOR] */
  34. /* Add loop to compensate Main Oscillator startup time */
  35. ldr r0, =0x00000010
  36. LoopOsc:
  37. subs r0, r0, #1
  38. bhi LoopOsc
  39. /* memory control configuration */
  40. /* this isn't very elegant, but what the heck */
  41. ldr r0, =SMRDATA
  42. ldr r1, _MTEXT_BASE
  43. sub r0, r0, r1
  44. ldr r2, =SMRDATAE
  45. sub r2, r2, r1
  46. pllloop:
  47. /* the address */
  48. ldr r1, [r0], #4
  49. /* the value */
  50. ldr r3, [r0], #4
  51. str r3, [r1]
  52. cmp r2, r0
  53. bne pllloop
  54. /* delay - this is all done by guess */
  55. ldr r0, =0x00010000
  56. /* (vs reading PMC_SR for LOCKA, LOCKB ... or MOSCS earlier) */
  57. lock:
  58. subs r0, r0, #1
  59. bhi lock
  60. ldr r0, =SMRDATA1
  61. ldr r1, _MTEXT_BASE
  62. sub r0, r0, r1
  63. ldr r2, =SMRDATA1E
  64. sub r2, r2, r1
  65. sdinit:
  66. /* the address */
  67. ldr r1, [r0], #4
  68. /* the value */
  69. ldr r3, [r0], #4
  70. str r3, [r1]
  71. cmp r2, r0
  72. bne sdinit
  73. /* switch from FastBus to Asynchronous clock mode */
  74. mrc p15, 0, r0, c1, c0, 0
  75. orr r0, r0, #ARM920T_CONTROL
  76. mcr p15, 0, r0, c1, c0, 0
  77. /* everything is fine now */
  78. mov pc, lr
  79. .ltorg
  80. SMRDATA:
  81. .word AT91_ASM_MC_EBI_CFG
  82. .word CONFIG_SYS_EBI_CFGR_VAL
  83. .word AT91_ASM_MC_SMC_CSR0
  84. .word CONFIG_SYS_SMC_CSR0_VAL
  85. .word AT91_ASM_PMC_PLLAR
  86. .word CFG_SYS_PLLAR_VAL
  87. .word AT91_ASM_PMC_PLLBR
  88. .word CONFIG_SYS_PLLBR_VAL
  89. .word AT91_ASM_PMC_MCKR
  90. .word CFG_SYS_MCKR_VAL
  91. SMRDATAE:
  92. /* here there's a delay */
  93. SMRDATA1:
  94. .word AT91_ASM_PIOC_ASR
  95. .word CONFIG_SYS_PIOC_ASR_VAL
  96. .word AT91_ASM_PIOC_BSR
  97. .word CONFIG_SYS_PIOC_BSR_VAL
  98. .word AT91_ASM_PIOC_PDR
  99. .word CFG_SYS_PIOC_PDR_VAL
  100. .word AT91_ASM_MC_EBI_CSA
  101. .word CONFIG_SYS_EBI_CSA_VAL
  102. .word AT91_ASM_MC_SDRAMC_CR
  103. .word CFG_SYS_SDRC_CR_VAL
  104. .word AT91_ASM_MC_SDRAMC_MR
  105. .word CFG_SYS_SDRC_MR_VAL
  106. .word CFG_SYS_SDRAM
  107. .word CFG_SYS_SDRAM_VAL
  108. .word AT91_ASM_MC_SDRAMC_MR
  109. .word CFG_SYS_SDRC_MR_VAL1
  110. .word CFG_SYS_SDRAM
  111. .word CFG_SYS_SDRAM_VAL
  112. .word CFG_SYS_SDRAM
  113. .word CFG_SYS_SDRAM_VAL
  114. .word CFG_SYS_SDRAM
  115. .word CFG_SYS_SDRAM_VAL
  116. .word CFG_SYS_SDRAM
  117. .word CFG_SYS_SDRAM_VAL
  118. .word CFG_SYS_SDRAM
  119. .word CFG_SYS_SDRAM_VAL
  120. .word CFG_SYS_SDRAM
  121. .word CFG_SYS_SDRAM_VAL
  122. .word CFG_SYS_SDRAM
  123. .word CFG_SYS_SDRAM_VAL
  124. .word CFG_SYS_SDRAM
  125. .word CFG_SYS_SDRAM_VAL
  126. .word AT91_ASM_MC_SDRAMC_MR
  127. .word CFG_SYS_SDRC_MR_VAL2
  128. .word CFG_SYS_SDRAM1
  129. .word CFG_SYS_SDRAM_VAL
  130. .word AT91_ASM_MC_SDRAMC_TR
  131. .word CFG_SYS_SDRC_TR_VAL
  132. .word CFG_SYS_SDRAM
  133. .word CFG_SYS_SDRAM_VAL
  134. .word AT91_ASM_MC_SDRAMC_MR
  135. .word CFG_SYS_SDRC_MR_VAL3
  136. .word CFG_SYS_SDRAM
  137. .word CFG_SYS_SDRAM_VAL
  138. SMRDATA1E:
  139. /* SMRDATA1 is 176 bytes long */
  140. #endif /* CONFIG_IS_ENABLED(SKIP_LOWLEVEL_INIT) */