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@@ -45,68 +45,12 @@
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#define GPIO_SLIC_PIN 30
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#define GPIO_SLIC_DATA (1 << (31 - GPIO_SLIC_PIN))
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-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
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-#define GPIO_DDR_RST_PORT 1
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-#define GPIO_DDR_RST_PIN 8
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-#define GPIO_DDR_RST_DATA (1 << (31 - GPIO_DDR_RST_PIN))
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-
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-#define GPIO_2BIT_MASK (0x3 << (32 - (GPIO_DDR_RST_PIN + 1) * 2))
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-#endif
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-
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-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
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-#define PCA_IOPORT_I2C_ADDR 0x23
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-#define PCA_IOPORT_OUTPUT_CMD 0x2
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-#define PCA_IOPORT_CFG_CMD 0x6
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-#define PCA_IOPORT_QE_PIN_ENABLE 0xf8
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-#define PCA_IOPORT_QE_TDM_ENABLE 0xf6
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-#endif
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-
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const qe_iop_conf_t qe_iop_conf_tab[] = {
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/* GPIO */
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{1, 1, 2, 0, 0}, /* GPIO7/PB1 - LOAD_DEFAULT_N */
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-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
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- {1, 8, 1, 1, 0}, /* GPIO10/PB8 - DDR_RST */
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-#endif
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{0, 15, 1, 0, 0}, /* GPIO11/A15 - WDI */
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{GPIO_GETH_SW_PORT, GPIO_GETH_SW_PIN, 1, 0, 0}, /* RST_GETH_SW_N */
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{GPIO_SLIC_PORT, GPIO_SLIC_PIN, 1, 0, 0}, /* RST_SLIC_N */
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-
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-#ifdef CONFIG_TARGET_P1025RDB
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- /* QE_MUX_MDC */
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- {1, 19, 1, 0, 1}, /* QE_MUX_MDC */
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-
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- /* QE_MUX_MDIO */
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- {1, 20, 3, 0, 1}, /* QE_MUX_MDIO */
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-
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- /* UCC_1_MII */
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- {0, 23, 2, 0, 2}, /* CLK12 */
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- {0, 24, 2, 0, 1}, /* CLK9 */
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- {0, 7, 1, 0, 2}, /* ENET1_TXD0_SER1_TXD0 */
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- {0, 9, 1, 0, 2}, /* ENET1_TXD1_SER1_TXD1 */
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- {0, 11, 1, 0, 2}, /* ENET1_TXD2_SER1_TXD2 */
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- {0, 12, 1, 0, 2}, /* ENET1_TXD3_SER1_TXD3 */
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- {0, 6, 2, 0, 2}, /* ENET1_RXD0_SER1_RXD0 */
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- {0, 10, 2, 0, 2}, /* ENET1_RXD1_SER1_RXD1 */
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- {0, 14, 2, 0, 2}, /* ENET1_RXD2_SER1_RXD2 */
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- {0, 15, 2, 0, 2}, /* ENET1_RXD3_SER1_RXD3 */
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- {0, 5, 1, 0, 2}, /* ENET1_TX_EN_SER1_RTS_B */
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- {0, 13, 1, 0, 2}, /* ENET1_TX_ER */
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- {0, 4, 2, 0, 2}, /* ENET1_RX_DV_SER1_CTS_B */
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- {0, 8, 2, 0, 2}, /* ENET1_RX_ER_SER1_CD_B */
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- {0, 17, 2, 0, 2}, /* ENET1_CRS */
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- {0, 16, 2, 0, 2}, /* ENET1_COL */
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-
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- /* UCC_5_RMII */
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- {1, 11, 2, 0, 1}, /* CLK13 */
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- {1, 7, 1, 0, 2}, /* ENET5_TXD0_SER5_TXD0 */
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- {1, 10, 1, 0, 2}, /* ENET5_TXD1_SER5_TXD1 */
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- {1, 6, 2, 0, 2}, /* ENET5_RXD0_SER5_RXD0 */
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- {1, 9, 2, 0, 2}, /* ENET5_RXD1_SER5_RXD1 */
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- {1, 5, 1, 0, 2}, /* ENET5_TX_EN_SER5_RTS_B */
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- {1, 4, 2, 0, 2}, /* ENET5_RX_DV_SER5_CTS_B */
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- {1, 8, 2, 0, 2}, /* ENET5_RX_ER_SER5_CD_B */
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-#endif
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-
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{0, 0, 0, 0, QE_IOP_TAB_END} /* END of table */
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};
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#endif
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@@ -156,16 +100,6 @@ void board_gpio_init(void)
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ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
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-#if defined(CONFIG_TARGET_P1021RDB) && !defined(CONFIG_SYS_RAMBOOT)
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- /* reset DDR3 */
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- setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
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- udelay(1000);
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- clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
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- udelay(1000);
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- setbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdat, GPIO_DDR_RST_DATA);
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- /* disable CE_PB8 */
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- clrbits_be32(&par_io[GPIO_DDR_RST_PORT].cpdir1, GPIO_2BIT_MASK);
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-#endif
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/* Enable VSC7385 switch */
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setbits_be32(&par_io[GPIO_GETH_SW_PORT].cpdat, GPIO_GETH_SW_DATA);
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@@ -316,6 +250,10 @@ int board_early_init_r(void)
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{
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const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
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int flash_esel = find_tlb_idx((void *)flashbase, 1);
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+#ifdef CONFIG_VSC7385_ENET
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+ unsigned int vscfw_addr;
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+ char *tmp;
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+#endif
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/*
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* Remap Boot flash region to caching-inhibited
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@@ -338,9 +276,24 @@ int board_early_init_r(void)
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set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, /* tlb, epn, rpn */
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MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,/* perms, wimge */
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0, flash_esel, BOOKE_PAGESZ_64M, 1);/* ts, esel, tsize, iprot */
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+
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+#ifdef CONFIG_VSC7385_ENET
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+ /* If a VSC7385 microcode image is present, then upload it. */
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+ tmp = env_get("vscfw_addr");
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+ if (tmp) {
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+ vscfw_addr = simple_strtoul(tmp, NULL, 16);
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+ printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
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+ if (vsc7385_upload_firmware((void *)vscfw_addr,
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+ CONFIG_VSC7385_IMAGE_SIZE))
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+ puts("Failure uploading VSC7385 microcode.\n");
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+ } else {
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+ puts("No address specified for VSC7385 microcode.\n");
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+ }
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+#endif
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return 0;
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}
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+#ifndef CONFIG_DM_ETH
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int board_eth_init(struct bd_info *bis)
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{
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struct fsl_pq_mdio_info mdio_info;
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@@ -348,10 +301,6 @@ int board_eth_init(struct bd_info *bis)
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ccsr_gur_t *gur __attribute__((unused)) =
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(void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
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int num = 0;
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-#ifdef CONFIG_VSC7385_ENET
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- char *tmp;
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- unsigned int vscfw_addr;
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-#endif
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#ifdef CONFIG_TSEC1
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SET_STD_TSEC_INFO(tsec_info[num], 1);
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@@ -375,19 +324,6 @@ int board_eth_init(struct bd_info *bis)
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return 0;
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}
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-#ifdef CONFIG_VSC7385_ENET
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- /* If a VSC7385 microcode image is present, then upload it. */
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- tmp = env_get("vscfw_addr");
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- if (tmp) {
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- vscfw_addr = simple_strtoul(tmp, NULL, 16);
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- printf("uploading VSC7385 microcode from %x\n", vscfw_addr);
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- if (vsc7385_upload_firmware((void *) vscfw_addr,
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- CONFIG_VSC7385_IMAGE_SIZE))
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- puts("Failure uploading VSC7385 microcode.\n");
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- } else
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- puts("No address specified for VSC7385 microcode.\n");
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-#endif
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-
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mdio_info.regs = TSEC_GET_MDIO_REGS_BASE(1);
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mdio_info.name = DEFAULT_MII_NAME;
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@@ -405,50 +341,6 @@ int board_eth_init(struct bd_info *bis)
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return pci_eth_init(bis);
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}
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-
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-#if defined(CONFIG_QE) && \
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- (defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB))
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-static void fdt_board_fixup_qe_pins(void *blob)
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-{
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- unsigned int oldbus;
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- u8 val8;
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- int node;
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- fsl_lbc_t *lbc = LBC_BASE_ADDR;
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-
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- if (hwconfig("qe")) {
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- /* For QE and eLBC pins multiplexing,
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- * there is a PCA9555 device on P1025RDB.
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- * It control the multiplex pins' functions,
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- * and setting the PCA9555 can switch the
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- * function between QE and eLBC.
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- */
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- oldbus = i2c_get_bus_num();
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- i2c_set_bus_num(0);
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- if (hwconfig("tdm"))
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- val8 = PCA_IOPORT_QE_TDM_ENABLE;
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- else
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- val8 = PCA_IOPORT_QE_PIN_ENABLE;
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- i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_CFG_CMD,
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- 1, &val8, 1);
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- i2c_write(PCA_IOPORT_I2C_ADDR, PCA_IOPORT_OUTPUT_CMD,
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- 1, &val8, 1);
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- i2c_set_bus_num(oldbus);
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- /* if run QE TDM, Set ABSWP to implement
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- * conversion of addresses in the eLBC.
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- */
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- if (hwconfig("tdm")) {
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- set_lbc_or(2, CONFIG_PMC_OR_PRELIM);
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- set_lbc_br(2, CONFIG_PMC_BR_PRELIM);
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- setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
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- }
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- } else {
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- node = fdt_path_offset(blob, "/qe");
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- if (node >= 0)
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- fdt_del_node(blob, node);
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- }
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-
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- return;
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-}
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#endif
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#ifdef CONFIG_OF_BOARD_SETUP
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@@ -478,9 +370,6 @@ int ft_board_setup(void *blob, struct bd_info *bd)
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#ifdef CONFIG_QE
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do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
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sizeof("okay"), 0);
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-#if defined(CONFIG_TARGET_P1025RDB) || defined(CONFIG_TARGET_P1021RDB)
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- fdt_board_fixup_qe_pins(blob);
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-#endif
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#endif
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#if defined(CONFIG_HAS_FSL_DR_USB)
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