p1020-post.dtsi 1.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P1020 Silicon/SoC Device Tree Source (post include)
  4. *
  5. * Copyright 2013 Freescale Semiconductor Inc.
  6. * Copyright 2019 NXP
  7. */
  8. &soc {
  9. #address-cells = <1>;
  10. #size-cells = <1>;
  11. device_type = "soc";
  12. compatible = "fsl,p1020-immr", "simple-bus";
  13. bus-frequency = <0x0>;
  14. usb@22000 {
  15. compatible = "fsl-usb2-dr";
  16. reg = <0x22000 0x1000>;
  17. phy_type = "ulpi";
  18. };
  19. usb@23000 {
  20. compatible = "fsl-usb2-dr";
  21. reg = <0x23000 0x1000>;
  22. phy_type = "ulpi";
  23. };
  24. mpic: pic@40000 {
  25. interrupt-controller;
  26. #address-cells = <0>;
  27. #interrupt-cells = <4>;
  28. reg = <0x40000 0x40000>;
  29. compatible = "fsl,mpic";
  30. device_type = "open-pic";
  31. big-endian;
  32. single-cpu-affinity;
  33. last-interrupt-source = <255>;
  34. };
  35. esdhc: esdhc@2e000 {
  36. compatible = "fsl,esdhc";
  37. reg = <0x2e000 0x1000>;
  38. /* Filled in by U-Boot */
  39. clock-frequency = <0>;
  40. };
  41. espi0: spi@7000 {
  42. compatible = "fsl,mpc8536-espi";
  43. #address-cells = <1>;
  44. #size-cells = <0>;
  45. reg = <0x7000 0x1000>;
  46. fsl,espi-num-chipselects = <4>;
  47. status = "disabled";
  48. };
  49. /include/ "pq3-i2c-0.dtsi"
  50. /include/ "pq3-i2c-1.dtsi"
  51. /include/ "pq3-etsec2-0.dtsi"
  52. enet0: enet0_grp2: ethernet@b0000 {
  53. };
  54. /include/ "pq3-etsec2-1.dtsi"
  55. enet1: enet1_grp2: ethernet@b1000 {
  56. };
  57. /include/ "pq3-etsec2-2.dtsi"
  58. enet2: enet2_grp2: ethernet@b2000 {
  59. };
  60. };
  61. /include/ "pq3-etsec2-grp2-0.dtsi"
  62. /include/ "pq3-etsec2-grp2-1.dtsi"
  63. /include/ "pq3-etsec2-grp2-2.dtsi"
  64. /* PCIe controller base address 0x9000 */
  65. &pci1 {
  66. compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  67. law_trgt_if = <1>;
  68. #address-cells = <3>;
  69. #size-cells = <2>;
  70. device_type = "pci";
  71. bus-range = <0x0 0xff>;
  72. };
  73. /* PCIe controller base address 0xa000 */
  74. &pci0 {
  75. compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  76. law_trgt_if = <2>;
  77. #address-cells = <3>;
  78. #size-cells = <2>;
  79. device_type = "pci";
  80. bus-range = <0x0 0xff>;
  81. };