p1023rdb.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. *
  5. * Authors: Roy Zang <tie-fei.zang@freescale.com>
  6. * Chunhe Lan <Chunhe.Lan@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <env.h>
  11. #include <image.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <pci.h>
  15. #include <asm/io.h>
  16. #include <asm/cache.h>
  17. #include <asm/processor.h>
  18. #include <asm/mmu.h>
  19. #include <asm/immap_85xx.h>
  20. #include <asm/fsl_pci.h>
  21. #include <fsl_ddr_sdram.h>
  22. #include <asm/fsl_portals.h>
  23. #include <fsl_qbman.h>
  24. #include <linux/libfdt.h>
  25. #include <fdt_support.h>
  26. #include <netdev.h>
  27. #include <malloc.h>
  28. #include <fm_eth.h>
  29. #include <fsl_mdio.h>
  30. #include <miiphy.h>
  31. #include <phy.h>
  32. #include <fsl_dtsec.h>
  33. DECLARE_GLOBAL_DATA_PTR;
  34. int board_early_init_f(void)
  35. {
  36. fsl_lbc_t *lbc = LBC_BASE_ADDR;
  37. /* Set ABSWP to implement conversion of addresses in the LBC */
  38. setbits_be32(&lbc->lbcr, CONFIG_SYS_LBC_LBCR);
  39. return 0;
  40. }
  41. int checkboard(void)
  42. {
  43. printf("Board: P1023 RDB\n");
  44. return 0;
  45. }
  46. #ifdef CONFIG_PCI
  47. void pci_init_board(void)
  48. {
  49. fsl_pcie_init_board(0);
  50. }
  51. #endif
  52. int board_early_init_r(void)
  53. {
  54. const unsigned int flashbase = CONFIG_SYS_FLASH_BASE;
  55. int flash_esel = find_tlb_idx((void *)flashbase, 1);
  56. /*
  57. * Remap Boot flash + PROMJET region to caching-inhibited
  58. * so that flash can be erased properly.
  59. */
  60. /* Flush d-cache and invalidate i-cache of any FLASH data */
  61. flush_dcache();
  62. invalidate_icache();
  63. if (flash_esel == -1) {
  64. /* very unlikely unless something is messed up */
  65. puts("Error: Could not find TLB for FLASH BASE\n");
  66. flash_esel = 2; /* give our best effort to continue */
  67. } else {
  68. /* invalidate existing TLB entry for flash + promjet */
  69. disable_tlb(flash_esel);
  70. }
  71. set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
  72. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  73. 0, flash_esel, BOOKE_PAGESZ_256M, 1);
  74. setup_qbman_portals();
  75. return 0;
  76. }
  77. unsigned long get_board_sys_clk(ulong dummy)
  78. {
  79. return gd->bus_clk;
  80. }
  81. unsigned long get_board_ddr_clk(ulong dummy)
  82. {
  83. return gd->mem_clk;
  84. }
  85. int board_eth_init(struct bd_info *bis)
  86. {
  87. ccsr_gur_t *gur = (ccsr_gur_t *)CONFIG_SYS_MPC85xx_GUTS_ADDR;
  88. struct fsl_pq_mdio_info dtsec_mdio_info;
  89. /*
  90. * Need to set dTSEC 1 pin multiplexing to TSEC. The default setting
  91. * is not correct.
  92. */
  93. setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_TSEC1_1);
  94. dtsec_mdio_info.regs =
  95. (struct tsec_mii_mng *)CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR;
  96. dtsec_mdio_info.name = DEFAULT_FM_MDIO_NAME;
  97. /* Register the 1G MDIO bus */
  98. fsl_pq_mdio_init(bis, &dtsec_mdio_info);
  99. fm_info_set_phy_address(FM1_DTSEC1, CONFIG_SYS_FM1_DTSEC1_PHY_ADDR);
  100. fm_info_set_phy_address(FM1_DTSEC2, CONFIG_SYS_FM1_DTSEC2_PHY_ADDR);
  101. fm_info_set_mdio(FM1_DTSEC1,
  102. miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
  103. fm_info_set_mdio(FM1_DTSEC2,
  104. miiphy_get_dev_by_name(DEFAULT_FM_MDIO_NAME));
  105. #ifdef CONFIG_FMAN_ENET
  106. cpu_eth_init(bis);
  107. #endif
  108. return pci_eth_init(bis);
  109. }
  110. #if defined(CONFIG_OF_BOARD_SETUP)
  111. int ft_board_setup(void *blob, struct bd_info *bd)
  112. {
  113. phys_addr_t base;
  114. phys_size_t size;
  115. ft_cpu_setup(blob, bd);
  116. base = env_get_bootm_low();
  117. size = env_get_bootm_size();
  118. fdt_fixup_memory(blob, (u64)base, (u64)size);
  119. #ifdef CONFIG_HAS_FSL_DR_USB
  120. fsl_fdt_fixup_dr_usb(blob, bd);
  121. #endif
  122. #ifdef CONFIG_SYS_DPAA_FMAN
  123. #ifndef CONFIG_DM_ETH
  124. fdt_fixup_fman_ethernet(blob);
  125. #endif
  126. #endif
  127. return 0;
  128. }
  129. #endif