t1024rdb.dts 1.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081
  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * T1024RDB Device Tree Source
  4. *
  5. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019-2020 NXP
  7. */
  8. /include/ "t102x.dtsi"
  9. / {
  10. model = "fsl,T1024RDB";
  11. compatible = "fsl,T1024RDB";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. aliases {
  16. sg_2500_aqr105_phy4 = &sg_2500_aqr105_phy4;
  17. spi0 = &espi0;
  18. };
  19. soc: soc@ffe000000 {
  20. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  21. reg = <0xf 0xfe000000 0 0x00001000>;
  22. fman@400000 {
  23. fm1mac1: ethernet@e0000 {
  24. phy-handle = <&xg_aqr105_phy3>;
  25. phy-connection-type = "xgmii";
  26. };
  27. fm1mac2: ethernet@e2000 {
  28. };
  29. fm1mac3: ethernet@e4000 {
  30. phy-handle = <&rgmii_phy2>;
  31. phy-connection-type = "rgmii";
  32. };
  33. fm1mac4: ethernet@e6000 {
  34. phy-handle = <&rgmii_phy1>;
  35. phy-connection-type = "rgmii";
  36. };
  37. mdio0: mdio@fc000 {
  38. rgmii_phy1: ethernet-phy@2 {
  39. reg = <0x2>;
  40. };
  41. rgmii_phy2: ethernet-phy@6 {
  42. reg = <0x6>;
  43. };
  44. };
  45. xmdio0: mdio@fd000 {
  46. xg_aqr105_phy3: ethernet-phy@1 {
  47. compatible = "ethernet-phy-ieee802.3-c45";
  48. reg = <0x1>;
  49. };
  50. sg_2500_aqr105_phy4: ethernet-phy@2 {
  51. compatible = "ethernet-phy-ieee802.3-c45";
  52. reg = <0x2>;
  53. };
  54. };
  55. };
  56. };
  57. };
  58. &espi0 {
  59. status = "okay";
  60. flash@0 {
  61. compatible = "jedec,spi-nor";
  62. #address-cells = <1>;
  63. #size-cells = <1>;
  64. reg = <0>;
  65. /* input clock */
  66. spi-max-frequency = <10000000>;
  67. };
  68. };
  69. #include "t1024si-post.dtsi"