p5040.dtsi 3.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P5040 Silicon/SoC Device Tree Source (pre include)
  4. *
  5. * Copyright 2012 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019-2020 NXP
  7. */
  8. /dts-v1/;
  9. /include/ "e5500_power_isa.dtsi"
  10. / {
  11. #address-cells = <2>;
  12. #size-cells = <2>;
  13. interrupt-parent = <&mpic>;
  14. cpus {
  15. #address-cells = <1>;
  16. #size-cells = <0>;
  17. cpu0: PowerPC,e5500@0 {
  18. device_type = "cpu";
  19. reg = <0>;
  20. fsl,portid-mapping = <0x80000000>;
  21. };
  22. cpu1: PowerPC,e5500@1 {
  23. device_type = "cpu";
  24. reg = <1>;
  25. fsl,portid-mapping = <0x40000000>;
  26. };
  27. cpu2: PowerPC,e5500@2 {
  28. device_type = "cpu";
  29. reg = <2>;
  30. fsl,portid-mapping = <0x20000000>;
  31. };
  32. cpu3: PowerPC,e5500@3 {
  33. device_type = "cpu";
  34. reg = <3>;
  35. fsl,portid-mapping = <0x10000000>;
  36. };
  37. };
  38. soc: soc@ffe000000 {
  39. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  40. reg = <0xf 0xfe000000 0 0x00001000>;
  41. #address-cells = <1>;
  42. #size-cells = <1>;
  43. device_type = "soc";
  44. compatible = "simple-bus";
  45. mpic: pic@40000 {
  46. interrupt-controller;
  47. #address-cells = <0>;
  48. #interrupt-cells = <4>;
  49. reg = <0x40000 0x40000>;
  50. compatible = "fsl,mpic", "chrp,open-pic";
  51. device_type = "open-pic";
  52. clock-frequency = <0x0>;
  53. };
  54. espi0: spi@110000 {
  55. compatible = "fsl,mpc8536-espi";
  56. #address-cells = <1>;
  57. #size-cells = <0>;
  58. reg = <0x110000 0x1000>;
  59. fsl,espi-num-chipselects = <4>;
  60. status = "disabled";
  61. };
  62. usb@210000 {
  63. compatible = "fsl-usb2-mph";
  64. reg = <0x210000 0x1000>;
  65. phy_type = "utmi";
  66. };
  67. usb@211000 {
  68. compatible = "fsl-usb2-dr";
  69. reg = <0x211000 0x1000>;
  70. phy_type = "utmi";
  71. };
  72. sata: sata@220000 {
  73. compatible = "fsl,pq-sata-v2";
  74. reg = <0x220000 0x1000>;
  75. interrupts = <68 0x2 0 0>;
  76. sata-offset = <0x1000>;
  77. sata-number = <2>;
  78. sata-fpdma = <0>;
  79. };
  80. esdhc: esdhc@114000 {
  81. compatible = "fsl,esdhc";
  82. reg = <0x114000 0x1000>;
  83. clock-frequency = <0>;
  84. };
  85. /include/ "qoriq-i2c-0.dtsi"
  86. /include/ "qoriq-i2c-1.dtsi"
  87. };
  88. pcie@ffe200000 {
  89. compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
  90. reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
  91. law_trgt_if = <0>;
  92. #address-cells = <3>;
  93. #size-cells = <2>;
  94. device_type = "pci";
  95. bus-range = <0x0 0xff>;
  96. ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
  97. 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
  98. };
  99. pcie@ffe201000 {
  100. compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
  101. reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
  102. law_trgt_if = <1>;
  103. #address-cells = <3>;
  104. #size-cells = <2>;
  105. device_type = "pci";
  106. bus-range = <0x0 0xff>;
  107. ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
  108. 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
  109. };
  110. pcie@ffe202000 {
  111. compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq";
  112. reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
  113. law_trgt_if = <2>;
  114. #address-cells = <3>;
  115. #size-cells = <2>;
  116. device_type = "pci";
  117. bus-range = <0x0 0xff>;
  118. ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
  119. 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
  120. };
  121. };