p3041.dtsi 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P3041 Silicon/SoC Device Tree Source (pre include)
  4. *
  5. * Copyright 2010 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019-2020 NXP
  7. */
  8. /dts-v1/;
  9. /include/ "e500mc_power_isa.dtsi"
  10. / {
  11. compatible = "fsl,P3041";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. cpus {
  16. #address-cells = <1>;
  17. #size-cells = <0>;
  18. cpu0: PowerPC,e500mc@0 {
  19. device_type = "cpu";
  20. reg = <0>;
  21. fsl,portid-mapping = <0x80000000>;
  22. };
  23. cpu1: PowerPC,e500mc@1 {
  24. device_type = "cpu";
  25. reg = <1>;
  26. fsl,portid-mapping = <0x40000000>;
  27. };
  28. cpu2: PowerPC,e500mc@2 {
  29. device_type = "cpu";
  30. reg = <2>;
  31. fsl,portid-mapping = <0x20000000>;
  32. };
  33. cpu3: PowerPC,e500mc@3 {
  34. device_type = "cpu";
  35. reg = <3>;
  36. fsl,portid-mapping = <0x10000000>;
  37. };
  38. };
  39. soc: soc@ffe000000 {
  40. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  41. reg = <0xf 0xfe000000 0 0x00001000>;
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. device_type = "soc";
  45. compatible = "simple-bus";
  46. mpic: pic@40000 {
  47. interrupt-controller;
  48. #address-cells = <0>;
  49. #interrupt-cells = <4>;
  50. reg = <0x40000 0x40000>;
  51. compatible = "fsl,mpic", "chrp,open-pic";
  52. device_type = "open-pic";
  53. clock-frequency = <0x0>;
  54. };
  55. espi0: spi@110000 {
  56. compatible = "fsl,mpc8536-espi";
  57. #address-cells = <1>;
  58. #size-cells = <0>;
  59. reg = <0x110000 0x1000>;
  60. fsl,espi-num-chipselects = <4>;
  61. status = "disabled";
  62. };
  63. usb0: usb@fe210000 {
  64. compatible = "fsl-usb2-mph";
  65. reg = <0x210000 0x1000>;
  66. phy_type = "utmi";
  67. };
  68. usb1: usb@fe211000 {
  69. compatible = "fsl-usb2-dr";
  70. reg = <0x211000 0x1000>;
  71. phy_type = "utmi";
  72. };
  73. sata: sata@220000 {
  74. compatible = "fsl,pq-sata-v2";
  75. reg = <0x220000 0x1000>;
  76. interrupts = <68 0x2 0 0>;
  77. sata-offset = <0x1000>;
  78. sata-number = <2>;
  79. sata-fpdma = <0>;
  80. };
  81. esdhc: esdhc@114000 {
  82. compatible = "fsl,esdhc";
  83. reg = <0x114000 0x1000>;
  84. clock-frequency = <0>;
  85. };
  86. /include/ "qoriq-i2c-0.dtsi"
  87. /include/ "qoriq-i2c-1.dtsi"
  88. };
  89. pcie@ffe200000 {
  90. compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
  91. reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */
  92. law_trgt_if = <0>;
  93. #address-cells = <3>;
  94. #size-cells = <2>;
  95. device_type = "pci";
  96. bus-range = <0x0 0xff>;
  97. ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */
  98. 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */
  99. };
  100. pcie@ffe201000 {
  101. compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
  102. reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */
  103. law_trgt_if = <1>;
  104. #address-cells = <3>;
  105. #size-cells = <2>;
  106. device_type = "pci";
  107. bus-range = <0x0 0xff>;
  108. ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */
  109. 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */
  110. };
  111. pcie@ffe202000 {
  112. compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
  113. reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */
  114. law_trgt_if = <2>;
  115. #address-cells = <3>;
  116. #size-cells = <2>;
  117. device_type = "pci";
  118. bus-range = <0x0 0xff>;
  119. ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */
  120. 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */
  121. };
  122. pcie@ffe203000 {
  123. compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq";
  124. reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */
  125. law_trgt_if = <3>;
  126. #address-cells = <3>;
  127. #size-cells = <2>;
  128. device_type = "pci";
  129. bus-range = <0x0 0xff>;
  130. ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */
  131. 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */
  132. };
  133. };