tlb.c 3.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2013 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <asm/mmu.h>
  7. struct fsl_e_tlb_entry tlb_table[] = {
  8. /* TLB 0 - for temp stack in cache */
  9. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR,
  10. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  11. 0, 0, BOOKE_PAGESZ_4K, 0),
  12. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  13. CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024,
  14. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  15. 0, 0, BOOKE_PAGESZ_4K, 0),
  16. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  17. CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024,
  18. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  19. 0, 0, BOOKE_PAGESZ_4K, 0),
  20. SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  21. CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024,
  22. MAS3_SX|MAS3_SW|MAS3_SR, 0,
  23. 0, 0, BOOKE_PAGESZ_4K, 0),
  24. /* TLB 1 */
  25. /* *I*** - Covers boot page */
  26. SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
  27. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I,
  28. 0, 0, BOOKE_PAGESZ_4K, 1),
  29. /* *I*G* - CCSRBAR */
  30. SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
  31. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  32. 0, 1, BOOKE_PAGESZ_4M, 1),
  33. /* W**G* - Flash, localbus */
  34. /* This will be changed to *I*G* after relocation to RAM. */
  35. SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
  36. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_W|MAS2_G,
  37. 0, 2, BOOKE_PAGESZ_256M, 1),
  38. /* *I*G* - PCI */
  39. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT, CONFIG_SYS_PCIE3_MEM_PHYS,
  40. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  41. 0, 3, BOOKE_PAGESZ_1G, 1),
  42. /* *I*G* - PCI */
  43. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x40000000,
  44. CONFIG_SYS_PCIE3_MEM_PHYS + 0x40000000,
  45. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  46. 0, 4, BOOKE_PAGESZ_256M, 1),
  47. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_MEM_VIRT + 0x50000000,
  48. CONFIG_SYS_PCIE3_MEM_PHYS + 0x50000000,
  49. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  50. 0, 5, BOOKE_PAGESZ_256M, 1),
  51. /* *I*G* - PCI I/O */
  52. SET_TLB_ENTRY(1, CONFIG_SYS_PCIE3_IO_VIRT, CONFIG_SYS_PCIE3_IO_PHYS,
  53. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  54. 0, 6, BOOKE_PAGESZ_256K, 1),
  55. /* Bman/Qman */
  56. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE, CONFIG_SYS_BMAN_MEM_PHYS,
  57. MAS3_SW|MAS3_SR, 0,
  58. 0, 7, BOOKE_PAGESZ_1M, 1),
  59. SET_TLB_ENTRY(1, CONFIG_SYS_BMAN_MEM_BASE + 0x00100000,
  60. CONFIG_SYS_BMAN_MEM_PHYS + 0x00100000,
  61. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  62. 0, 8, BOOKE_PAGESZ_1M, 1),
  63. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE, CONFIG_SYS_QMAN_MEM_PHYS,
  64. MAS3_SW|MAS3_SR, MAS2_M,
  65. 0, 9, BOOKE_PAGESZ_1M, 1),
  66. SET_TLB_ENTRY(1, CONFIG_SYS_QMAN_MEM_BASE + 0x00100000,
  67. CONFIG_SYS_QMAN_MEM_PHYS + 0x00100000,
  68. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  69. 0, 10, BOOKE_PAGESZ_1M, 1),
  70. SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
  71. MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
  72. 0, 11, BOOKE_PAGESZ_16K, 1),
  73. #ifdef CONFIG_SYS_RAMBOOT
  74. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE,
  75. CONFIG_SYS_DDR_SDRAM_BASE,
  76. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  77. 0, 12, BOOKE_PAGESZ_256M, 1),
  78. SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
  79. CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000,
  80. MAS3_SX|MAS3_SW|MAS3_SR, MAS2_M,
  81. 0, 13, BOOKE_PAGESZ_256M, 1),
  82. #endif
  83. };
  84. int num_tlb_entries = ARRAY_SIZE(tlb_table);