p2020rdb-pc.dts 1.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P2020RDB-PC Device Tree Source
  4. *
  5. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019 NXP
  7. */
  8. /include/ "p2020.dtsi"
  9. / {
  10. model = "fsl,P2020RDB-PC";
  11. compatible = "fsl,P2020RDB-PC";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. soc: soc@ffe00000 {
  16. ranges = <0x0 0x0 0xffe00000 0x100000>;
  17. };
  18. pci2: pcie@ffe08000 {
  19. reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */
  20. status = "disabled";
  21. };
  22. pci1: pcie@ffe09000 {
  23. reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
  24. ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
  25. 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
  26. };
  27. pci0: pcie@ffe0a000 {
  28. reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
  29. ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
  30. 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
  31. };
  32. aliases {
  33. spi0 = &espi0;
  34. };
  35. };
  36. /include/ "p2020rdb-pc.dtsi"
  37. /include/ "p2020-post.dtsi"
  38. &espi0 {
  39. status = "okay";
  40. flash@0 {
  41. compatible = "jedec,spi-nor";
  42. #address-cells = <1>;
  43. #size-cells = <1>;
  44. reg = <0>;
  45. spi-max-frequency = <10000000>; /* input clock */
  46. };
  47. };