p1020rdb-pc.dts 1.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P1020RDB-PC Device Tree Source
  4. *
  5. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019 NXP
  7. */
  8. /include/ "p1020.dtsi"
  9. / {
  10. model = "fsl,P1020RDB-PC";
  11. compatible = "fsl,P1020RDB-PC";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. soc: soc@ffe00000 {
  16. ranges = <0x0 0x0 0xffe00000 0x100000>;
  17. };
  18. pci1: pcie@ffe09000 {
  19. reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
  20. ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
  21. 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
  22. };
  23. pci0: pcie@ffe0a000 {
  24. reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
  25. ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
  26. 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
  27. };
  28. aliases {
  29. spi0 = &espi0;
  30. };
  31. };
  32. /include/ "p1020rdb-pc.dtsi"
  33. /include/ "p1020-post.dtsi"
  34. &espi0 {
  35. status = "okay";
  36. flash@0 {
  37. compatible = "jedec,spi-nor";
  38. #address-cells = <1>;
  39. #size-cells = <1>;
  40. reg = <0>;
  41. spi-max-frequency = <10000000>; /* input clock */
  42. };
  43. };