p4080ds.dts 3.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P4080DS Device Tree Source
  4. *
  5. * Copyright 2011 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019-2020 NXP
  7. */
  8. /include/ "p4080.dtsi"
  9. / {
  10. model = "fsl,P4080DS";
  11. compatible = "fsl,P4080DS";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. aliases {
  16. phy_rgmii = &phyrgmii;
  17. phy5_slot3 = &phy5slot3;
  18. phy6_slot3 = &phy6slot3;
  19. phy7_slot3 = &phy7slot3;
  20. phy8_slot3 = &phy8slot3;
  21. emi1_slot3 = &p4080mdio2;
  22. emi1_slot4 = &p4080mdio1;
  23. emi1_slot5 = &p4080mdio3;
  24. emi1_rgmii = &p4080mdio0;
  25. emi2_slot4 = &p4080xmdio1;
  26. emi2_slot5 = &p4080xmdio3;
  27. spi0 = &espi0;
  28. };
  29. soc: soc@ffe000000 {
  30. ranges = <0x00000000 0xf 0xfe000000 0x1000000>;
  31. reg = <0xf 0xfe000000 0 0x00001000>;
  32. fman@400000 {
  33. ethernet@e0000 {
  34. phy-handle = <&phy0>;
  35. phy-connection-type = "sgmii";
  36. };
  37. ethernet@e2000 {
  38. phy-handle = <&phy1>;
  39. phy-connection-type = "sgmii";
  40. };
  41. ethernet@e4000 {
  42. phy-handle = <&phy2>;
  43. phy-connection-type = "sgmii";
  44. };
  45. ethernet@e6000 {
  46. phy-handle = <&phy3>;
  47. phy-connection-type = "sgmii";
  48. };
  49. ethernet@f0000 {
  50. phy-handle = <&phy10>;
  51. phy-connection-type = "xgmii";
  52. };
  53. };
  54. fman@500000 {
  55. ethernet@e0000 {
  56. phy-handle = <&phy5>;
  57. phy-connection-type = "sgmii";
  58. };
  59. ethernet@e2000 {
  60. phy-handle = <&phy6>;
  61. phy-connection-type = "sgmii";
  62. };
  63. ethernet@e4000 {
  64. phy-handle = <&phy7>;
  65. phy-connection-type = "sgmii";
  66. };
  67. ethernet@e6000 {
  68. phy-handle = <&phy8>;
  69. phy-connection-type = "sgmii";
  70. };
  71. ethernet@f0000 {
  72. phy-handle = <&phy11>;
  73. phy-connection-type = "xgmii";
  74. };
  75. };
  76. };
  77. mdio-mux-emi1 {
  78. #address-cells = <1>;
  79. #size-cells = <0>;
  80. compatible = "mdio-mux-gpio", "mdio-mux";
  81. mdio-parent-bus = <&mdio0>;
  82. gpios = <&gpio0 1 0>, <&gpio0 0 0>;
  83. p4080mdio0: mdio@0 {
  84. #address-cells = <1>;
  85. #size-cells = <0>;
  86. reg = <0>;
  87. phyrgmii: ethernet-phy@0 {
  88. reg = <0x0>;
  89. };
  90. };
  91. p4080mdio1: mdio@1 {
  92. #address-cells = <1>;
  93. #size-cells = <0>;
  94. reg = <1>;
  95. phy5: ethernet-phy@1c {
  96. reg = <0x1c>;
  97. };
  98. phy6: ethernet-phy@1d {
  99. reg = <0x1d>;
  100. };
  101. phy7: ethernet-phy@1e {
  102. reg = <0x1e>;
  103. };
  104. phy8: ethernet-phy@1f {
  105. reg = <0x1f>;
  106. };
  107. };
  108. p4080mdio2: mdio@2 {
  109. #address-cells = <1>;
  110. #size-cells = <0>;
  111. reg = <2>;
  112. status = "disabled";
  113. phy5slot3: ethernet-phy@1c {
  114. reg = <0x1c>;
  115. };
  116. phy6slot3: ethernet-phy@1d {
  117. reg = <0x1d>;
  118. };
  119. phy7slot3: ethernet-phy@1e {
  120. reg = <0x1e>;
  121. };
  122. phy8slot3: ethernet-phy@1f {
  123. reg = <0x1f>;
  124. };
  125. };
  126. p4080mdio3: mdio@3 {
  127. #address-cells = <1>;
  128. #size-cells = <0>;
  129. reg = <3>;
  130. phy0: ethernet-phy@1c {
  131. reg = <0x1c>;
  132. };
  133. phy1: ethernet-phy@1d {
  134. reg = <0x1d>;
  135. };
  136. phy2: ethernet-phy@1e {
  137. reg = <0x1e>;
  138. };
  139. phy3: ethernet-phy@1f {
  140. reg = <0x1f>;
  141. };
  142. };
  143. };
  144. mdio-mux-emi2 {
  145. #address-cells = <1>;
  146. #size-cells = <0>;
  147. compatible = "mdio-mux-gpio", "mdio-mux";
  148. mdio-parent-bus = <&xmdio0>;
  149. gpios = <&gpio0 3 0>, <&gpio0 2 0>;
  150. p4080xmdio1: mdio@1 {
  151. #address-cells = <1>;
  152. #size-cells = <0>;
  153. reg = <1>;
  154. phy11: ethernet-phy@0 {
  155. compatible = "ethernet-phy-ieee802.3-c45";
  156. reg = <0x0>;
  157. };
  158. };
  159. p4080xmdio3: mdio@3 {
  160. #address-cells = <1>;
  161. #size-cells = <0>;
  162. reg = <3>;
  163. phy10: ethernet-phy@4 {
  164. compatible = "ethernet-phy-ieee802.3-c45";
  165. reg = <0x4>;
  166. };
  167. };
  168. };
  169. };
  170. &espi0 {
  171. status = "okay";
  172. flash@0 {
  173. compatible = "jedec,spi-nor";
  174. #address-cells = <1>;
  175. #size-cells = <1>;
  176. reg = <0>;
  177. /* input clock */
  178. spi-max-frequency = <10000000>;
  179. };
  180. };
  181. /include/ "p4080si-post.dtsi"