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- // SPDX-License-Identifier: GPL-2.0+ OR X11
- /*
- * P1020RDB-PD Device Tree Source
- *
- * Copyright 2013 - 2015 Freescale Semiconductor Inc.
- * Copyright 2019 NXP
- */
- /include/ "p1020.dtsi"
- / {
- model = "fsl,P1020RDB-PD";
- compatible = "fsl,P1020RDB-PD";
- #address-cells = <2>;
- #size-cells = <2>;
- interrupt-parent = <&mpic>;
- soc: soc@ffe00000 {
- ranges = <0x0 0x0 0xffe00000 0x100000>;
- mdio@24000 {
- phy0: ethernet-phy@0 {
- interrupts = <3 1 0 0>;
- reg = <0x0>;
- };
- phy1: ethernet-phy@1 {
- interrupts = <2 1 0 0>;
- reg = <0x1>;
- };
- };
- mdio@25000 {
- tbi1: tbi-phy@11 {
- reg = <0x11>;
- device_type = "tbi-phy";
- };
- };
- mdio@26000 {
- tbi2: tbi-phy@11 {
- reg = <0x11>;
- device_type = "tbi-phy";
- };
- };
- enet0: ethernet@b0000 {
- phy-connection-type = "rgmii-id";
- fixed-link {
- speed = <1000>;
- full-duplex;
- };
- };
- enet1: ethernet@b1000 {
- phy-handle = <&phy0>;
- tbi-handle = <&tbi1>;
- phy-connection-type = "sgmii";
- };
- enet2: ethernet@b2000 {
- phy-handle = <&phy1>;
- phy-connection-type = "rgmii-id";
- };
- };
- pci1: pcie@ffe09000 {
- reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
- ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
- pci0: pcie@ffe0a000 {
- reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
- ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
- 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
- };
- aliases {
- spi0 = &espi0;
- };
- };
- /include/ "p1020-post.dtsi"
- &espi0 {
- status = "okay";
- flash@0 {
- compatible = "jedec,spi-nor";
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0>;
- spi-max-frequency = <10000000>; /* input clock */
- };
- };
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