p1020rdb-pd.dts 1.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P1020RDB-PD Device Tree Source
  4. *
  5. * Copyright 2013 - 2015 Freescale Semiconductor Inc.
  6. * Copyright 2019 NXP
  7. */
  8. /include/ "p1020.dtsi"
  9. / {
  10. model = "fsl,P1020RDB-PD";
  11. compatible = "fsl,P1020RDB-PD";
  12. #address-cells = <2>;
  13. #size-cells = <2>;
  14. interrupt-parent = <&mpic>;
  15. soc: soc@ffe00000 {
  16. ranges = <0x0 0x0 0xffe00000 0x100000>;
  17. mdio@24000 {
  18. phy0: ethernet-phy@0 {
  19. interrupts = <3 1 0 0>;
  20. reg = <0x0>;
  21. };
  22. phy1: ethernet-phy@1 {
  23. interrupts = <2 1 0 0>;
  24. reg = <0x1>;
  25. };
  26. };
  27. mdio@25000 {
  28. tbi1: tbi-phy@11 {
  29. reg = <0x11>;
  30. device_type = "tbi-phy";
  31. };
  32. };
  33. mdio@26000 {
  34. tbi2: tbi-phy@11 {
  35. reg = <0x11>;
  36. device_type = "tbi-phy";
  37. };
  38. };
  39. enet0: ethernet@b0000 {
  40. phy-connection-type = "rgmii-id";
  41. fixed-link {
  42. speed = <1000>;
  43. full-duplex;
  44. };
  45. };
  46. enet1: ethernet@b1000 {
  47. phy-handle = <&phy0>;
  48. tbi-handle = <&tbi1>;
  49. phy-connection-type = "sgmii";
  50. };
  51. enet2: ethernet@b2000 {
  52. phy-handle = <&phy1>;
  53. phy-connection-type = "rgmii-id";
  54. };
  55. };
  56. pci1: pcie@ffe09000 {
  57. reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */
  58. ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */
  59. 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */
  60. };
  61. pci0: pcie@ffe0a000 {
  62. reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */
  63. ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */
  64. 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */
  65. };
  66. aliases {
  67. spi0 = &espi0;
  68. };
  69. };
  70. /include/ "p1020-post.dtsi"
  71. &espi0 {
  72. status = "okay";
  73. flash@0 {
  74. compatible = "jedec,spi-nor";
  75. #address-cells = <1>;
  76. #size-cells = <1>;
  77. reg = <0>;
  78. spi-max-frequency = <10000000>; /* input clock */
  79. };
  80. };