p2020-post.dtsi 1.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+ OR X11
  2. /*
  3. * P2020 Silicon/SoC Device Tree Source (post include)
  4. *
  5. * Copyright 2013 Freescale Semiconductor Inc.
  6. * Copyright 2019 NXP
  7. */
  8. &soc {
  9. #address-cells = <1>;
  10. #size-cells = <1>;
  11. device_type = "soc";
  12. compatible = "fsl,p2020-immr", "simple-bus";
  13. bus-frequency = <0x0>;
  14. usb@22000 {
  15. compatible = "fsl-usb2-dr";
  16. reg = <0x22000 0x1000>;
  17. phy_type = "ulpi";
  18. };
  19. mpic: pic@40000 {
  20. interrupt-controller;
  21. #address-cells = <0>;
  22. #interrupt-cells = <4>;
  23. reg = <0x40000 0x40000>;
  24. compatible = "fsl,mpic";
  25. device_type = "open-pic";
  26. big-endian;
  27. single-cpu-affinity;
  28. last-interrupt-source = <255>;
  29. };
  30. esdhc: esdhc@2e000 {
  31. compatible = "fsl,esdhc";
  32. reg = <0x2e000 0x1000>;
  33. /* Filled in by U-Boot */
  34. clock-frequency = <0>;
  35. };
  36. espi0: spi@7000 {
  37. compatible = "fsl,mpc8536-espi";
  38. #address-cells = <1>;
  39. #size-cells = <0>;
  40. reg = <0x7000 0x1000>;
  41. fsl,espi-num-chipselects = <4>;
  42. status = "disabled";
  43. };
  44. /include/ "pq3-i2c-0.dtsi"
  45. /include/ "pq3-i2c-1.dtsi"
  46. /include/ "pq3-etsec1-0.dtsi"
  47. /include/ "pq3-etsec1-1.dtsi"
  48. /include/ "pq3-etsec1-2.dtsi"
  49. };
  50. /* PCIe controller base address 0x8000 */
  51. &pci2 {
  52. compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  53. law_trgt_if = <0>;
  54. #address-cells = <3>;
  55. #size-cells = <2>;
  56. device_type = "pci";
  57. bus-range = <0x0 0xff>;
  58. };
  59. /* PCIe controller base address 0x9000 */
  60. &pci1 {
  61. compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  62. law_trgt_if = <1>;
  63. #address-cells = <3>;
  64. #size-cells = <2>;
  65. device_type = "pci";
  66. bus-range = <0x0 0xff>;
  67. };
  68. /* PCIe controller base address 0xa000 */
  69. &pci0 {
  70. compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq";
  71. law_trgt_if = <2>;
  72. #address-cells = <3>;
  73. #size-cells = <2>;
  74. device_type = "pci";
  75. bus-range = <0x0 0xff>;
  76. };