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Add missing docs

optixx 8 years ago
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      files/Quickdev16_1.5_sdcard.txt
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      files/Quickdev16_Seeedstudio2.6_orderlist.ods
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      files/Quickdev16_ascii_banner.txt
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      files/docs/avr/at90usb_short.pdf
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      files/docs/avr/stk500.pdf
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      files/docs/ftdi/DS_FT232R_V202.pdf
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      files/docs/ftdi/FT232RL.pdf
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      files/docs/snes/65816.STD
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      files/docs/snes/65816/addrmode.txt
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      files/docs/snes/65816/detailop.txt
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      files/docs/snes/65816/diagram.gif
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      files/docs/snes/65816/feature.txt
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      files/docs/snes/65816/funcdesc.txt
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      files/docs/snes/65816/instnote.txt
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      files/docs/snes/65816/instruct.txt
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      files/docs/snes/65816/intrrpts.txt
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      files/docs/snes/65816/mnemonic.txt
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      files/docs/snes/65816/opcodes.txt
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      files/docs/snes/65816/scnfrmt.txt
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      files/docs/snes/65816/thetrip.tag
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      files/docs/snes/Architektur des SNES - Final.doc
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      files/docs/snes/Intrrpts.txt
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      files/docs/snes/LoROM.png
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      files/docs/snes/Qaddress.txt
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      files/docs/snes/SNES-ROM.TXT
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      files/docs/snes/SNESKart-TurtleGroupInc..pdf
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      files/docs/snes/SNESMAP2.TXT
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      files/docs/snes/SNESMNEM.TXT
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      files/docs/snes/SNESMem.txt
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      files/docs/snes/SNESMem2.txt
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      files/docs/snes/SNESROM.PIN
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      files/docs/snes/SNES_Lockout.txt
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      files/docs/snes/SWC.TXT
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      files/docs/snes/SWC.ZIP
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      files/docs/snes/Sneskart.txt
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      files/docs/snes/Snesmath.txt
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      files/docs/snes/Snesrom.txt
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      files/docs/snes/Swchead.txt
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      files/docs/snes/U12675EJ7V0DS00.pdf
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      files/docs/snes/board_cpld_01.png
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      files/docs/snes/book1.pdf
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      files/docs/snes/book2.pdf
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      files/docs/snes/fairligh.txt
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      files/docs/snes/famitec2.txt
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      files/docs/snes/fastrom.txt
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      files/docs/snes/how2code.txt
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      files/docs/snes/memmap.txt
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      files/docs/snes/memory_mapping_and_io.txt
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      files/docs/snes/memory_mapping_overview.txt
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      files/docs/snes/memory_mapping_table.txt
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      files/docs/snes/mmio.txt
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      files/docs/snes/oam_flags.txt
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      files/docs/snes/pilotwings.pdf
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      files/docs/snes/romformat_overview.txt
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      files/docs/snes/romhacking.txt
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      files/docs/snes/snes_cart1.txt
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      files/docs/snes/snesmap.txt
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      files/docs/snes/snestech.txt
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      files/docs/snes/tile_format.txt
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      files/docs/snes/tiles.txt
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      files/docs/snes/vram.txt
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      files/docs/snes/w65c816s.pdf
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      files/docs/snes/yoshi/READ.ME
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      files/docs/snes/yoshi/SID-SPC.SRC
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      files/docs/snes/yoshi/SNES.0
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      files/docs/snes/yoshi/SNES.1
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      files/docs/snes/yoshi/SNES.2
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      files/docs/snes/yoshi/SNES.3
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      files/docs/snes/yoshi/SNES.4
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      files/docs/snes/yoshi/SNES.5
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      files/docs/snes/yoshi/SNES.6
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      files/docs/snes/yoshi/SNES.7
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      files/docs/snes/yoshi/SNES.8
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      files/docs/snes/yoshi/SOUND.DOC
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      files/docs/snes/yoshi/SPRITE.DOC
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      files/docs/ttl/7400_DS.pdf
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      files/docs/ttl/74HC645.pdf
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      files/docs/ttl/74HC_HCT245_3.pdf
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      files/docs/ttl/74LCX245.pdf
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      files/docs/usb/usb-in-a-nutshell.pdf

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+--------------------------------
+SDcard Board
+--------------------------------
+Connector 
+
+1  DO   -> 7  
+2  GND  -> 6 
+3  VCC  -> 4
+4  CS   -> 1
+5  DI   -> 2
+6  CLK  -> 5
+-
+SDcard
+------------------\
+|                  \
+| 8 7 6 5 4 3 2 1 9 |
+|                   |
+
+1 CS
+2 CMD/DI
+3 GND
+4 VCC
+5 CLK/SCLK
+6 GND
+7 DAT/DO
+8 --
+9 --	
+
+
+--------------------------------
+Quickdev Header
+--------------------------------
+top/usb
+1 GND                -> GND
+2 ISP RST  - RESET   -      
+3 ISP SCK  - PB7     - CLK
+4 ISP MISO - PB6     - DI
+5 ISP MOSI - PB5     - DO
+6 MMC CS   - PB4     - CS 
+7 VCC                -> VCC 
+
+
+
+#define SPI_DI				6		MISO
+#define SPI_DO				5		MOSI

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+________        .__        __    ________               ____  ________
+\_____  \  __ __|__| ____ |  | __\______ \   _______  _/_   |/  _____/
+ /  / \  \|  |  \  |/ ___\|  |/ / |    |  \_/ __ \  \/ /|   /   __  \
+/   \_/.  \  |  /  \  \___|    <  |    `   \  ___/\   / |   \  |__\  \
+\_____\ \_/____/|__|\___  >__|_ \/_______  /\___  >\_/  |___|\_____  /
+       \__>             \/     \/        \/     \/                 \/
+             ___.
+ __ __  _____\_ |__
+|  |  \/  ___/| __ \
+|  |  /\___ \ | \_\ \
+|____//____  >|___  /
+           \/     \/
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+
+

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+   A Proposed Assembly Language Syntax For 65c816 Assemblers
+       by Randall Hyde
+       
+
+ This is a proposed standard for 65c816 assembly language.  The
+proposed standard comes in three levels: subset, full, and extended.  The
+subset standard is intended for simple (or inexpensive) products,
+particularly those aimed at beginning 65c816 assembly language programmers.
+The full standard is the focus of this proposal.  An assembler meeting the
+full level adopts all of the requirements outlined in this paper.  The
+extended level is a mechanism whereby a vendor can claim full compliance
+with the standard and point out that there are extensions as well.  An
+assembler cannot claim extended level compliance unless it also complies with
+the full standard.  An assembler, no matter how many extensions are
+incorporated, will have to claim subset level unless the full standard is
+supported.  This ensures that programmers who do not use any assembler
+extensions can assemble their programs on any assembler meeting the full or
+extended compliance levels.  
+
+ In addition to the items required for compliance, this proposal 
+suggests several extensions in the interests of compatibility with existing
+65c816 assemblers.  These recommendations are not required for full
+compliance with the standard, they're included in this proposal as suggestions
+to help make conversion of existing programs easier.  The suggestions are
+presented in two levels: recommended and optional.  Recommended items should
+be present in any decent 65c816 package.  Inclusion of the optional items
+is discouraged (since there are other ways to accomplish the same operation
+within the confines of the standard) but may be included in the assembler
+at the vendor's discretion to help alleviate conversion problems.
+
+
+
+
+
+
+
+
+
+   65c816 Instruction Mnemonics 
+   ----------------------------
+
+
+ All of the following mnemonics are required at the subset, full,
+and extended standard levels.
+
+ The following mnemonics handle the basic 65c816 instruction set:
+
+ADC - add with carry
+AND - logical AND
+BCC - branch if carry clear
+BCS - branch if carry set
+BEQ - branch if equal
+BIT - bit test
+BMI - branch if minus
+BNE - branch if not equal
+BPL - branch if plus
+BRA - branch always
+BRK - break point instruction
+BVC - branch if overflow clear
+BVS - branch if overflow set
+CLC - clear the carry flag
+CLD - clear the decimal flag
+CLI - clear the interrupt flag
+CLP - clear bits in P
+CLR - store a zero into memory
+CMP - compare accumulator
+CPX - compare x register
+CPY - compare y register
+CSP - call system procedure
+DEC - decrement acc or memory
+DEX - decrement x register
+DEY - decrement y register
+EOR - exclusive-or accumulator
+HLT - halt (stop) the clock
+INC - increment acc or memory
+INX - increment x register
+INY - increment y register
+JMP - jump to new location
+JSR - jump to subroutine
+LDA - load accumulator
+LDX - load x register
+LDY - load y register
+MVN - block move (decrement)
+MVP - block move (increment)
+NOP - no operation
+ORA - logical or accumulator
+PHA - push accumulator
+PHP - push p
+PHX - push x register
+PHY - push y register
+PLA - pop accumulator
+PLP - pop p
+PLX - pop x register
+PLY - pop y register
+PSH - push operand
+PUL - pop operand
+RET - return from subroutine
+ROL - rotate left acc/mem
+ROR - rotate right acc/mem
+RTI - return from interrupt
+RTL - return from long subroutine
+RTS - return from short subroutine
+SBC - subtract with carry
+SED - set decimal flag
+SEI - set interrupt flag
+SEP - set bits in P
+SHL - shift left acc/mem
+SHR - shift right acc/mem
+STA - store accumulator
+STX - store x register
+STY - store y register
+SWA - swap accumulator halves
+TAD - transfer acc to D
+TAS - transfer acc to S
+TAX - transfer acc to x
+TAY - transfer acc to y
+TCB - test and clear bit
+TDA - transfer D to acc
+TSA - transfer S to acc
+TSB - test and set bit
+TSX - transfer S to X
+TXA - transfer x to acc
+TXS - transfer x to S
+TXY - transfer x to y
+TYA - transfer y to acc
+TYX - transfer y to x
+WAI - wait for interrupt
+XCE - exchange carry with emulation bit
+
+Comments:
+
+ CLP replaces REP in the original 65c816 instruction set, since CLP
+is a tad more consistent with the original 6502 instruction set.  See 
+"recommended options" for the status of REP.  CLR replaces the STZ
+instruction.  Since STA, STX, and STY are used to store 65c816 registers,
+STZ seems to imply that there is a Z register.  Using CLR (clear) eliminates
+any confusion.  CSP (call system procedure) replaces the COP mnemonic.  COP
+was little more than a software interrupt in both intent and implementation.
+CSP helps make this usage a little clearer.  HLT replaces the STP mnemonic.
+STP, like the STZ mnemonic, implies that the P register is being stored
+somewhere.  HLT (for halt) is just as obvious as "stop the clock" yet it
+doesn't have the same "look and feel" as a store instruction.   JML and JSL
+are not really required by the new standard;  but see recommended options
+concerning these two instructions.  Most of the new 65c816 push and pull
+instructions have been collapsed into two instructions: PSH and PUL.
+
+ PEA label   becomes  PSH #label
+ PEI (label) becomes  PSH label
+ PER label   becomes  PSH @label
+ PHB         becomes  PSH DBR
+ PHD         becomes  PSH D
+ PHK     becomes  PSH PBR
+
+ PLB      becomes  PUL DBR
+ PLD     becomes  PUL D
+ 
+These mnemonics are more in line with the original design of the 6502
+instruction set whereby the mnemonic specifies the operation and the operand
+specifies the addressing mode and address.  The RET instruction gets converted
+to RTS or RTL, depending on the type of subroutine being declared.  RTS and 
+RTL still exist in order to force a short or long return.  SHL and SHR (shift
+left and shift right) are used instead of ASL and LSR.  The 6500 family has
+NEVER supported an arithmetic shift left instruction.  The operation performed
+by the ASL mnemonic is really a logical shift left. To simplify matters, SHL
+and SHR are used to specify shift left and shift right.  SWA (swap accumulator
+halves) is used instead of XBA.  Since this is the only instruction that
+references the "B" accumulator, there's no valid reason for even treating
+the accumulator as two distinct entities (this is just a carry-over from the
+6800 MPU).  Likewise, since the eight-bit accumulator cannot be distinguished
+from the 16-bit accumulator on an instruction by instruction basis (it depends
+on the setting of the M bit in the P register), the accumulator should always
+be referred to as A, regardless of whether the CPU is in the eight or sixteen
+bit mode.  Therefore, instructions like TCD, TCS, TDC, and TSC should be
+replaced by TAD, TAS, TDA, and TSA.  For more info on these new mnemonics,
+see the section on "recommended options".
+
+
+   Built-in Macros
+   ---------------
+
+ The following instructions actually generate one or more instructions.
+They are not required at the subset level, but are required at the full and
+extended levels.
+ 
+
+ADD - emits CLC then ADC
+BFL - emits BEQ (branch if false)
+BGE - emits BCS
+BLT - emits BCC
+BTR - emits BNE (branch if true)
+BSR - emits PER *+2 then BRA (short) or PER *+3 then BRL (long)
+SUB - emits SEC then SBC
+
+
+   Recommended Options
+   -------------------
+
+ The following mnemonics are aliases of existing instructions.  The
+(proposed) standard recommends that the assembler support these mnemonics,
+mainly to provide compatibility with older source code, but does not
+recommend their use in new programs.  Some (or all) of these items may be
+removed from the recommended list in future revisions of the standard.  None
+of these recommended items need be present at the subset level.  If these
+are the only extensions over and above the full syntax, the assembler
+CANNOT claim to be an extended level assembler.
+
+ASL BRL COP JML JSL LSR PEA PEI PER
+PHB PHK PHK PLB PLD REP TCD TCS TDC
+TSC TRB WDM XBA
+
+
+
+
+  Symbols, Constants, and Other Items
+  -----------------------------------
+
+ Symbols may contain any reasonable number of characters at the full
+level.  At the subset compliance level, at least 16 characters should be
+supported and 32 is recommeded.  A "reasonable" number of characters should
+be at least 64 if the implementor needs a maximum value.
+
+ Symbols must begin with an alphabetic character and may contain
+(only) the following symbols:  A-Z, a-z, 0-9, "_", "$", and "!".  The
+assembler must be capable of treating upper and lower case alphabetic
+characters identically.  Note that this does not disallow an assembler from
+allowing the programmer to choose that upper and lower case be distinct, it
+simply requires that in the default case, upper and lower case characters
+are treated identically.  Note that the standard does not require case
+sensitivity in the assembler (and, in fact, recommends against it).
+Therefore, anyone foolish enough (for many, many reasons) to create variables
+that differ only in the case of the letters they contain is risking port-
+ability problems (as well as maintenence, readability, and other problems).
+
+ The following symbols are reserved and may not be redefined within
+the program:
+
+  A, X, Y, S, DBR, PBR, D, M, P
+
+Nor may these symbol appear as fields to a record or type definition (which
+will be described later).
+
+
+ Constants take six different forms: character constants, string
+constants, binary constants, decimal constants, hexadecimal constants and
+set constants.
+
+ Character constants are created by surrounding a single character by 
+a pair of apostrophes or quotation marks, e.g., "s", "a", '$', and 'p'.  If 
+the character is surrounded by apostrophes, then the ASCII code for that 
+character WITH THE H.O. BIT CLEAR will be used.  If the quotation marks are 
+used, then the ASCII code for the character WITH THE H.O. BIT SET will be 
+used.  If you need to represent the apostrophe with the H.O. bit clear or a
+quotation mark with the H.O. bit set, simply double up the characters, e.g.,
+
+  '''' - emits a single apostrophe.
+  """" - emits a single quotation mark.
+
+ String constants are generated by placing a sequence of two or more
+characters within a pair of apostrophes or quotation marks.  The choice of
+apostrophe or quotation mark controls the H.O. bit, as for character
+constants.  Likewise, to place an apostrophe or quote within a string
+delimited by the same character, just double up the apostrophe or quotation
+mark:
+
+ 'This isn''t bad!'  - generates  --This isn't bad--
+ "He said ""Hello""" - generates  --He said "Hello"--
+
+
+ Binary integer constants consist of a sequence of 1 through 32 zeros
+or ones preceded by a percent sign ("%").  Examples:
+
+   %10110010
+   %001011101
+   %10
+   %1100
+
+ Decimal integer constants consist of strings of decimal digits without
+any preceding characters.  E.g.,  25,  235,  8325, etc.  Decimal constants
+may be (optionally) preceded by a minus sign.
+
+ Hexadecimal constants consist of a dollar sign ("$") followed by
+a string of hexadecimal digits (0..9 and A..F).  Values in the range $0 
+through $FFFFFFFF are allowed.
+
+ Set constants are only required at the full and  extended compliance
+levels.  A set constant consists of a list of items surrounded by braces,
+e.g., {0,3,5}.  For more information, see the .SET directive.
+
+
+
+   Address Expressions
+   -------------------
+   
+ Most instructions and many pseudo-opcode/assembler directives require
+operands of some sort.  Often these operands contain some sort of address
+expression (some, ultimately, numeric or string value).  This proposed 
+standard defines the operands, precision, accuracy, and available operations 
+that constitutes an address expression.
+
+Precision: all integer expressions are computed using 32 bits.  All string
+expressions are computed with strings up to 255 characters in length.  All
+floating point operations are performed using IEEE 80-bit extended floating
+point values (i.e., Apple SANE routines).  All set operations are performed
+using 32 bits of precision.
+
+Accuracy: all integer operations (consisting of two 32-bit operands and an
+operator on those operands) must produce the correct result if the actual
+result can fit within 32 bits.  If an overflow occurs, the value is truncated
+and only the low order 32 bits are retained.  If an underflow occurs, zero
+is used as the result.  If an overflow or underflow occurs, a special bit will
+be set (until the next value is computed) that can be tested by the ".IFOVR"
+and ".IFUNDR" directives.  Other than that, such errors are ignored.  All
+arithmetic is performed using unsigned arithmetic operations. All
+floating point operations follow the IEEE (and Apple SANE) suggestions, and
+are otherwise ignored by the assembler.  Any string operation producing a
+string longer than 255 characters produces an assembly time error.  All set
+operations must be exact.
+
+Integer operations: The following integer operations must be provided at all
+compliance levels:
+
++ (binary) adds the two operands.
+- (binary) subracts second operand from the first.
+* multiplies the two operands.
+/ divides the first operand by the second.
+\ divides the first operand by the second and returns the remainder.
+& logically ANDs the two operands.
+| logically ORs the two operands.
+^ logically XORs the two operands.
+
+
+=
+<> These operators compare the two operands (unsigned comparison) and
+<  return 1 if the comparison is true, 0 otherwise.
+>
+<=
+>=
+
+- (unary) negates (2's complement) the operand
+~ (unary) complements (inverts - 1's complement) the operand
+
+
+The following operators must be provided at the full and extended compliance
+levels:
+
+<- shifts the first operand to the left the number of bits specified by the
+   second operand.
+-> shifts the first operand to the right the number of bits specified by the
+   second operand.
+
+@ (unary) subtracts the location counter at the beginning of the current
+          statement from the following address expression.
+
+% (ternary, e.g.: X%Y:Z)  This operator extracts bits Y through Z from X and
+  returns that result right justified.
+
+
+Floating point operations: floating point numbers and operations are required
+only at the full and extended levels.  The following operations must be
+available as well:
+
++ adds the two operands.
+- subtracts the second operand from the first.
+* multiplies the two operands.
+/ divides the first operand by the second.
+- (unary) negates the operand.
+
+=
+<> These operators compare the two operands and
+<  return 1 if the comparison is true, 0 otherwise.
+>
+<=
+>=
+
+
+
+String operations: strings and string operations are not required at the
+subset level, but the standard recommends their presence.  The following
+string operations must be provided at the full and extended levels:
+
++ concatenates two strings
+% (ternary, e.g., X%Y:Z) returns the substring composed of the characters in
+  X starting at position Y of length Z.  Generate an error if X doesn't
+  contain sufficient characters.
+
+=
+<> These operators compare the two operands and
+<  return 1 if the comparison is true, 0 otherwise.
+>
+<=
+>=
+
+
+Set operations: sets and set operations are required only at the full and
+extended levels.  The following set operations must be provided:
+
++  union of two sets  (logical OR of the bits).
+*  intersection of two sets (logical AND of the bits).
+-  set difference (set one ANDed with the NOT of the second set)
+
+=  returns 1 if the two sets are equal, zero otherwise.
+<> returns 1 if the two sets are not equal, zero otherwise.
+<  returns 1 if the first set is a proper subset of the second.
+<= returns 1 if the first set is a subset of the second.
+>  returns 1 if the first set is a proper superset of the second.
+>= returns 1 if the first set is a superset of the second.
+
+% (ternary, e.g., X % Y:Z) extracts elements Y..Z from X and returns those
+  items.
+
+
+In addition to the above operators,  several pre-defined functions are also
+available.  Note that these functions are not required at the subset
+compliance level, only at the full and extended levels:
+
+float(i) - Converts integer "i" to a floating point value.
+trunc(r) - Converts real "r" to a 32-bit unsigned integer (or generates an 
+    error).
+valid(r) - returns "1" if r is a valid floating point value, 0 otherwise
+           (for example, if r is NaN, infinity, etc.)
+length(s)- returns the length of string s.
+lookup(s)- returns "1" if s is a valid symbol in the symbol table.
+value(s) - returns value of symbol specified by string "s" in the symbol
+           table.
+type(s)  - returns type of symbol "s" in symbol table.  Actual values
+           returned are yet to be defined.
+mode(a)  - returns the addressing mode of item "a".  Used mainly in macros.
+STR(s)   - returns string s with a prefixed length byte.
+ZRO(s)   - returns string s with a suffixed zero byte.
+DCI(s)   - returns string s with the H.O. bit of its last char inverted.
+RVS(s)   - returns string s with its characters reversed.
+FLP(s)   - returns string s with its H.O. bits inverted.
+IN(v,s)  - returns one if value v is in set s, zero otherwise.
+
+
+The following integer functions must be present at all compliance levels:
+
+LB(i),
+LBYTE(i),
+BYTE(i)  - returns the L.O. byte of i.
+HB(i),
+HBYTE(i) - returns byte #1 (bits 8-15) of i.
+BB(i),
+BBYTE(i) - returns bank byte (bits 16-23) of i.
+XB,
+XBYTE(i) - returns H.O. byte of i.
+LW(i),
+LWORD(i),
+WORD(i)  - returns L.O. word of i.
+HW(i),
+HWORD(i) - returns H.O. word of i.
+WORD(i)
+
+Pack(i,j)- returns a 16-bit value whose L.O. byte is the L.O. byte of i and
+    whose H.O. byte is the L.O. byte of j.
+    
+Pack(i,j,k,l)- returns a 32-bit value consisting of (i,j,k,l) where i is the
+        L.O. byte and l is the H.O. byte.  Note: l is optional.  If
+        it isn't present, substitute zero for l.
+
+
+
+
+ The order of evaluation for an expression is strictly left to right
+unless parentheses are used to modify the precedence of a sub-expression.
+Since parentheses are used to specify certain indirect addressing modes, the
+use of paretheses to override the strict left-to-right evaluation order
+introduces some ambiguity.  For example, should the following be treated
+as jump indirect through location $1001 or jump directly to location $1001?
+
+  JMP ($1000+1)
+
+The ambiguity is resolved as follows: if the parenthesis is the first char-
+acter in the operand field, then the indirect addressing mode is assumed.
+Otherwise, the parentheses are used to override the left-to-right precedence.
+The example above would be treated as a jump indirect through location $1001.
+If you wanted to jump directly to location $1001 in this fashion, the state-
+ment could be modified to
+
+  JMP 0+($1000+1)
+
+so that the parenthesis is no longer the first character in the operand
+field.
+
+ The use of parentheses to override the left-to-right precedence is
+only required at the full and extended compliance levels.  It is not
+required at the subset compliance level.
+
+
+
+
+
+    Expression Types
+    ----------------
+
+ Expressions, in addition to having a value associated with
+them, also have a specific type.  The three basic types of expressions are
+integer, floating point, and string expressions.  Integer expressions can
+be broken down into subtypes as well.  A hierarchical diagram is the easiest
+way to describe integer expressions:
+
+
+
+integers ------ constants ------------ user defined (enumerated) types
+     |   |
+     |   +----- simple numeric constants
+     |
+     |
+     +-- addresses ------------ direct page addresses
+    |
+    +----- absolute addresses --- full 16-bit
+    |                          |
+    |      +- relative 8-bit
+    |
+    +----- long addresses
+
+ This diagram points out that there are two types of integer expres-
+sions: constants and addresses.  Further, there are two types of constants
+and four types of addresses.  Before discussion operations on these different
+types of integer values, their purpose should be presented.
+
+ Until now, most 65xxx assembler did little to differentiate between
+the different types of integer values.  In this proposed standard, however,
+strong type checking is enforced.  Whereas in previous assemblers you could
+use the following code:
+
+ label equ $1000
+  lda #Label
+  sta Label
+
+such operations are illegal within the confines of the new standard.  The
+problem with this short code segment is that the symbol "label" is used as
+both an integer constant (in the LDA instruction) and as an address 
+expression (in the STA instruction).  To help prevent logical errors from
+creeping into a program, the assembler doesn't allow the use of addresses
+where constants are expected and vice versa.  To that end, a new assembler
+directive, CON, is used to declare constants while EQU is used to declare
+an (absolute) address.  Symbols declared by CON cannot be (directly) used
+as an address.  Likewise, symbols declared by EQU (and others) cannot be
+used where a constant is expected (such as in an immediate operand).
+
+ Although this type checking can be quite useful for locating bugs
+within the source file, it can also be a source of major annoyance.  Some-
+times (quite often, in fact) you may want to treat an address expression
+as a constant or a constant expression as an address.  Two functions are
+used to coerce these expressions to their desired form: PTR and OFS.
+PTR(expr) converts the supplied constant expression to an address expression.
+OFS(expr) converts the supplied address expression to a constant expression.
+The following is perfectly legal:
+
+ Cons1 CON $5A
+ DataLoc EQU $1000
+  lda #OFS(DataLoc)
+  sta PTR(Cons1)
+
+For more information, see the section on assembler directives.  PTR and OFS
+are required at all compliance levels of this proposed standard.
+
+ While any constant value may be used anywhere a constant is allowed,
+the 65c816 microprocessor must often differentiate between the various types
+of address expressions.  This is particularly true when emitting code since
+the length of an instruction depends on the particular address expression.
+If an expression contains only constants, direct page values, absolute
+values, or long values,  there isn't much of a problem.  The assembler uses
+the specified type as the addressing mode.  If the expression contains mixed
+types, the resulting type is as follows:
+
+Expression contains:    Result is:
+ |      |
+ |      |
+ +------------+-- Constants  - Constant
+ |       |
+ +-- Direct   |    -       Direct
+       |
+       +--+  Absolute  - Absolute
+       |
+       +--+- Long   - Long
+
+Allowable forms:
+
+ constant
+ direct  constant+direct
+ absolute constant+absolute
+ long  constant+long  
+   absolute+long
+   constant+absolute+long
+ 
+
+This says that if you expression contains only constants, then the
+result is a constant.  If it contains a mixture of constants and direct
+page addresses, the result is a direct page address.  Note that direct page
+addresses cannot be mixed with other types of addresses.  An error must be
+reported in this situation (although you could get around it with an
+expression of the form "abs+OFS(direct)").  Likewise, adding a constant to
+an absolute address produces an absolute address.  Adding an absolute and
+a long address produces a long address, etc.
+
+ Sometimes, you need to force an expression to be a certain type.
+For example, the instruction "LDA $200" normally assembles to a load
+absolute from location $200 in the current data bank.  If you need to force
+this to location $200 in bank zero, regardless of the content of the DBR,
+the address expression must be coerced to a long address.  Coercion of this
+type is accomplished with the ":D", ":A", ":L", and ":S" expression suffixes.
+To force "LDA $200" to be assembled using the long address mode, the in-
+struction is modified to be "LDA $200:L".  The coercion suffix must always
+follow the full address expression.  The ":S" (for short branches) suffix
+is never required, since a short branch (for BRA and BSR) is always assumed,
+but it is included for completeness.  For BRA and BSR, the ":L" suffix is
+used to imply a long branch (+/- 32K) rather than the long addressing mode.
+
+ Caveats: If ":D" or ":A" is used to coerce a large address expression
+to direct or absolute, the high order byte(s) of the expression are truncated
+and ignored.  The assembler must assume that when a programmer uses these
+constructs he knows exactly what he's doing.  Therefore, "LDA $1001:D" will
+happily assemble this instruction into a "LDA $01" instruction despite the
+actual value of the address expression.
+
+
+
+
+
+Addressing Mode Specification
+-----------------------------
+
+ 65c816 addressing modes are specified by certain symbols in the op-
+erand field.  A quick rundown follows:
+
+ Addressing mode  Format(s)  Example(s)
+ ---------------  ------------------ ----------------------
+
+ Immediate  #<expression>  LDA #0
+    =<expression>  CMP =LastValue
+
+ Direct Page  <expression>  LDA DPG
+    <expression>:D  LDA ANY:D
+
+ Absolute  <expression>  LDA ABS
+    <expression>:A  LDA ANY:A
+
+ Long   <expression>  LDA LONG
+    <expression>:L  LDA ANY:L
+
+ Accumulator  {no operand}  ASL
+       INC
+
+ Implied   {no operand}  CLC
+       SED
+
+ Direct, Indirect,
+ Indexed by Y  (<direct expr>),Y LDA (DPG),Y
+    (<direct expr>).Y LDA (ANY:D).Y
+
+ Direct, Indirect,
+ Indexed by Y, Long [<direct expr>],Y LDA [DPG],Y
+    [<direct expr>].Y LDA [DPG].Y
+
+ Direct, Indexed by X,
+ Indirect  (<direct expr>,X) LDA (DPG,X)
+    (<direct expr>.X) LDA (ANY:D.X)
+
+ Direct, Indexed by X <direct expr>,X  LDA DPG,X
+    <direct expr>.X  LDA DPG.X
+
+ Direct, Indexed by Y <direct expr>,Y  LDX DPG,Y
+    <direct expr>.Y  LDX DPG.Y
+
+ Absolute, Indexed by X <abs expr>,X  LDA ABS,X
+    <abs expr>.X  LDA ANY:A.X
+
+ Long, Indexed by X <long expr>,X  LDA ANY:L,X
+    <long expr>.X  LDA LONG.X
+
+ Absolute, Indexed by Y <abs expr>,Y  LDA ANY:A,Y
+    <abs expr>.Y  LDA ABS.Y
+
+ Program Counter
+ Relative (branches) <expression>  BRA ABS
+    @<expression>  BRA @ABS
+
+ PC Relative (PSH) @<expression>  PSH @ABS
+
+ Absolute, Indirect (<abs expr>)  JMP (ABS)
+
+ Absolute, Indexed,
+ Indirect  (<abs expr>,X)  JMP (ABS,X)
+    (<abs expr>.X)  JMP (ABS.X)
+
+ Direct, Indirect (<dpg expr>)  LDA (DPG)
+       STA (ANY:D)
+
+ Stack Relative  <expr8>,S  LDA 2,S
+    <expr8>.S  LDA 2.S
+
+ Stack Relative,
+ Indirect, Indexed (<expr8>,S),Y  LDA (2,S),Y
+    (<expr8).S),Y  LDA (2.S),y
+    (<expr8),S).Y  LDA (2,S).y
+    (<expr8).S).Y  LDA (2.S).y
+
+ Block Move  <long expr>,<long expr> MVN LONG,LONG
+       MVP LONG,LONG
+
+
+ <dpg expr>, DPG- Any direct page expression or symbol.
+ <abs expr>, ABS- Any absolute expression or symbol.
+ <long expr>, Long- Any long expression or symbol.
+ expr8-   Any expression evaluating to a value less than
+    256.
+
+
+Note: the only real difference between the existing standard and the proposed 
+standard is that the period (".") can be used to form an indexed address ex-
+pression.  This is compatible (in practice, as well as philosophy) with the 
+record structure mechanism supported by this proposed standard.  This syntax 
+for the various addressing modes is required at all compliance levels.
+
+ Suggestion: (<dpg expr>):L,  (<dpg expr>):L,Y, and (<dpg expr):L.Y 
+should be allowed as substitutes for [<dpg expr>],  [<dpg expr>],Y, and 
+[<dpg expr].Y, respectively.  This, however, is not required by this proposed 
+standard.
+
+
+
+
+
+
+Assembler Directives and Pseudo-Opcodes
+---------------------------------------
+
+ An assembler directive is a message to the assembler to change some
+status or otherwise affect the assembly operation.  It does not generate any
+object code.  A pseudo-opcode, on the other hand, is not a standard 65c816
+instruction but does generate object code.  Examples of assembler directives
+include instructions that turn the listing on or off, define procedures,
+equate labels to values, etc.  Examples of pseudo-opcodes include instructions
+like .BYTE which emit bytes of object code based on the instruction's
+parameters.
+
+
+Equates:
+--------
+
+ Probably the most important assembler directives are the equates.
+The equate directives let you associate a value and a type with a symbol.
+The possible equates use the syntax:
+
+ <label>  .EQU <16-bit value>
+ <label>  .EDP <8-bit value>
+ <label>  .EQL <24-bit value>
+ <label>  .CON <32-bit value>
+ <label>  .FCON <SANE floating point value>
+
+All except .FCON are required at all compliance levels.  .FCON is required
+at the full and extended levels.
+
+ .EQU lets you define a absolute symbol; an address whose value is
+relative to the DBR.  An error should be generated if the value in the
+operand field requires more than 16 bits.  The type of the operand expression
+is ignored.  It may be a constant expression, a direct page expression, or
+even a long address expression.  As long as it's an integer expression an
+can fit into 16 bits, it's quite acceptable.
+
+ .EDP (equate to direct page) is used to define direct page symbols.
+Again, the operand field may be of any integer type as long as the result
+fits into 8 bits.  A recommended synonym for .EDP is .EPZ (equate to page
+zero) in deference to the 6502's zero page addressing mode.
+
+ .EQL (equate long) defines long address expressions.  As usual, the
+operand field may contain any integer expression that fits within 24 bits.
+
+ .CON (constant) is used to define integer numeric constants.  Any
+32 bit numeric value may be specified in the operand field.
+
+ .FCON (floating point constant) is used to declare symbolic floating
+point constants.  Such constants must be stored in the symbol table as
+80-bit SANE extended values.
+
+ In addition to the typed equates, this proposed standard also allows
+an untyped equate, which takes the form:
+
+  <label>  = <operand>
+
+where "<operand>" is any valid operand that may appear in the operand field
+of any instruction.  <operand>'s type may be integer, string, floating point
+and may also include an addressing mode.  The following are all legal:
+
+  lbl = 5
+  lbl = 5.5
+  lbl = "Five"
+  lbl = Array,X
+  lbl = (dp,s),y
+
+Labels defined by "=" may appear anywhere the operand field specified for
+that label is allowed.  In general, a simple string substitution should be
+performed when a label defined by "=" is used.  Note: a label declared by
+"=" can be redefined without error throughout the program.  The "=" directive
+is required only at the full and extended compliance levels.
+
+
+
+Data Definitions:
+-----------------
+
+ While the equates are probably the most important assembler 
+directives, the data definition instructions are probably the most important
+pseudo-opcodes around.  These instructions are classed into four groups
+determined by the types of operands they accept.  In the following paragraphs
+all optional items are enclosed within braces.
+
+ The first group of data reservation instructions accept any integer
+type expression as operands.  They are:
+
+ {label}  .BYTE {expr1, expr2, ..., exprn}
+ {label}  .WORD {expr1, expr2, ..., exprn}
+ {label}  .LONG {expr1, expr2, ..., exprn}
+ 
+If a label is present, it is treated as a statement label within the current
+segment and assigned the value of the location counter before any bytes are
+emitted.  For the .BYTE opcode, one byte of data is emitted for each operand
+in the operand field, that byte being the L.O. byte of each expression.  
+Operands are purely optional.  If no operand appears, then an indeterminate
+value is emitted. The .WORD opcodes outputs two bytes for each expression in 
+the operand field (or two indeterminate bytes if no operand is present).  The
+.LONG instruction outputs four bytes for each operand.  These three pseudo-
+opcodes must be present at all compliance levels.
+
+ The next group of pseudo-opcodes are used to create tables of
+addresses.  As such, they only allow symbols that have been defined by
+.EQU, .EQL, "=" (as applicable), statement labels, procedure labels, and
+segment labels in their operand fields.  They are:
+
+ {label}  .OFFS expr1 {,expr2, ..., exprn}
+ {label}  .ADRS   expr1 {,expr2, ..., exprn}
+ {label}  .PTR expr1 {,expr2, ..., exprn}
+
+.OFFS outputs two bytes for each operand;  .ADRS outputs three bytes for
+each operand; and .PTR outputs four bytes for each operand.  These three
+pseudo-opcodes are only required at the full and extended compliance levels.
+
+ The third group of declarations are used to create constant tables.
+As such, they only allow symbols declared by .CON.  They are:
+
+ {label}  .SHORT  expr1 {,expr2, ..., exprn}
+ {label}  .INTEGER expr1 {,expr2, ..., exprn}
+ {label}  .LONGINT expr1 {,expr2, ..., exprn}
+
+These pseudo-ops output one, two, and four bytes respectively.  These
+pseudo-opcodes are not required at the subset compliance level, they are
+required only at the full and extended levels.
+
+ Note: non-symbolic constants are allowed in any of the above
+pseudo-opcodes.  Only symbols should have their type information checked.
+
+ The last group of data declaration pseudo-opcodes are used to
+initialize floating point values.  These pseudo-ops are:
+
+ {label}  .FLOAT  {item1, item2, ..., itemn}
+ {label}  .DOUBLE  {item1, item2, ..., itemn}
+ {label}  .EXTENDED {item1, item2, ..., itemn}
+ {label}  .COMP  {item1, item2, ..., itemn}
+
+each instruction generates operands of 4, 8, 10, or 8  bytes in length,
+respectively.  If the operand field is left blank, the corresponding bytes
+contain an indeterminate value, but the assembler should initialize them to
+NaN (not a number).  These four pseudo-opcodes are required only at the
+full and extended levels.
+
+ Although not required by the standard, the following data declaration
+directives are recommended and should be supported:
+
+ {label}  .HBYTE  expr1 {,expr2, ..., exprn}
+ {label}  .BBYTE  expr1 {,expr2, ..., exprn}
+ {label}  .XBYTE  expr1 {,expr2, ..., exprn}
+ {label}  .HWORD  expr1 {,expr2, ..., exprn}
+
+the first three reserve one byte of memory for each operand and store the
+H.O (bits 8-15), bank (bits 16-23), or extra byte (bits 24-31) respectively.
+.HWORD reserves two bytes composed of bits 16-31 for each operand.
+
+
+Arrays:
+-------
+
+ Space for arrays and data tables can be reserved using the data
+declaration statement mentioned above in conjunction with the "DUP" operator.
+DUP is a binary operator that takes the form:
+
+  count DUP (list)
+
+where count is some constant value and list is a (possibly empty) list of
+values.  The items in (list) are repeated "count" times.  For example, the
+following .BYTE statement reserves space for an array of 64 bytes and
+initializes each byte to zero:
+
+ MyArray  .BYTE  64 DUP (0)
+
+The following statement reserves 256 bytes consisting of the values 1, 2, 3,
+4, 5, 6, 7, and 8 repeated 32 times:
+
+ MyArray  .BYTE  32 DUP (1,2,3,4,5,6,7,8)
+
+
+ The DUP operator is fully recursive.  That is, one of the items in
+the list may, itself, be a list defined by the DUP operator.  For example,
+
+ Example  .BYTE  16 DUP (0,1,2 DUP (3,4,5))
+
+reserves 128 bytes consisting of the list "0,1,3,4,5,3,4,5" repeated 16 times.
+
+ If the DUP list is empty,  e.g., "16 dup ()", then exactly one item
+is reserved for each entry, but it is not initialized.  The following example
+reserves space for 128 uninitialized words:
+
+ OffsetTable .WORD  128 DUP ()
+
+
+
+
+Type definitions:
+-----------------
+
+ Enumerated data types can be declared with the ".TYPE" directive.
+This directive takes the form:
+
+ {label}  .TYPE  item1 {,item2, ..., itemn}
+
+The items in the list are assigned consecutive values starting from zero.
+For example, in the following .TYPE statement, the symbols red, green, and
+blue are assigned the values zero, one, and two, respectively:
+
+ colors  .TYPE  red,green,blue
+
+The symbols in the operand field of a .TYPE statement must be unique and
+undefined elsewhere (within the current scope, more on that later).  The
+.TYPE statement above is almost identical to the statements:
+
+  red .con 0
+  green .con 1
+  blue .con 2
+
+However, there is one major difference.  The .TYPE statement also defines a
+symbol specified in the label field.  This symbol can be used as a pseudo-
+opcode to reserve space for values of the specified type.  In the example
+above, "colors" could be used as a pseudo-opcode to reserve space for the
+values red, green, and blue.  To differentiate type declarations from other
+instructions, a special lead-in character is used.  The slash ("/") is
+recommended by this standard, but the user should have the option of choosing
+this character via a setup program for the assembler.  From the example
+above, colors could be used as a pseudo-opcode in the following manner:
+
+ Christmas /colors  red,green
+ Ocean  /colors  blue,green
+ Sky  /colors  blue
+   /colors  red
+ Primaries /colors  red,blue,green
+
+Unlike other data reserving pseudo-opcodes, a "/colors" definition only
+allows symbols that appear in the operand field of the associated .TYPE
+statement or one of those symbols in a expression that contains a single
+such symbol plus or minus a numeric constant, as long as the result is still
+within the range of symbols declared for that type.  E.g.,
+
+ Okay  /colors  red,green+1,blue
+ NotOkay1 /colors  blue+2  ;Outside allowable range
+ NotOkay2 /colors  red+blue ;can't add two such symbols
+ NotOkay3 /colors  $25  ;Not red, green, or blue
+
+If you need to coerce an expression to the proper form, simply use the type
+name as a pseudo-function.  E.g.,
+
+ ThisIsOkay /colors  colors(0),blue ;Same as red, blue
+
+If the operand is not appropriate, the assembler should generate a warning
+and emit the code as though the .BYTE statement were used.
+ 
+
+ If there isn't a label starting in column one of a .TYPE statement
+then the symbols defined in the operand field are applied to the previous
+.TYPE statement.  This allows you to create .TYPEs where several symbols
+(which couldn't possibly fit on a single line) are declared as constants.
+E.g.,
+
+ colors  .TYPE  red, yellow, blue
+   .TYPE  orange, green violet
+   .TYPE  brown, black, white
+
+All of these symbols will be associated with "colors".   A maximum of 256
+symbols can be associated with a symbol via the .TYPE statement.  Whenever
+the data reservation form is used, exactly one byte is reserved for each
+item in the operand field.  If you need to reserve more than a single byte
+for each item, use the record declarations described next.
+
+ The DUP operator can be used to define enumerated data type arrays,
+e.g.,
+
+ LotsOfRed /colors  16 DUP (red)
+
+
+
+ Another form of the .TYPE statement allows you to declare byte
+subrange values.  A definition of this type takes the form:
+
+ label  .TYPE start..stop
+
+where start and stop are constant values in the range 0..255 and 
+start <= stop.   Examples:
+
+ LessThan10 .TYPE 0..9
+ Nibbles  .TYPE 0..$F
+ PrimaryColors .TYPE red..blue   ;From above, is red, yellow, blue
+
+
+ Implementation of the .TYPE statement is required only at the full
+and extended compliance levels.
+
+
+
+Records:
+--------
+
+ A record data structure can be defined with the ".RECORD" and ".ENDR"
+directives using the syntax:
+
+ label .RECORD
+       <data declarations>
+  .ENDR
+
+This creates a template, but does not generate any code.  An example might
+be:
+
+ CursorPosn .RECORD
+ ROW  .BYTE 0
+ COLUMN  .BYTE 0
+   .ENDR
+
+This definition creates the type "CursorPosn".  Like the .TYPE definitions,
+the symbol defined by .RECORD can be used as a pseudo-opcode to reserve
+storage for a variable.  For example, to declare a variable of type
+"CursorPosn" the following statement is used:
+
+ MyCursor /CursorPosn
+
+This statement reserves two bytes, initialized to zeros, at the current
+location counter.
+
+ Access to the fields of the record is accomplished by using the
+"." operator, just like Pascal.   E.g.,
+
+   lda MyCursor.ROW ;Fetches first byte.
+   lda MyCursor.COLUMN ;Fetches the second byte.
+
+
+ In the example above, the ROW and COLUMN fields of each variable
+declared with CursorPosn are always initialized to zero.  Any other value
+could have been used by substituting the appropriate value, or an 
+indeterminate value could have been specified by the definition:
+
+ CursorPosn .RECORD
+ ROW  .BYTE
+ COLUMN  .BYTE
+   .ENDR
+
+
+ On occasion, you may want each record variable definition to
+specify the initial values.  This can be accomplished by specifying
+parameters in the record definition.  Parameters are specified by the
+symbols:  ?0, ?1, ..., ?9.  ?0 corresponds to the first parameter, ?1 to
+the second, etc.   Consider the following record and variable definitions:
+
+ CursorPosn .RECORD
+ ROW  .BYTE ?0
+ COLUMN  .BYTE ?1
+   .ENDR
+
+ HomePosn /CursorPosn 0,0
+ LowerRight /CursorPosn 23,79
+ MyCursor /CursorPosn 5,10
+
+
+ The only problem with this definition form is that each CursorPosn
+variable must supply exactly two operands.  Sometimes you may want to have
+a default value in the event an operand isn't specified.  This is accomplished
+using a record defintion of the form:
+
+ CursorPosn .RECORD ?0=0,?1=0
+ ROW  .BYTE ?0
+ COLUMN  .BYTE ?1
+   .ENDR
+
+This definition instructions the assembler to allow zero or more parameters,
+defaulting ?0 and ?1 to zero if their respective entries aren't present.
+The .DEFAULT directive can also be used, particularly if you run out of
+room on the .RECORD line:
+
+ OpenRec  .RECORD  ?0=0, ?1=1
+   .DEFAULT ?2=ZRO('Hello there'), ?3=2
+ FirstItem .WORD  ?0
+   .LONG  ?3
+ SecondItem .BYTE  ?1, ?2
+   .ENDR
+
+
+ Record definitions are required at the full and extended compliance
+levels, they are not required at the subset compliance level.
+
+
+
+Sets:
+-----
+
+ Bit string types can be declared using the .SET directive.  .SET is
+used in a manner quite similar to .TYPE except the items in the operand field
+can be any constant whose value is less than 32.  Up to 32 items may 
+appear in the operand field of a .SET definition.  The syntax is
+
+ label  .SET item1 {,item2, ..., itemn}  ;n <= 32.
+
+An alternate form is to specify the name of some type variable in the operand
+field.  The following definition creates a set of integers in the range
+0..9:
+
+ LessThan10 .TYPE 0..9
+ SetOfDigits .SET LessThan10
+
+
+ Declaring a set variable is quite similar to declaring an enumerated
+type variable or a record variable: simply use the set name as a pseudo-opcode
+prefaced by a "/":
+
+ Digits  /SetOfDigits
+
+
+ Set constants are specified by placing the items in the set within
+a pair of braces.  E.G.:
+
+ BitValues .TYPE  0..7
+ SetOfBitValues .SET  BitValues
+ Bits  /SetOfBitValues {0,1,2,3}
+ ;
+ ;
+   lda  #{0,2,7}
+   sta  Bits
+
+
+ The assembler, by default, should allow set constants composed of
+the integer values 0..31.  This allows programmers to easily deal with bits
+by bit numbers rather than the integers those bit patterns represent.  For
+example, to strip all but the H.O. two bits in the (8-bit) accumulator, the
+instruction "AND #{6,7}" makes a lot more sense than "AND #$C0".  All other
+entities appearing within "{" and "}" must appear somewhere in the operand
+field of a .SET statement (or must be a member of a .TYPE definition if that
+type appears in the operand field of a .SET).
+
+
+
+Macros:
+-------
+
+ Macros are created using the .MACRO and .ENDM directives.  The syntax
+for a macro definition is
+
+ label  .MACRO  {default parameter values}
+        <macro body>
+   .ENDM
+
+Macros are invoked by placing an underscore, followed by the macro name (the
+label in the .MACRO statement).  The user should be able to change the macro
+lead-in character from underscore to some other character via an assembler
+set up program.
+
+All labels declared within the macro are local to that definition unless the
+".GLOBAL" directive is used to extend their scope.  In general, global
+macro labels (except, possibly, those defined by "=") are not useful anyway
+since a duplicate label error might occur on the second invocation of the 
+macro.
+
+ The macro body consists of a sequence of assembler statements.  Most
+reasonable statements may be included in the macro body.  The standard does
+not required nested macro definitions.  Nor need the macro definitions allow
+.RECORD, .TYPE, or .SET definitions (since labels are local to the macro,
+such definitions are dubious anyway).
+ 
+ Macro parameters are specified using ?0, ?1, ..., ?9, just as for
+.RECORD definitions.  "?#" can be used to determine the actual number of
+parameters present.  "?:expr" can be used to select a parameter using a
+numeric expression.  For example, "?:?#-1" returns the value of the last
+parameter specified.  Default values for the parameters can be specified
+in the .MACRO operand field, or in a .DEFAULT statement, just like specifying
+default values for .RECORD parameters.  E.g.,
+
+  MyMacro .MACRO  ?0=0, ?1=2
+   .DEFAULT ?2="Hello there"
+   .BYTE  ?0
+   .WORD  ?1
+   .BYTE  ?2
+   .ENDM
+
+then:
+
+   _MyMacro 10,20
+
+generates the bytes:
+   10, 20, 0, Hello there
+
+
+ Macros, by the very nature, allow a variable number of parameters.
+If more parameters are specified than there are references for, the extra
+parameters are ignored.  If fewer parameters are specified than there are
+references for, the additional references will be treated as undefined
+symbols.  If you want to be able to force the user to enter an exact number
+of parameters, then use the ?# in the default field to specify a fixed number
+of parameters.  The following macro definition requires the user to enter
+exactly two parameters whenever TwoParms is invoked:
+
+ TwoParms .MACRO ?#=2
+   lda ?0
+   sta ?1
+   .ENDM
+
+If the number of parameters is fixed at a certain value, default values
+are not allowed in the macro definition.
+
+ Since macro parameters, in a macro invocation, are separated by
+commas, you cannot directly create a macro of the form:
+
+ LDAIX  .MACRO ?#=1
+   lda ?0
+   .ENDM
+
+and invoke it by:
+
+   _LDAIX LBL,X
+
+intending the "LDA LBL,X" instruction to be generated.  Instead, the macro
+mechanism will think that LBL and X are two different parameters and generate
+an error since only a single parameter is allowed.  The "<<" and ">>" symbols
+are used as an escape mechanism to parenthesize such operands.  To handle the
+case above, the following statement could be used:
+
+   _LDAIX <<LBL,X>>
+
+and this would generate the instruction "LDA LBL,X".
+
+ The lookup, value, type, and mode functions are quite useful for
+dealing with macro parameters.  The exact values returned by these functions
+will be described at a later time.
+
+ For additional information on macros and dealing with macro para-
+meters, see the sections on conditional assembly and while loops.
+
+ Macros are required only at the full and extended compliance levels.
+
+
+
+Address Expression Functions:
+-----------------------------
+
+ Format:
+
+  label .FUNC {default parameter values}
+        <function body>
+   .RETURN expr
+   .ENDF
+
+ The .FUNC statement lets programmers define their own address
+expression functions that can be used in operand fields of assembly language
+statements.  The function body typically contains a sequence of equates
+and other value computing statements;  it may not contain any code generating
+statements.
+
+ Like a macro definition, all symbols defined inside an address
+expression function are local to that function.  Likewise,  default parameters
+may be declared in the operand field of the .FUNC statement or via the
+.DEFAULT statement.  Alternately, you can specify that a fixed number of
+parameters are required by using the "?#=expr" item in the operand field
+of the .FUNC statement.
+
+ The expression following the .RETURN statement is the value returned
+by the addressing mode function.  Note that more than one .RETURN may appear
+within the function (perhaps within the confines of a conditional assembly
+sequence).  If more than one .RETURN statement is encountered, all but the
+last are ignored.  The expression returned in the .RETURN operand field may
+contain addressing modes in addition to the actual expression value.  In
+general, anything allowed as a macro parameter can be returned as an address
+expression value.
+
+ An address expression function is invoked by placing the function
+name in some other expression followed by the parameters enclosed within
+parentheses.  The parentheses are required even if the parameter list is
+empty (just like the "C" programming language).  Examples follow:
+
+ StripLONibble .FUNC ?#=1
+ value  = ?0 AND $F0
+   .RETURN value
+   .ENDF
+ ;
+ AppendTXT .FUNC ?#=1
+ string  = ?0 + ".TXT"
+   .RETURN string
+   .ENDF
+ ;
+    .
+    .
+    .
+   LDA #StripLONibble($FF)
+    .
+    .
+    .
+   .BYTE AppendTxt("MyString")
+
+The LDA instruction generates 
+
+   LDA #$F0,  
+
+the .BYTE statement becomes
+
+   .BYTE "MyString.TXT"
+
+The latter example demonstrates that address expression functions can
+return any valid type.  This includes strings, records, sets, and any
+other entity allowed in an operand field.  Consider the following:
+
+  LBLX .FUNC ?#=2
+  L = ?0-?1,X
+   .RETURN L
+   .ENDF
+
+   LDA LBLX($100,10)
+
+This generates the code:
+
+   LDA $100-10,X
+
+
+ Address expression functions are required only at the full and
+extended compliance levels.
+
+
+
+
+The Label Type
+--------------
+
+ The ".LABEL" directive is used to declare a valueless symbol, that is, one which
+is defined but is assigned no particular value.  The syntax for the .LABEL directive is:
+
+   .LABEL symbol1 {, symbol2, ..., symboln}
+
+Each symbol appearing in the operand field is inserted into the symbol table as a "label"
+typed symbol.
+
+ Label-typed symbols are useful mainly in macros and in the operand fields of
+conditional assembly statements.  The only operations you can perform using label-typed
+symbols are "=" and "<>".  Most of the reserved symbols in the assembler (such as A, X,
+Y, DBR, D, M, S, etc.) are actually label-typed symbols.
+
+ An example of where you might use a label-typed symbol follows:
+
+  CmpReg .MACRO ?#=2
+   .IF ?0=A
+   cmp ?1
+   .ELSE
+   .IF ?0=X
+   cpx ?1
+   .ELSE
+   .IF ?0=Y
+   cpy ?1
+   .ELSE
+   .PAUSE
+   .ENDIF
+   .ENDIF
+   .ENDIF
+   .ENDM
+
+ The "=" equate can also be used to defined label-typed symbols by specifying a
+label-typed symbol in the operand field, e.g.,
+
+  ACC = A
+  XReg = X
+   etc.
+
+Note that the last equate above does not allow you to enter indexed by X addressing modes as
+
+   <expression>,XReg
+
+it simply allows you to use a statement of the form:
+
+   .IF XReg=X
+
+and wind up assemblying the code after the ".IF".
+
+ The ".LABEL" directive is required at the full and extended compliance levels; it
+is not required at the subset compliance level.
+
+
+
+
+
+Procedures:
+-----------
+
+ At the full and extended compliance levels, the .PROC and .ENDP
+directives can be used to declare 65c816 procedures (subroutines).  Procedure
+declarations take the form:
+
+ procname .PROC {near|far}
+
+      <procedure body>
+
+   .ENDP
+
+If an operand appears after the .PROC statement, it must be either "near" or
+"far".  If no operand appears, "near" is assumed.
+
+ The  procedure name that appears in the label field of the .PROC
+statement is assigned the current value of the location counter at that
+point in the program.  It is also given the type of near procedure or
+far procedure, depending upon the .PROC operand field.
+
+ All labels defined inside a procedure are local to that  procedure
+unless the .GLOBAL directive is used to extend their scope beyond the
+procedure.  Therefore, labels inside one procedure may be reused outside
+that procedure.  If a label inside a procedure is already defined outside
+that procedure an error is not generated, instead the new label supercedes
+the old one INSIDE THE PROCEDURE (scoping rules are the same as for Pascal).
+Procedures may be nested inside one other, the scoping rules used by Pascal
+apply in such situations.
+
+ Inside the procedure, RET can be used in place of RTS or RTL.  The
+assembler will automatically choose the appropriate version depending upon
+whether the procedure is a near or far procedure.  If RTS is used inside a
+FAR procedure or RTL is used inside a NEAR procedure, the assembler will
+generate a warning.
+
+ The assembler automatically assembles JSR using the absolute or
+long addressing mode depending upon the procedure definition.  If the
+assembler supports the JSL mnemonic and a JSL is used to call a NEAR
+procedure, the assembler must generate an warning.  If the address expression
+following a JSR was coerced using the ":A" or ":L" suffixes, no warning will
+be generated if the incorrect distance was specified.  I.e., the following
+does NOT generate an error:
+
+   JSR mysub:L
+    .
+    .
+    .
+  mysub .PROC NEAR
+    .
+    .
+    .
+
+If you use a coercion operator, the assembler assumes that you know what
+you are doing.
+
+ Note that the use of the .PROC statement is optional.  You may con-
+tinue to build and call subroutines without the .PROC directive.  However,
+using .PROC allows the assembler to perform additional type checking on
+certain operations.  An external data flow analysis program can also use the
+procedure declarations to help locate logical bugs in your code.
+
+ .PROC and .ENDP are required at all compliance levels of the
+standard.
+
+
+
+
+
+Module Communication Directives:
+--------------------------------
+
+ Three directives, .GLOBAL, .PUBLIC, and .EXTERNAL, are used to
+communicate symbolic values across procedure, segment, and module boundaries
+(a module is any one source file which is assembled as a whole unit).  The
+.GLOBAL directive is used to make symbols visible outside of procedures,
+macros, functions, and records.  The .PUBLIC directive is used to make
+certain symbols visible outside the current module.  The .EXTERNAL directive
+is used to make symbols defined outside the current module visible within
+the module.
+
+ The syntax for the .PUBLIC and .GLOBAL directives is identical, it
+takes the form:
+
+   .PUBLIC  symbol1 {,symbol2, ..., symboln}
+and,   .GLOBAL  symbol1 {,symbol2, ..., symboln}
+
+A label is not allowed in the label field of either mnemonic.  The symbols
+specified in the operand field of these two instructions are made known
+outside the procedure or module where they currently reside.  If a procedure
+is nested inside another, the .GLOBAL statement makes its symbols known
+only to the procedure encompassing the nested procedure.  In the following
+example, LCL is known only inside procedure X1 and X2, not to the whole
+program:
+
+  X1 .PROC
+     .
+     .
+  X2 .PROC
+   .GLOBAL LCL
+     .
+     .
+   .ENDP
+   .ENDP
+
+If you wanted to make LCL visible at the level above X1, then another
+.GLOBAL statement must appear inside the X1 procedure declaring LCL to
+be global to that procedure.
+
+ Another alternative is to use the .PUBLIC statement.  Any symbol
+declared public with .PUBLIC is instantly visible throughout the program
+(within the confines of the scoping rules).  However, keep in mind that
+symbols declared as public are visible outside the current module as well
+and may intefere with other modules.
+
+ The .EXTERNAL directive is used to obtain access to symbols declared
+outside the current module.  The syntax for the .EXTERNAL directive is:
+
+  .EXTERNAL  symbol1:type {,symbol2:type, ..., symboln:type}
+
+Again, no label is allowed in the label field of the .EXTERNAL directive.
+The type item is any of NEAR, FAR, CONST, DIRECT, ABS, or LONG.  
+
+ Note: symbols declared with "=", .MACRO, .RECORD, .SET, and .TYPE
+may not appear as operands to the .GLOBAL, .PUBLIC, or .EXTERNAL directives.
+
+ These directives are not required at the subset compliance level,
+only at the full and extended levels.
+
+
+
+
+Segments:
+---------
+
+ Segments are used to group a collection of logically and physically
+related entities within a program.  A segment may contain the program code,
+variables, stack area, direct page area, or other such data.  Typically
+a segment is a load module.  That is, a segment is loaded as a whole into
+memory.  If a program consists of two or more segments, they need not all
+reside in memory at the same time.  The memory manager/loader may load
+segments as needed into memory.
+
+ Segment definitions are required at all compliance levels.  All
+programs must consist of at least one segment (this is a source of minor
+incompatibility with existing assemblers).  The most general form of the
+segment definition is:
+
+ label .SEGMENT TYPE=expr {,ALIGN=expr} {,ORG=expr} {,NOCODE}
+
+       <segment body>
+
+  .ENDS
+
+
+.SEGMENT lets you declare any general type of segment.  The symbol in the
+label field need not be unique, but if it is redefined elsewhere within the
+current scope, it must appear on a .SEGMENT definition whose type is exactly
+the same as the current definition.
+
+ Unlike .PROCs, .MACROs, etc.,  symbols defined inside a segment are
+not local to the segment, but are instantly visible to the reset of the
+module.  If you need to declare local variables within a segment, use the
+.LOCAL and .RELEASE directives.
+
+ The type of segment must be specified in the .SEGMENT operand field.
+The actual segment types will be defined at a later date.  For now, assume 
+the types used by the Apple //GS loader are specified after the TYPE= item.
+The segment type describes the attributes of the segment, attributes such
+as whether the segment is relocatable or absolute, fixed or movable, etc.
+
+ The optional ALIGN operand is used to determine some number of bytes
+to which this segment (portion) must be aligned.  If ALIGN=1 , the segment
+will be aligned on any byte boundary.  If ALIGN=2 then the segment will be
+aligned on a word boundary, etc.  Any value between 1 and $10000 can be used
+(ALIGN=$10000 will align the segment on a bank boundary).
+
+ The ORG=expr option can be used to fix the starting address of the
+segment.  This option isn't normally used with code-generating segments.
+It's mainly used to define I/O port addresses and other absolute variables.
+
+ The NOCODE option is used to declare that a segment will not generate
+any code (i.e., it's just used to declare variables).  If any 65c816 instruct-
+ion appears in a NOCODE segment, an error will be generated.  All data
+declaring pseudo-opcodes (e.g., .BYTE) must specify indeterminate values else
+an error will be reported.
+
+ If multiple segments with the same name appear in a module (or
+across modules, for that matter), they will be combined into a single,
+contiguous module by the assembler and/or linker.  Consider the following:
+
+ MyCode  .SEGMENT Type=$1AF
+      .
+      .
+      .
+   .ENDS
+ ;
+ MyData  .SEGMENT Type=$100
+      .
+      .
+      .
+   .ENDS
+ ;
+ MyCode  .SEGMENT Type=$1AF
+      .
+      .
+      .
+   .ENDS
+
+
+Although MyCode appears in two completely disjoint areas, the assembler/linker
+will combine these items into a single segment.  Segments appear in the
+load module in the order they are declared in the source file.  In the
+example above,  segment MyCode appears before segment MyData (even though
+a portion of MyCode appears after MyData, MyCode was still declared before
+MyData).
+
+ Segments may be nested, but they don't follow any scoping rules.
+Declaring one segment inside another is no different that declaring those
+two segments completely separate.
+
+ If you have two separate segments (different names but the same
+type), you can combine them together using the .GROUP directive.  This
+directive takes the form
+
+ label .GROUP seg1, seg2 {,seg3, ..., segn}
+
+Referring to "label" refers to the segment obtained by combining the
+segments in the .GROUP operand field.
+
+ To simply segment usage, there are six predeclared segments.  They
+may be declared with the directives:
+
+  .CODE .DATA .DIRECT
+  .STACK .VAR .CONST
+
+.CODE is used to declare static, code-generating segments which allow
+65c816 instructions.  .DATA is used to declare static data-generating
+segments.  .CONST is identical to .DATA except data items inside the
+.CONST directive are read-only.  Any attempt to write to items inside a
+.CONST segment should generate an error by the assembler or data flow
+analysis programs.  .DIRECT is used to declare segments containing direct
+page variables.  This is a NOCODE segment, so only definitions are allowed,
+initial values are illegal.  .STACK segments are also NOCODE segments.  They
+are useful for declaring stack space down in bank zero.  The .VAR segment
+is used like the .DATA segment, except .VAR segments are NOCODE segments.
+They are used for declaring unintialized variables in main RAM.
+
+ The syntax for these six directives is
+
+ label .xxxx {ALIGN=expr | ORG=expr}
+
+       <segment body>
+
+  .ENDS
+
+
+
+
+The ASSUME Directive
+--------------------
+
+ With the addition of the bank registers and the mode bits in the
+65c816 processor, an assembler can no longer determine the proper addressing
+mode to use in all circumstances without help from the programmer.  For
+example, if the assembler encounters an instruction of the form "LDA Label"
+and Label is a statement label inside some segment (i.e., not declared with
+EDP, EQU, EQL, or other type-defining directive), it has no idea whether to
+use the direct, absolute, or long addressing mode.  To do so would require
+that the assembler know the current values of the direct page and data bank
+registers at assembly time.  Frankly, it is not possible for the assembler
+to always know the content of these registers, hence the programmer must
+manually supply this information to the assembler.  This information, as well
+as some other useful information, is supplied to the assembler via the
+.ASSUME directive.
+
+ The .ASSUME directive uses the syntax:
+
+   .ASSUME operand1 {,operand2, ..., operandn}
+
+where operand(i) is one of the following:
+
+ DBR:expression24
+ DBR:NOTHING
+ DP:expression16
+ DP:NOTHING
+ M:expression1
+ M:NOTHING
+ X:expression1
+ X:NOTHING
+ CPU:cpu_type
+
+where expression24 is an expression yielding a 24-bit value, expression16 is
+an expression yielding a 16-bit value, expression1 is an expression yielding
+zero or one, NOTHING is a reserved word, and cpu_type is one of {6502, 65c02,
+65802, 65816} or one of the later versions of the 65c816 microprocessor.
+
+ DP (direct page) is used to let the assembler know where the direct
+page register is pointing.  If a segment name is given as the expression,
+that segment must be one that resides in bank zero and is of type DIRECT.
+If the assembler encounters a symbol declared in a segment that is assumed
+to be a direct page segment via the DP:expression operand, the assembler will
+reference that location using the direct page addressing mode (if posssible).
+If the "DP:NOTHING" form is used, the assembler will only use the direct page
+addressing mode if a symbol was declared with the EDP equate.  None of the
+segments will be treated as direct page segments, even if they were declared
+as type DIRECT.  If you want to simultaneously refer to several segments as
+direct page segments, group them together using the .GROUP directive and
+specify the group name as the expression value after the DP:, i.e.,
+
+ DPGroup  .GROUP DPSeg1, DPSeg2, DPSeg3
+   .ASSUME DP:DPGroup
+
+By default, the assembler should assume DP:NOTHING.
+
+
+ DBR is used to tell the assembler which segment/bank the DBR (data 
+bank register) points at.  References to variables within that segment will
+be assembled as absolute references (unless that segment name is also
+specified after DP:expr, in which case the direct page addressing mode will
+be used, if possible).  If DBR:NOTHING is specified, absolute addressing will
+be used only for those symbols declared via EQU, all other references will
+be assumed to be long references.  Note that the H.O. eight bits of the
+24-bit expression are used.  Therefore, to set the DBR assumption to an
+absolute bank in memory, an expression of the form:
+
+   .ASSUME DBR:$200000 ;Assume DBR=$20
+
+must be used.  By default, the assembler should assume DBR:NOTHING.
+
+ Normally, a programmer should use "#" and "=" to specify eight or
+sixteen bit immediate operand sizes.  To help ensure upwards compatibility
+with existing source code, a mechanism has been added whereby the "#" is
+used and the .ASSUME directive controls the size of immediate operands.  This
+task is achieved using the M:expr and X:expr operands.  Normally the assembler
+defaults to M:NOTHING and X:NOTHING.  In this mode,  "#" specifies 8-bit
+immediate operands and "=" specifies 16-bit operands.  If the expression
+following the M or X is zero or one,  then any immediate operand containing
+an equal sign is flagged as an error and the "#" specifies an eight-bit
+operand if the expression was 1, a sixteen-bit operand if the expression was
+zero.  If the expression evaluates to any other value an error is generated.
+Note that M only affects accumulator and memory operations while X affects
+the index register operations.  It is perfectly permissible to have an
+.ASSUME of the form:
+
+   .ASSUME  M:NOTHING,X:1
+
+The "=" immediate specifier would be allowed for accumulator operations but
+not for X/Y index register operations.
+
+ To help ensure compatibility with the existing defacto standard,
+LONGI, LONGA, SHORTI, and SHORTA should be provided as built-in macros
+generating the appropriate .ASSUME statement.
+
+ The "CPU:cpu_type" operand to the .ASSUME statement lets users
+specify the exact 6500 family CPU they are using.  The effect of this
+operand is to "disconnect" certain instructions.  If a certain CPU is
+specified and a programmer uses an addressing mode or instruction which isn't
+available on that CPU, the assembler will generate an error.  By default,
+the assembler should assume the CPU of the machine on which the assembler
+is intended to run (e.g., 65c816 for Apple //GS machines).  If the assembler
+is running on a different processor other than a 6500 family chip, it should
+default to 65c816.  The user should be able to choose this default value
+from an assembler set-up program.
+
+ The .ASSUME directive, and all operands available to it, must be
+supported at all compliance levels.
+
+
+
+Local Symbols
+-------------
+
+ In addition to local labels automatically specified inside procedures,
+macros, and expression functions, you can also explicitly declare local sym-
+bols within the source file.  User-defined local symbols come in two
+varieties: numeric and symbolic.
+
+ Up to 10 active numeric local labels can be specified at any given
+time.  The numeric local labels are similar to those used by D. E. Knuth
+in "The Art of Computer Programming, Vol 1", although the syntax is different.
+Numeric local labels are declared by placing a caret (up-arrow) in front of
+a single decimal digit in the label field.  Examples follow:
+
+  ^0 LDX #05
+  ^9 DEX
+  ^4 LDA LBL
+
+Numeric local labels are referenced with the ">n" and "<n" items, where "n"
+represents a single decimal digit.  If the greater than symbol prefaces a
+digit, then the next occurrence of that numeric local label in the source
+file is referenced.  If a less than ("<") symbol is used, then the previous
+numeric local label is used.  Examples:
+
+
+   LDX #5
+  ^0 CLR Array,X
+   DEX
+   BPL <0   ;References 2nd line above.
+  ;
+   LDA Array+2
+   bne >0  ;References ^0 below.
+   TXA
+  ^0 STA Array+1
+
+Note that multiple occurrences of the same numeric local label may appear
+within the program.  The are differentiated by the "<" and ">" symbols.
+
+ Since "<" and ">" may appear both as operators and as the beginning
+of an operand, a minor ambiguity results.  If you see a portion of an ex-
+pression like ">0",  does it mean  'is some value greater than zero' or does
+it refer to the next occurrence of "^0"?  This is easily handled from context.
+If the ">" or "<" appears where an operator is expected, then the appropriate
+operation is performed.  If they appear where an operand is expected and they
+are followed by a single decimal digit, then they are used as lead-ins for
+numeric local labels.  Otherwise an error must be generated.
+
+ Numeric local labels are great for those cases where you need to
+perform a short branch or to set up a small loop and you don't want to use
+meaningless mnemonics like "loop1",  "SkipInstr12", etc.  Other times, you
+may want to use a meaningful name like "MainLoop" or "ElseQuit", without
+having to worry about conflicts in other parts of the program.  Such cases
+are easily handled by the symbolic local label facility specified by this
+proposal.  Two assembler directives: .LOCAL and .RELEASE are used to define
+the scope of user-specified local labels.  The syntax for these two directives
+is identical, it is:
+
+   .LOCAL label1  {,label2, ..., labeln}
+   .RELEASE label1 {,label2, ..., labeln}
+
+A label defined with .LOCAL is confined to the scope of the .LOCAL/.RELEASE
+pair.   .LOCAL/.RELEASE pairs may be nested allowing you to redefine a symbol
+to any reasonable depth (say, a minimum of 8 levels).
+
+ Numeric local labels are required at all compliance levels.  Symbolic
+local labels are required at the full and extended compliance levels.
+
+
+
+Conditional Assembly
+--------------------
+
+ Conditional assembly is handled by the  .IF, .ELSE, .IF1, .IF2,
+.IFDEF,  .IFNDEF, and .ENDIF directives.  .IF is followed by a numeric
+address expression that yields a zero (false) or non-zero (true) result.
+The following code (up to the .ELSE or .ENDIF) is assembled if the result is
+true.  Otherwise the code after the .ELSE (if it is present) is assembled in
+its stead.   .IF1 and .IF2 assemble their respective code during passes
+one and two.  .IFDEF and .IFNDEF accept a single symbol as their parameter
+and test whether or not this symbol is currently defined.   The .ELSE
+directive can be used to assemble additional code in the event the tested
+condition is false.  Finally, the .ENDIF directive is used to terminate
+a conditional assembly sequence.
+
+ Conditional assembly blocks can be nested to at least eight levels,
+preferably more.  Since all conditional assembly blocks are terminated with
+.ENDIF, there is no need to worry about matching .ELSEs as you would, say,
+in Pascal.  Every form of the IF statement is terminated with its own .ENDIF.
+
+ The .IF1 and .IF2 directives are normally used to print messages and
+perform other minor housekeeping chores.  In general, there's absolutely no
+reason why anyone would want to generate code inside one of these conditional
+assembly blocks.  Therefore, the assembler may optionally generate an error
+message if the location counter is modified anywhere inside the .IF1/.IF2
+conditional assembly block.
+
+ .IF, .ELSE, and .ENDIF are required at all compliance levels.  .IF1,
+.IF2, .IFDEF, and .IFNDEF are required only at the full and extended com-
+pliance levels.
+
+
+
+While Loops
+-----------
+
+ Sometimes, especially within macros, you will need some sort of
+looping structure to process parameters or otherwise generate sequences of
+code;  the .WHILE/.ENDW directives are used for this purpose.  The syntax
+for the while section is:
+
+   .WHILE expression
+      <body of loop>
+   .ENDW
+
+The instructions in the loop body are repeated as long as the expression
+yields a non-zero value.  For the loop to terminate, the variable(s)
+controlling the loop must be defined using the "=" assembler directive
+since this is the only directive that allows you to redefine an instance
+of a variable.
+
+ The .WHILE directive is especially useful for  processing a macro
+(or record definition) with a variable number of parameters.  Consider the
+following macro:
+
+ ByteTable .MACRO
+ ParmCnt  = ?#
+   .WHILE ParmCnt
+   .BYTE ?:(?#-ParmCnt)
+ ParmCnt  = ParmCnt-1
+   .ENDW
+   .ENDM
+
+   _ByteTable  0,5,4,2,7
+
+This example emits the five bytes  0, 5, 4, 2, and 7 into the object code
+stream.
+
+INCLUDE Mechanism
+-----------------
+
+ A source file include mechanism is provided by the .INCLUDE directive.
+Its syntax is
+
+   .INCLUDE "filename"
+
+The specified file will be inserted at the point of the .INCLUDE directive
+in the current assembly, as though the code were actually inserted at that
+point.
+
+ The include mechanism must be capable of nested includes up to four
+levels deep.  The .INCLUDE directive must be supported at all compliance
+levels of the assembler, although assemblers operating at the subset
+compliance level need not support nested include files.
+
+
+
+
+Programs, Modules, and Units
+----------------------------
+
+ The assembler handles three types of sources files: programs, modules,
+and units.  Unless otherwise specified, all source files are assumed to be
+programs.  A program is differentiated from a module or unit in that the
+assembler/linker assumes that control is transferred to some point in a
+'program' when it is loaded into memory.  Modules and units are assumed to
+be subserviant sections of code that contain data and/or code used by
+programs.
+
+ By default, a piece of code is assumed to be a program and control
+is transferred to the first byte of that code when the program is loaded
+into memory.  This helps improve compatibility with existing source files.
+The .PROGRAM directive can be used to explicitly declare a piece of code as
+a main program, as well as provide an entry address other than the first byte
+of code emitted.  The syntax for the .PROGRAM directive is
+
+   .PROGRAM label
+
+where "label" is a program statement label somewhere within the current
+assembly.  The address of this label is passed on to the linker/loader where
+it will be used to provide a starting address for the code.   All of the
+statements in the source file will be assembled into the program from the
+.PROGRAM directive till the .END directive.  If a .PROGRAM directive appears
+in the source file, it must appear before any other statement (other than a
+comment or listing directive) and there may only be one .PROGRAM directive
+encountered per assembly.  No modules or units may appear as part of a
+program assembly (see below).
+
+ The .MODULE directive is used to tell the assembler that it is
+assemblying an object code module which is to be linked into a separate
+program before execution.   The .PUBLIC statement is used as the means
+to communicate linkage information to other modules, units, and programs.
+Like the .PROGRAM directive,  the .MODULE directive must appear before most
+statements in the source file and the module is terminated with the .END
+directive.  However,  another module may appear in the source file immediately
+after the .END directive.  Such modules are assembled as independent entries
+in a library.  The syntax for the .MODULE directive is:
+
+   .MODULE  ModuleName
+
+The module name operand is stored as part of the source file for use by the
+linker, but is not otherwise refereced during the assembly process.  In fact,
+this symbol may be redefined later in the source file.
+
+ The .LINK directive can be used to link a module into another module,
+unit, or program at assembly time.  The syntax for this directive is:
+
+   .LINK  "filename",ModuleName
+
+where filename is the operating system name of the object code file or
+library file containing the module, and ModuleName is the actual module
+name specified with the .MODULE directive.  The specified object code is
+inserted into the assembly at the point of the .LINK directive.  Access to
+the symbols declared public within the module is accomplished using the
+.EXTERNAL directive.
+
+ Units are a much more structured form of modules.  With a unit,
+you specify not only the symbols visible to the code using the unit, but
+also how that data is used.  Units also allow you to pass type checking
+information so the assembler can check for possible logical errors during
+assembly.  Finally, as an added bonus, within units you can link in macros,
+records, types, symbols defined by "=", and other entities that cannot be
+handled by modules and the .PUBLIC/.EXTERNAL mechanism.
+
+ A unit takes the form:
+
+   .UNIT UnitName
+
+      <interface section>
+
+   .BEGIN
+
+      <implementation section>
+
+   .END
+
+Like .MODULEs, several units may appear in the source file by simply following
+the .END directive with the next unit definition.  In fact, .MODULEs and 
+.UNITs can be intermixed in the same source file.  If more than one module or
+unit appears in the source file, they will be assembled into different slots
+in the object file generated (i.e., a library file will be generated).
+
+ The interface section of a unit contains those items that will be
+public to the unit.  Equates, records, macros, types, sets, and any other
+non-code generating declaration can be used in the interface section (note:
+an exact list of items will be specified later).  Such definitions will be
+made available to the code that uses this unit as well as to the code in the
+implementation section.  In addition to such declarations, the interface
+section may also contain .PROC definitions and .ENTRY definitions.  The
+.PROC definitions simply contain the .PROC statement (which must also appear
+in the implementation section), the .ENTRY definition is used in lieu of the
+.PUBLIC directive and takes the form:
+
+  label .ENTRY {NEAR or FAR}
+
+An example of a simple unit might be:
+
+   .UNIT SimpleUnit
+  MyMac .macro
+   lda #0
+   sta ?0
+   .endm
+  ;
+  ClrSub .proc near
+  SetTrue .proc far
+  SetIt .entry far
+  ;
+   .BEGIN  ;Start implemenation section.
+  ;
+  ClrSub .proc near
+   _MyMac $11
+   ret
+   .endp
+  ;
+  SetTrue .proc far
+   lda #1
+  SetIt sta $23
+   ret
+   .endp
+   .end
+
+
+ To use the code defined in a unit, the ".USE" directive is used in
+a fashion not unlike the .LINK directive, namely,
+
+   .USE "filename",UnitName
+
+where filename is the operating system pathname and UnitName is the name
+specified in the operand field of the unit directive.  Whenever the .USE
+directive appears in a source file, the content of the implementation section
+will be listed if the source listing option is turned on.
+
+ Whenever the .USE or .LINK directives are employed, the corresponding 
+object code is always inserted into the assembly.  Therefore the assembler
+is performing double duty, it's acting as both the assembler and linker.
+With units, the assembler always performs the link operation.  With modules,
+you can defer the link operation to a separate linkage step, although there
+are only a few instances where this would be beneficial (for example, while
+creating libraries).
+
+ All of the program linkage directives are optional at the subset
+compliance level, but required at the full and extended levels.
+
+
+
+Listing Controls
+----------------
+
+ Several directives are used to control the appearence of the assem-
+bled source listing.  The exact format of the listing will be specified with-
+in this proposal (although at a later date).  The exact listing format must
+be adhered to so that symbolic debuggers can take advantage of an assembled
+source listing saved as a text file for use when stepping through a program.
+
+   .ON operands
+   .OFF operands
+
+ These two directives are used to turn certain listing options or
+or off.  Valid operands include  LIST, OBJ, MAC, and COND.  LIST controls
+whether or not the source file is listed and supercedes all other options.
+OBJ (if on) will force the assembler to display all bytes of object code
+emitted by an instruction, even if it takes more than one line to display it
+all;  if off, OBJ will only display the number of emitted object code bytes
+that fit on the current source line.  MAC controls macro expansions during
+the listing.  If off, only the macro name, not the expansion, will be dis-
+played.  COND controls the printing of statements in a false conditional or
+while loop section.
+
+ The .TITLE and .SUBTITLE directives let you assign titles and sub-
+titles to the source file.  The syntax for these directives is
+
+   .TITLE  "Title of source file"
+   .SUBTITLE "Subtitle for this section"
+
+The title is displayed at the top of each page and the subtitle is displayed
+immediately below the title.  .TITLE always forces a page eject, .SUBTITLE
+never does.
+
+ The .PAGE directive forces an immediate page ejection on the listing.
+It requires no operands.
+
+ The .PRINTF directive has the syntax:
+
+   .PRINTF "Control string" {,operands}
+
+It is used in a manner analogous to the PRINTF in the "C" programming
+language.  If expressions follow the control string, "%" modifiers in the
+control string specify their output format.  E.g.,
+
+   .PRINTF "Label = $%4h",Label
+
+would print
+
+   Label = $1234
+
+assuming the value associated with Label was $1234.
+
+
+ The .PAUSE directive can be used to force an assembly time error.
+It is useful mainly in macros, records, expression functions, etc. to force
+an error if an illegal condition (like bad number of parameters) occurs.
+
+ The listing control directives are required only at the full and
+extended compliance levels.
+
+
+
+Data Flow Analysis Directives
+-----------------------------
+
+ The following directives are quite useful to add-on debuggers and
+data flow analysis programs.  They are required only at the full and extended
+compliance levels:
+
+  label .table
+        <data table>
+   .endt
+
+For .table, the label is assigned the current value of the location counter
+and label is treated like a statement label.  .TABLE and .ENDT are otherwise
+ignored.
+
+  label .REF label1 {, label2, ..., labeln}
+
+This statement is ignored by the assembler.  The statement label, if present,
+is also ignored.
+
+
+
+Other Optional Goodies
+----------------------
+
+ The following are not required by this proposal, but should be
+provided nonetheless:
+
+   .system  "DOS command"
+
+.SYSTEM issues the specified command to the operating system.  This command
+is useful for deleteing files during assembly, changing directories, etc.
+
+
+
+
+
+Operation of the Assembler
+--------------------------
+
+ Given the structure of the assembler, there's no way it can accomplish
+its job in less than three passes without placing severe burdens on the
+user (I could provide you with a mathematical proof of this, but I don't want
+to bore you to death).  Therefore, the standard specifies that the assembler
+must use three (or more) passes to do its job.  During the first pass the
+assembler associates labels with segments (and groups of segments), determines
+whether or not those symbols are near or far, and performs other housekeeping
+chores fit for pass one.  Pass two of the assembler is equivalent to the
+traditional pass one of an assembler, it computes the values for all of the
+symbols in the program.  Pass three generates the actual object code.
+
+
+ 
+In Addition to the Assembler...
+-------------------------------
+
+ The standard should also include specifications for a run-time
+library to be provided with the assembler as well as a list of tools
+(e.g., debugger, linker, librarian, etc.) which must be provided with the
+product to meet the full compliance level.  I would like to propose the 
+following items in the run-time library:
+
+ TTY_IO: A set of routines to communicate with a text-based
+user console.  INIT, GETC, and PUTC are the basic routines.  These three
+routines are easily supported on any system supporting a user console.
+
+ TERMINAL_IO: A set of routines to communicate with a cursor-based
+terminal device.  Routines supported should include INIT, GETC, PUTC, GOTOXY,
+HOME, CLREOLN, and CLREOP.
+
+ CONSOLE_IO: A set of routines to communicate with a DMA-based video
+display device.  See the specifications for ANIX's CHARIO driver for the
+routines to be supplied with this library entry.
+
+ AUX_IO: A driver for a set of one or more serial communication ports.
+Routines should include INITA, SETUPA, GETA, PUTA, STATUSA.
+
+ PRT_IO: A driver for a set of one or more printer ports.  Routines
+should include INITP, SETUPP, PUTP, and STATUSP.
+
+ NET_IO: A driver for a set of one or more network ports.  Routines
+should include INITN, SETUPN, GETPacket, SendPacket, etc.
+
+ CLK_IO: A driver for a real time clock or clock-calendar unit.
+
+ FP: An IEEE floating point package for the 65c816 chip.
+
+ MATH: A set of integer math routines (multiply, divide, extended
+precision, etc.).
+
+ CONV: A set of conversion routines (binary -> decimal, etc.).
+
+ FILE_IO: A set of routines that interface to the host's operating
+system providing a common interface to various operating systems.
+
+ DVC_IO: A hardware independent device I/O package (allowing named
+devices which can be connected through a BIOS (like the AUX_IO and PRT_IO
+packages) to various hardware devices.
+
+ STD_IO: A set of routines to perform various I/O operations such
+as PRINT, PRINTF, SCANF, PUTI (integer), GETI, PUTH (hex), GETH, etc.
+
+ MEM_MGR: A set of memory management routines to efficiently allocate
+and deallocate memory.
+
+ 
+This is, by no means, an exhaustive list, but a quick sample of the types of
+routines that should be provided.
+
+ Apple //GS users may complain that many of these routines already
+exist within the confines of the Apple toolbox.  The intent, however, is to
+provide a set of useful routines that can be utilized on ANY 65c816 system
+so 65c816 code can be easily ported to systems other than the Apple //GS.
+

+ 515 - 0
files/docs/snes/65816/addrmode.txt

@@ -0,0 +1,515 @@
+
+G65SC802 and G65SC816
+Microprocessor Addressing modes
+
+The G65SC816 is capable of directly addressing 16 MBytes of memory.
+This address space has special significance within certain addressing
+modes, as follows:
+
+Reset and Interrupt Vectors
+The Reset and Interrupt vectors use the majority of the fixed addresses
+between 00FFE0 and 00FFFF.
+
+Stack
+The Native mode Stack address will always be within the range 000000 to
+00FFFF. In the Emulation mode, the Stack address range is 000100 to 0001FF.
+The following opcodes and addressing modes can increment or decrement beyond
+this range when accessing two or three bytes:
+JSL; JSR (a,x); PEA; PEI; PER; PHD; PLD; RTL; d,s; (d,s),y.
+
+Direct
+The Direct addressing modes are often used to access memory registers and
+pointers. The contents of the Direct Register (D) is added to the offset
+contained in the instruction operand to produce an address in the range 000000
+to 00FFFF. Note that in the Emulation mode, [Direct] and [Direct],y addressing
+modes and the PEI instruction will increment from 0000FE or 0000FF into the
+Stack area, even if D=0.
+
+Program Address Space
+The Program Bank register is not affected by the Relative, Relative Long,
+Absolute, Absolute Indirect, and Absolute Indexed Indirect addressing modes
+or by incrementing the Program Counter from FFFF. The only instructions that
+affect the Program Bank register are: RTI, RTL, JML, JSL, and JMP Absolute
+Long. Program code may exceed 64K bytes altough code segments may not span
+bank boundaries.
+
+Data Address Space
+The data address space is contiguous throughout the 16 MByte address space.
+Words, arrays, records, or any data structures may span 64K byte bank
+boundaries with no compromise in code efficiency. As a result, indexing from
+page FF in the G65SC802 may result in data accessed in page zero. The
+following addressing modes generate 24-bit effective addresses.
+
+	* Direct Indexed Indirect (d,x)
+	* Direct Indirect Indexed (d),y
+	* Direct Indirect (d)
+	* Direct Indirect Long [d]
+	* Direct Indirect Indexed Long [d],y
+	* Absolute
+	* Absolute,x
+	* Absolute,y
+	* Absolute long
+	* Absolute long indexed
+	* Stack Relative Indirect Indexed (d,s),y
+
+The following addressing mode descriptions provide additional detail as
+to how effective addresses are calculated.
+
+Twenty-four addressing modes are available for use with the G65SC802
+and G65SC816 microprocessors. The "long" addressing modes may be
+used with the G65SC802; however, the high byte of the address is not
+available to the hardware. Detailed descriptions of the 24 addressing
+modes are as follows:
+
+
+1. Immediate Addressing -- #
+The operand is the second byte (second and third bytes when in the 16-bit
+mode) of the instruction.
+
+
+2. Absolute -- a
+
+With Absolute addressing the second and third bytes of the instruction form
+the low-order 16 bits of the effective address. The Data Bank Register
+contains the high-order 8 bits of the operand address.
+
+                __________________________
+   Instruction: | opcode | addrl | addrh |
+		~~~~~~~~~~~~~~~~~~~~~~~~~~
+   Operand
+   Address:     |  DB    | addrh | addrl |
+
+
+
+3. Absolute Long -- al
+
+The second, third, and fourth byte of the instruction form the 24-bit
+effective address.
+
+                 __________________________________
+    Instruction: | opcode | addrl | addrh | baddr |
+                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+    Operand
+    Address:     |  baddr | addrh | addrl |
+
+
+4. Direct -- d
+
+The second byte of the instruction is added to the Direct Register
+(D) to form the effective address. An additional cycle is required
+when the Direct Register is not page aligned (DL not equal 0). The
+Bank register is always 0.
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          | Direct Register   |
+
+                         +         |  offset  |
+                          ---------------------
+    Operand
+    Address:     |  00    | effective address |
+
+
+5. Accumulator -- A
+This form of addressing always uses a single byte instruction. The
+operand is the Accumulator.
+
+
+6. Implied -- i
+
+Implied addressing uses a single byte instruction. The operand is implicitly
+defined by the instruction.
+
+
+7. Direct Indirect Indexed -- (d),y
+
+This address mode is often referred to as Indirect,Y. The second byte of the
+instruction is added to the Direct Register (D). The 16-bit contents of this
+memory location is then combined with the Data Bank register to form a 24-bit
+base address. The Y Index Register is added to the base address to form the
+effective address.
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          | Direct Register   |
+
+                         +         |  offset  |
+                          ---------------------
+                 |  00    |  direct address   |
+
+
+    then:
+                 |  00    | (direct address)  |
+
+               + |  DB    |
+                -------------------------------
+                 |         base address       |
+
+               +          |        |  Y Reg   |
+                 ------------------------------
+    Operand
+    Address:     |     effective address      |
+
+
+
+8. Direct Indirect Indexed Long -- [d],y
+
+With this addressing mode the 24-bit base address is pointed to by
+the sum of the second byte of the instruction and the Direct
+Register The effective address is this 24-bit base address plus the Y
+Index Register
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          | Direct Register   |
+
+                         +         |  offset  |
+                          ---------------------
+                 |  00    |  direct address   |
+
+
+    then:
+                 |       (direct address)     |
+
+               +          |        |  Y Reg   |
+                 ------------------------------
+    Operand
+    Address:     |     effective address      |
+
+
+
+9. Direct Indexed Indirect -- (d,x)
+
+This address mode is often referred to as Indirect X The second
+byte of the Instruction is added to the sum of the Direct Register
+and the X Index Register. The result points to the low-order 16 bits
+of the effective address. The Data Bank Register contains the high-
+order 8 bits of the effective address.
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          | Direct Register   |
+
+                         +         |  offset  |
+                          ---------------------
+                          |  direct address   |
+
+                        + |        |  X Reg   |
+                          ---------------------
+                 |  00    |      address      |
+
+
+    then:
+                 |  00    |     (address)     |
+
+               + |  DB    |
+                -------------------------------
+    Operand
+    Address:     |     effective address      |
+
+
+
+10. Direct Indexed With X -- d,x
+
+The second byte of the instruction is added to the sum of the Direct Register
+and the X Index Register to form the 16-bit effective address. The operand is
+always in Bank 0.
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          | Direct Register   |
+
+                         +         |  offset  |
+                          ---------------------
+                          |  direct address   |
+
+                        + |        |  X Reg   |
+                -------------------------------
+    Operand
+    Address:     |  00    | effective address |
+
+
+
+11. Direct Indexed With Y -- d,y
+
+The second byte of the instruction is added to the sum of the Direct Register
+and the Y Index Register to form the 16-bit effective address. The operand is
+always in Bank 0.
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          | Direct Register   |
+
+                         +         |  offset  |
+                          ---------------------
+                          |  direct address   |
+
+                        + |        |  Y Reg   |
+                -------------------------------
+    Operand
+    Address:     |  00    | effective address |
+
+
+
+12. Absolute Indexed With X -- a,x
+
+The second and third bytes of the instruction are added to the
+X Index Register to form the low-order 16 bits of the ef~ective ad-
+dress The Data Bank Register contains the high-order 8 bits of the
+effective address
+
+                 ____________________________
+    Instruction: | opcode | addrl  | addrh  |
+                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+                 |  DB    | addrrh | addrl  |
+
+                        + |        |  X Reg |
+                -------------------------------
+    Operand
+    Address:     |     effective address    |
+
+
+
+13. Absolute Indexed With Y -- a,y
+
+The second and third bytes of the instruction are added to the
+Y Index Register to form the low-order 16 bits of the eftective ad-
+dress The Data Bank Register contains the high-order 8 bits of tne
+effective address.
+
+                 ____________________________
+    Instruction: | opcode | addrl  | addrh  |
+                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+                 |  DB    | addrrh | addrl  |
+
+                        + |        |  Y Reg |
+                -------------------------------
+    Operand
+    Address:     |     effective address    |
+
+
+
+14. Absolute Long Indexed With X -- al,x
+
+The second third and fourth bytes ot the instruction form a 24-bit base
+address. The effective address is the sum of this 24-bit address and the
+X Index Register.
+
+                 ____________________________________
+    Instruction: | opcode | addrl  | addrh  | baddr |
+                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+                 |  baddr | addrrh | addrl  |
+
+                        + |        |  X Reg |
+                -------------------------------
+    Operand
+    Address:     |     effective address    |
+
+
+
+15. Program Counter Relative -- r
+
+This address mode referred to as Relative Addressing is used only with the
+Branch instructions. If the conditlon being tested is met, the second byte
+of the instruction is added to the Program Counter, which has been updated
+to point to the opcode of the next instruction. The offset is a signed 8-bit
+quantity in the range from -128 to 127 The Program Bank Register is not
+affected.
+
+
+16. Program Counter Relative Long -- rl
+
+This address mode referred to as Relative Long Addressing is used only with
+the Unconditional Branch Long instruction (BRL) and the Push Effective
+Relative instruction (PER). The second and third 2 bytes of the instruction
+are added to the Program Counter which has been updated to point to the opcode
+of the next instruction. With the branch instruction the Program Counter is
+loaded with the result With the Push Effective Relative instruction the result
+is stored on the stack. The offset and result are both an unsigned 16-bit
+quantity in the range 0 to 65535.
+
+
+17. Absolute Indirect -- (a)
+
+The second and third bytes of the instruction form an address to a pointer
+in Bank 0. The Program Counter is loaded with the first and second bytes at
+this pointer With the Jump Long (JML) instruction the Program Bank Register
+is loaded with the third byte of the pointer
+
+                 ____________________________
+    Instruction: | opcode | addrl  | addrh  |
+                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+                 |  baddr | addrrh | addrl  |
+
+
+    Indirect Address = |   00   | addrh  | addrl  |
+
+    New PC = (indirect address)
+
+ with JML:
+
+    New PC = (indirect address)
+
+    New PB = (indirect address +2)
+
+
+
+18. Direct Indirect -- (d)
+
+The second byte of the instruction is added to the Direct Register to form
+a pointer to the low-order 16 bits of the effective address. The Data Bank
+Register contains the high-order 8 bits of the effective address.
+
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          | Direct Register   |
+
+                         +         |  offset  |
+                          ---------------------
+                 |  00    |  direct address   |
+
+
+    then:
+                 |  00    | (direct address)  |
+
+               + |  DB    |
+                -------------------------------
+    Operand
+    Address:     |     effective address      |
+
+
+
+19. Direct Indirect Long -- [d]
+
+The second byte of the instruction is added to the Direct Register to form
+a pointer to the 24-bit effective address.
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          | Direct Register   |
+
+                         +         |  offset  |
+                          ---------------------
+                 |  00    |  direct address   |
+
+
+    then:
+                -------------------------------
+    Operand
+    Address:     |       (direct address)     |
+
+
+
+20. Absolute Indexed Indirect -- (a,x)
+
+The second and third bytes of the instruction are added to the X Index
+Register to form a 16-bit pointer in Bank 0. The contents of this pointer
+are loaded in the Program Counter. The Program Bank Register is not changed.
+
+                 ____________________________
+    Instruction: | opcode | addrl  | addrh  |
+                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+                          | addrrh | addrl  |
+
+                        + |        |  X Reg |
+                -------------------------------
+                 |  00    |    address      |
+
+    then:
+	PC = (address)
+
+
+
+21. Stack -- s
+
+Stack addressing refers to all instructions that push or pull data from the
+stack such as Push, Pull, Jump to Subroutine, Return from Subroutine,
+Interrupts, and Return from Interrupt. The bank address is always 0.
+Interrupt Vectors are always fetched from Bank 0.
+
+
+22. Stack Relative -- d,s
+
+The low-order 16 bits of the effective address is formed from the sum of the
+second byte of the instruction and the Stack Pointer. The high-order 8 bits
+of the effective address is always zero. The relative offset is an unsigned
+8-bit quantity in the range of 0 to 255.
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          |   Stack Pointer   |
+
+                         +         |  offset  |
+                          ---------------------
+                 |  00    | effective address |
+
+
+
+23. Stack Relative Indirect Indexed -- (d,s),y
+
+The second byte of the instruction is added to the Stack Pointer to form
+a pointer to the low-order 16-bit base address in Bank 0. The Data Bank
+Register contains the high-order 8 bits of the base address. The effective
+address is the sum of the 24-bit base address and the Y Index Register.
+
+                 ___________________
+    Instruction: | opcode | offset |
+                 ~~~~~~~~~~~~~~~~~~~
+                          |   Stack Pointer   |
+
+                         +         |  offset  |
+                          ---------------------
+                 |  00    |     S + offset    |
+
+
+    then:
+                          |     S + offset    |
+
+               + |  DB    |
+                -------------------------------
+                 |         base address       |
+
+               +          |        |  Y Reg   |
+                 ------------------------------
+    Operand
+    Address:     |     effective address      |
+
+
+
+24. Block Source Bank, Destination Bank -- xyc
+
+This addressing mode is used by the Block Move instructions.
+The second byte of the instruction contains the high-order 8 bits of the
+destination address.
+The Y Index Register contains the low-order 16 bits of the destination
+address. The third byte of the instruction contains the high-order 8 bits
+of the source address.
+The X Index Register contains the low-order 16 bits of the source address.
+The Accumulator contains one less than the number of bytes to move.
+The second byte of the block move instructions is also loaded into the Data
+Bank Register.
+
+                 ____________________________
+    Instruction: | opcode | dstbnk | srcbnk |
+                 ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+
+                   dstbnk  -> DB
+
+    Source Address:       | scrbnk |      X reg      |
+
+    Destination Address:  |   DB   |      Y reg      |
+
+
+       Increment (MVN) or decrement (MVP) X and Y.
+       Decrement A (if greaterthan zero) then PC-3 -> PC.
+

+ 823 - 0
files/docs/snes/65816/detailop.txt

@@ -0,0 +1,823 @@
+
+		Table 9. Detailed Instruction Operation
+
+  ADDRESS MODE
+		CYCLE /VP /ML VDA VPA	ADDRESS BUS	DATA BUS	R/W
+
+
+ 1 Immediate -- #
+  (LDY,CPY,CPX,LDX,ORA,AND,EOR,ADC,BIT,LDA,CMP,SBC,REP,SEP)
+  (14 Op Codes)
+  (2 and 3 bytes)			
+  (2 and 3 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	IDL		1
+		2a	1  1   0  1	PBR,PC+2	IDH		1
+
+
+
+ 2a Absolute -- a
+  (BIT,STY,STZ,LDY,CPY,CPX,STX,LDX,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+  (16 Op Codes)
+  (3 bytes)
+  (4 and 5 cycles)	
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+2	AAH		1
+		4	1  1   1  0	DBR,AA		Data Low	1/0
+	    (1) 4a	1  1   1  0	DBR,AA+1	Data High	1/0
+
+
+ 2b Absolute (R-M-W) -- a
+  (ASL,ROL,LSR,ROR,DEC,INC,TSB,TRB)
+  (8 Op Codes)
+  (3 bytes)
+  (6 and 8 cycles)
+
+		1	1  1   1  1	PBA,PC		Op Code		1  
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+2	AAH		1
+		4	1  0   1  0	DBR,AA		Data Low	1
+	    (1) 4a	1  0   1  0	DBR,AA+1	Data High	1
+	    (3) 5	1  0   0  0	DBR,AA+2	IO		1
+	    (1) 6a	1  0   1  0	DBR,AA+3	Data Hiqh	0
+		6	1  0   1  0	DBR,AA		Data Low	0
+
+	
+ 2c Absolute(JUMP) -- a
+  (JMP)(4C)
+  (1 Op Code)
+  (3 bytes)
+  (3 cycles)
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	NEW PCL		1
+		3	1  1   0  1	PBR,PC+2	NEW PCH		1
+		1	1  1   1  1	PBR,NEWPC	New Op Code	1
+
+
+ 2d Absolute (Jump to subroutine) -- a
+  (JSR)
+  (1 Op Code)
+  (3 bytes)
+  (6 cycles)
+  (different order from N6502)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBA,PC+1	NEW FCC		1
+		3	1  1   0  1	PBR,PC+2	NEW PCH		1
+		4	1  1   0  0	PBR,PC+2	IO		1
+		5	1  1   1  0	0,S		PCH		0
+		6	1  1   1  0	0,S-1		PCL		0
+		1	1  1   1  1	PBA,NEWPC	New Op Code	1
+
+
+
+ 3a Absolute Long -- al
+  (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+  (8 Op Codes)
+  (4 bytes)
+  (5 and 6 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+2	AAH		1
+		4	1  1   0  1	PBR,PC+3	AAB		1
+		5	1  1   1  0	AAB,AA		Data Low	1/0
+	    (1) 5a	1  1   1  0	AAB,AA+1	Data High	1/0
+
+
+ 3b Absolute Long (JUMP) -- al
+  (JMP)
+  (1 Op Code)
+  (4 bytes)
+  (4 cycles)
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	NEW PCL		1
+		3	1  1   0  1	PBR,PC+2	NEW PCH		1
+		4	1  1   0  1	PBR,PC+3	NEW BR		1
+		1	1  1   1  1	NEW PBR,PC	New Op Code	1
+
+
+ 3c Absolute Long (Jump to Subroutine Long) -- al
+  (JSL)
+  (1 Op Code)
+  (4 bytes)
+  (7 cycles)
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	NEW PCL		1
+		3	1  1   0  1	PBR,PC+2	NEW PCH		1
+		4	1  1   1  0	0,S		PBR		0
+		5	1  1   0  0	0,S		IO		1
+		6	1  1   0  1	PBR,PC+3	NEW PBR		1
+		7	1  1   1  0	0,S-1		PCH		0
+		8	1  1   1  0	0,S-2		FCL		0
+		1	1  1   1  1	NEW PBR,PC	New Op Code	1
+
+
+
+ 4a Direct -- d
+  (BIT,STZ,STY,LDY,CPY,CPX,STX,LDX,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+  (16 Op Codes)
+  (2 bytes)
+  (3,4 and 5 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+2	IO		1 
+		3	1  1   1  0	0,D+DO		Data Low	1/0
+	    (1) 3a	1  1   1  0	0,D+DO+1	Data High	1/0
+
+
+ 4b Direct (R-M-W) -- d
+   (ASL,ROL,LSR,ROR,DEC,INC,TSB,TRB)
+   (8 Op Codes)
+   (2 bytes)
+   (5,6,7 and 8 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 3a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  0   1  0	0,D+DO		Data Low	1
+	    (1) 3a	1  0   1  0	0,D+DO+1	Data High	1
+	    (3) 4	1  0   0  0	0,D+DO+1	IO		1
+	    (1) 5a	1  0   1  0	0,D+D0+1	Data High	0
+		5	1  0   1  0	0,D+DO		Data Low	0
+
+
+
+ 5 Accumurator -- A
+   (ASL,INC,ROL,DEC,LSR,ROR)
+   (6 Op Codes)		
+   (1 byte)
+   (2 cycles)
+
+		1	1  1   1  1	PBR,PC		Op COde		1
+		2	1  1   0  0	PBR,PC+1	IO		1
+
+
+	
+ 6a Implied -- i
+   (DEY,INY,INX,DEX,NOP,XCE,TYA,TAY,TXA,TXS,TAX,TSX,TCS,TSC,TCD,TDC,
+    TXY,TYX,CLC,SEC,CLI,SEI,CLV,CLD,SED)
+   (25 Op Codes)
+   (1 byte)
+   (2 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  0	PBR,PC+1	IO		1
+
+
+ *6b Implied -- i
+   (XBA)
+   (1 Op Code)
+   (1 byte)
+   (3 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+
+
+
+  ADDRESS MODE
+		CYCLE /VP /ML VDA VPA RDY	ADDRESS BUS DATA BUS	R/W
+
+
+ 6c Wait for Interrupt		
+   (WAI)
+   (1 Op Code)
+   (1 byte)
+   (3 cycles)
+
+		1	1  1   1   1   1	PBR,PC	  Op Code	1
+	    (9) 2	1  1   0   0   1	PBR,PC+1  IO		1
+		3	1  1   0   0   0	PBR,PC+1  IO		1
+	IRQ,NMI	1	1  1   1   1   1	PBR,PC+1  IRO(BRK)	1
+
+
+ 6d Stop-The-Clock
+   (STP)
+   (1 Op Code)
+   (1 byte)
+   (3 cycles)
+
+		1	1  1   1   1   1	PBR,PC	  Op Code	1
+		2	1  1   0   0   1	PBR,PC+1  IO		1
+	RES=1	3	1  1   0   0   1	PBR,PC+1  IO		1
+	RES=0	1c	1  1   0   0   1	PBR,PC+1  RES(BRK)	1
+	RES=0	1b	1  1   0   0   1	PBR,PC+1  RES(BRK)	1
+	RES=1	1a	1  1   0   0   1	PBR,PC+1  RES(BRK)	1
+		1	1  1   1   1   1	PBR,PC+1  BEGIN		1
+
+   See 21a Stack (Hardware interrupt)
+
+
+
+  ADDRESS MODE
+		CYCLE /VP /ML VDA VPA	ADDRESS BUS	DATA BUS	R/W
+
+ 7 Direct Indirect Indexed -- (d),y
+   (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+   (8 Op Codes)
+   (2 bytes)
+   (5,6,7 and 8 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   1  0	0,D+DO		AAL		1
+		4	1  1   1  0	0,D+DO+1	AAH		1
+	    (4) 4a	1  1   0  0	DBR,AAH,AAL+YL	IO		1
+		5	1  1   1  0	DBR,AA+Y	Data Low	1/0
+	    (1) 5a	1  1   1  1	DBR,AA+Y+1	Data High	1/0
+
+
+
+ 8 Direct Indirect Indexed Long -- [d],y
+  (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+   (8 Op Codes)
+   (2 bytes)
+   (6,7 and 8 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   1  0	0,D+DO		AAL		1
+		4	1  1   1  0	0,D+DO+1	AAH		1
+		5	1  1   1  0	0,D+DO+2	AAB		1
+		6	1  1   1  0	AAB,AA+Y	Data Low	1/0
+	    (1) 6a	1  1   1  0	AAB,AA+Y+1	Data High	1/0
+
+
+
+ 9 Direct Indexed Indirect -- (d,x)
+   (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+   (8 Op Codes)
+   (2 bytes)
+   (6,7 and 8 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+		a	1  1   1  0	0,D+DO+X	AAL		1
+		5	1  1   1  0	0,D+DO+X+1	AAH		1
+		6	1  1   1  0	DBR,AA		Data Low	1/0
+	    (1) 6a	1  1   1  0	DBR,AA+1	Data High	1/0
+
+
+
+ 10a Direct,X -- d,x
+   (BIT,STZ,STY,LDY,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+   (12 Op Codes)
+   (2 bytes)
+   (4,5 and 6 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+		4	1  1   1  0	0,D+DO+X	Data Low	1/0
+	    (1) 4a	1  1   1  0	0,D+DO+X+1	Data High	1/0
+
+
+ 10b Direct,X (R-M-W) -- d,x
+   (ASL,ROL,LSR,ROR,DEC,INC)
+   (6 Op Codes)
+   (2 bytes)
+   (6,7,8 and 9 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+		4	1  0   1  0	0,D+DO+X	Data Low	1
+	    (1) 4a	1  0   1  0	0,D+DO+X+1	Data High	1
+	    (3) 5	1  0   0  0	0,D+DO+X+1	IO		1
+	    (1) 6a	1  0   1  0	0,D+DO+X+1	Data High	0
+		6	1  0   1  0	0,D+DO+X	Data Low	0
+
+
+
+ 11 Direct,Y -- d,y
+   (STX,LDX)
+   (2 Op Codes)
+   (2 bytes)
+   (4,5 and 6 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+		4	1  1   1  0	0,D+DO+Y	Data Low	1/0
+	    (1) 4a	1  1   1  0	0,D+DO+Y+1	Data High	1/0
+
+
+
+ 12a Absolute,X -- a,x
+   (BlT,LDY,STZ,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+   (11 Op Codes)
+   (3 bytes)
+   (4,5 and 6 cycles)
+
+		1	1  1   1  1	PBR,PC		Op code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+2	AAH		1
+	    (4) 3a	1  1   0  0	DBR,AAH,AAL+XL	IO		1
+		4	1  1   1  0	DBR,AA+X	Data Low	1/0
+	    (1) 4a	1  1   1  0	DBR,AA+X+1	Data High 	1/0
+
+
+ 12b Absolute,X (R-M-W) -- a,x
+   (ASC,ROL,LSR,ROR,DEC,INC)
+   (6 Op Codes)
+   (3 bytes)
+   (7 and 9 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+2	AAH		1
+		4	1  1   0  0	DBR,AAH,AAL+XL	IO		1
+		5	1  0   1  0	DBR,AA+X	Data Low	1
+	    (1) 5a	1  0   1  0	DBR,AA+X+1	Data High	1
+	    (3) 6	1  0   0  0	DBR,AA+X+1	lO		1
+	    (1) 7a	1  0   1  0	DBR,AA+X+1	Data High	0
+		7	1  0   1  0	DBR,AA+X	Data Low	0
+
+
+
+ *13 Absolute Long,X -- al,x
+   (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+   (8 Op Codes)
+   (4 bytes)
+   (5 and 6 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+7	AAH		1
+		4	1  1   0  1	PBA,PC+3	AAB		1
+		5	1  1   1  0	AAB,AA+X	Data Low	1/0
+	    (1) 5a	1  1   1  0	AAB,AA+X+1	Data High  	1/0
+
+
+
+ 14 Absolute,Y -- a,y
+   (LDX,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+   (9 Op Codes)
+   (3 bytes)
+   (4,5 and 6 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+2	AAH		1
+	    (4) 3a	1  1   0  0	DBR,AAH,AAL+YL	IO		1
+		4	1  1   1  0	DBR,AA+Y	Data Low	1/0
+	    (1) 4a	1  1   1  0	DBR,AA+Y+1	Data High	1/0
+
+
+
+ 15 Relative -- r
+   (BPL,BMI,BVC,BVS,BCC,BCS,BNE,BEQ,BRA)
+   (9 Op Codes)
+   (2 bytes)
+   (2,3 and 1 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	Offset		1
+	    (5) 2a	1  1   0  0	PBR,PC+2	IO		1
+	    (61 2b	1  1   0  0	PBR,PC+2+OFF	IO		1
+		1	1  1   1  1	PBR,NewPC	New Op Code	1
+
+
+
+ *16 Relative Long -- rl
+  (BRL)
+  (1 Op Code)
+  (3 bytes)
+  (4 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	Offset Low	1
+		3	1  1   0  1	PBR,PC+2	Offset High	1
+		4	1  1   0  0	PBR,PC+2	IO		1
+		1	1  1   1  1	PBR,NewPC	New Op Code	1
+
+
+
+ 17a Absolute Indirect -- (a)
+  (JMP)
+  (1 Op Code)
+  (3 bytes)
+  (5 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+2	AAH		1
+		4	1  1   1  0	0,AA		NEW PCL		1
+		5	1  1   1  0	0,AA+1		NEW PCH		1
+		1	1  1   1  1	PBR,NewPC	New Op Code	1
+
+
+ *17b Absolute Indirect -- (a)
+  (JML)
+  (1 Op Code)
+  (3 bytes)
+  (6 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+1	AAH		1
+		4	1  1   1  0	0,AA		NEW PCL		1
+		5	1  1   1  0	0,AA+1		NEW PCH		1
+		6	1  1   1  0	0,AA+2		NEW PBR		1
+		1	1  1   1  1	NEW PBR,PC	New Op Code	1
+
+
+
+ **18 Direct Indirect -- (d)
+  (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+  (8 Op Codes)
+  (2 bytes)
+  (5,6 and 7 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   1  0	0,D+DO		AAL		1
+		1	1  1   1  0	0,D+DO+1	AAH		1
+		5	1  1   1  0	DBR,AA		Data Low	1/0
+	    (1) 5a	1  1   1  0	DBR,AA+1	Data Low	1/0
+
+
+
+ *19 Direct Indirect Long -- [d]
+  (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+  (8 Op Codes)
+  (2 bytes)
+  (6,7 and 8 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   1  0	0,D+DO		AAL		1
+		4	1  1   1  0	0,D+DO+1	AAH		1
+		5	1  1   1  0	0,D+DO+2	AAB		1
+		6	1  1   1  0	AAB,AA		Data Low	1/0
+	    (1) 6a	1  1   1  0	AAB,AA+1	Data High	1/0
+
+
+
+ 20a Absolute Indexed Indirect -- (a,x)
+  (JMP)
+  (1 Op Code)
+  (3 bytes)
+  (6 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+2	AAH		1
+		4	1  1   0  0	PBR,PC+2	IO		1
+		5	1  1   0  1	PBR,AA+X	NEW PCL		1
+		6	1  1   0  1	PBR,AA+X+1	NEW PCH		1
+		1	1  1   1  1	PBR,NEWPC	New Op Code	1
+
+
+ *20b Absolute Indered Indirect (Jump to Subroutine Indexed Indirect) -- (a,x)
+  (JSR)
+  (1 Op Code)
+  (3 bytes)
+  (8 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   1  0	0,S		PCH		0
+		4	1  1   1  0	0,S-1		PCL		0
+		5	1  1   0  1	PBR,PC+2	AAH		1
+		6	1  1   0  0	PBR,PC+2	IO		1
+		7	1  1   0  1	PBR,AA+X	NEW PCL		1
+		8	1  1   0  1	PBR,AA+X+1	NEW PCH		1
+		1	1  1   1  1	PBR,NEWPC	New Op Code	1
+
+
+
+ 21a Stack (Hardware Interrupts) -- s
+  (IRQ,NMI,ABORT,RES)
+  (4 hardware Interrupts)
+  (0 bytes)
+  (7 and 8 cycles)
+
+		1	1  1   1  1	PBR,PC		IO		1
+	    (3) 2	1  1   0  0	PBR,PC		IO		1
+	    (7) 3	1  1   1  0	0,S		PBR		0
+	   (10) 4	1  1   1  0	0,S-1		PCH		0
+	   (10) 5	1  1   1  0	0,S-2		PCL		0
+	(10,11) 6	1  1   1  0	0,S-3		P		0
+		7	0  1   1  0	0,VA		AAVL		1
+		8	0  1   1  0	0,VA+1		AAVH		1
+		1	1  1   1  1	0,AAV		New Op Code	1
+
+
+ 21b Stack (Software  Interrupts) -- s
+  (BRK,COP)
+  (2 Op Codes)
+  (2 bytes)
+  (7 and 8 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+	    (3) 2	1  1   0  1	PBR,PC+1	Signature	1
+	    (7) 3	1  1   1  0	0,S		PBR		0
+		4	1  1   1  0	0,S-1		PCH		0
+		5	1  1   1  0	0,S-2		PCL		0
+		6	1  1   1  0	0,S-3  (COP Latches) P		0
+		7	0  1   1  0	0,VA		AAVL		1
+		8	0  1   1  0	0,VA+1		AAVH		1
+		1	1  1   1  1	0,AAV		New Op Code	1
+
+
+ 21c Stack (Return from Interrupt) -- s
+  (RTI)
+  (1 Op Code)
+  (1 byte)
+  (6 and 7 cycles)
+  (different order from N6502)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  0	PBR,PC+1	IO		1
+	    (3) 3	1  1   0  0	PBR,PC+1	IO		1
+		4	1  1   1  0	0,S+1		P		1
+		5	1  1   1  0	0,S+2		New PCL		1
+		6	1  1   1  0	0,S+3		New PCH		1
+	    (7)	7	1  1   1  0	0,S+4		PBR		1
+		1	1  1   1  1	PBR,NewPC	New Op Code	1
+
+
+ 21d Stack (Return from Subroutine) -- s
+  (RTS)
+  (1 Op Code)
+  (1 byte)
+  (6 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+		4	1  1   1  0	0,S+1		New PCL-1	1
+		5	1  1   1  0	0,S+2		New PCH		1
+		6	1  1   0  0	0,S+2		IO		1
+		1	1  1   1  1	PBR,NewPC	New Op Code	1
+
+
+ *21e Stack (Return from Subroutine Long) -- s
+  (RTL)
+  (1 Op Code)
+  (1 byte)
+  (6 cycles)
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+		4	1  1   1  0	0,S+1		NEW PCL		1
+		5	1  1   1  0	0,S+2		NEW PCH		1
+		6	1  1   1  0	0,S+3		NEW PBR		1
+		1	1  1   1  1	NEWPBR,PC	New Op Code	1
+
+
+ 21f Stack (Push) -- s
+  (PHP,PHA,PHY,PHX,PHD,PHK,PHB)
+  (7 Op Codes)
+  (1 byte)
+  (3 and 4 cycles)			
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  0	PBR,PC+1	IO		1
+		3a	1  1   1  0	0,S		Register High	0
+		3	1  1   1  0	0,S-1		Register Low	0
+
+
+ 21g Stack (Pull) -- s
+  (PLP,PLA,PLY,PLX,PLD,PLB)
+  (Different than N6502)
+  (6 Op Codes)
+  (1 byte)
+  (4 and 5 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+		4	1  1   1  0	0,S+1		Register Low	1
+	    (1) 4a	1  1   1  0	0,S+2		Register High	1
+
+
+ *21h Stack (Push Effective Indirect Address) -- s
+  (PEI)
+  (1 Op Code)
+  (2 bytes)
+  (6 and 7 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	DO		1
+	    (2) 2a	1  1   0  0	PBR,PC+1	IO		1
+		3	1  1   1  0	0,D+DO		AAL		1
+		d	1  1   1  0	0,D+DO+1	AAH		1
+		5	1  1   1  0	0,S		AAH		0
+		6	1  1   1  0	0,S-1		AAL		0
+
+
+ *21i Stack (Push Effective Absolute Address) -- s
+  (PEA)
+  (1 Op Code)
+  (3 bytes)
+  (5 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	AAL		1
+		3	1  1   0  1	PBR,PC+2	AAH		1
+		4	1  1   1  0	0,S		AAH		0
+		5	1  1   1  0	0,S-1		AAL		0
+				
+
+
+ *21j Stack (Push Effective Program Counter Relative Address) -- s
+  (PER)
+  (1 Op Code)
+  (3 bytes)
+  (6 cycles)
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	Offset Low	1
+		3	1  1   0  1	PBR,PC+2	Offset High	1
+		4	1  1   0  0	PBR,PC+2	IO		1
+		5	1  1   1  0	0,S		PCH+Offset+CARRY 0
+		6	1  1   1  0	0,S-1		PCL + Offset	0
+
+
+
+ *22 Stace Relative -- d,s
+  (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
+  (8 Op Codes)
+  (2 bytes)
+  (4 and 5 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	SO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+		4	1  1   1  0	0,S+SO		Data Low	1/0
+	    (1) 4a	1  1   1  0	0,S+SO+1	Data High	1/0
+
+
+	
+ *23 Stack Relative Indirect Indexed -- (d,s),y
+  (8 Op Codes)
+  (2 bytes)
+  (7 and 8 cycles)
+
+		1	1  1   1  1	PBR,PC		Op Code		1
+		2	1  1   0  1	PBR,PC+1	SO		1
+		3	1  1   0  0	PBR,PC+1	IO		1
+		4	1  1   1  0	0,S+SO		AAL		1
+		5	1  1   1  0	0,S+SO+1	AAH		1
+		6	1  1   0  0	0,S+SO+1	IO		1
+		7	1  1   1  0	DBR,AA+Y	Data Low	1/0
+	    (1) 7a	1  1   1  0	DBR,AA+Y+1	Data High	1/0
+
+
+
+ *24a Block Move Positive (forward) -- xyc
+   (MVP)
+   (1 Op Code)
+   (3 bytes)
+   (7 cycles)
+
+	     +-	1	1  1   1  1	PBR,PC		Op Code		1
+   	     |	2	1  1   0  1	PBR,PC+1	DBA		1
+	     |	3	1  1   0  1	PBR,PC+2	SBA		1
+	N-2  |	4	1  1   1  0	SBA,X		Source Data	1
+	Byte |	5	1  1   1  0	DBA,Y		Dest Data	0
+	C=2  |	6	1  1   0  0	DBA,Y		IO		1
+	     +-	7	1  1   0  0	DBA,Y		IO		1
+
+	     +-	1	1  1   1  1	PBR,PC		Op Code		1
+	     |	2	1  1   0  1	PBR,PC+1	DBA		1
+	N-1  |	3	1  1   0  1	PBR,PC+2	SBA		1
+	Byte |	4	1  1   1  0	SBA,X-1		Source Data	1
+	C=1  |	5	1  1   1  0	DBA,Y-1		Dest Data	0
+	     |	6	1  1   0  0	DBA,Y-1		IO		1
+	     +-	7	1  1   0  0	DBA,Y-1		IO		1
+
+	     +-	1	1  1   1  1	PBR,PC		Op Code		1
+	     |	2	1  1   0  1	PBR,PC+1	DBA		1
+      N Byte |	3	1  1   0  1	PBR,PC+2	SBA		1
+	Last |	4	1  1   1  0	SBA,X-2		Source Data	1
+	C=0  |	5	1  1   1  0	DBA,Y-2		Dest Data	0
+	     |	6	1  1   0  0	DBA,Y-2		IO		1
+	     |	7	1  1   0  0	DBA,Y-2		IO		1
+	     +-	1	1  1   1  1	PBR,PC+3	New Op Code	1
+
+   x = Source Address
+   y = Destination
+   c = Number of Bytes to move -1
+   x,y Decrement
+   MVP is used when the destination start address is higher (more positive)
+   than the source start address.
+
+   FFFFFF
+     ^	Dest Start
+     |	Source Start
+     |	Dest End
+     |	Source End
+   000000
+
+
+ *24b, Block Move Negative (backward) -- xyc
+   (MVN)
+   (1 Op Code)
+   (3 bytes)
+   (7 cycles)
+
+	     +-	1	1  1   1  1	PBR,PC		Op Code		1
+   	     |	2	1  1   0  1	PBR,PC+1	DBA		1
+	     |	3	1  1   0  1	PBR,PC+2	SBA		1
+	N-2  |	4	1  1   1  0	SBA,X		Source Data	1
+	Byte |	5	1  1   1  0	DBA,Y		Dest Data	0
+	C=2  |	6	1  1   0  0	DBA,Y		IO		1
+	     +-	7	1  1   0  0	DBA,Y		IO		1
+
+	     +-	1	1  1   1  1	PBR,PC		Op Code		1
+	     |	2	1  1   0  1	PBR,PC+1	DBA		1
+	N-1  |	3	1  1   0  1	PBR,PC+2	SBA		1
+	Byte |	4	1  1   1  0	SBA,X+1		Source Data	1
+	C=1  |	5	1  1   1  0	DBA,Y+1		Dest Data	0
+	     |	6	1  1   0  0	DBA,Y+1		IO		1
+	     +-	7	1  1   0  0	DBA,Y+1		IO		1
+
+	     +-	1	1  1   1  1	PBR,PC		Op Code		1
+	     |	2	1  1   0  1	PBR,PC+1	DBA		1
+      N Byte |	3	1  1   0  1	PBR,PC+2	SBA		1
+	Last |	4	1  1   1  0	SBA,X+2		Source Data	1
+	C=0  |	5	1  1   1  0	DBA,Y+2		Dest Data	0
+	     |	6	1  1   0  0	DBA,Y+2		IO		1
+	     |	7	1  1   0  0	DBA,Y+2		IO		1
+	     +-	1	1  1   1  1	PBR,PC+3	New Op Code	1
+
+   x = Source Address
+   y = Destination
+   c = Number of Bytes to move -1
+   x,y Increment
+   MVN is used when the destination start address is lower (more negative)
+   than the source start address.
+
+   FFFFFF
+     |	Source End
+     |	Dest End
+     |	Source Start
+     v	Dest Start
+   000000
+
+
+
+  Notes
+    (1) Add 1 byte (for immediate only) for M=O or X=O (i.e. 16 bit data),
+	 add 1 cycle for M=O or X=0.
+    (2) Add 1 cycle for direct register low (DL) not equal 0.
+    (3) Special case for aborting instruction. This is the last cycle which
+	 may be aborted or the Status, PBR or DBR registers will be updated.
+    (4) Add 1 cycle for indexing across page boundaries, or write, or X=0.
+	 When X=1 or in the emulation mode, this cycle contains invalid
+	 addresses.
+    (5) Add 1 cycle if branch is taken.
+    (6) Add 1 cycle if branch is taken across page boundaries in 6502 emutation
+	 mode (E=1).
+    (7) Subtract 1 cycle for 6502 emulation mode (E=1).
+    (8) Add 1 cycle lor REP, SEP.
+    (9) Wait at cycle 2 for 2 cycles after /NMI or /IRQ active input.
+   (10) R/W remains high during Reset.
+   (11) BRK bit 4 equals "0" in Emulation mode.
+
+
+  Abbreviations
+	AAB	Absolute Address Bank
+	AAH	Absolute Address High
+	AAL	Absolute Address Low
+	AAVH	Absolute Address Vector High
+	AAVL	Absolute Address Vector Low
+	C	Accumulator
+	D	Direct Register
+	DBA	Destination Bank Address
+	DBR	Data Bank Register
+	DO	Direct Offset
+	IDH	Immediate Data High
+	IDL	Immediate Data Low
+	IO	Internal Operation
+	P	Status Register
+	PBR	Program Bank Register
+	PC	Program Counter
+	R-M-W	Read-Modify-Write
+	S	Stack Address
+	SBA	Source Bank Address
+	SO	Stack Offset
+	VA	Vector Address
+	x, y	Index Registers
+	*	New G65SC816/802 Addressing Modes
+	**	New G65SC02 Addressing Modes
+	Blank	NMOS 6502 Addressing Modes
+
+

BIN
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+ 72 - 0
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@@ -0,0 +1,72 @@
+
+GTE						G 65 SC 802 / G 65 SC 816
+Microcircuits
+
+
+CMOS 8/16-Bit Microprocessor Family
+
+Features
+	Advanced CMOS design for low power consumption and increased
+	  noise immunity
+	Emulation mode for total software compatibility with 6502 designs
+	Full 16-bit ALU, Accumulator, Stack Pointer, and Index Registers
+	Direct Register for ''zero page'' addressing
+	24 addressing modes (including 13 original 6502 modes)
+	Wait for Interrupt (WAI) and Stop the Clock (STP) instructions
+	  for reduced power consumption and decreased interrupt latency
+	91 instructions with 255 opcodes
+	Co-Processor (COP) instruction and associated vector
+	Powerful Block Move instructions
+
+Features (G65SC802 Only)
+	8-Bit Mode with both software and hardware (pin-to-pin) compatibility
+	  with 6502 designs (64 KByte memory space)
+	Program selectable 16-bit operation
+	Choice of external or on-board clock generation
+
+Features (G65SC816 Only)
+	Full 16-bit operation with 24 address lines for 16 MByte memory
+	Program selectable 8-Bit Mode for 6502 coding compatibility.
+	Valid Program Address (VPA) and Valid Data Address (VDA) outputs
+	  for dual cache and DMA cycle steal implementation
+	Vector Pull (VP) output indicates when interrupt vectors are being
+	  fetched. May be used for vectoring/prioritizing interrupts.
+	Abort interrupt and associated vector for interrupting any instruction
+	  without modifying internal registers
+	Memory Lock (ML) for multiprocessor system implementation
+
+
+General Description
+
+The G65SC802 and G65SC816 are ADV-CMOS (ADVanced CMOS) 16-bit microprocessors
+featuring total software compatibility with 8-bit NMOS and CMOS 6500 series
+microprocessors. The G65SC802 is pin-to-pin compatible with 8-bit 6502 devices
+currently available, while also providing full 16-bit internal operation. The
+G65SC816 provides 24 address lines for 16 MByte addressing, while providing
+both 8-bit and 16-bit operation.
+
+Each microprocessor contains an Emulation (E) mode for emulating 8-bit NMOS
+and CMOS 6500-Series microprocessors. A software switch determines whether the
+processor is in the 8-bit ernulation mode or in the Native 16-bit mode.
+This allows existing 8-bit system designs to use the many powerful features of
+the G65SC802 and G65SC816.
+
+The G65SC802 and G65SC816 provide the system engineer with many powerful
+features and options. A 16-bit Direct Page Register is provided to augment the
+Direct Page addressing mode, and there are separate Program Bank Registers
+for 24-bit memory addressing.
+Other valuable features Include:
+ * An Abort input which can interrupt the current instruction without
+   modifying internal registers
+ * Valid Data Address (VDA) and Valid Program Address (VPA) outputs which
+   facilitate dual cache memory by indicating whether a data or program
+   segment is being accessed.
+ * Vector modification by simply monitoring the Vector Pull (VP) output.
+ * Block Move Instructions
+
+
+G65SC802 and G65SC816 microprocessors offer the design engineer a new freedom
+of design and application, and the many advantages of state-of-the-art
+ADV-CMOS technology.
+
+This is advanced information and specifications are subject to change without notice.

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+
+
+Functional Description
+
+The G65SC802 offers the design engineer the opportunity to utilize both
+existing software programs and hardware configurations, while also
+achieving the added advantages of increased register lengths and faster
+execution times. The G65SC802's "ease of use" design and implementation
+features provide the designer with increased flexibility and reduced
+implementation costs In the Emulation mode, the G65SC802 not only offers
+software compatibility, but is also hardware (pin-to-pin) compatible with
+6502 designs plus it provides the advantages of 16-bit internal operation
+in 6502-compatible applications. The G65SC802 is an excellent direct
+replacement microprocessor for 6502 designs.
+
+The G65SC816 provides the design engineer with upward mobility and software
+compatibility in applications where a 16-bit system configuration is desired.
+The G65SC816's 16-bit hardware configuration, coupled with current software
+allows a wide selection of system applications. In the Emulation mode, the
+G65SC816 ofters many advantages, including full software compatibility with
+6502 coding. In addition, the G65SC816's powerful instruction set and
+addressing modes make it an excellent choice for new 16-bit designs.
+
+Internal organization of the G65SC802 and G65SC816 can be divided into two
+parts: 1) The Register Section, and 2) The Control Section Instructions
+(or opcodes) obtained from program memory are executed by implementing a
+series of data transfers within the Register Section.
+Signals that cause data transfers to be executed are generated within the
+Control Section. Both the G65SC802 and the G65SC816 have a 16-bit internal
+architecture with an 8-bit external data bus.
+
+
+Instructlon Register and Decode
+
+An opcode enters the processor on the Data Bus, and is latched into the
+Instruction Register during the instruction fetch cycle. This instruction is
+then decoded, along with timing and interrupt signals, to generate the
+various Instruction Register control signals.
+
+
+Timing Control Unit (TCU)
+
+The Timing Control Unit keeps track of each instruction cycle as it is
+executed. The TCU is set to zero each time an instruction fetch is executed,
+and is advanced at the beginning of each cycle for as many cycles as is
+required to complete the instruction Each data transfer between registers
+depends upon decoding the contents of both the Instruction Register and
+the Timing Control Unit.
+
+
+Arithmetic and Logic Unit (ALU)
+
+All arithmetic and logic operations take place within the 16-bit ALU. In
+addition to data operations, the ALU also calculates the effective address
+for relative and indexed addressing modes. The result of a data operation
+is stored in either memory or an internal register. Carry, Negative, Over-
+flow and Zero flags may be updated following the ALU data operation.
+
+
+Internal Registers (Refer to Figure 2, Programming Model)
+
+Accumulator (A)
+The Accumulator is a general purpose register which stores one of the
+operands, or the result of most arithmetic and logical operations. In the
+Native mode (E=0), when the Accumulator Select Bit (M) equals zero, the
+Accumulator is established as 16 bits wide. When the Accumulator Select
+Bit (M) equals one, the Accumulator is 8 bits wide. In this case, the upper
+8 bits (AH) may be used for temporary storage in conjunction with the
+Exchange AH and AL instruction.
+
+Data Bank (DB)
+During the Native mode (E=0), the 8-bit Data Bank Register holds the default
+bank address for memory transfers. The 24-bit address is composed of the
+16-bit instruction effective address and the 8-bit Data Bank address. The
+register value is multiplexed with the data value and is present on the
+Data/Address lines during the first half of a data transfer memory cycle for
+the G65SC816. The Data Bank Register is initialized to zero during Reset.
+
+Direct (D)
+The 16-bit Direct Register provides an address offset for all instructions
+using direct addressing. The effective bank zero address is formed by adding
+the 8-bit instruction operand address to the Direct Register. The Direct
+Register is initialized to zero during Reset.
+
+Index (X and Y)
+There are two Index Registers (X and Y) which may be used as general purpose
+registers or to provide an index value for calculation of the effective
+address. When executing an instruction with indexed addressing, the
+microprocessor fetches the opcode and the base address, and then modifies the
+address by adding the Index Register contents to the address prior to
+performing the desired operation.
+Pre-indexing or postindexing of Indirect addresses may be selected. In the
+Native mode (E=0), both Index Registers are 16 bits wide (providing the Index
+Select Bit (X) equals zero). If the Index Select Bit (X) equals one, both
+registers will be 8 bits wide.
+
+Processor Status (P)
+The 8-bit Processor Status Register contains status flags and mode select bits.
+The Carry (C), Negative (N). Overflow (V), and Zero (Z) status flags serve to
+report the status ot most ALU operations. These status flags are tested by use
+of Conditional Branch instructions. The Decimal (D), IRQ Disable (I), Memory,
+Accumuiator (M), and Index (X) bits are used as mode select flags. These flags
+are set by the program to change microprocessor operations.
+
+The Emulation (E) select and the Break (B) flags are accessible only through
+the Processor Status Register. The Emulation mode select flag is selected by
+the Exchange Carry and Emulation Bits (XCE) instruction.
+Table 2, G65SC802 and G65SC816 Mode Comparison, illustrates the features of
+the Native (E=0) and Emulation (E=1) modes. The M and X flags are always equal
+to one in the Emulation mode. When an interrupt occurs during the Emulation
+mode, the Break flag is written to stack memory as bit 4 of the Processor
+Status Register.
+
+Program Bank (PB)
+The 8-bit Program Bank Register holds the bank address for all instruction
+fetches. The 24-bit address consists of the 16-bit instruction effective
+address and the 8-bit Program Bank address. The register value is multiplexed
+with the data value and presented on the Data/Address lines during the first
+half of a program memory read cycle. The Program Bank Register is initialized
+to zero during Reset.
+
+Program Counter (PC)
+The 16-bit Program Counter Register provides the addresses which are used to
+step the microprocessor through sequential program instructions. The register
+is incremented each time an instruction or operand is fetched from program
+memory.
+
+Stack Pointer (S)
+The Stack Pointer is a 16-bit register which is used to indicate the next
+available location in the stack memory area. It serves as the effective address
+in stack addressing modes as well as subroutine and interrupt processing. The
+Stack Pointer allows simple implementation of nested subroutines and multiple-
+level interrupts. During the Emulation mode, the Stack Pointer high-order byte
+(SH) is always equal to 01. The Bank Address is 00 for all Stack operations.
+
+
+Signal Description
+
+The following Signal Description applies to both the G65SC802 and the
+SSC816 except as otherwise noted.
+
+
+Abort (/ABORT) -- G65SC816
+The Abort input prevents modification of any internal registers during
+execution of the current instruction. Upon completion of this instruction,
+an interrupt sequence is initiated. The location of the aborted opcode is
+stored as the return address in Stack memory. The Abort vector address is
+00FFF8, 9 (Emulation mode) or 00FFE8, 9 (Native mode). Abort is asserted
+whenever there is a low level on the Abort input. and the Phi2 clock is high.
+The Abort internal latch is cleared during the second cycle of the interrupt
+sequence. This signal may be used to handle out-of-bounds memory references
+in virtual memory systems.
+
+Address Bus (A0-A15)
+These sixteen output lines form the Address Bus for memory and I/O exchange on
+the Data Bus. When using the G65SC816, the address lines may be set to the
+high impedance state by the Bus Enable (BE) signal.
+
+Bus Enable (BE)
+The Bus Enable input signal allows external control of the Address and Data
+Buffers, as well as the R/W signal With Bus Enable high, the R/W and Address
+Buffers are active. The Data/Address Buffers are active during the first half
+of every cycle and the second half of a write cycle. When BE is low, these
+buffers are disabled. Bus Enable is an asynchronous signal.
+
+Data Bus (D0-D7) -- G65SC802
+The eight Data Bus lines provide an 8-bit bidirectional Data Bus for use
+during data exchanges between the microprocessor and external memory or
+peripherals. Two memory cycles are required for the transfer of 16-bit values.
+
+Data/Address Bus (D0/BA0-D7/BA7) -- G65SC816
+These eight lines multiplex bits BAO-BA7 with the data value. The Bank Address
+is present during the first half of a memory cycle, and the data value is read
+or written during the second half of the memory cycle.
+The Bank address external transparent latch should be latched when the Phi2
+clock is high or RDY is low. Two memory cycles are required to transfer 16-bit
+values. These lines may be set to the high impedance state by the Bus Enable
+(BE) signal.
+
+Emulation Status (E) -- G65SC816 (Also Applies to G65SC802, 44-Pin Version)
+The Emulation Status output reflects the state of the Emulation (E) mode flag
+in the Processor Status (P) Register. This signal may be thought of an opcode
+extension and used for memory and system management.
+
+Interrupt Request (/IRQ)
+The Interrupt Request input signal is used to request that an interrupt
+sequence be initiated. When the IRQ Disable (I) flag is cleared, a low input
+logic level initiates an interrupt sequence after the current instruction is
+completed. The Wait for Interrupt (WAI) instruction may be executed to ensure
+the interrupt will be recognized immediately. The Interrupt Request vector
+address is 00FFFE,F (Emulation mode) or 00FFEE,F (Native mode). Since IRQ is a
+level-sensitive input, an interrupt will occur if the interrupt source was not
+cleared since the last interrupt.
+Also, no interrupt will occur if the interrupt source is cleared prior to
+interrupt recognition.
+
+Memory Lock (/ML) -- G65SC816 (Also Applies to G65SC802, 44-Pin Version)
+The Memory Lock output may be used to ensure the integrity of Read-Modify-Write
+instructions in a multiprocessor system. Memory Lock indicates the need to
+defer arbitration of the next bus cycle. Memory Lock is low during the last
+three or five cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory
+referencing instructions, depending the state of the M flag.
+
+Memory/Index Select Status (M/X) -- G65SC816
+This multiplexed output reflects the state ot the Accumulator (M) and index (X)
+select flags (bits 5 and 4 of the Processor Status (P) Register).
+Flag M is valid during the Phi2 clock positive transition. Instructions PLP,
+REP, RTI and SEP may change the state of these bits. Note that the M/X output
+may be invalid in the cycle following a change in the M or X bits. These bits
+may be thought of as opcode extensions and may be used for memory and system
+management.
+
+Non-Maskable Interrupt (/NMI)
+A high-to-low transition initiates an intenupt sequence after the current
+instruction is completed. The Wait for Interrupt (WAI) instruction may be
+executed to ensure that the interrupt will be recognized immediately. The
+Non-Maskable Interrupt vector address is 00FFFA,B (Emulation mode) or 00FFEA,B
+(Native mode). Since NMI is an edge-sensitive Input, an interrupt will occur
+if there is a negative transition while servicing a previous interrupt. Also,
+no interrupt will occur if NMI remains low.
+
+Phase 1 Out (Phi1 (OUT)) -- G65SC802
+This inverted clock output signal provides timing for external read and write
+operations. Executing the Stop (STP) instruction holds this clock in the low
+state.
+
+Phase 2 In (Phi2 (IN))
+This is the system clock input to the microprocessor internal clock generator
+(equivalent to Phi0 (IN) on the 6502). During the low power Standby Mode, Phi2
+(IN) should be held in the high state to preserve the contents of internal
+registers.
+
+Phase 2 Out (Phi2 (OUT)) -- G65SC802
+This clock output signal provides timing for external read and write
+operations. Addresses are valid (after the Address Setup Time (TADS))
+following the negative transition of Phase 2 Out. Executing the Stop (STP)
+instruction holds Phase 2 Out in the High state.
+
+Read/Write (R/W)
+When the R/W output signal is in the high state, the microprocessor is reading
+data from memory or I/O. When in the low state, the Data Bus contains valid
+data from the microprocessor which is to be stored at the addressed memory
+location. When using the G65SC816, the R/W signal may be set to the high
+impedance state by Bus Enable (BE).
+
+Ready (RDY)
+This bidirectional signal indicates that a Wait for Interrupt (WAI) instruction
+has been executed allowing the user to halt operation of the microprocessor.
+A low input logic level will halt the microprocessor in its current state (note
+that when in the Emulation mode, the G65SC802 stops only during a read cycle).
+Returning RDY to the active high state allows the microprocessor to continue
+following the next Phase 2 In Clock negative transition. The RDY signal is
+internally pulled low following the execution of a Wait for Interrupt (WAI)
+instruction, and then returned to the high state when a /RES, /ABORT, /NMI, or
+/IRQ external interrupt is provided. This feature may be used to eliminate
+interrupt latency by placing the WAI instruction at the beginning of the IRQ
+servicing routine. If the IRQ Disable flag has been set, the next instruction
+will be executed when the IRQ occurs. The processor will not stop after a WAI
+instruction if RDY has been forced to a high state. The Stop (STP) instruction
+has no effect on RDY.
+
+Reset (/RES)
+The Reset input is used to initialize the microprocessor and start program
+execution. The Reset input buffer has hysteresis such that a simple R-C timing
+circuit may be used with the internal pullup device. The /RES signal must be
+held low for at least two clock cycles after VDD reaches operating voltage.
+Ready (RDY) has no effect while RES is being held low. During this Reset
+conditioning period, the following processor initialization takes place:
+
+		   Registers
+
+	   D  = 0000		SH = 01
+	   DB = 00		XH = 00
+	   PB = 00		YH = 00
+
+		  N V M X D I Z C/E
+	   P =  * * 1 1 0 1 * */1
+
+		* = Not Initialized
+		STP and WAI instructions are cleared.
+
+
+	              Signals
+
+	   E    = 1		VDA = 0
+	   M/X  = 1		/VP = 1
+	   R/W  = 1		VPA = 0
+	   SYNC = 0
+
+
+When Reset is brought high, an interrupt sequence is initiated:
+* R/W remains in the high state during the stack address cycles.
+* The Reset vector address is 00FFFC,D.
+
+
+Set Overtlow (/SO) -- G65SC802
+A negative transition on this input sets the Overflow (V) flag, bit 6 of the
+Processor Status (P) Register.
+
+Synchronlze (SYNC) -- G65SC802
+The SYNC output is provided to identify those cycles during which the
+microprocessor is fetching an opcode. The SYNC signal is high during an opcode
+fetch cycle, and when combined with Ready (RDY), can be used for single
+instruction execution.
+
+
+Valid Data Address (VDA) and
+Valid Program Address (VPA) -- G65SC816
+These two output signals indicate the type of memory being accessed by
+the address bus. The following coding applies:
+
+VDA VPA
+ 0   0	Internal Operation -- Address and Data Bus available. Address
+	outputs may be invalid due to low byte additions only.
+
+ 0   1	Valid program address -- may be used for program cache control.
+
+ 1   0	Valid data address -- may be used for data cache control.
+
+ 1   1	Opcode fetch -- may be used for program cache control
+	and single step control.
+
+
+VDD and Vss
+VDD Vss the positive supply voltage and Vss is system ground. When
+using only one ground on the G65SC802 DIP package, pin 21 preferred.
+
+Vector Pull (VP) -- G65SC816 (Also Applies to G65SC802 44-Pin Version)
+The Vector Pull output indicates that a vector location is being addressed
+during an interrupt sequence. /VP is low during the last two interrupt sequence
+cycles, during which time the processor reads the interrupt vector. The /VP
+signal may be used to select and prioritize interrupts from several sources by
+modifying the vector addresses.
+
+--------------------------------------------------------------------------
+
+8 bits		8 bits		8 bits
+
+  DB						DB Data Bank Register
+		  XH		  XL		Index Register (X)
+		  YH		  YL		Index Register (Y)
+  00		  SH		  SL		Stack Pointer  (S)
+		  AH		  AL		Accumulator    (A)
+  PB		  PCH		  PCL		Program Counter (PC)
+						Program Bank Register (PB)
+  00		  DH		  DL		Direct Register (D)
+
+		L = Low, H = High
+
+
+	Processor Status Register (P)
+	____________________________
+	|        1  B           E  |
+	|__________________________|
+	|  N  V  M  X  D  I  Z  C  |
+	|__________________________|
+
+	1	Always 1 if E=1
+	B	Break			0 on Stack after interupt if E=1
+	E	Emulation Bit		0= Native mode, 1= 6502 emulation
+
+	N	Negative		1= Negative
+	V	Overflow		1= True
+	M	Memory/Acc. Select	1= 8 bit, 0= 16 bit
+	X	Index Register Select	1= 8 bit, 0= 16 bit
+	D	Decimal mode		1= Decimal Mode
+	I	IRQ Disable		1= Disable
+	Z	Zero			1= Result Zero
+	C	Carry			1= True
+
+
+	Figure 2. Programming model
+
+--------------------------------------------------------------------------
+
+
+Table 1. G65SC802 and G65SC816 Compability
+
+   Function			G65SC802/816	G65SC02		NMOS 6502
+				 Emulation
+Decimal Mode:
+* After Interrupts		0 -> D		0 -> D		Not initialized
+* N, Z Flags			Valid		Valid		Undefined
+* ADC, SBC			No added cycle	Add 1 cycle	No added cycle
+
+Read-Modify-Write:
+* Absolute Indexed, No Page Crossing
+				7 cycles	6 cycles	7 cycles
+* Write				Last 2 cycles	Last cycle	Last 2 cycles
+* Memory Lock			Last 3 cycles	Last 2 cycles	Not available
+
+Jump Indirect:
+* Cycles			5 cycles	6 cycles	5 cycles
+* Jump Address, operand = xxFF	Correct		Correct		Invalid
+
+Branch or Index Across Page Boundary
+				Read last	Read last	Read invalid
+				program byte	program byte	address
+
+0 -> RDY During Write	G65SC802: Ignored	Processor	Ignored until
+				until read	stops		read
+			G65SC816: Processor
+				stops
+
+Write During Reset		No		Yes		No
+
+Unused Opcodes			No operation	No operation	Undefined
+
+Phi1 (OUT), Phi2 (OUT), /SO, SYNC Signals
+				Available with	Available	Available
+				G65SC802 only
+
+RDY Signal			Bidirectional	Input		Input
+
+--------------------------------------------------------------------------
+
+Table 2. G65SC802 and G65SC816 Mode Comparison
+
+   Function		Emulation (E = 1)	Native (E = 0)
+
+Stack Pointer (S)	8 bits in page 1	16 bits
+
+Direct Index Address	Wrap within page	Crosses page boundary
+
+Processor Status (P):
+* Bit 4			Always one, except zero	  X flag (8/16-bit Index)
+			in stack after hardware
+			interrupt
+
+* Bit 5			Always one		M flag (8/16-bit Accumulator)
+
+
+Branch Across Page Boundary
+			4 cycles		3 cycles
+
+Vector Locations:
+	ABORT		00FFF8,9		00FFF8,9
+	BRK		00FFFE,F		00FFF6,7
+	COP		00FFF4,5		00FFF4,5
+	IRQ		00FFFE,F		00FFFE,F
+	NMI		00FFFA,B		00FFFA,B
+	RES		00FFFC,D		00FFFC,D (1 -> E)
+
+
+Program Bank (PB) During Interrupt, RTI
+			Not pushed, pulled	Pushed and pulled
+
+0 -> RDY During Write
+		G65SC802: Ignored until read	Processor stops
+		G65SC816: Processor stops
+
+Write During Read-Modify-Write
+			Last 2 cycles		Last 1 or 2 cycles depending
+						on M flag
+

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+
+Notes on G65SC802/816 Instructions
+
+All Opcodes Function in All Modes of Operation
+
+It should be noted that all opcodes function in all modes of operation.
+However, some instructions and addressing modes are intended for G65SC816
+24-bit addressing and are therefore less useful for the G65SC802. The
+following is a list of Instructions and addressing modes which are primarily
+intended for G65SC816 use:
+
+	JSL; RTL; [d]; [d],y; JMP al; JML; al; al,x
+
+The following instructions may be used with the G65SC802 even though a
+Bank Address is not multiplexed on the Data Bus:
+
+	PHK; PHB; PLB
+
+The following instructions have "limited" use in the Emulation mode.
+
+* The REP and SEP instructions cannot modify the M and X bits when in the
+Emulation mode. In this mode the M and X bits will always be high (logic 1).
+
+* When in the Emulation mode, the MVP and MVN instructions only move data
+in page zero since X and Y Index Register high byte is zero.
+
+
+Indirect Jumps
+
+The JMP (a) and JML (a) instructions use the direct Bank for indirect
+addressing, while JMP (a,x) and JSR (a,x) use the Program Bank for indirect
+address tables.
+
+
+Switching Modes
+
+When switching from the Native mode to the Emulation mode, the X and M bits
+of the Status Register are set high (logic 1), the high byte of the Stack is
+set to 01, and the high bytes of the X and Y Index Registers are set to 00.
+To save previous values, these bytes must always be stored before changing
+modes. Note that the low byte of the S, X and Y Registers and the low and high
+byte of the Accumulator AL and AH are not affected by a mode change.
+
+
+WAI Instruction
+
+The WAI instruction pulls RDY low and places the processor in the WAI
+"low power" mode. /NMI, /IRQ or /RESET will terminate the WAI condition and
+transfer control to the interrupt handler routine. Note that an /ABORT input
+will abort the WAI instruction, but will not restart the processor. When the
+Status Register I flag is set (IRQ disabled), the IRQ interrupt will cause the
+next instruction (following the WAI instruction) to be executed without going
+to the IRQ interrupt handler. This method results in the highest speed response
+to an IRQ input. When an interrupt is received after an ABORT which occurs
+during the WAI instruction, the processor will return to the WAI instruction.
+Other than RES (highest priority), ABORT is the next highest priority, followed
+by NMI or IRQ interrupts.
+
+
+STP Instruction
+
+The STP instruction disables the Phi2 clock to all circuitry. When disabled,
+the Phi2 clock is held in the high state. In this case, the Data Bus will
+remain in the data transfer state and the Bank address will not be multiplexed
+onto the Data Bus. Upon executing the STP instruction, the /RES signal is the
+only input which can restart the processor. The processor is restarted by
+enabling the Phi2 clock, which occurs on the falling edge of the /RES input.
+Note that the external oscillator must be stable and operating properly before
+RES goes high.
+
+
+Tranters trom 8-Bit to 16-Bit, or 16-Bit to 8-Bit Registers
+
+All transfers from one register to another will result in a full 16-bit output
+from the source register. The destination register size will determine the
+number of bits actually stored in the destination register and the values
+stored in the processor Status Register. The following are always 16-bit
+transfers, regardless of the accumulator size:
+
+	TCS; TSC; TCD; TDC
+
+
+Stack Transfers
+
+When in the Emulation mode, a 01 is forced into SH. In this case, the B
+Accumulator will not be loaded into SH during a TCS instruction. When in the
+Native mode, the B Accumulator is transferred to SH. Note that in both the
+Emulation and Native modes, the full 16 bits of the Stack Register are
+transferred to the Accumulator, regardless of the state of the M bit in the
+Status Register.
+

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+
+
+	 Table 5. Arithmetic and Logical Instructions
+
+Mne-			  Operation						Addressing Mode							Status
+monic	M/X	E=1 or			E = 0 and	               dir, dir, (dir) (dir, (dir) [dir] abs abs, abs, absl absl d,s (d,s)
+		E=0 and M/X=1		M/X = 0		Immed Accu dir   x    y          x)   ,y               x    y        ,x        ,y	N V M X D I Z C
+
+ADC	Pm	AL + B + Pc -> AL	A + W + Pc -> A	 69        65   75         72    61   71    67    6D  7D   79   6F   7F   63   73	N V . . . . Z C
+AND	Pm	AL /\B -> AL		A /\W -> A	 29        25   35         32    21   31    27    2D  3D   39   2F   3F   23   33	N . . . . . Z .
+ASL	Pm	Pc <-B <- 0		Pc <- W <- 0	      0A   06   16				  0E  1E				N . . . . . Z C
+BIT	Pm	AL /\B			A /\W		 89        24   34				  2C  3C				N V . . . . Z .
+
+CMP	Pm	AL - B			A - W		 C9        C5   D5         D2    C1   D1    C7    CD  DD   D9   CF   DF   C3   D3	N . . . . . Z C
+CPX	Px	XL - B			X - W		 E0        E4					  EC					N . . . . . Z C
+CPY	Px	YL - B			Y - W		 C0        C4					  CC					N . . . . . Z C
+DEC	Pm	B  - 1 -> B		W - 1 -> W	      3A   C6   D6				  CE  DE				N . . . . . Z .
+
+EOR	Pm	AL V- B -> AL		A V- W -> A	 49        45   55         52    41   51    47    4D  5D   59   4F   5F   43   53	N . . . . . Z .
+INC	Pm	B  + 1 -> B		W + 1 -> W	      1A   E6   F6				  EE  FE				N . . . . . Z .
+LDA	Pm	B  -> AL		W -> A		 A9        A5   B5         B2    A1   B1    B7    AD  BD   B9   AF   BF   A3   B3	N . . . . . Z .
+LDX	Px	B  -> XL		W -> X		 A2        A6         B6			  AE       BE				N . . . . . Z .
+
+LDY	Px	B  -> YL		W -> Y		 A0        A4   B4				  AC  BC				N . . . . . Z .
+LSR	Pm	0  -> B -> Pc		0 -> W -> Pc	      4A   46   56				  4E  5E				0 . . . . . Z C
+ORA	Pm	AL V B -> AL		A V W -> A	 09        05   15         12    01   11    17    0D  1D   19   0F   1F   03   13	N . . . . . Z .
+ROL	Pm	Pc <- B <- Pc		Pc <- W <- Pc	      2A   26   36				  2E  3E				N . . . . . Z C
+
+ROR	Pm	Pc -> B -> Pc		Pc -> W -> Pc	      6A   66   76				  6E  7E				N . . . . . Z C
+SBC	Pm	AL - B - Pc -> AL	A - W - Pc -> A	 E9        E5   F5         F2    E1   F1    F7    ED  FD   F9   EF   FF   E3   F3	N V . . . . Z C
+STA	Pm	AL -> B			A -> W		           85   95         92    81   91    97    8D  9D   99   8F   9F   83   93	. . . . . . . .
+STX	Px	XL -> B			X -> W		           86         96			  8E					. . . . . . . .
+
+STY	Px	YL -> B			Y -> W		           84   94				  8C					. . . . . . . .
+STZ	Pm	0  -> B			0 -> W		           64   74				  9C  9E				. . . . . . . .
+TRB	Pm	/AL /\ B -> B		/A /\ W -> W	           14					  1C					. . . . . . Z .
+TSB	Pm	AL V B -> B		A V W -> W	           04					  0C					. . . . . . Z .
+
+
+
+  V	logical OR		  B    byte per effective address
+  /\	logical AND		  W    word per effective address
+  V-	logical exclusive OR      r    relative offset
+  +	arithmetic addition	  A    Accumulator, AL low half of Accumulator
+  -	arithmetic subtraction    X    Index Register, XL low half of X register
+  !=	not equal		  Y    Index Register, YL low half of Y register
+  .	status bit not affected   Pc   carry bit
+  /	negation		  M/X  effective mode bit in Status Register (Pm or Px)
+				  Ws   word per stack pointer
+				  Bs   byte per stack pointer
+
+Notes:
+
+  BIT instruction does not affect N and V flags when using immediate
+  addressing mode. When using other addressing modes, the N and V flags
+  are respectively set to bits 7 and 6 or 15 and 14 of the addressed memory
+  depending on mode (byte or word).
+
+  For all Read/Modify/Write instruction addressing modes except accumulator
+    Add 2 cycles for E=1 or E=0 and Pm=1 (8-bit mode)
+    Add 3 cycles for E=0 and Pm=0 (16-bit mode).
+
+  Add one cycle when indexing across page boundary and E=1 except for STA and
+  STZ instructions.
+
+  If E=1 then 1 -> SH and XL -> SL If E=0 then X -> S regardless of Pm or Px.
+
+  Exchanges the carry (Pc) and E bits. Whenever the E bit is set the following
+  registers and status bits are locked into the indicated state:
+  XH=0, YH=0, SH=1, Pm=1, Px=1.
+
+  Add 1 cycle if branch is taken. In Emulation (E= 1 ) mode only --add 1 cycle
+  if the branch is taken and crosses a page boundary.
+
+  Add 1 cycle in Emulation mode (E=1) for (dir),y; abs,x; and abs,y addressing
+  modes.
+
+  With TSB and TRB instruction, the Z flag is set or cleared by the result
+  of AAB or AAW.
+  For all Read/Modify/Write instruction addressing modes except accumulator --
+    Add 2 cycles for E=1 or E=0 and Pm=1 (8-bit mode)
+    Add 3 cycles for E=0 and Pm=0 (16-bit mode).
+
+
+
+	 Table 6. Branch, Transter, Push, Pull, and Implied Addressing Mode Instructions
+
+				   Operation		    Operation					    Status
+Mnemonic Bytes M/X   Cycles  8 Bit		Cycles   16 Bit	    Implied Stack Relative	N V M X D I Z C Mnemonic
+
+BCC (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    90		. . . . . . . .	BCC
+BCS (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    B0		. . . . . . . .	BCS
+BEQ (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    F0		. . . . . . . .	BEQ
+BMI (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    30		. . . . . . . .	BMI
+
+BNE (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    D0		. . . . . . . .	BNE
+BPL (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    10		. . . . . . . .	BPL
+BRA (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    80		. . . . . . . .	BRA
+BVC (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    50		. . . . . . . .	BVC
+BVS (6)	  2	-	2    PC+r -> PC		2	PC+r -> PC		    70		. . . . . . . .	BVS
+
+CLC	  1	-	2    0 -> Pc		2	0 -> Pc		18			. . . . . . . 0	CLC
+CLD	  1	-	2    0 -> Pd		2	0 -> Pd		D8			. . . . 0 . . .	CLD
+CLI	  1	-	2    0 -> Pi		2	0 -> Pi		58			. . . . . 0 . .	CLI
+CLV	  1	-	2    0 -> Pv		2	O -> Pv		B8			. 0 . . . . . .	CLV
+
+DEX	  1	Px	2    XL - 1 -> XL	2	X - 1 -> X	CA			N . . .	. . Z . DEX
+DEY	  1	Px	2    YL - 1 -> YL	2	Y - 1 ->Y	88			N . . .	. . Z . DEY
+INX	  1	Px	2    XL + 1 -> XL	2	X + 1 -> X	E8			N . . . . . Z .	INX
+INY	  1	Px	2    YL + 1 -> YL	2	Y + 1 -> Y	C8			N . . .	. . Z . INY
+
+NOP	  1	-	2    no operation	2	no operation	EA			. . . . . . . .	NOP
+PEA	  3	-	5    W->Ws, S-2 ->S	5	same		    F4			. . . . . . . .	PEA
+PEI	  2	-	6    W->Ws, S-2 ->S	6	same		    D4			. . . . . . . .	PEI
+
+PER	  3	-	6    W ->Ws, S-2 ->S	6	same		    62			. . . . . . . .	PER
+PHA	  1	Pm	3    AL->Bs, S-1 ->S	4	A ->Ws, S-2 ->S	    48			. . . . . . . .	PHA
+PHB	  1	-	3    DB->Bs, S-1 ->S	3	same		    8B			. . . . . . . .	PHB
+PHD	  1	-	4    D ->Ws, S-2 ->S	4	same		    OB			. . . . . . . .	PHD
+
+PHK	  1	-	3    PB->Bs, S-1 ->S		same		    4B			. . . . . . . . PHK
+PHP	  1	-	3    P ->Bs, S-1 ->S	3 	same		    08			. . . . . . . .	PHP
+PHX	  1	Px	3    XL->Bs, S-1 ->S	4	X-Ws, S-2 -> S	    DA			. . . . . . . . PHX
+PHY	  1	Px	3    YL->Bs, S-1 ->S	4	Y ->Ws, S-2 ->S	    5A			. . . . . . . .	PHY
+
+PLA	  1	Pm	4    S+1 ->S, Bs -> AL	5	S+2 ->S, Ws->A	    68			N . . . . . Z .	PLA
+PLB	  1	-	4    S+1 ->S, Bs -> DB	4 	same		    AB			N . . . . . Z .	PLB
+PLD	  1	-	5    S+2 ->S, Ws -> D	5 	same		    2B			N . . . . . Z .	PLD
+PLP	  1	-	4    S+1 ->S, Bs -> P	4 	same		    28			N V M X D I Z C	PLP
+
+PLX	  1	Px	4    S+1 ->S, Bs -> XL	5	S+2 ->S, Ws->X	    FA			N . . . . . Z .	PLX
+PLY	  1	Px	4    S+1 ->S, Bs -> YL	5	S+2 ->S, Ws->Y	    7A			N . . . . . Z .	PLY
+
+SEC	  1	-	2    1 -> Pc		2	1 -> Pc		38			. . . . . . . 1	SEC
+SED	  1	-	2    1 -> Pd		2	1 -> Pd		F8			. . . . 1 . . .	SED
+SEI	  1	-	2    1 -> Pi		2	1 -> Pi		78			. . . . . 1 . .	SEI
+
+TAX	  1	Px	2    AL -> XL		2	A -> X		AA			N . . . . . Z .	TAX
+TAY	  1	Px	2    AL -> YL		2	A -> Y		A8			N . . . . . Z .	TAY
+TCD	  1	-	2    A -> D		2	A -> D		5B			N . . . . . Z .	TCD
+
+TCS	  1	-	2    A -> S			A -> S		1B			. . . . . . . .	TCS
+TDC	  1	-	2    D -> A		2	D -> A		7B			N . . . . . Z .	TDC
+TSC	  1	-	2    S -> A		2	S -> A		3B			N . . . . . Z .	TSC
+TSX	  1	Px	2    SL -> XL		2	S -> X		BA			N . . . . . Z .	TSX
+
+TXA	  1	Pm	2    XL -> AL		2	X -> A		8A			N . . . . . Z .	TXA
+TXS	  1	-	2    see note 4		2	X -> S		9A			. . . . . . . .	TXS
+TXY	  1	Px	2    XL -> YL		2	X -> Y		9B			N . . . . . Z .	TXY
+TYA	  1	Pm	2    YL -> AL		2	Y -> A		98			N . . . . . Z .	TYA
+
+TYX	  1	Px	2    YL -> XL		2	Y -> X		BB			N . . . . . Z .	TYX
+XCE	  1	-	2    see note 5		2	see note 5	FB			. . . . . . . C	XCE
+
+See Notes on page 13.
+
+
+
+
+		Table 7. Other Addressing Mode Instructions
+
+
+							    Status
+Mnemonic  Addressing Mode	Opcode Cycles Bytes	N V M X D I Z C	   Mnemonic	Function
+
+ BRK	stack			  00	7/8	2	. . . . 0 1 . .		BRK	See discussion in Interrupt Processing Sequence section.
+ BRL	relative long		  82	 3	3	. . . . . . . .		BRL	PC+r -> PC where -32768 < r < 32767.
+ COP	stack			  02	7/8	2	. . . . 0 1 . .		COP	See discussion in Interrupt Processing Sequence section.
+ JML	absolute indirect	  DC	 6	3				 	JMLW -> PC, B-PB
+
+ JMP	absolute		  4C	 3	3	. . . . . . . .		JMP	W -> PC
+ JMP	absolute indirect	  6C	 5	3	. . . . . . . .		JMP	W -> PC
+ JMP	absolute indexed indirect 7C	 6	3	. . . . . . . .		JMP	W -> PC
+ JMP	absolute long		  5C	 4	4				JMP	W -> PC, B -> PB
+
+ JSL	absolute long		  22	 8	4	. . . . . . . .		JSL	PB -> Bs, S-1 -S, PC -> Ws, S-2 -> S, W -> PC,	B -> PB
+ JSR	absolute		  20	 6	3	. . . . . . .		JSR	PC -> Ws, S-2 -> S, W -> PC
+ JSR	absolute indexed indirect FC	 6	3	. . . . . . . .		JSR	PC -> Ws, S-2 -> S, W -> PC
+ MVN	block			  54  7/byte	3	. . . . . . . .		MVN	See discussion in Addressing Mode section
+ MVP	block			  44  7/byte	3	. . . . . . . .		MVP
+ REP	immediate		  C2	 3	2	N V M X D I Z C		REP	P /\ /B -> P
+ RTI	stack			  40	6/7	1	N V M X D I Z C		RTI	S+1 -> S, Bs -> P, S+2 -> S, Ws -> PC,
+											 if E=0 then S+1 -> S, Bs -> PB
+
+ RTL	stack			  6B	 6	1	. . . . . . . .		RTL	S+2 -> S, Ws~1 -> PC, S+1 -> S, Bs -> PB
+
+ RTS	stack			  60	 6	1	. . . . . . . .		RTS	S+2 -> S, Ws+1 -> PC
+ SEP	immediate		  E2	 3	2	N V M X D I Z C		SEP	PVB -> P
+ STP	implied			  DB	 3+	1	. . . . . . . .		STP	Stop the clock. Requires reset to continue.
+ WAI	implied			  CB	 3+	1	. . . . . . . .		WAI	Wait for inte-rupt. RDY held low until Interrupt.
+ XBA	implied			  EB	 3	1	N . . . . . Z .		XBA	Swap AH and AL. Status bits reflect final condition of AL.
+
+Notes on page 13.
+
+
+
+				16

+ 61 - 0
files/docs/snes/65816/intrrpts.txt

@@ -0,0 +1,61 @@
+
+	Interrupt Processing Sequence
+
+
+The interrupt processing sequence is initiated as the direct result of hard-
+vare Abort, Interrupt Request, Non-Maskable Interrupt, or Reset inputs.
+The interrupt sequence can also be initiated as a result of the Break or
+Co-Processor instructions within the software. The following listings
+describe the function of each cycle in the interrupt processing sequence:
+
+
+Hardware Interrupt /ABORT, /IRQ, /NMI, /RES Inputs
+
+Cycle No.
+ E = 0 E = 1 Address  Data   R/W  SYNC VDA VPA  VP Description
+
+   1     1    PC        X     1    1    1   1   1  Internal Operation
+   2     2    PC        X     1    0    0   0   1  Internal Operation
+   3    [1]    S       PB     0    0    1   0   1  Write PB to Stack, S-1ÑS
+   4     3     S     PCH [2] 0[3]  0    1   0   1  Write PCH to Stack, S-1ÑS
+   5     4     S     PCL 12] 0[3]  0    1   0   1  Write PCL to Stack, S-1ÑS
+   6     5     S      P [4]  0[3]  0    1   0   1  Write P to Stack, S-1ÑS
+   7     6    VL      (VL)    1    0    1   0   0  Read Vector Low Byte,
+							 0->PD, 1->P1, OO->PB
+   8     7    VH      (VH)    1    0    1   0   0  Read Vector High 8yte
+
+
+Software Interrupt - BRK, COP Instructions
+
+Cycle No.
+ E = 0 E = 1 Address  Data   R/W  SYNC VDA VPA  VP Description
+   1     1   PC-2       X     1    1    1   1   1  Opcode
+   2     2   PC-1       X     1    0    0   1   1  Signature
+   3    111    S       PB     0    0    1   0   1  Write PB to Stack, S-1ÑS
+   4     3     S       PCH    0    0    1   0   1  Write PCH to Stack, S-1 - S
+   5     4     S       PCL    0    0    1   0   1  Write PCL to Stack, S-1ÑS
+   6     5     S        P     0    0    1   0   1  Write P to Stack, S-1ÑS
+   7     6    VL      (VL)    1    0    1   0   0  Read Vector Low Byte,
+							 0ÑPo, 1ÑPl, 00ÑPB
+   8     7    VH      (VH)    1    0    1   0   0  Read Vector High Byte
+
+Notes:
+	[1] Delete this cycle in Emulation mode.
+	[2] Abort writes address of aborted opcode.
+	[3] R/W remains in the high state during Reset.
+	[4] In Emulation mode, bit 4 written to stack is changed to 0.
+
+
+
+	Table 3. Vector Locations
+
+				Emulation   Native	Priority
+	Name	Source		(E = 1)	    (E = 0)	Level
+
+	ABORT	Hardware	00FFF8,9    00FFE8,9	 2
+	BRK	Software	00FFFE,F    00FFE6,7	N/A
+	COP	Software	00FFF4,5    00FFE4,5	N/A
+	IRQ	Hardware	00FFFE,F    00FFEE,F	 4
+	NMI	Hardware	00FFFA,B    00FFEA,B	 3
+	RES	Hardware	00FFFC.D    00FFFC,D	 1
+

+ 117 - 0
files/docs/snes/65816/mnemonic.txt

@@ -0,0 +1,117 @@
+
+    Table 4. G65SC802 and G65SC816 Instruction Set -- Alphabetical Sequence
+
+	ADC	Add Memory to Accumulator with Carry
+	AND	"AND" Memory with Accumulator
+	ASL	Shift One Bit Left, Memory or Accumulator
+	BCC*	Branch on Carry Clear (Pe = O)
+	BCS*	Branch on Carry Set (Pe = 1)
+	BEQ	Branch if Equal (Pz = 1)
+	BIT	Bit Test
+	BMI	Branch if Result Minus (PN = 1)
+	BNE	Branch if Not Equal (Pz = 0)
+	BPL	Branch if Result Plus (PN = 0)
+	BRA	Branch Always
+	BRK	Force Break
+	BRL	Branch Always Long
+	BVC	Branch on Overflow Clear (Pv = 0)
+	BVS	Branch on Overflow Set (Pv = 1)
+	CLC	Clear Carry Flag
+	CLD	Clear Decimal Mode
+	CLI	Clear Interrupt Disable Bit
+	CLV	Clear Overflow Flag
+	CMP*	Compare Memory and Accumulator
+	COP	Coprocessor
+	CPX	Compare Memory and Index X
+	CPY	Compare Memory and Index Y
+	DEC*	Decrement Memory or Accumulator by One
+	DEX	Decrement Index X by One
+	DEY	Decrement Index Y by One
+	EOR	Exclusive "OR" Memory with Accumulator
+	INC*	Increment Memory or Accumulator by One
+	INX	Increment Index X by One
+	INY	Increment Index Y by One
+	JML**	Jump Long
+	JMP	Jump to New Location
+	JSL**	Jump Subroutine Long
+	JSR	Jump to New Location Saving Return Address
+	LDA	Load Accumulator with Memory
+	LDX	Load Index X with Memory
+	LDY	Load Index Y with Memory
+	LSR	Shift One Bit Right (Memory or Accumulator)
+	MVN	Block Move Negative
+	MVP	Block Move Positive
+	NOP	No Operation
+	ORA	"OR" Memory with Accumulator
+	PEA	Push Effective Absolute Address on Stack (or Push Immediate Data on Stack)
+	PEI	Push Effective Indirect Address on Stack (add one cycle if DL f 0)
+	PER	Push Effective Program Counter Relative Address on Stack
+	PHA	Push Accumulator on Stack
+	PHB	Push Data Bank Register on Stack
+	PHD	Push Direct Register on Stack
+	PHK	Push Program Bank Register on Stack
+	PHP	Push Processor Status on Stack
+	PHX	Push Index X on Stack
+	PHY	Push index Y on Stack
+	PLA	Pull Accumulator from Stack
+	PLB	Pull Data Bank Register from Stack
+	PLD	Pull Direct Register from Stack
+	PLP	Pull Processor Status from Stack
+	PLX	Pull Index X from Stack
+	PLY	Pull Index Y form Stack
+	REP	Reset Status Bits
+	ROL	Rotate One Bit Left (Memory or Accumulator)
+	ROR	Rotate One Bit Right (Memory or Accumulator)
+	RTI	Return from Interrupt
+	RTL	Return from Subroutine Long
+	RTS	Return from Subroutine
+	SBC	Subtract Memory from Accumulator with Borrow
+	SEC	Set Carry Flag
+	SED	Set Decimal Mode
+	SEI	Set Interrupt Disable Status
+	SEP	Set Processor Status Bits
+	STA	Store Accumulator in Memory
+	STP	Stop the Clock
+	STX	Store Index X in Memory
+	STY	Store Index Y in Memory
+	STZ	Store Zero in Memory
+	TAX	Transfer Accumulator to Index X
+	TAY	Transfer Accumulator to Index Y
+	TCD*	Transfer Accumulator to Direct Register
+	TCS*	Transfer Accumulator to Stack Pointer Register
+	TDC*	Transfer Direct Register to Accumulator
+	TRB	Test and Reset Bit
+	TSB	Test and Set Bit
+	TSC*	Transfer Stack Pointer Register to Accumulator
+	TSX	Transfer Stack Pointer Register to Index X
+	TXA	Transfer Index X to Accumulator
+	TXS	Transfer Index X to Stack Polnter Register
+	TXY	Transfer Index X to Index Y
+	TYA	Transfer Index Y to Accumulator
+	TYX	Transfer Index Y to Index X
+	WAI	Wait for Interrupt
+	XBA*	Exchange AH and AL
+	XCE	Exchange Carry and Emulation Bits
+
+
+	*) Common Mnemonic Aliases
+
+		Mnemonic	Alias
+		BCC		BLT
+		BCS		BGE
+		CMP		CPA
+		DEC A		DEA
+		INC A		INA
+		TCD		TAD
+		TCS		TAS
+		TDC		TDA
+		TSC		TSA
+		XBA		SWA
+
+	**)	JSL should be recognized as equivalent to JSR
+			when it is specified with long absolute addresses.
+		JML is equivalent to JMP with long addressing forced.
+
+
+
+				-13-

+ 97 - 0
files/docs/snes/65816/opcodes.txt

@@ -0,0 +1,97 @@
+
+
+			Table 8. Opcode Matrix
+
+
+MSD                                                                     LSD                                                                      MSD
+--+-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------+--
+  |   0   |    1   |   2    |    3     |    4   |   5    |   6    |    7    |   8   |   9    |   A   |   B   |   C    |   D    |    E   |    F    |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+0 | BRK s |ORA(d,x)| COP s  | ORA d,s  | TSB d  | ORA d  | ASL d  | ORA [d] | PHP s | ORA #  | ASL A | PHD s | TSB a  | ORA a  | ASL a  | ORA al  | 0
+  |  2 8  |  2 6   |  2 8   |   2 4    |  2 5   |  2 3   |  2 5   |   2 6   |  1 3  |  2 2   |  1 2  |  1 4  |  3 6   |  3 4   |  3 6   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+1 | BPL r |ORA(d),y| ORA(d) |ORA(d,s),y| TRB d  | ORA d,x| ASL d,x|ORA [d],y| CLC i | ORA a,y| INC A | TCS i | TRB a  | ORA a,x| ASL a,x| ORA al,x| 1
+  |  2 2  |  2 5   |  2 5   |   2 7    |  2 5   |  2 4   |  2 6   |   2 6   |  1 2  |  3 4   |  1 2  |  1 2  |  3 6   |  3 4   |  3 7   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+2 | JSR a |AND(d,x)| JSL al | AND d,s  | BIT d  | AND d  | ROL d  | AND [d] | PLP s | AND #  | ROL A | PLD s | BIT a  | AND a  | ROL a  | AND al  | 2
+  |  3 6  |  2 6   |  4 8   |   2 4    |  2 3   |  2 3   |  2 5   |  2 6    |  1 4  |  2 2   |  1 2  |  1 5  |  3 4   |  3 4   |  3 6   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+3 | BMI r |AND(d),y| AND (d)|AND(d,s),y| BIT d,x| AND d,x| ROL d,x|AND [d],y| SEC i | AND a,y| DEC A | TSC i | BIT a,x| AND a,x| ROL a,x| AND al,x| 3
+  |  2 2  |  2 5   |  2 5   |   2 7    |  2 4   |  2 4   |  2 6   |  2 6    |  1 2  |  3 4   |  1 2  |  1 2  |  3 4   |  3 4   |  3 7   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+4 | RTI s |EOR(d,x)| reserve| EOR d,s  | MVP xya| EOR d  | LSR d  | EOR [d] | PHA s | EOR #  | LSR A | PHK s | JMP a  | EOR a  | LSR a  | EOR al  | 4
+  |  1 7  |  2 6   |  2 2   |   2 4    |  3 7   |  2 3   |  2 5   |  2 6    |  1 3  |  2 2   |  1 2  |  1 3  |  3 3   |  3 4   |  3 6   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+5 | BVC r |EOR(d),y| EOR (d)|EOR(d,s),y| MVN xya| EOR d,x| LSR d,x|EOR [d],y| CLI i | EOR a,y| PHY s | TCD i | JMP al | EORa,x | LSRa,x | EOR al,x| 5
+  |  2 2  |  2 5   |  2 5   |   2 7    |  3 7   |  2 4   |  2 6   |  2 6    |  1 2  |  3 4   |  1 3  |  1 2  |  4 4   |  3 4   |  3 7   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+6 | RTS s |ADC(d,x)| PER s  | ADC d,s  | STZ d  | ADC d  | ROR d  | ADC [d] | PLA s | ADC #  | ROR A | RTL s | JMP (a)| ADC a  | ROR a  | ADC al  | 6
+  |  1 6  |  2 6   |  3 6   |   2 4    |  2 3   |  2 3   |  2 5   |  2 6    |  1 4  |  2 2   |  1 2  |  1 6  |  3 5   |  3 4   |  3 6   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+7 | BVS r |ADC(d),y| ADC (d)|ADC(d,s),y| STZ d,x| ADC d,x| ROR d,x|ADC [d],y| SEI i | ADC a,y| PLY s | TDC i |JMP(a,x)| ADC a,x| ROR a,x| ADC al,x| 7
+  |  2 2  |  2 5   |  2 5   |   2 7    |  2 4   |  2 4   |  2 6   |  2 6    |  1 2  |  3 4   |  1 4  |  1 2  |  3 6   |  3 4   |  3 7   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+8 | BRA r |STA(d,x)| BRL rl | STA d,s  | STY d  | STA d  | STX d  | STA [d] | DEY i | BIT #  | TXA i | PHB s | STY a  | STA a  | STX a  | STA al  | 8
+  |  2 2  |  2 6   |  3 3   |   2 4    |  2 3   |  2 3   |  2 3   |  2 6    |  1 2  |  2 2   |  1 2  |  1 3  |  3 4   |  3 4   |  3 4   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+9 | BCC r |STA(d),y| STA (d)|STA(d,s),y| STYd,x | STA d,x| STX d,y|STA [d],y| TYA i | STA a,y| TXS i | TXY i | STZ a  | STA a,x| STZ a,x| STA al,x| 9
+  |  2 2  |  2 6   |  2 5   |   2 7    |  2 4   |  2 4   |  2 4   |  2 6    |  1 2  |  3 5   |  1 2  |  1 2  |  3 4   |  3 5   |  3 5   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+A | LDY # |LDA(d,x)|  LDX # | LDA d,s  | LDY d  | LDA d  | LDX d  | LDA [d] | TAY i | LDA #  | TAX i | PLB s | LDY a  | LDA a  | LDX a  | LDA al  | A
+  |  2 2  |  2 6   |  2 2   |   2 4    |  2 3   |  2 3   |  2 3   |  2 6    |  1 2  |  2 2   |  1 2  |  1 4  |  3 4   |  3 4   |  3 4   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+B | BCS r |LDA(d),y| LDA (d)|LDA(d,s),y| LDY d,x| LDA d,x| LDX d,y|LDA [d],y| CLV i | LDA a,y| TSX i | TYX i | LDY a,x| LDA a,x| LDX a,y| LDA al,x| B
+  |  2 2  |  2 5   |  2 5   |   2 7    |  2 4   |  2 4   |  2 4   |  2 6    |  1 2  |  3 4   |  1 2  |  1 2  |  3 4   |  3 4   |  3 4   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+C | CPY # |CMP(d,x)| REP #  | CMP d,s  | CPY d  | CMP d  | DEC d  | CMP [d] | INY i | CMP #  | DEX i | WAI i | CPY a  | CMP a  | DEC a  | CMP al  | C
+  |  2 2  |  2 6   |  2 3   |   2 4    |  2 3   |  2 3   |  2 5   |  2 6    | 1 2   |  2 2   |  1 2  |  1 3  |  3 4   |  3 4   |  3 4   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+D | BNE r |CMP(d),y| CMP (d)|CMP(d,s),y| PEI s  | CMP d,x| DEC d,x|CMP [d],y| CLD i | CMP a,y| PHX s | STP i | JML (a)| CMP a,x| DEC a,x| CMP al,x| D
+  |  2 2  |  2 5   |  2 5   |   2 7    |  2 6   |  2 4   |  2 6   |  2 6    |  1 2  |  3 4   |  1 3  |  1 3  |  3 6   |  3 4   |  3 7   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+E | CPX # |SBC(d,x)| SEP #  | SBC d,s  | CPX d  | SBC d  | INC d  | SBC [d] | INX i | SBC #  | NOP i | XBA i | CPX a  | SBC a  | INC a  | SBC al  | E
+  |  2 2  |  2 6   |  2 3   |   2 4    |  2 3   |  2 3   |  2 5   |  2 6    |  1 2  |  2 2   |  1 2  |  1 3  |  3 4   |  3 4   |  3 6   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+F | BEQ r |SBC(d),y| SBC (d)|SBC(d,s),y| PEA s  | SBC d,x| INC d,x|SBC [d],y| SED i | SBC a,y| PLX s | XCE i |JSR(a,x)| SBC a,x| INC a,x| SBC al,x| F
+  |  2 2  |  2 5   |  2 5   |   2 7    |  3 5   |  2 4   |  2 6   |   2 6   |  1 2  |  3 4   |  1 4  |  1 2  |  3 6   |  3 4   |  3 7   |   4 5   |
+  |-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------|
+  |   0   |    1   |   2    |    3     |    4   |   5    |   6    |    7    |   8   |   9    |   A   |   B   |   C    |   D    |    E   |    F    |
+--+-------+--------+--------+----------+--------+--------+--------+---------+-------+--------+-------+-------+--------+--------+--------+---------+--
+
+
+
+	Symbol		Addressing mode
+
+	  #		immediate
+	  A		accumulator
+	  r		program counter relative
+	  rl		program counter relative long
+	  i		implied
+	  s		stack
+	  d		direct
+	  d,x		direct indexed (with x)
+	  d,y		direct indexed (with y)
+	 (d)		direct Indirect
+	 (d,x)		direct indexed Indirect
+	 (d),y		direct Indirect indexed
+	 [d]		direct indirect long
+	 [d],y		direct indirect indexed long
+	  a		absolute
+	  a,x		absolute indexed (with x)
+	  a,y		absolute indexed (with y)
+	  al		absolute long
+	  al,x		absolute indexed long
+	  d,s		stack relative
+	 (d,s),y	stack relative indirect Indexed
+	 (a)		absolute indirect
+	 (a,x)		absoite Indxed Indirect
+	  xya		block move
+
+
+
+	Legend
+		Instruction mnemonic		Addressing mode
+
+		Base number of base number	Cycles
+		of bytes
+

+ 188 - 0
files/docs/snes/65816/scnfrmt.txt

@@ -0,0 +1,188 @@
+[Image]
+
+                             SNES Screen Format
+
+[Image]
+
+
+                SNES GRAPHICS INFO FILE V1.0
+                ----------------------------
+                     By DAX on 28/2/93
+
+This is a short text file on how the data for the gfx on the SNES are
+set up..
+Everything is based around an 8x8 pixel 'Tile' and thinking in terms of
+tiles makes the whole thing a lot easier.
+
+4 Colour mode - 2 Bitplanes
+---------------------------
+If you split the screen into 8x8 pixel tiles, the order of the graphics data
+is tile 0,1,2,3,4 etc.(with tile 0 being the first, and 1 being the one on
+the right of it.)
+
+Then for each tile, the data is stored as shown below.
+        00 01 02 03 04 05 06 07
+        10 11 12 13 14 15 16 17    Each number representing one pixel in
+        20 21 22 23 24 25 26 27    the 8x8 tile.
+        30 31 32 33 34 35 36 37
+        40 41 42 43 44 45 46 47
+        50 51 52 53 54 55 56 57
+        60 61 62 63 64 65 66 67
+        70 71 72 73 74 75 76 77
+
+The data is stored in the SNES binary in the following format.
+        Bitplane 0 ..   Line 00-07 (One Byte)
+                        Line 10-17
+                        Line 20-27
+                        Line 30-37
+                        Line 40-47
+                        Line 50-57
+                        Line 60-67
+                        Line 70-77
+then    Bitplane 1 ..   Line 00-07
+                        Line 10-17
+                        Line 20-27
+                        Line 30-37
+                        Line 40-47
+                        Line 50-57
+                        Line 60-67
+                        Line 70-77
+then comes the data for the next tile (the one on the right).etc.
+
+16 Colour - 4 Bitplanes
+-----------------------
+The data for this mode is stored in the same format, with one main change.
+The data is stored in the format
+        Bitplane 0 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 1 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 2 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 3 ..   Line 00-07
+                               |
+                        Line 70-77
+
+then the data for the next tile.
+
+256 Colour - 8 Bitplanes
+------------------------
+This is simply an expansion of the 4 and 16 colour modes.
+        Bitplane 0 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 1 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 2 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 3 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 4 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 5 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 6 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 7 ..   Line 00-07
+                               |
+                        Line 70-77
+
+then the data for the next tile.
+
+256 Colours - Mode 7 format
+---------------------------
+This has some very major differences to the other graphics data formats
+
+there are two mode7 modes, normal and EXTBG, the data is stored in the
+same way in both, apart from in EXTBG the Bitplane 7 value will be a
+priority bit for the pixel, which cuts the colours down to 128.
+
+Each byte of 'graphics data' is actually the colour value for that pixel
+on the screen, so if the value is 64, then the colour of that pixel will
+be the contents of colour register 64.
+
+The data is stored in VRAM differently to the other modes, with the tile
+numbers, and the graphics data 'interleaved', starting at $0000 in VRAM,
+with alternate bytes containing one byte of tile, one byte of gfx - this
+is shown below.
+
+        Word of VRAM.        HI                         LO
+        Bit  15  14  13  12  11  10  09  08  07  06  05  04  03  02  01  00
+content     |------------------------------||------------------------------|
+               Graphics data(CHAR DATA)             Tile number(NAME)
+
+Because of the storing of 16 bit data in reverse format (LO-HI) this means
+that if you set the VRAM addr to $0.the first byte written should be the
+tile name for that position on screen and the second byte should be the first
+byte of the Mode7 graphics data.if the VRAM addr is set to $1 the first byte
+written will be the tile name for that position on scr, and the second byte
+should be the second byte of the mode7 graphics data.
+  ETC
+
+In mode7 you can only have a maximum of 256 tiles, because of the fact that
+the mode7 data only takes up the first half of VRAM(32k) you can only have 16k
+of graphics data which is 256 tiles of 8x8 with 256 colours.
+This is quite a limitation, but can be used quite effectively.
+
+The tile numbers are stored in a format according to a 128x128 tile screen
+so tile 128($80) would be the tile below 0($0) on the screen, and so on.
+so VRAM addr $0 is the top left tile, and $1 is the one on the right of it
+$80 is the one on the left side, one row down.
+
+the graphics data is stored based on an 8x8 tile again.
+but slightly different.
+Each byte(pixel) is stored so...
+                        Bit number    Contents
+                                0          Bitplane 0 pixel value
+                                1          Bitplane 1 pixel value
+                                2          Bitplane 2 pixel value
+                                3          Bitplane 3 pixel value
+                                4          Bitplane 4 pixel value
+                                5          Bitplane 5 pixel value
+                                6          Bitplane 6 pixel value
+                                7          Bitplane 7 pixel value /
+                                           (EXTBG mode - Priority value)
+
+The data is then stored in the sequence
+                00,01,02,03,04,05,06,07
+                10,11,12,13,14,15,16,16  (Look at diagram at start of file
+                    |      |      |       for explanation)
+                70,71,72,73,74,75,76,77
+
+with one byte for each position(pixel), according to the 8x8 tile format,
+with one tile after another.
+
+---------------------------------------------------------------------------
+I hope this text file helps those of you having trouble converting graphics
+for use on the SNES, I have been asked a few times recently for this info
+so I decided to type up this short text file on it.
+Hopefully it should explain it!
+
+
+
+                                  [Image]
+
+                         © 1996 Damaged Cybernetics
+
+
+
+                                  [Image]

+ 14 - 0
files/docs/snes/65816/thetrip.tag

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+
+    This File Passed thru:
+        _                            _                       _
+       /{____________  ___________  /{_______________________)\
+       \\ ;   ----._/:\ :     --./  \\ ;   ----._/  .\.  ,/ _  \
+        \.        / :: \.      ;/    \.        /  /; /.  | /_; :
+         \_|     /      |   ___/      \_|     //  ` / :  :;   ,/
+           |   |/|  ..  |.    \         |   |/;  .  \ |  |;  |
+          /.    \|  :.  |;  __/\       /.    \   \  .\|. |.  |
+          \___  / \ || /____.  ')      \___ ./_ "/_  /____\ /
+              \/   \||/     \ ;/           \/  \/  \/      V
+                             )/
+                             `                   T1! 207.8.XXX.XX
+                             SiteOp: Stumble

+ 2762 - 0
files/docs/snes/65816info.txt

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+                               A 65816 Primer
+
+       [----------------------------------------------------------]
+
+No republication or redistribution of the following is permitted without
+the authors express written consent.
+
+Table of Contents
+
+  ------------------------------------------------------------------------
+
+     i    Preface
+     1.00 Introduction
+     2.00 New 65816 Instructions
+     3.00 65816 Native Mode Programming Model
+     3.01    Native Mode Processor Status Register
+     3.10 Native Mode Registers
+     3.11    Accumulator:
+     3.12    X,Y Index Registers
+     3.13    Direct Page Register (D)
+     3.14    Stack Pointer (S)
+     3.15    Program Bank Register (PBR)
+     3.16    Data Bank Register (DBR)
+     3.20    Status Register
+     3.21       Emulation Bit E: Hidden Bit
+     3.22       Sixteen BIT User Registers
+     3.23       Index Register Select
+     3.24       Accumulator/Memory Select
+     3.30    Setting Status Register Bits
+     4.00 65816 Emulation Mode Programming Model
+     4.10    Emulation Mode Registers
+     5.00 Relocating the Stack and Direct Page
+     6.00 Addressing Modes
+     6.10       New 65816 Specific Addressing Modes
+     6.20       Addressing Mode Descriptions
+     7.00 Interrupts
+     7.10      Hardware Vectors
+
+     Appendix A: 65816 Instruction Set
+     Appendix B: Composite Instruction List
+     Appendix C: IC Pinouts
+
+Disclaimer:
+
+Some of the following information was referenced with various documents and
+public documentation available for the Apple IIGS computer system and the
+Super NES game console system via the world wide web and other user group
+publications. No claim is made or intended against any copyrighted
+information that may be contained within this document. The main
+sub-content that could be construed as a copyright infringement, would be
+the usage of mnemonic tables and the similarity of programming models.
+Although these tables were built specifically for this project, it is
+unclear what the legal status of mnemonic information is at present. Brett
+Tabke 1997
+
+This document is intended to aid those programming the 65816 Processor from
+The Western Design Center. This chip is the basis for the Apple IIGS, the
+Creative Micro Designs SuperCPU addon cartridge for the Commodore 64 & 128,
+and the Super NES game console that are all based around the 65816 micro
+processor.
+
+  ------------------------------------------------------------------------
+
+Preface
+
+This document was pulled from several chapters of book project I had
+started. I'd intended to publish a small booklet on programming the CMD
+Super CPU cartridge detailing the operation of the 65816 - however, I have
+been unable to acquire a release to republish some critical information.
+So, the following is a few chapters that I feel are worthy of public
+disclosure and distribution.
+
+HTML Conversion Notes
+
+This document was originally in IBM CG/ANSI format and the conversion to
+HTML was marginal. Even with the file being fairly generic text, four
+different browsers rendered it differently. Lynx 2.7 and Lynx 2.6 will not
+render it the same - I tried to strike a happy medium - your mileage may
+vary.
+
+TOC
+                               [ Image Jet ]
+
+  ------------------------------------------------------------------------
+
+1.00 Introduction
+-----------------
+
+Welcome to the world of 65816 programming. The 65816 is an advanced upgrade
+to the vintage 6502 Central Processing Unit. The main new features include
+full 24 bit addressing for direct memory access of up to 16 megabytes.
+Additionally, the 65816 offers full 6502 emulation, new addressing modes,
+full 16 bit user registers, and dozens of new instructions.
+
+If you have been a 6502 programmer for long, the advantages of the 65816
+will become clear very quick. Regardless of CPU operating speed (mhz) a the
+65816 will operate a bit faster simply by the nature of the 16 bit user
+registers. By using 16 bit registers for operations such as addition and
+subtraction the 65816 also offers the programmer a substantial speed
+increase.
+
+The following document is not meant as a definitive guide to programming
+the 65816, but rather a primer for those who are familiar with the 6502 and
+wish to find the new 65816 (good) stuff.
+
+The 65816 offers two primary modes of operation, Native 65816 Mode and 6502
+emulation mode. The default power-up status of the processor is in 6502
+emulation mode. Other than correcting a few bugs in the 6502, emulation
+mode "looks and feels" just like a 6502.
+
+There are a few notable differences between the 65816's emulation mode and
+the original 6502. The 6502 opcodes that were unimplemented, are now
+available as additional instructions on the 65816, thus they will not
+produce the results they do on a stock NMOS 6502 CPU. The 65816 implements
+ALL of the available 256 opcodes, whether in emulation or Native mode.
+
+Also different between a 6502 and emulation mode is that the indirect jump
+JMP ($XXXX) bug that caused the processor to retrieve the wrong data when
+the low byte was $xx has been fixed.
+
+While in emulation mode, the 65816's Direct (zero) Page register is set for
+zero. The Stack pointer high byte is set for one (just as a 6502). The
+Program and Data Bank Registers are initialized to zero. Timing of all
+instructions is identical.
+
+While in Native mode, the processor has full access to the 16 megabyte
+address space via 24 bit addressing. Native mode also makes available
+several new and extended processor registers. The 65816 has the ability to
+relocate the Stack and Zero Page any where within the first 64k bank of
+memory. For old Commodore 128 programmers, this will sound suspiciously
+like the 128's Memory Management Units ability to relocate zero page and
+the stack also - so it will be old hat from the start. (On a side note, it
+will be interesting to program on CMD's Super CPU 128 - which will give you
+a Relocatable Relocatable Zero Page and Stack. hmmm ;)
+
+Native mode also opens up the world of 16 bit user registers. The
+accumulator may be 8 or 16 bits and the XY index registers may also be 8 or
+16 bits. The accumulator maybe seen in terms of two 8 bit registers with
+one accessible and the other hidden, or as a full 16 bit register. While
+the accumulator is set for 16 bits, memory is also treated in 16 bit (2
+byte) fashion.
+
+Two other new registers are the Data Bank Register and the Program Bank
+register. The Program Bank Register functionally extends the program
+counter out to 24 bits, while the Data Bank register allows code flow
+control to branch or jump to points outside of the 6502's 64k address
+space.
+
+Lastly, while in Native mode the status register of the 65816 includes
+several new bits. The old BRK bit is no longer needed as the 65816 has a
+BRK hardware vector. The BRK bit is now replaced with the X bit to select
+either 8 or 16 bit index registers. However while in emulation mode, the
+BRK bit is still there. The old "reserved" bit 5 of the status register is
+replaced with the 16/8 bit accumulator/memory select bit. There is also a
+hidden emulation bit that is only accessible by exchanging it will the
+carry flag.
+
+Here is a run down of some of the new fun stuff:
+
+   * XYA registers can be 16 or 8 bits wide.
+   * Wow, two actual Block Move Memory instructions.
+   * New push/pull instructions phx,plx,phy,ply.
+   * New xfer instructions tyx,txy.
+   * Set or Reset any memory bit without loading the accumulator.
+   * INC and DEC the accumulator.
+   * JSR indirect, Branch Always, or Branch Long to 64k.
+   * Zero Page has been renamed to Direct Page. Like many strange things,
+     this will be totally confusing at first. The only thing you can do is,
+     "get over it and get on with it".
+
+TOC
+
+2.00 New 65816 Instructions:
+----------------------------
+
+There are some new instructions worthy of short detail:
+
+New transfer instructions include:
+
+     TXY,TYX xfer between x and y.
+     TCD,TCD xfer between the accumulator and direct page pointer(D).
+     TCS,TSC xfer between the accumulator and stack pointer(S).
+     XBA     exchange the low 8 bits (a) and the high 8 bits
+                    of the accumulator.
+     XCE     exchange the contents of the emulation bit (E) with
+                    the contents of the carry flag (C).
+
+New Stack pushes and pulls:
+
+     PHX,PHY,PLX,PLY  push and pull the XY index registers.
+     PHB,PLB     to push/pull the data bank register.
+     PHK         to push the program bank register (no pull present)
+     PHD,PLD     to push/pull the direct page register.
+     PEA         to push effect absolute address.
+     PEI         to push effective indirect address.
+     PER         to push effective relative address.
+
+   Misc:
+     MVN   Move block in negative direction.
+     MVP   Move block in positive direction.
+     STZ   Store a zero to any location.
+     BRA   Branch always.
+     BRL   Branch to any address in bank 0 (64k).
+     RTL   Return Long. Pulls one more byte. (pc bank byte)
+
+As you can see, there is plenty new to digest. The remainder of this
+document will assume prior 6502 knowledge. Lets go.
+TOC
+
+  ------------------------------------------------------------------------
+
+==========================================
+3.00 65816 Native Mode Programming Model
+==========================================
+  ------------------------------------------------------------------------
+
+Bits:23                          15                    7                 0
+                                 /--------------------l-------------------\
+                                 IAccumulator (B) (A or C) Accumulator (A)I
+                                 \--------------------I-------------------/
+     /--------------------------\
+     I Data Bank Register (DBR) I
+     \--------------------------/
+                                 /--------------------l-------------------\
+                                 I           X Index  I Register (X)      I
+                                 \--------------------I-------------------/
+                                 /--------------------l-------------------\
+                                 I           Y Index  I Register (Y)      I
+                                 \--------------------I-------------------/
+      ---------------------------/--------------------l-------------------\
+     |         0 0 0 0 0 0 0 0   I             Direct I Page Pointer (D)  I
+      ---------------------------\--------------------I-------------------/
+      ---------------------------/--------------------l-------------------\
+     |         0 0 0 0 0 0 0 0   I             Stack  I Pointer (S)       I
+      ---------------------------\--------------------I-------------------/
+     /---------------------------l--------------------l-------------------\
+     IProgram Bank Register(PBR) I            Program I Counter (PC)      I
+     \---------------------------I--------------------I-------------------/
+
+===================================
+3.01 Processor Status Register (P)
+===================================
+
+Bits  7   6   5   4   3   2   1   0
+                                /---\
+                                I e --- Emulation 0 = Native Mode
+    /---l---l---l---l---l---l---+---I
+    I n I v I m I x I d I i I z I c I
+    \-l-I-l-I-l-I-l-I-l-I-l-I-l-I-l-/
+      I   I   I   I   I   I   I   \-------- Carry 1 = Carry
+      I   I   I   I   I   I   \------------- Zero 1 = Result Zero
+      I   I   I   I   I   \---------- IRQ Disable 1 = Disabled
+      I   I   I   I   \------------- Decimal Mode 1 = Decimal, 0 = Binary
+      I   I   I   \-------- Index Register Select 1 = 8-bit, 0 = 16-bit
+      I   I   \-------- Memory/Accumulator Select 1 = 8-bit, 0 = 16 bit
+      I   \----------------------------- Overflow 1 = Overflow
+      \--------------------------------- Negative 1 = Negative
+
+65816 Native Mode Programming Model
+
+TOC
+
+======================================
+3.10 Native Mode Registers
+======================================
+
+3.11 Accumulator
+-----------------
+
+Although shown as a 16 bit register, it may be either 16 or 8 depending on
+the status of bit 5 (memory/accumulator select) of the status register bit
+designated M.
+
+When in 8 bit mode (M=1) then the accessible low order 8 bit accumulator is
+designated as A and the hidden but exchangeable is designated B. When in
+full 16 bit accumulator mode (M=0) then the accumulator is designated as C.
+
+3.12 X,Y Index Registers
+-------------------------
+
+The X and Y index registers are 8 or 16 bit selectable. When status
+register bit 4 designated X is set to 1 then 8 bit registers are selected.
+When set to 0 then 16 bit registers are selected.
+
+TOC
+
+3.13 Direct Page Register (D)
+------------------------------
+
+This register is formerly known as Zero Page. The Direct Page pointer
+specifies where in the first bank of 64k Direct Page (zero page) will be
+located. The Direct Page may be moved to ANY location within Bank 0.
+
+The Bank byte (bits 16-23) is shown in a dashed line to represent the fact
+that the Direct Page is always located within bank 0.
+
+3.14 Stack Pointer (S):
+-----------------------
+
+Like the Direct (zero) Page Pointer, the Stack is now totally relocatable
+within Bank 0 (first 64k) of memory. The Bank byte (bits 16-23) is shown in
+a dashed line to represent the fact that the Stack is always located within
+bank 0. While in Native Mode the stack is not restricted to 256 bytes in
+length.
+while in emulation mode (e=1) the stack is located at page 1.
+
+TOC
+
+3.15 Program Bank Register (PBR):
+---------------------------------
+
+Much like the DBR below, the Program Bank Register is used to specify
+address's above and beyond the 6502 64k limit. The PBR is referred to as
+the Bank Byte or the highest 8 bits of the Program Counter. Flow control
+instructions such as JSR and JMP, may jump to full 23 bit address's. The
+PBR is used to specify the highest order 8 bits of the effective address.
+However; relative branches do not roll out of the current bank. Branch
+commands that branch across $FFFF roll back into the current bank. Also;
+program segments may not cross bank boundaries - the program counter goes
+from $FFFF to $0000 during such and occurrence.
+
+3.16 Data Bank Register (DBR):
+------------------------------
+
+Certain addressing modes take advantage of the 65816's ability to address
+up to 16meg of data. Those modes that retrieve and store data to absolute
+16 meg/(24 bit address's use the DBR as the top 8 bits of the effective
+address. The DBR is also referred to as the Data Bank Byte. The term Bank
+Byte is used so that High Byte still refers to bits 8-15 of a given
+location or register.
+
+When indexed addressing mode branch across 64k bank boundaries, DBR is
+temporarily incremented.
+
+TOC
+
+3.20 Status Register
+=====================
+
+The status register bits 7,6,3,2,1,0 (nvdizc) function the same as the 6502
+status register bits.
+
+The B break bit is no longer needed to detect a BRK. Instead a new hardware
+vector has been implemented to direct code flow to a OS ROM handler in the
+same way as an IRQ. However, while in emulation mode (E=1) BRK and the B
+bit work as a 6502 does.
+
+3.21 Emulation Bit E: Hidden Bit
+--------------------------------
+
+The emulation status bit E specifies whether the processor is in 6502
+emulation mode or Native 65816 mode. 1=emulation. The processor powers up
+in default 6502 emulation mode. When in 6502 emulation mode, the processor
+is functionally a 6502. With the exceptions of un implemented opcodes, all
+other opcodes perform identically to their true 6502 counter parts. In
+emulation mode, the stack is defined as page one, direct page is defined as
+page zero, and the Data Bank and Program Bank bytes are set to zero. The
+additional 65816 opcodes are also available in emulation mode.
+
+The emulation status bit is a hidden or phantom bit that is not directly
+set, tested, or cleared. Therefore, a new instruction is used to exchange
+the values of the carry bit and the emulation bit (XCE:eXchange Carry with
+emulation bit). After exchanging, the carry can be tested to determine the
+previous status of the E bit.
+
+    To switch to Native Mode use the following:
+
+        clc    ;clear carry to zero.
+
+        xce    ;exchange (swap) carry with the emulation bit.
+
+    To return to Emulation mode:
+
+        sec    ;set carry to one.
+        xce    ;exchange (swap) carry with the emulation bit.
+
+TOC
+
+3.22 Sixteen BIT User Registers
+--------------------------------
+
+The main advantage of the 65816 over the 6502 is that the Accumulator and
+the XY index registers can be toggle between 8 and 16 bits wide. The width
+of the Accumulator and the XY registers are independently selectable. Thus
+you may select any combination of either:
+
+       16 bit accum. m=0  - 16 bit XY regs x=0
+       16 bit accum. m=0  -  8 bit XY regs x=1
+        8 bit accum. m=1  - 16 bit XY regs x=0
+        8 bit accum. m=1  -  8 bit XY regs x=1
+
+When the accumulator is switched from or to 16 bits, the high order byte is
+retained in either direction.
+
+When the XY registers are switched from 16 bits to 8 bits, the high byte
+(bits 8-15) are lost. When switching the XY registers to 16 bits, the high
+byte becomes a zero.
+
+TOC
+
+3.23 Status Bit 4 X: Index Register Select
+-------------------------------------------
+
+Bit 4 of the status register selects either 8 bit or 16 bit XY index
+register operation. When x=1 (8 bit), the XY registers function identically
+to the 6502 index registers.
+
+When x=0 (16 bit), both the X and Y registers become 16 bits wide. All
+operations involving the X and Y registers act on all 16 bits of the index
+register.
+
+When switching from 8 to 16 or 16 to 8 bit index register, the high byte of
+either X or Y will be come zero.
+
+While in emulation mode (E=1) bit 4 is the B BRK flag bit.
+
+TOC
+
+3.24 Status Bit 5: Accumulator/Memory Select
+---------------------------------------------
+
+Bit 5 specifies whether the accumulator will be treated as an 8 bit or 16
+bit register. When in 16 bit mode (m=0) all operations involving the
+accumulator will act upon 16 bits of data. Such as, when in 16 bit mode, a
+standard load (lda $1000) will load the load by ($1000) in the low order 8
+bits of the accumulator and load ($1001) into the high order of the
+accumulator.
+
+When switching the accumulator from 16 to 8 or from 8 to 16 bits, the high
+byte is perfectly retained. While in 8 bit mode, the high byte of the
+accumulator (B) maybe exchanged with the low byte with the XBA instruction.
+
+While in emulation mode, bit 5 is not present.
+
+TOC
+
+3.30 Setting Status Register Bits
+----------------------------------
+
+Two new instructions have been added to 65816 Native mode to set and reset
+bits of the status register. The two instructions are SEP (set processor
+status bits) and REP (reset processor status bits). They both use a single
+byte operand to specify which bits should be set or reset. For example to
+set bit 4 of the status register to 1 for 8 bit registers:
+
+          SEP  #%00010000   ;set bit 4.
+
+Or to clear bit 4 for 16 bit XY index registers:
+
+          REP #%00010000   ;reset (clear) bit 4.
+
+You may set or reset more than 1 bit at a time. For example, to set both 16
+bit accumulator/memory and 16 bit XY registers use the following:
+
+          REP #%00110000   ;set 16 bit accum/xy registers.
+
+  ------------------------------------------------------------------------
+
+=============================================
+4.00 65816 Emulation Mode Programming Model I
+=============================================
+  ------------------------------------------------------------------------
+
+Bits:23                          15                    7                 0
+                                  --------------------l-------------------\
+                                 |Accumulator (B)    (C)   Accumulator (A)I
+                                  --------------------I-------------------/
+     /--------------------------\
+     I Data Bank Register (DBR) I
+     \--------------------------/
+                                                      /-------------------\
+                                                      I X Index Register  I
+                                                      \-------------------/
+                                                      /-------------------\
+                                                      I Y Index Register  I
+                                                      \-------------------/
+      ---------------------------l--------------------l-------------------\
+     |         0 0 0 0 0 0 0 0   I             Direct I Page Pointer (D)  I
+      ---------------------------I--------------------I-------------------/
+      ---------------------------l--------------------l-------------------\
+     |         0 0 0 0 0 0 0 0   I    0 0 0 0 0 0 0 1 I Stack Pointer (S) I
+      ---------------------------I--------------------I-------------------/
+     /---------------------------l--------------------l-------------------\
+     IProgram Bank Register(PBR) I            Program I Counter (PC)      I
+     \---------------------------I--------------------I-------------------/
+
+4.10 Emulation Mode Registers
+
+=============================
+
+TOC
+
+Emulation Mode Processor Status Register (P)
+--------------------------------------------
+
+Bits  7   6   5   4   3   2   1   0
+                                /---\
+                                I e --- Emulation 1 = 6502 Emulation Mode
+    /---l---l---l---l---l---l---+---I
+    I n I v I   I b I d I i I z I c I
+    \-l-I-l-I---I-l-I-l-I-l-I-l-I-l-/
+      I   I       I   I   I   I   \-------- Carry 1 = Carry
+      I   I       I   I   I   \------------- Zero 1 = Result Zero
+      I   I       I   I   \---------- IRQ Disable 1 = Disabled
+      I   I       I   \------------- Decimal Mode 1 = Decimal, 0 = Binary
+      I   I       \------------ Break Instruction 1 = BRK caused IRQ
+      I   I
+      I   \----------------------------- Overflow 1 = Overflow
+      \--------------------------------- Negative 1 = Negative
+
+              65816 Emulation Mode Programming Model.
+
+TOC
+
+The above 6502 emulation mode Programming Model shows some interesting
+features of the 65816 while in emulation mode. Even though 16 bit index
+registers are not available in emulation mode, you can still do the
+following:
+
+   * Relocate Direct Page.
+   * Use the stack addressing modes.
+   * Swap the lower A accumulator with the hidden B accumulator.
+   * The Program and Data Bank Registers can be changed.
+   * Use the new instructions.
+
+Things lost or changed in Emulation mode verses Native mode:
+
+   * The ability to use 16 bit user registers. The M and X bits of the
+     status register are returned to their 6502 form.
+   * The utility of the Block Move instructions. Block Move instructions
+     use the index registers to specify the source and destination
+     address's of a move - with only 8 bits available in emulation mode,
+     you can only move data within zero page because the high byte will
+     always be zero.
+   * Zero page addressing "wraps" in emulation mode, whereas in Native mode
+     it rolls into the next page.
+   * The stack pointer is ALWAYS on page one.
+
+When switching from emulation to native mode the processor replaces the B
+BREAK flag and bit 5 with the 65816 M and X flags, and sets them to one.
+This leaves the index registers and accumulator/memory into 8 bit mode
+(which is the same as emulation mode). The remaining bits in the status
+register are unchanged. The stack pointer remains at page one.
+
+When switching from native mode into emulation mode; the M and X status
+register bit disappear, putting the accumulator and index registers at 8
+bit. The X and Y low bytes are retained, but the high bytes are lost. The
+accumulator low and high bytes are retained. (of course the high byte is
+hidden but accessible with the XBA instruction). The stack pointer is
+returned to eights bits with the high byte forced to one and the high byte
+is lost.
+
+I think that after you work with the 65816 in emulation mode you will
+realize that it is not about what you lose over native mode, but how much
+you gain over a 6502. The fact that all of the extra opcodes and
+instructions are still available even in emulation mode, makes for a
+powerful processor even without the 16 bit registers.
+
+  ------------------------------------------------------------------------
+
+TOC
+
+5.00 Relocating the Stack and Direct Page:
+------------------------------------------
+
+On power-up, the Stack is set to page one and the direct page (Zero Page)
+to page zero. When in emulation mode (E=1) the Stack is initialized to Page
+one, and Zero page is initialized to Page zero to emulate the default
+status of the 6502.
+
+Relocating the Direct Page (formerly known as Zero Page) is accomplished by
+use of the PLD:pull direct page instruction.
+
+        LDA #$5900   ; lda with immediate 16 bit data.
+        PHA          ; on the stack with 16 bits.
+        PLD          ; pull it back into the direct page register.
+
+Always keep in mind that PLD pulls 16 bits (2 bytes) off the stack. You may
+also use the TCD:transfer C register to Direct page register. (the C
+register refers to the Accumulator as 16 bits)
+
+
+
+        LDA #$5900   ; load 16 bit accum with immediate 16 bit data.
+        TCD          ; transfer accum to direct page register.
+
+Although you generally will want to keep Direct Page starting on an even
+256 page boundary (low byte zero), you can specify a low byte address at
+any 1-255 value. However all of the Direct Page (zero page) addressing
+modes will add one clock cycle to the execution time if the low byte of the
+direct page register is other than zero.
+
+While in emulation mode, a direct page addressing mode where the index
+rolls out of direct page will wrap around to the beginning of the direct
+page, just as a 6502 does. For example:
+
+      LDX #$2C
+
+      LDA ($E0,X)
+
+Would yield an effective address of $0C and not $10C.
+
+While in Native mode, a direct page addressing mode where the index rolls
+out of direct page will wrap into the next page of memory. Using the
+example from above would yield the expected $10C effect address.
+
+For those old Commodore 128 programmers, the concept of a relocatable
+Direct Page is nothing new - we've been tweaking it on the MMU for years.
+However; relocating zero page to something other than a page boundary has
+some strong implications for the right style of code.
+
+The power behind changing the direct page, is the same as 6502 zero page
+addressing has always been. You can save bytes by using direct page
+addressing (zero page) modes and acquire faster execution times as well. It
+will take some time to find the best ways to program with a relocated
+direct page, but once mastered, you wont get along with out.
+
+TOC
+
+  ------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------
+
+=======================
+6.00 Addressing Modes
+=======================
+
+All 6502 and 65C02 addressing modes and opcodes are supported in 65816
+Native mode. Nine other new addressing modes are also supported in both
+emulation and Native mode. However; there are a few notable addressing
+differences between 816 Native mode and its 6502 counter part.
+
+While in emulation mode there is no page wraparound when using Zero Page
+Indexed addressing from a base address+index that "rolls over" $FF. While
+in Native 65816 mode indexes can be 16 bits, so if the base address+index
+rolls over into the next page the proper effective address in generated.
+With 16 bit index registers, a direct page addressing mode where indexing
+rolls over $FFFF the effective address roll back into the current bank not
+into the next bank (ie:lda $20,x where x is $FFFF will result in an
+effective address of $1F).
+
+When using absolute indexed addressing where the base address is $FF01 to
+$FFFF an index value that would cause the eFFective address to roll over
+$FFFF would result in the next ram bank being accessed. Whereas on a 6502
+there would be a wrap around into zero page.
+
+Remember that when index registers are 16 bit, that absolute indexed X or
+absolute indexed Y can now reach up to a full 64k! (ie: lda $6000,y where
+y=$2000 would result in an effective address of $8000).
+
+The 85618 also fixed the 6502 indirect JMP bug. A JMP ($12FF) now yields
+the proper address of $12FF-$1300.
+
+TOC
+
+6.10 New 65816 Specific Addressing Modes:
+-----------------------------------------
+        New Mode Name                             Example
+        -------------------------------------------------------
+        Program Counter Relative Long             BRL $1234
+        Stack Relative                            LDA 15,S
+        Stack Relative Indirect Indexed Y         LDA (9,S),Y
+        Block Move                                MVP 0,0
+        Absolute Long                             LDA $123456
+        Absolute Long Indexed X                   LDA $123456,X
+        Absolute Indexed Indirect                 JMP ($1234,X)
+        Absolute Indirect Long                    JMP [$1234]
+        Direct Page Indirect                      LDA ($12)
+        Direct Page Indirect Long                 LDA [$12]
+        Direct Page Indirect Long Indexed Y       LDA [$77],Y
+
+6.20 Addressing Mode Descriptions
+
+----------------------------------
+
+Program Counter Relative Long: BRL #$44
+
+Program Counter Relative Long extends the range of the branch instructions
+from the standard -127/+128 to 64k (+32767/-32768). Thus; the operand of
+the BRL branch command is 16 bits. This address mode will help enormously
+when writing relocatable code.
+
+Stack Relative: LDA 7,S
+
+Stack Relative addressing uses the Stack Pointer as a base address and then
+adds the one byte user supplied operand as an offset into the stack. The S
+specifies that this mode is Stack addressing via the stack pointer.
+
+When using Stack Relative Addressing you should keep in mind that the Stack
+Pointer will always point to the NEXT available spot on the stack. Thus, an
+operand of one will retrieve the last item pushed onto the stack. An
+operand of zero maybe useful to get another copy of the last thing PULLED
+off the stack - but, of course, if an interrupt hits, then you would be in
+trouble as the stack is manipulated via the interrupt routine.
+
+Stack Relative Indirect Indexed Y: LDA ($22,S),Y
+
+This addressing mode, locates and indirect address that points to the base
+data located elsewhere (same as zero page indirect indexed). This two byte
+instruction starts with the current location of the stack, then adds the
+first operand, and finally adds in the Y index as and offset.
+
+The value of this addressing mode is that suppose you have an address you
+pushed onto the stack, by using this mode you can easily reach to where the
+data was located.
+
+                10   LDY #0
+
+                20   LDA (1,S),Y   ; get the address 16 bits
+
+                30   TAX           ; save it in x
+
+                40   LDY #2
+
+                50   LDA (1,S),Y   ; get a second address
+
+
+
+In the example above, we start with the current stack pointer location as
+the base address. In line 20 we load from an offset of one (1,S) and then
+add in the offset to give the effective address. The above assumes we are
+in 16 bit index and 16 bit accumulator mode.
+
+     Block Move:                               MVP 0,0
+
+This is a major new addressing mode used by two instructions on the 65816.
+The two new instructions Block Move Positive and Block Move Negative can
+move up to 64K of data from one memory location to another. To setup a
+move, the accumulator is loaded with the number of bytes to copy, the X
+register is loaded with source address, and the Y register holds the
+destination address. Then issue the Block move instruction and data is
+moved at 7 cycles per byte.
+
+     Absolute Long:                            LDA $123456
+
+Absolute Long is used to locate any data within the 16 bit address space of
+the 65816. The operand is three bytes (24 bits long). The main usage of
+this addressing mode is to temporarily override the contents of the DBR
+Data Bank Register for the execution of the single instruction. If standard
+absolute addressing is used, then the bank byte is concatenated to the
+address from the DBR.
+
+
+
+ Absolute Long Indexed X: LDA $123456,X
+
+Absolute Long Indexed starts with the base operand and then adds the X
+index value to create an effective address. This is the same as 6502
+Absolute Indexed X, except the base operand is 24 bits wide. Note that the
+actual order of bytes is Opcode, low byte, high byte, bank byte and that it
+is up to the assembler to arrange the bytes in this order.
+
+ Absolute Indexed Indirect JMP ($1234,X)
+
+Absolute Indexed Indirect is a three byte instruction that creates the
+effective address by starting with the specified operand and then adding in
+the index value. Old 6502 programmers will recognize the following command
+lookup and execute example:
+
+               SEC
+               SBC "0"        ; subtract ascii zero off accumulator.
+               ASL            ; times two into a table.
+               TAX            ; into x as offset into word table.
+               LDA TABLE,X    ; get command address byte.
+               STA PTR        ; save in indirect pointer.
+               LDA TABLE+1,X  ; get table command address high byte.
+               STA PTR+1      ; save in pointer high byte.
+               JMP (PTR)      ; jump to command.
+
+               TABLE .WORD RUT1,RUT2,RUT3,...
+               PTR   .BYTE 0,0
+
+Using Absolute Indexed Indirect addressing it could be written in half the
+bytes and cycles:
+
+               SEC
+               SBC "0"        ; subtract ascii zero off accumulator.
+               ASL            ; times two into a table.
+               TAX            ; into x as index into word table.
+               JMP (TABLE,X)  ; jump to command.
+
+               TABLE .WORD RUT1,RUT2,RUT3,...
+
+A JMP Indexed Indirect [JMP ($1234,x)] assumes that the operand address is
+in the current program bank. A JMP indirect [JMP ($1234)] assumes that the
+operand address is in BANK ZERO.
+
+     Absolute Indirect Long                    JMP [$1234]
+
+This addressing mode will form and effective address from the location
+pointed to by the operand.
+
+     Direct Page Indirect                       LDA ($12)
+
+This instruction is two bytes long. The operand points to a 16 bit Direct
+Page (zero page) pointer that will form the effective address. For example,
+if the Direct Page pointer is $70, then the low byte with come from $70,
+and the high byte from $71, and the Bank Byte from $72. The bank byte will
+be the current data bank register.
+
+     Direct Page Indirect Long                 LDA [$12]
+
+This instruction is two bytes long. The operand points to a 24 bit Direct
+Page (zero page) pointer that will form the effective address. For example,
+if the Direct Page pointer is $70, then the low byte with come from $70,
+the high byte from $71, and the Bank Byte from $72. The bank byte will
+temporarily override the data bank register.
+
+     Direct Page Indirect Long Indexed Y       LDA [$77],Y
+
+This instruction in two bytes long and allows you to temporarily reach into
+any memory bank. The operand is a direct page (zero page) pointer. The
+address located at the direct page offset is three bytes long. First is the
+low byte, then high byte, followed by the bank byte of the base effect
+address. The Y index register is then added to this three byte destination
+address to form the effective address. Square brackets are used to denote
+that the address is a full 24 bit address and not a simple 16 bit address.
+
+TOC
+
+  ------------------------------------------------------------------------
+
+7.00 Interrupts
+---------------
+
+
+There are some quirks to 65816 interrupts that you should consider. If you
+are going to be writing native 65816 code you should give some
+consideration to how your interrupt routine is going to be handled. If you
+have written custom a IRQ routine that assumes Native mode, then your
+considerations are minor. However, if you are writing Native mode 65816
+code with 16 bit accumulator and/or 16 bit index registers, and you are
+using a stock kernal IRQ that assumes emulation mode, then you must do some
+coding to handle the discrepancies. In 6502 emulation mode, and IRQ pushes
+the program counter high, then pc low, and finally the status register on
+to the stack. When in Native mode an IRQ starts by stacking the following:
+
+    Program Counter Bank (PBR)
+
+    Program Counter High
+
+    Program Counter Low
+
+    Status Register
+
+Next; the status register decimal mode bit (d) is cleared (setting binary
+mode), and the IRQ flag is set (non NMI only). Finally, the program bank
+(PBR) is set to zero and the 65816 jumps through the IRQ hardware vector.
+
+The implications are that if the 65816 is running in emulation mode in a
+ram bank other than Bank zero, then the program bank is going to be lost
+(not good). There are two solutions to the problem. One is never to run in
+emulation mode outside of Ram Bank zero. Second; you could save off the
+current program bank value somewhere in Ram before running in emulation
+mode beyond Bank Zero.
+
+One thing that is unclear at this point, is if the CMD Super CPU can even
+handle a Native Mode IRQ. Native Mode features a new hardware vector table:
+
+TOC
+
+7.10 Hardware Vectors:
+----------------------
+     Native Mode           6502 Emulation Mode
+     -----------------------------------------
+     IRQ   $FFEE-$FFEF     IRQ/BRK $FFFE-$FFFF
+                           RESET   $FFFC-$FFFD
+     NMI   $FFEA-$FFEB     NMI     $FFFA-$FFFB
+     ABORT $FFE8-$FFE9     ABORT   $FFF8-$FFF9
+     BRK   $FFE6-$FFE7
+     COP   $FFE5-$FFE6     COP     $FFF4-$FFF5
+
+
+Notice that there is a separate BRK vector for Native mode, and no need to
+poll bit 5 for the brk flag. However when running in emulation mode,
+remember that bit 5 is still the BRK flag, and your IRQ will still need to
+check for the source of the IRQ.
+
+While in Native mode, a BRK instruction is two bytes. The Zero BRK opcode
+followed by an optional "signature" byte. This way, you can detect what BRK
+caused the vector to be taken for multiple BRK's while debugging.
+
+COP is for a coprocessor interrupt. (see the instruction COP)
+
+Notice in Native mode where the IRQ vector destinations are...hmm
+
+When an IRQ is triggered, the current instruction is completed before the
+interrupt is processed. This "interrupt latency" may be up to 7 clock
+cycles. If you are running a time critical IRQ you may want to examine the
+WAI:wait for interrupt instruction whereby you can stop the processor until
+and interrupt occurs.
+
+The ABORT vector listed above is taken when the 65816's Abort pin is pulled
+low. This pin is only available on the 65816.
+
+TOC
+
+  ------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------
+
+================================
+Appendix A: 65816 Instruction Set
+
+================================
+  ------------------------------------------------------------------------
+  ------------------------------------------------------------------------
+
+Syntax Conventions:
+
+   addr              two byte address.
+   addr/const        two byte value: either an address or a constant.
+   const             one- or two-byte constant.
+   destbk            64k bank to which string will be moved.
+   dp                one-byte direct page offset (6502 zero page).
+   label             label of code in same 64K bank as instruction.
+   long              three-byte address (includes bank byte)
+   nearlabel         label of code close enough to instruction to be
+                     reachable by a one-byte signed offset.
+   sr                one-byte stack relative offset.
+   srcebk            64k bank from which string will be moved.
+
+   Flags
+   Bits         76543210
+                nvmxdizc
+                       e
+
+                n - negative.
+                v - overflow.
+                m - 8/16 memory/accumulator.
+                x - 8/16 bit index registers.
+                d - decimal mode.
+                i - irq enable disable.
+                z - zero result.
+                c - carry.
+                e - emulation.
+  ------------------------------------------------------------------------
+
+ADC  Add with carry.
+
+When using 16 bit accumulator mode, as expected, a carry will be properly
+rolled over from bit 7 to bit 8 when generated by the operation. (ie: $FF+4
+= $0103 with 1 in high byte an 3 in low byte of the accumulator.) Thus
+carry need only be cleared when the low order bytes are added. Manual
+checking for carry above bit 15 will still have to be done just as when in
+8 bit accumulator mode.
+
+When in 16 bit mode, the low-order bits are located in the effective
+address, and the high order bits are located in the effective address plus
+one.
+
+     Flags Altered nv----zc
+                   n Set if most-significant bit of result is set.
+                   v Set if signed overflow.
+                   z Set if result is zero.
+                   c Set if overflow.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                     ADC #const     69      2*      2 | 1
+  Absolute                      ADC addr       6D      3       4 | 1
+  Absolute Long                 ADC long       6F      4       5 | 1
+  Direct Page                   ADC dp         65      2       3 | 1,2
+  Direct Page Indirect          ADC (dp)       72      2       5 | 1,2
+  Direct Page Indirect Long     ADC [dp]       67      2       6 | 1,2
+  Absolute Indexed,X            ADC addr,X     7D      3       4 | 1,3
+  Absolute Long Indexed,X       ADC long,X     7F      4       5 | 1
+  Absolute Indexed,Y            ADC addr,Y     79      3       4 | 1,3
+  Direct Page Indexed,X         ADC dp,X       75      2       4 | 1,2
+  DP Indexed Indirect,X         ADC (dp,X)     61      2       6 | 1,2
+  DP Indirect Indexed,Y         ADC (dp),Y     71      2       5 | 1,2,3
+  DP Indirect Long Indexed,Y    ADC [dp],Y     77      2       6 | 1,2
+  Stack Relative                ADC sr,S       63      2       4 | 1
+  SR Indirect Indexed,Y         ADC (sr,S),Y   73      2       7 | 1
+-----------------------------------------------------------------------
+  * Add 1 byte if m=0 (16-bit memory/accumulator).
+  1 Add 1 cycle if m=0 (16-bit memory/accumulator).
+  2 Add 1 cycle if low byte of Direct Page register is <>0.
+  3 Add 1 cycle if adding index crosses a page boundary.
+
+AND And Accumulator with Memory
+
+    Logically ANDs the data located at the effective address
+    specified by the operand and the accumulator.
+    If in 16 bit accumulator mode (m=0) Data ANDed from memory is
+    16 bits wide, the low byte is the effective address and the high
+    byte is the effective address+1.
+
+     Flags Altered n-----z-
+                   n Set if most significant bit of result is set.
+                   z Set if result of and is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    AND #const     29      2*      2 | 1
+  Absolute                     AND addr       2D      3       4 | 1
+  Absolute Long                AND long       2F      4       5 | 1
+  Direct Page                  AND dp         25      2       3 | 1,2
+  Direct Page Indirect         AND (dp)       32      2       5 | 1,2
+  DP Indirect Long             AND [dp]       27      2       6 | 1,2
+  Absolute Indexed,X           AND addr,X     3D      3       4 | 1,3
+  Absolute Long Indexed,X      AND long,X     3F      4       5 | 1
+  Absolute Indexed,Y           AND addr,Y     39      3       4 | 1,3
+  Direct Page Indexed,X        AND dp,X       35      2       4 | 1,2
+  DP Indexed Indirect,X        AND (dp,X)     21      2       6 | 1,2
+  DP Indirect Indexed,Y        AND (dp),Y     31      2       5 | 1,2,3
+  DP Indirect Long Indexed,Y   AND [dp],Y     37      2       6 | 1,2
+  Stack Relative (SR)          AND sr,S       23      2       4 | 1
+  SR Indirect Indexed,Y        AND (sr,S),Y   33      2       7 | 1
+----------------------------------------------------------------------
+   * Add 1 byte if m=0 (16-bit memory/accumulator).
+   1 Add 1 cycle if m=0 (16-bit memory/accumulator).
+   2 Add 1 cycle if low byte of Direct Page register is <>0.
+   3 Add 1 cycle if adding index crosses a page boundary.
+
+ASL Arithmetic Shift Left
+
+    Shifts all bits left with most significant bit moving into the
+    carry flag.  If in 16 bit accumulator mode (m=0), data shifted
+    is 16 bits.
+
+     Flags Altered n-----zc
+                   n Set if most significant bit of result is set.
+                   z Set if result is zero.
+                   c High bit (7 or 15) is moved into carry.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Accumulator                  ASL a          0A      1       2 |
+  Absolute                     ASL addr       0E      3       6 | 1
+  Direct Page                  ASL dp         06      2       5 | 1,2
+  Absolute Indexed,X           ASL addr,X     1E      3       7 | 1
+  Direct Page Indexed,X        ASL dp,X       16      2       6 | 1,2
+----------------------------------------------------------------------
+   1 Add 2 cycles if m=0 (16-bit memory/accumulator).
+   2 Add 1 cycle if low byte of Direct Page register is <>0.
+
+TOC
+
+Branching Instructions:
+-----------------------
+
+The following branch instructions work identically to a 6502 - therefore,
+no indepth discussion will be presented.
+Branching commands do not affect any status register flags. The single byte
+operand range is +128 to -127.
+
+        BCC Branch Carry Clear     alias BLT Branch Less Than.
+        BCS Branch Carry Set       alias BGE Branch Greater Than or Equal.
+        BEQ Branch Equal
+        BNE Branch Not Equal
+        BMI Branch Result Minus
+        BPL Branch Result Positive
+        BVC Branch Overflow Clear
+        BVS Branch Overflow Set
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Program Counter Relative     BCC near       90      2       2 | 1,2
+  Program Counter Relative     BCS near       B0      2       2 | 1,2
+  Program Counter Relative     BEQ near       F0      2       2 | 1,2
+  Program Counter Relative     BNE near       D0      2       2 | 1,2
+  Program Counter Relative     BMI near       30      2       2 | 1,2
+  Program Counter Relative     BPL near       10      2       2 | 1,2
+  Program Counter Relative     BVC near       50      2       2 | 1,2
+  Program Counter Relative     BVS near       70      2       2 | 1,2
+----------------------------------------------------------------------
+   1 Add 1 cycle if branch is taken.
+   2 Add 1 more cycle if in 6502 emulation mode (e=1).
+
+TOC
+
+New Branch Instructions:
+------------------------
+
+BRA Branch Always
+
+Branch always takes the operand branch without regard for the current state
+of the status register. The single byte operand range is +128 to -127. This
+instruction and the following BRL instruction ease the task of writing
+relocatable code.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Program Counter Relative     BRA near       80      2       3 | 1
+----------------------------------------------------------------------
+    2 Add 1 more cycle if in 6502 emulation mode (e=1).
+
+BRL   Branch Always Long
+
+Same as BRA, but the operand is 2 bytes giving the instruction a 64k range.
+This instruction is similar to the JMP command, with the advantage being
+that JMP is and absolute address and BRL is a relative address.
+No flags are affected.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+-----------------------------------------------------------------
+  Program Counter Relative Long BRL $xxxx     82      3       4
+-----------------------------------------------------------------
+
+BIT  Test Memory Bits against Accumulator
+
+The 65816 provides 3 new addressing modes for the old standard BIT
+instruction. The only true difference is that when the processor is in 16
+bit mode, the top two bits xfered to the status register will come from
+bits 14 and 15. When in 8 bit mode bits 6 and 7 are xfered to the status
+register.
+
+     Flags affected nv----z-  (Other than immediate addressing).
+                    ------z-  (Immediate addressing only).
+                    n Takes value of most significant bit of memory data.
+                    v Takes value from bit 6 or 14 of memory data.
+                    z Set if logical AND of mem and acc is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    BIT #const     89      2*      2 | 1
+  Absolute                     BIT addr       2C      3       4 | 1
+  Direct Page                  BIT dp         24      2       3 | 1,2
+  Absolute Indexed,X           BIT addr,X     3C      3       4 | 1,3
+  Direct Page Indexed,X        BIT dp,X       34      2       4 | 1,2
+----------------------------------------------------------------------
+  * Add 1 byte if m=0 (16-bit memory/accumulator).
+  1 Add 1 cycle if m=0 (16-bit memory/accumulator).
+  2 Add 1 cycle if low byte of Direct Page register is <>0.
+  3 Add 1 cycle if adding index crosses a page boundary.
+
+BRK Software Break
+
+While in native 65816 mode, BRK is unaffected by the I interrupt disable
+flag. Additionally, you may now pass a one byte signature byte to indicate
+which BRK instruction caused the BRK to be preformed.
+The new BRK handler includes a Hardware Vector- thus, it is no longer
+required to check for the BRK bit flag via the IRQ.
+
+When a BRK is performed in 65816 Native mode:
+
+
+   * the program counter bank register is pushed onto stack.
+
+   * the program counter is incremented by two and pushed on the stack.
+
+   * the status register is pushed onto the stack
+
+   * the interrupt disable flag is set.
+
+   * the decimal mode flag is cleared.
+
+   * the program bank register is cleared to zero.
+
+   * the program counter is loaded from the break vector at $FFE6-$FFE7.
+
+While in 6502 emulation mode, (e=1) a BRK is preformed true to it's 6502
+forerunner (b flag set, status pushed onto stack, SEI and IRQ performed.).
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Stack/Interrupt              BRK            00      2*      7 | 1
+----------------------------------------------------------------------
+  * BRK is one byte, but program counter value pushed onto stack is
+    incremented by 2 allowing for optional signature byte.
+  1 Add one cycle for 65816 native mode (e=0).
+
+Status Register Setting and Clearing:
+-------------------------------------
+
+The following status set and reset instructions operate the same in 65816
+native mode and 6502 emulation mode.
+
+      CLC  Clear carry flag.
+      CLD  Clear decimal flag.
+      CLI  Clear interrupt flag.
+      CLV  Clear overflow flag.
+      SEC  Set carry flag.
+      SED  Set decimal flag.
+      SEI  Set interrupt flag.
+
+                 Flags
+Addressing Mode nvmxdizc     Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied       -------0      CLC            18      1       2
+  Implied       ----0---      CLD            D8      1       2
+  Implied       -----0--      CLI            58      1       2
+  Implied       -0------      CLV            B8      1       2
+  Implied       -------1      SEC            38      1       2
+  Implied       ----1---      SED            F8      1       2
+  Implied       -----1--      SEI            78      1       2
+----------------------------------------------------------------------
+
+TOC
+
+CMP Compare Accumulator with Memory
+
+For the most part, this instruction works the same in 6502 emulation mode
+and 65816 mode.
+While in 16 bit accumulator mode the low byte of the compare will come from
+the effective address and the high byte from the effective address plus
+one.
+
+     Flags Altered n-----zc
+                   n Set if most significant bit of result is set.
+                   z Set if result is zero.
+                   c Set if no borrow was required. Acc => memory.
+                     C=0 if borrow required Acc < memory.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    CMP #const     C9      2*      2 | 1
+  Absolute                     CMP addr       CD      3       4 | 1
+  Absolute Long                CMP long       CF      4       5 | 1
+  Direct Page                  CMP dp         C5      2       3 | 1,2
+  Direct Page Indirect         CMP (dp)       D2      2       5 | 1,2
+  Direct Page Indirect Long    CMP [dp]       C7      2       6 | 1,2
+  Absolute Indexed,X           CMP addr,X     DD      3       4 | 1,3
+  Absolute Long Indexed,X      CMP long,X     DF      2       7 | 1
+  Absolute Indexed,Y           CMP addr,Y     D9      3       4 | 1,3
+  Direct Page Indexed,X        CMP dp,X       D5      2       4 | 1,2
+  DP Indexed Indirect,X        CMP (dp,X)     C1      2       6 | 1,2
+  DP Indirect Indexed,Y        CMP (dp),Y     D1      2       5 | 1,2,3
+  DP Indirect Long Indexed,Y   CMP [dp],Y     D7      2       6 | 1,2
+  Stack Relative (SR)          CMP sr,S       C3      2       4 | 1
+  SR Indirect Indexed,Y        CMP (sr,S),Y   D3      2       7 | 1
+----------------------------------------------------------------------
+  * Add 1 byte if m=0 (16-bit memory/accumulator).
+  1 Add 1 cycle if m=0 (16-bit memory/accumulator).
+  2 Add 1 cycle if low byte of Direct Page register is <>0.
+  3 Add 1 cycle if adding index crosses a page boundary.
+
+COP Coprocessor Empowerment
+
+COP cause a software interrupt through a separate COP hardware vector. The
+vector is to be located at $FFF$-$FFF5. In 6502 emulation mode:
+
+   * The program counter is incremented by 2 and pushed on stack.
+   * The status register is pushed onto the stack.
+   * The interrupt status bit is set.
+   * The program counter is loaded with the hardware vector.
+   * The decimal flag is cleared.
+
+In Native mode:
+
+   * The PC bank register is pushed onto stack.
+   * The PC is incremented by two and pushed onto stack.
+   * The status register is pushed onto stack.
+   * The interrupt status flag is set.
+   * The program bank register is cleared to zero.
+   * The PC is loaded with the hardware vector.
+   * The decimal flag is cleared after COP executed.
+
+     Flags Altered ----di--
+                   d decimal mode flag is reset to zero.
+                   i Interrupt disable is set.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Stack/Interrupt              COP const      02      2**     7 | 1
+----------------------------------------------------------------------
+  * COP is a 1 byte instruction, but the PC in incremented by to and
+    pushed onto stack, allowing for an optional signature byte.
+  1 Add 1 cycle for 65816/65802 native mode (e=0)
+
+CPX Compare X Index register with Memory
+
+CPX functions the same as a 6502. The only notable exception is to remember
+that when in 16 bit index register mode (x=0) that date/memory will be 16
+bits wide. The low order byte will come from the the effect address and the
+high order byte from the effective address plus one.
+
+     Flags Altered n-----zc
+                   n Set if most significant bit of result is set.
+                   z Set if result is zero.
+                   c Set if no borrow was required ( X >= memory).
+                     Cleared if borrow required (X < memory).
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    CPX #const     E0      2*      2 | 1
+  Absolute                     CPX addr       EC      3       4 | 1
+  Direct Page                  CPX dp         E4      2       3 | 1,2
+----------------------------------------------------------------------
+  * Add 1 byte if m=0 (16-bit index registers).
+  1 Add 1 cycle if x=0 (16-bit index registers).
+  2 Add 1 cycle if low byte of Direct Page register is <>0.
+
+CPY Compare Y Index register with Memory
+
+CPY functions the same as a 6502. The only notable exception is to remember
+that when in 16 bit index register mode (x=0) that date/memory will be 16
+bits wide. The low order byte will come from the the effect address and the
+high order byte from the effective address plus one.
+
+     Flags Altered n-----zc
+                   n Set if most significant bit of result is set.
+                   z Set if result is zero.
+                   c Set if no borrow was required ( Y >= memory).
+                     Cleared if borrow required (Y < memory).
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    CPY #const     C0      2*      2 | 1
+  Absolute                     CPY addr       CC      3       4 | 1
+  Direct Page                  CPY dp         C4      2       3 | 1,2
+----------------------------------------------------------------------
+    * Add 1 byte if m=0 (16-bit index registers).
+    1 Add 1 cycle if x=0 (16-bit index registers).
+    2 Add 1 cycle if low byte of Direct Page register is <> 0.
+
+DEC Decrement Memory
+
+DEC also works nearly the same as a 6502 mode. When in 16 bit
+accumulator/memory mode (m=0) data altered will be 16 bits wide with
+automatic underflow from high byte to low byte. The low order byte will
+come from the the effect address and the high order byte from the effective
+address plus one.
+
+     Flags Altered n-----z-
+                   n Set if most significant bit of result is set.
+                   z Set if result is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Accumulator                  DEC A          3A      1       2 |
+                        Alias: DEA
+  Absolute                     DEC addr       CE      3       6 | 1
+  Direct Page                  DEC dp         C6      2       5 | 1,2
+  Absolute Indexed,X           DEC addr,X     DE      3       7 | 1
+  Direct Page Indexed,X        DEC dp,X       D6      2       6 | 1,2
+----------------------------------------------------------------------
+    1 Add 2 cycles if m=0 (16-bit memory/accumulator).
+    2 Add 1 cycle if low byte of Direct Page register is <>0.
+
+DEX, DEY Decrement Index Registers
+
+Both instructions operate just as a 6502. When in 16 bit index register
+mode, the register will be treated as 16 bits wide.
+
+     Flags Altered n-----z-
+                   n Set if most significant bit of result is set.
+                   z Set if result is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      DEX            CA      1       2
+  Implied                      DEY            88      1       2
+----------------------------------------------------------------------
+
+EOR Exclusive-OR Accumulator with Memory
+
+Another instruction that operates just as a 6502, only new addressing
+modes. When in 16 bit memory/accumulator mode data is 16 bits wide - as
+usual the low byte will come from the effective address and the high byte
+from the effective address plus one.
+
+     Flags Altered n-----z-
+                   n Set if most significant bit of result is set.
+                   z Set if result is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    EOR #const     49      2*      2 | 1
+  Absolute                     EOR addr       4D      3       4 | 1
+  Absolute Long                EOR long       4F      4       5 | 1
+  Direct Page                  EOR dp         45      2       3 | 1,2
+  Direct Page Indirect         EOR (dp)       52      2       5 | 1,2
+  Direct Page Indirect Long    EOR [dp]       47      2       6 | 1,2
+  Absolute Indexed,X           EOR addr,X     5D      3       4 | 1,3
+  Absolute Long Indexed,X      EOR long,X     5F      4       5 | 1
+  Absolute Indexed,Y           EOR addr,Y     59      3       4 | 1,3
+  Direct Page Indexed,X        EOR dp,X       55      2       4 | 1,2
+  DP Indexed Indirect,X        EOR (dp,X)     41      2       6 | 1,2
+  DP Indirect Indexed,Y        EOR (dp),Y     51      2       5 | 1,2,3
+  DP Indirect Long Indexed,Y   EOR [dp],Y     57      2       6 | 1,2
+  Stack Relative (SR)          EOR sr,S       43      2       4 | 1
+  SR Indirect Indexed,Y        EOR (sr,S),Y   53      2       7 | 7
+----------------------------------------------------------------------
+    * Add 1 byte if m=0 (16-bit memory/accumulator).
+    1 Add 1 cycle if m=0 (16-bit memory/accumulator).
+    2 Add 1 cycle if low byte of Direct Page register is <>0.
+    3 Add 1 cycle if adding index crosses a page boundary.
+
+INC Increment Data
+
+Also operates just as the 6502 INC instruction. When in 16 bit
+memory/accumulator mode (m=0) data acted upon is 16 bits wide.
+One new addressing mode is Accumulator addressing that will increment the
+Accumulator.
+
+     Flags Altered n-----z-
+                   n Set if most significant bit of result is set.
+                   z Set if result is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Accumulator                  INC a          1A      1       2 |
+                        Alias: INA
+  Absolute                     INC addr       EE      3       6 | 1
+  Direct Page                  INC dp         E6      2       5 | 1,2
+  Absolute Indexed,X           INC addr,X     FE      3       7 | 1
+  Direct Page Indexed,X        INC dp,X       F6      2       6 | 1,2
+----------------------------------------------------------------------
+    1 Add 2 cycles if m=0 (16-bit memory/accumulator).
+    2 Add 1 cycle if low byte of Direct Page register is <>0.
+
+INX, INY  Increment Index Registers
+
+Both instructions operate just as a 6502. When in 16 bit index register
+mode, the register will be treated as 16 bits wide.
+
+     Flags Altered n-----z-
+                   n Set if most significant bit of result is set.
+                   z Set if result is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Implied                      INX            E8      1       2 |
+  Implied                      INY            C8      1       2 |
+----------------------------------------------------------------------
+
+JMP Jump to New Location
+
+JMP transfers control to the operand address. If a long jump is executed
+the program counter bank register is loaded with the third byte of the
+target address.
+
+The 65816 Designers also specify that an assembler could possibly use JML
+in place of a JMP Long instruction, and also JML [adr] for Absolute
+indirect long.
+
+        Flags Affected:--------
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Absolute                     JMP addr       4C      3       3 |
+  Absolute Indirect            JMP (addr)     6C      3       5 | 1
+  Absolute Indexed Indirect    JMP (addr,X)   7C      3       6 |
+  Absolute Long                JMP long       5C      4       4 |
+                        Alias: JML long
+  Absolute Indirect Long       JMP [addr]     DC      3       6 |
+                        Alias: JML [addr]
+----------------------------------------------------------------------
+    1 6502: If low byte of addr is $FF (ie: addr is $xxFF) yields
+      incorrect result.
+
+JSR, JSL Jump to Subroutine (gosub)
+
+JSR works just as a 6502 with the new addressing modes available. If an
+absolute address is coded by the assembler that is less than $FFFF then a
+standard JSR is used, else if it is greater than $FFFF then absolute long
+addressing is used. A standard JSR gosubs to the the routine in the current
+program bank.
+
+JSR can also use Indexed Indirect addressing. (see section on addressing
+modes for an example.)
+
+JML is a four byte instruction that will JSR to a subroutine located in any
+bank. When executed the current program counter bank is pushed onto the
+stack before the program counter high/low bytes.
+
+         Flags Affected: --------
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Absolute Long                JSL long       22      4       8
+                        Alais: JSR long
+  Absolute                     JSR addr       20      3       6
+  Absolute Indexed Indirect    JSR (addr,X)   FC      3       8
+----------------------------------------------------------------------
+
+LDA Load the Accumulator with Memory
+
+LDA is nearly identical to the standard 6502 LDA instruction. New features
+are the implementation of the new addressing modes. While the status
+register is set for 16 bit memory/accumulator mode (m=0), data loaded is 16
+bits wide with the load byte coming from the effective address and the high
+byte of the accumulator coming from the effective address plus one.
+
+     Flags affected n-----z-
+                    n Takes value of most significant bit of memory data.
+                    z Set if data loaded is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    LDA #const     A9      2*      2 | 1
+  Absolute                     LDA addr       AD      3       4 | 1
+  Absolute Long                LDA long       AF      4       5 | 1,2
+  Direct Page                  LDA dp         A5      2       3 | 1,2
+  Direct Page Indirect         LDA (dp)       B2      2       5 | 1,2
+  Direct Page Indirect Long    LDA [dp]       A7      2       6 | 1,2
+  Absolute Indexed,X           LDA addr,X     BD      3       4 | 1,3
+  Absolute Long Indexed,X      LDA long,X     BF      4       5 | 1
+  Absolute Indexed,Y           LDA addr,Y     B9      3       4 | 1,3
+  Direct Page Indexed,X        LDA dp,X       B5      2       4 | 1,2
+  DP Indexed Indirect,X        LDA (dp,X)     A1      2       6 | 1,2
+  DP Indirect Indexed,Y        LDA (dp),Y     B1      2       5 | 1,2,3
+  DP Indirect Long Indexed,Y   LDA [dp],Y     B7      2       6 | 1,2
+  Stack Relative (SR)          LDA sr,S       A3      2       4 | 1
+  SR Indirect Indexed,Y        LDA (sr,S),Y   B3      2       7 | 1
+----------------------------------------------------------------------
+  * Add 1 byte if m=0 (16-bit memory/accumulator).
+  1 Add 1 cycle if m=0 (16-bit memory/accumulator).
+  2 Add 1 cycle if low byte of Direct Page register is <>0.
+  3 Add 1 cycle if adding index crosses a page boundary.
+
+LDX Load X Register from Memory
+
+LDX is identical to a stock 6502.
+The only new feature to remember is that when in 16 bit index register mode
+(x=0) that data will be 16 bits wide. The X register low byte will come
+from the effective address and the high byte from the effective address
+plus one.
+
+     Flags affected n-----z-
+                    n Takes value of most significant bit of memory data.
+                    z Set if data loaded is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    LDX #const     A2      2*      2 | 1
+  Absolute                     LDX addr       AE      3       4 | 1
+  Direct Page                  LDX dp         A6      2       3 | 1,2
+  Absolute Indexed,Y           LDX addr,Y     BE      3       4 | 1,3
+  DP Indexed,Y                 LDX dp,Y       B6      2       4 | 1,2
+----------------------------------------------------------------------
+  * Add 1 byte if m=0 (16-bit index registers).
+  1 Add 1 cycle if x=0 (16-bit index registers).
+  2 Add 1 cycle if low byte of Direct Page register is <>0.
+  3 Add 1 cycle if indexing crosses page boundary.
+
+LDY Load Y Register from Memory
+
+LDY is identical to a stock 6502.
+The only new diversion is to remember that when in 16 bit index register
+mode (x=0) that data will be 16 bits wide. The Y register low byte will
+come from the effective address and the high byte from the effective
+address plus one.
+
+     Flags affected n-----z-
+                    n Takes value of most significant bit of memory data.
+                    z Set if data loaded is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    LDY #const     A0      2*      2 | 1
+  Absolute                     LDY addr       AC      3       4 | 1
+  Direct Page                  LDY dp         A4      2       3 | 1,2
+  Absolute Indexed,X           LDY addr,X     BC      3       4 | 1,3
+  Direct Page Indexed,X        LDY dp,X       B4      2       4 | 1,2
+----------------------------------------------------------------------
+  * Add 1 byte if m=0 (16-bit index registers).
+  1 Add 1 cycle if x=0 (16-bit index registers).
+  2 Add 1 cycle if low byte of Direct Page register is <>0.
+  3 Add 1 cycle if indexing crosses page boundary.
+
+LSR Logical Shift Right.
+
+Yet another instruction unchanged from the standard 6502 instruction set.
+16 bit mode (m=0) data shifted will be 16 bits wide.
+
+     Flags Altered n-----zc
+                   n Cleared.
+                   z Set if result is zero.
+                   c Bit zero becomes new carry.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Accumulator                  LSR a          4A      1       2 |
+  Absolute                     LSR addr       4E      3       6 | 1
+  Direct Page                  LSR dp         46      2       5 | 1,2
+  Absolute Indexed,X           LSR addr,X     5E      3       7 | 1
+  Direct Page Indexed,X        LSR dp,X       56      2       6 | 1,2
+----------------------------------------------------------------------
+    1 Add 2 cycles if m=0 (16-bit memory/accumulator).
+    2 Add 1 cycle if low byte of Direct Page register is <>0.
+
+Block Move Instructions
+=======================
+
+MVP Move Positive destination > source
+MVN Move Negative destination < source
+
+This instruction is new 65816 only. MVN and MVP move data from memory
+location to memory location without user intervention.
+
+Two instructions are necessary so that as the data is being moved in a
+negative direction it will not overwrite itself.
+
+The source address for the move is taken from the X register. The
+destination address for the move is taken for the Y register. The 16 bit
+length of the move is taken from the Accumulator regardless of the m flag
+setting. This value should be one less than the actual length of the move
+(ie a=$0000 and one byte will be moved).
+
+The two operand bytes specify the source bank of 64k and the destination
+bank of 64k. The assembler order of the operand bytes is source,
+destination - however, the actual binary output code will be the MVN or MVP
+opcode followed byte the destination bank byte and the source bank byte.
+
+MVN Move Negative is used when the source address is greater than the
+destination address, or conversely when the destination range is lower than
+the source range.
+
+The MVN instruction uses the X and Y registers to denote the bottom
+(beginning) address of the two memory segments to be moved. With MVN the
+data is moved from the source in X to the destination in Y, then the X and
+Y registers are are incremented and the accumulator decremented until the
+accumulator underflows to $FFFF.
+
+MVP Move Positive is used with the source address is less than the
+destination, or conversely when the destination range is higher in memory
+than the source range.
+
+The MVP instruction uses the X and Y registers to denote the top address of
+the two blocks of memory. The data is moved from the source in X to the
+address in Y and then the XY and accumulator registers are decremented
+until the accumulator underflows to $FFFF.
+
+If the index registers are set for 8 bit mode (x=1) or the processor is set
+for 6502 emulation mode, then the data moved will be in page zero only
+because the high bytes will default to zero.
+
+To reduce code length it is very easy to setup the move instructions in a
+subroutine, then use dynamically modified code to exchange the MVN and MVP
+opcodes on-the-fly.
+
+Status register flags are NOT affect by the move instructions.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Block Move                   MVN src,dest   54      3      *
+  Block Move                   MVP src,dest   44      3      *
+----------------------------------------------------------------------
+   * 7 cycles each byte moved.
+
+TOC
+
+NOP No Operation.
+
+Same as 6502. No flags are affected with NOP.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      NOP            EA      1       2
+----------------------------------------------------------------------
+
+ORA OR Accumulator with Memory.
+
+Same function as 6502 ORA with new addressing modes.
+When in 16 bit memory/accumulator mode (m=0) data acted upon is 16 bits
+wide. The low byte is the effective address and the high byte is the
+effective address plus one.
+
+    Flags Affected: n-----z-
+                    n Set if most significant bit of result is set.
+                    z Set if result is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    ORA #const     09      2*      2 | 1
+  Absolute                     ORA addr       0D      3       4 | 1
+  Absolute Long                ORA long       0F      4       5 | 1
+  Direct Page                  ORA dp         05      2       3 | 1,2
+  Direct Page Indirect         ORA (dp)       12      2       5 | 1,2
+  Direct Page Indirect Long    ORA [dp]       07      2       6 | 1,2
+  Absolute Indexed,X           ORA addr,X     1D      3       4 | 1,3
+  Absolute Long Indexed,X      ORA long,X     1F      4       5 | 1
+  Absolute Indexed,Y           ORA addr,Y     19      3       4 | 1,3
+  Direct Page Indexed,X        ORA dp,X       15      2       4 | 1,2
+  DP Indexed Indirect,X        ORA (dp,X)     01      2       6 | 1,2
+  DP Indirect Indexed,Y        ORA (dp),Y     11      2       5 | 1,2,3
+  DP Indirect Long Indexed,Y   ORA [dp],Y     17      2       6 | 1,2
+  Stack Relative (SR)          ORA sr,S       03      2       4 | 1
+  SR Indirect Indexed,Y        ORA (sr,S),Y   13      2       7 | 1
+----------------------------------------------------------------------
+   * Add 1 byte if m=0 (16-bit memory/accumulator).
+   1 Add 1 cycle if m=0 (16-bit memory/accumulator).
+   2 Add 1 cycle if low byte of Direct Page register is <>0.
+   3 Add 1 cycle if adding index crosses a page boundary.
+
+PEA Push Effective Absolute Address
+
+PEA pushes the sixteen-bit operand onto the stack. The stack pointer is
+decremented by two. No flags are affected. Unlike other instructions that
+use similar assembler notations, PEA pushes the value of the operands onto
+the stack, NOT the data located at an effective address. A more appropriate
+name should have been to push Immediate data onto the stack - it is unclear
+why this discrepancy exists.
+
+    For example:
+
+               PEA $1234
+
+Pushes a #$12 and then a #$34 onto the stack.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Stack (Absolute)             PEA addr      F4      3       5
+----------------------------------------------------------------------
+
+PEI Push Effective Indirect Address
+
+This 65816 instruction pushes the address of the effective address onto the
+stack. This instruction always pushes 16 bits of data onto the stack
+without regard for the settings of the x and m status bits.
+
+The address of the effective address plus one is pushed on the stack first
+and then the address of the effective address is pushed on second.
+
+For example: suppose $5678 is stored at location $21/$22 in standard low
+byte/high byte format, then a
+
+         PEI ($21)
+
+would get the $5678 from $21/$22 and push it onto the stack.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Stack (Direct Page Indirect) PEI (dp)      D4       2       6 | 1
+----------------------------------------------------------------------
+   1 Add 1 cycle if low byte of direct page is <>0.
+
+PER Push effective PC Relative Indirect Address
+
+This instruction takes the program counter and adds the 16 bit operand and
+pushes the resulting 16 bits onto the stack. The destination address must
+be located within the current bank of 64k memory. The value of the program
+counter used in the calculation is the address of the NEXT instruction
+following the PER and two operand bytes.
+
+The result high byte is pushed first, followed by the low byte of the
+result.
+
+Because this instruction uses a relative offset for the operand, it can aid
+in writing relocatable code. One could envision pushing an unknown run-time
+address onto the stack with PER and then pulling the address off to
+determine the programs run time origin.
+
+Another use of this instruction could be to push a return address onto the
+stack for 6502 pha:pha:rts style coding
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Stack (PC Relative Long)   PER label       62      3       6
+----------------------------------------------------------------------
+
+Push, Pull APXY Instructions
+
+PHA,PHP,PLA,PLP are unchanged from their 6502 forerunners. The only notable
+difference is that 16 bits will be pushed on when in accumulator/memory
+(m=0) mode and a PHA or PLA is executed (PHP/PLP only operate on 8 bits).
+
+New push and pull stack instructions include PHY,PLY,PHX,PLX. These four
+new instructions push and pull the index registers on and off the stack.
+When the status register is set to 16 bit index register mode (x=0), the
+pull and push index registers will operate on 16 bits when the status
+register x is set to 0.
+
+Addressing Mode   Flags      Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Stack (Push)   --------      PHA            48      1       3 | 1
+  Stack (Push)   --------      PHP            08      1       3 |
+  Stack (Push)   --------      PHX            DA      1       3 | 2
+  Stack (Push)   --------      PHY            5A      1       3 | 2
+  Stack (Pull)   n-----z-      PLA            68      1       4 | 1
+  Stack (Pull)   nvmxdizc      PLP            28      1       4 |
+  Stack (Pull)   n-----z-      PLX            FA      1       4 | 2
+  Stack (Pull)   n-----z-      PLY            7A      1       4 | 2
+----------------------------------------------------------------------
+   1 Add 1 cycle if 16 bit accumulator/memory mode (m=0).
+   2 Add 1 cycle if 16 bit index registers (x=0).
+
+Push, Pull Bank Registers
+
+PHB Pushes the 8 bit contents of the data bank register on the stack.
+
+PHD Pushes the 16 bit contents of the direct page register on stack.
+The high byte is pushed first, followed by the low byte.
+
+PHK Pushes the 8 bit contents of the program bank register on stack.
+
+PLB Pulls a byte off the stack into the data bank register. This is the
+only instruction that can directly change the data bank register.
+
+PLD Pulls a sixteen bit value off stack into the direct page register. The
+low byte is pulled first, followed by the high byte.
+
+Pulled Flags Affected by pull instructions:
+
+             n Set if most significant bit of value pulled is set.
+             z Set if value pulled is zero.
+
+Addressing Mode   Flags      Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Stack (Push)                 PHB            8B      1       3
+  Stack (Push)                 PHD            0B      1       4
+  Stack (Push)                 PHK            4B      1       3
+  Stack (Pull)   n-----z-      PLB            AB      1       4
+  Stack (Pull)   n-----z-      PLD            2B      1       5
+----------------------------------------------------------------------
+
+REP Reset Status Bits.
+
+REP is a new 65816 instruction. When used, it will reset (clear) the bits
+specified by the 1 byte immediate value.
+
+For Example to clear bit 5 of the status register:
+
+REP #%00100000 ;clear bit 5.
+
+or to clear multiple bits:
+
+REP #%10110000 ;clear 7,5 and 4.
+
+Any combination is acceptable.
+
+To set a bit, see SEP.
+
+    Flags affected: nvmxdizc
+                 All flags that have an operand bit set are cleared.
+                 Other flags are not affected.
+
+Addressing Mode               Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Immediate                    REP #const     C2      2       3
+----------------------------------------------------------------------
+
+ROL Rotate Memory or Accumulator Left
+
+ROL works same as the 6502 ROL instruction.
+When in 16 bit accumulator/memory mode (m=0) Data rotated is 16 bits wide
+with the former bit 15 becoming the new carry. - the low-order bits are
+located in the effective address, and the high order bits are located in
+the effective address plus one.
+
+    Flags affected: n-----zc
+                    n Set if most significant bit of result is set.
+                    z Set if result is zero.
+                    c The high bit (7 or 15) becomes the new carry.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Accumulator                  ROL A          2A      1       2 |
+  Absolute                     ROL addr       2E      3       6 | 1
+  Direct Page                  ROL dp         26      2       5 | 1,2
+  Absolute Indexed,X           ROL addr,X     3E      3       7 | 1
+  Direct Page Indexed,X        ROL dp,X       36      2       6 | 1,2
+----------------------------------------------------------------------
+   1 Add 2 cycles if 16 bit memory accumulator mode (m=0).
+   2 Add 1 cycle if direct page pointer is <>0.
+
+ROR Rotate Memory or Accumulator Right.
+
+Works as 6502 ROR expected.
+When in 16 bit memory/accumulator mode (m=0) data rotated will be 16 bits
+wide, plus the carry - the low-order bits are located in the effective
+address, and the high order bits are located in the effective address plus
+one.
+
+    Flags affected: n-----zc
+                    n Set if most significant bit of result is set.
+                    z Set if result is zero.
+                    c Low bit becomes the new carry.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Accumulator                  ROR a          6A      1       2 |
+  Absolute                     ROR addr       6E      3       6 | 1
+  Direct Page                  ROR dp         66      2       5 | 1,2
+  Absolute Indexed,X           ROR addr,X     7E      3       7 | 1
+  Direct Page Indexed,X        ROR dp,X       76      2       6 | 1,2
+----------------------------------------------------------------------
+   1 Add 2 cycles if 16 bit memory accumulator mode (m=0).
+   2 Add 1 cycle if direct page pointer is <>0.
+
+RTI Return from Interrupt
+
+While in 6502 emulation mode (e=1) RTI is handled the same as a stock 6502.
+While in native 65816 mode (e=0) RTI also pulls the program bank register
+byte off of the stack. Since this extra byte is present, it is essential
+that the RTI be executed in the same mode (e=?) that the processor was in
+when the interrupt was executed.
+
+    Flags Affected:  The status register is pulled from the stack,
+                     therefore all flags are affected.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Stack (RTI)                  RTI            40      1       6 |  1
+----------------------------------------------------------------------
+  1 add 1 cycle if 65816 native mode.
+
+RTL Return from Subroutine Long
+
+RTL works similar to an RTS but it also pulls the program bank register off
+of the stack. This instruction should be used in conjunction with the JSR
+long instruction or by a setup routine that also pushes the program bank
+onto the stack. RTL pulls 24 bits off of the stack. First the two bytes of
+the program counter low/high are pulled and incremented, then the program
+bank register is pulled.
+
+No Flags are affected by RTL.
+
+TOC
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Stack (RTL)                  RTL            6B      1       6
+----------------------------------------------------------------------
+
+RTS Return from Subroutine
+
+Same as the 6502 instruction. No flags are affected.
+
+One interesting use of RTS is to push a return address on the stack and
+then execute it via RTS. In order to use this type of coding the address
+pushed onto the stack must be one less than the actual routine address
+because when pulled back off, the processor automatically inc's the program
+counter before continuing. While in Native mode with 16 bit
+accumulator/memory set, this can easily be accomplished by:
+
+          DEC A   ; dec 16 be accum. or DEA.
+          PHA     ; push 16 bit return adr on stack.
+          RTS     ; return to execute the instruction.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Stack (RTS)                  RTS            60      1       6
+----------------------------------------------------------------------
+
+SBC Subtract from Accumulator
+
+SBC also works just a a 6502. Again the only difference is a few new
+addressing modes, and the fact that data maybe worked in a 16 bit
+accumulator or 16 bit memory location.
+SBC and ADC when used in 16 bit memory/accumulator mode greatly enhance the
+overall utility of the 65816. A programmer can easily see how much faster
+addition and subtraction routines could be performed while operating on 16
+bits instead of 8.
+
+     Flags Altered nv----zc
+                   n Set if most-significant bit of result is set.
+                   v Set if signed overflow.
+                   z Set if result is zero.
+                   c Set if unsigned borrow not required.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Immediate                    SBC #const     E9      2*      2 | 1
+  Absolute                     SBC addr       ED      3       4 | 1
+  Absolute Long                SBC long       EF      4       5 | 1
+  Direct Page                  SBC dp         E5      2       3 | 1,2
+  Direct Page Indirect         SBC (dp)       F2      2       5 | 1,2
+  Direct Page Indirect Long    SBC [dp]       E7      2       6 | 1,2
+  Absolute Indexed,X           SBC addr,X     FD      3       4 | 1,3
+  Absolute Long Indexed,X      SBC long,X     FF      4       5 | 1
+  Absolute Indexed,Y           SBC addr,Y     F9      3       4 | 1,3
+  Direct Page Indexed,X        SBC dp,X       F5      2       4 | 1,2
+  DP Indexed Indirect,X        SBC (dp,X)     E1      2       6 | 1,2
+  DP Indirect Indexed,Y        SBC (dp),Y     F1      2       5 | 1,2,3
+  DP Indirect Long Indexed,Y   SBC [dp],Y     F7      2       6 | 1,2
+  Stack Relative (SR)          SBC sr,S       E3      2       4 | 1
+  SR Indirect Indexed,Y        SBC (sr,S),Y   F3      2       7 | 1
+----------------------------------------------------------------------
+   * Add 1 byte if m=0 (16-bit memory/accumulator).
+   1 Add 1 cycle if m=0 (16-bit memory/accumulator).
+   2 Add 1 cycle if low byte of Direct Page register is <>0.
+   3 Add 1 cycle if adding index crosses a page boundary.
+
+SEP Set Status Bits
+
+SEP is a new 65816 instruction. When used, it will set the bits specified
+by the 1 byte immediate value.
+This is the only means of setting the M and X status register bits.
+
+    For Example to set bit 5 of the status register:
+
+       SEP #%00100000   ;set bit 5.
+
+       or to clear multiple bits:
+
+       SEP #%10110000   ;set bits 7,5 and 4.
+
+    Any combination is acceptable.
+
+    To reset a bit, see REP.
+
+    Flags affected: nvmxdizc
+                 All flags that have an operand bit set are set.
+                 Other flags are not affected.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Immediate                 SEP #const       E2      2       3
+----------------------------------------------------------------------
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Absolute                     STA addr       8D      3       4 | 1
+  Absolute Long                STA long       8F      4       5 | 1
+  Direct Page                  STA dp         85      2       3 | 1,2
+  Direct Page Indirect         STA (dp)       92      2       5 | 1,2
+  Direct Page Indirect Long    STA [dp]       87      2       6 | 1,2
+  Absolute Indexed,X           STA addr,X     9D      3       5 | 1
+  Absolute Long Indexed,X      STA long,X     9F      4       5 | 1
+  Absolute Indexed,Y           STA addr,Y     99      3       5 | 1
+  Direct Page Indexed,X        STA dp,X       95      2       4 | 1,2
+  DP Indexed Indirect,X        STA (dp,X)     81      2       6 | 1,2
+  DP Indirect Indexed,Y        STA (dp),Y     91      2       6 | 1,2
+  DP Indirect Long Indexed,Y   STA [dp],Y     97      2       6 | 1,2
+  Stack Relative (SR)          STA sr,S       83      2       4 | 1
+  SR Indirect Indexed,Y        STA (sr,S),Y   93      2       7 | 1
+----------------------------------------------------------------------
+   * Add 1 byte if m=0 (16-bit memory/accumulator).
+   1 Add 1 cycle if m=0 (16-bit memory/accumulator).
+   2 Add 1 cycle if low byte of Direct Page register is <>0.
+
+STP Stop the Processor
+
+STP shuts the processor down until a hardware reset. It is used in some
+systems to put the processor to sleep and reduce power consumption. There
+is a RESet B pin on some 65816 processors that allow for the usage of this
+instruction.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      STP            DB      1       3
+----------------------------------------------------------------------
+
+STX Store X Register to Memory
+
+Another the same as 6502 mode.
+Only exception is that when set for 16 bit index registers (x=0) data
+stored will be 16 bits wide. Low 8 bits of Y will be stored to the
+effective address and the high byte to the effective address plus one.
+No flags are affected by STX.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Absolute                     STX addr       8E      3       4 | 1
+  Direct Page                  STX dp         86      2       3 | 1,2
+  Direct Page Indexed,Y        STX dp,y       96      2       4 | 1,2
+----------------------------------------------------------------------
+  1 Add 1 cycle if 16 bit index registers (x=0)
+  2 Add 1 more cycle if low byte of Direct Page is <>0.
+
+STY Store Y Register to Memory
+
+Same as 6502 mode.
+Only exception is that when set for 16 bit index registers (x=0) data
+stored will be 16 bits wide. Low 8 bits of Y will be stored to the
+effective address and the high byte to the effective address plus one.
+No flags are affected by STY.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Absolute                     STY addr       8C      3       4 | 1
+  Direct Page                  STY dp         84      2       3 | 1,2
+  Direct Page Indexed,X        STY dp,X       94      2       4 | 1,2
+----------------------------------------------------------------------
+  1 Add 1 cycle if 16 bit index registers (x=0)
+  2 Add 1 more cycle if low byte of Direct Page is <>0.
+
+STZ Store Zero byte to Memory
+
+A new instruction of the 65816. STZ stores a zero byte to the destination
+address. When in 8 bit accumulator/memory mode (m=1) one byte is stored at
+the effective address. While in 16 bit memory/accumulator mode (m=0) a zero
+is stored to the effective address and to the effective address plus one.
+No flags are affected.
+
+This instruction could be defined as a replacement for stock 6502 code as:
+
+       lda #0
+       sta $xxxx
+
+The perky thing about STZ is that the accumulator is unchanged and the
+status register is also unchanged.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Absolute                     STZ addr       9C      3       4 | 1
+  Direct Page                  STZ dp         64      2       3 | 1,2
+  Absolute Indexed,X           STZ addr,X     9E      3       5 | 1
+  Direct Page Indexed,X        STZ dp,X       74      2       4 | 1,2
+----------------------------------------------------------------------
+   1 Add 1 cycle if 16 bit index registers (x=0)
+   2 Add 1 more cycle if low byte of Direct Page is <>0.
+
+Register Transfer Instructions:
+
+TAX,TXA,TAY,TYA,TSX,TXS transfer instructions transfer bytes between the
+processor registers.
+
+     TAX: Transfer accumulator to X index register.
+     TAY: Transfer accumulator to Y index register.
+     TYA: Transfer Y index register to the accumulator.
+     TXA: Transfer X index register to the accumulator.
+     TSX: Transfer Stack pointer to the X index register.
+     TXS: Transfer X index register to the Stack pointer.
+
+Two new register transfer instructions are TXY to transfer directly from
+the X register into the Y register and TYX to transfer from Y register to X
+register.
+
+Because the accumulator and index registers can be set for either 8 or 16
+bits independently, the width of the transfer is determined by the
+destination register. The following table shows the possible combinations:
+
+   8 bit acc to  8 bit index regs. (m=1,x=1) 8 bits transferred.
+   8 bit acc,to 16 bit index regs (m=1, x=0), 16 bits are transferred.
+                The hidden high order accumulator byte becomes the
+                X or Y high byte.
+  16 bit index regs to 8 bit acc (m=1, x=0), 8 bits are transferred.
+                The hidden high order accumulator byte is not
+                affected and the previous values remain.
+   8 bit index regs to 16 bit acc (m=0, x=1), Two bytes
+                transferred with the high byte being zero.
+  16 bit acc to 8 bit index regs (m=0, x=1),  Only the low byte of the
+                accumulator is transferred to the index register.
+  16 bit acc to 16 bit index regs (m=0, x=0) 16 bits transferred.
+
+  16 bit stack pointer to 8 bit X register.  Only the low byte
+                address is transferred.
+   8 bit X reg to 16 bit stack pointer, sets stack high byte to zero.
+
+      Flags Affected: n-----z-
+                      n Set if most significant bit of transfer value
+                        is set.
+                      z Set if transferred value is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      TAX            AA      1       2
+  Implied                      TAY            A8      1       2
+  Implied                      TXA            8A      1       2
+  Implied                      TYA            98      1       2
+  Implied                      TSX            BA      1       2
+  Implied                      TXS            9A      1       2
+  Implied                      TXY            9B      1       2
+  Implied                      TYX            BB      1       2
+----------------------------------------------------------------------
+
+Direct Page Instructions:
+=========================
+
+Two new 65816 instructions are used to exchange data between the
+accumulator and the Direct Page Register.
+
+TCD Transfer Accumulator to Direct Page Register.
+TDC Transfer Direct Page Register to Accumulator.
+
+TCD transfers a 16 bit value from the accumulator into the direct (zero
+page) pointer. A full 16 bits is transferred regardless of the 16/8 bit
+setting (m) of the accumulator.
+The C in TCD is used to specify that the accumulator is referenced as C
+when it is 16 bits wide (low byte being A and high byte being B).
+TDC transfers from the Direct Page register into the full 16 bit
+accumulator without regard for the setting of status bit m.
+
+Some assemblers also allow TAD or TDA for the mnemonics.
+
+      Flags Affected: n-----z-
+                      n Set if most significant bit of transfer value
+                        is set.
+                      z Set if transferred value is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      TCD            5B      1       2
+                        Alais: TAD
+  Implied                      TDC            7B      1       2
+                        Alais: TDA
+----------------------------------------------------------------------
+
+TCS Transfer Accumulator to Stack Pointer
+
+TCS transfers a full 16 bits to the stack pointer without regard for the
+setting of status bit m.
+As with TCD and TDC the C in TCS refers to the accumulator as a full 16
+bits.
+The mnemonic TAS, transfer a to stack pointer, is used by some assemblers.
+While in 6502 emulation mode only the eight-bit A accumulator value is
+transferred because the stack is always located at page 1 on a 6502 TCS and
+TXS are the only two instructions that alter the stack pointer register.
+
+No flags are affected by TCS.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      TCS            1B      1       2
+                        Alais: TAS
+----------------------------------------------------------------------
+
+TSC Transfer Stack Pointer to Accumulator
+
+TSC transfers a full 16 bits of the stack pointer to the 16 bit accumulator
+without regard for the setting of status bit m.
+As with TCD and TDC the C in TSC refers to the accumulator as a full 16
+bits.
+The mnemonic TSA, transfer a to stack pointer, is used by some assemblers.
+
+While in 6502 emulation mode a one will be transferred to the hidden B
+(upper 8 bits) accumulator because the stack is always located at page one
+in 6502 mode.
+
+      Flags Affected: n-----z-
+                      n Set if most significant bit of transfer value
+                        is set.
+                      z Set if transferred value is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      TSC            3B      1      2
+                        Alais: TSA
+----------------------------------------------------------------------
+
+TRB Test and Reset Memory Bits
+------------------------------
+
+TRB performs a logical AND of the accumulator's compliment and the
+effective address - data is then rewritten back to the specified address.
+This clears each memory bit that has a corresponding bit set in the
+accumulator, leaving all other memory bits unchanged.
+
+To put it another way - TRB flips or inverts the accumulator value and then
+AND's that value with memory operand and stores the result back to the
+effective address.
+
+While is 16 bit accumulator mode (m=0) data is operated on in the expected
+16 bit fashion. The low byte of the operation is at the effective address
+and the high byte at the effective address plus one.
+
+       Flags Affected: ------z-
+                       z Set if memory value AND'ed with accumulator
+                       value is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Absolute                     TRB addr       1C      3       6 | 1
+  Direct Page                  TRB dp         14      2       5 | 1,2
+----------------------------------------------------------------------
+    1 Add 2 cycles if 16 bit memory/accumulator mode (m=0)
+    2 Add 1 cycle if direct page register low byte is <>0.
+
+TSB Test and Set Memory Bits
+----------------------------
+
+TSB logically OR's the accumulator and the data at the effective address.
+This effectively sets a bit at the memory location for each bit set in the
+accumulator.
+
+While is 16 bit accumulator mode (m=0) data is operated on in the expected
+16 bit fashion. The low byte of the operation is at the effective address
+and the high byte at the effective address plus one.
+
+The status register zero flag is set after the accumulator is AND'd with
+the memory value. (same as the BIT instruction).
+
+       Flags Affected: ------z-
+                       z Set if memory value AND'ed with accumulator
+                       value is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+  Absolute                     TSB addr       0C      3       6 | 1
+  Direct Page                  TSB dp         04      2       5 | 1,2
+----------------------------------------------------------------------
+    1 Add 2 cycles if 16 bit memory/accumulator mode (m=0)
+    2 Add 1 cycle if direct page register low byte is <>0.
+
+WAI Wait for Interrupt
+----------------------
+
+WAI suspends operations until and external hardware interrupt is generated.
+Power consumption by the processor is also reduced. If the disable
+interrupt flag (i=1) is set and an IRQ is pending before the execution of
+the WAI, then the WAIT is terminated and execution continues with the next
+instruction.
+
+No flags are affected by WAI.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      WAI            CB      1       3
+----------------------------------------------------------------------
+
+WDM Reserved for Future Expansion
+---------------------------------
+
+WDM is the first byte of a multi-byte instruction set to be used in future
+versions of the processor.
+At current WDM is treated like a NOP no operation.
+This instruction should NOT be used in current versions of the processor.
+WDM: William D. Mensch, JR. (65816 designer).
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles Ref
+----------------------------------------------------------------------
+                               WDM            42      2
+----------------------------------------------------------------------
+
+XBA Exchange B and A Accumulators
+---------------------------------
+
+XBA exchanges the low eight bits of the accumulator (A) with the high order
+8 bits of the accumulator (B). This operation has no regard for the setting
+of the status bit M.
+This instruction will also work in 6502 emulation mode.
+
+XBA can be used to save a temp copy of the low accumulator in the upper
+accumulator. It is also good when in 16 bit mode to invert a low and high
+byte value.
+
+XBA is the only instruction that can access the upper 8 bits of the
+accumulator in emulation mode.
+
+Some assemblers will also accept SWA (swap) for a mnemonic.
+
+      Flags Affected: n------z-
+                      n Set if the most significant bit of the new
+                        value in the low order 8 bits (A) of the
+                        accumulator is set. (former bit 15)
+                      z Set if new value of the lower order 8 bit
+                        accumulator (A) is zero.
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      XBA            EB      1       3
+                        Alais: SWA
+----------------------------------------------------------------------
+
+XCE Exchange Carry and Emulation Bits
+-------------------------------------
+
+XCE exchanges (swaps) the value in the E emulation bit and the C carry
+flag. This is the only means to access the E emulation bit.
+
+    To set emulation mode:
+            sec  ;set carry.
+            xce  ;exchange carry and emulation bits.
+
+    To set native mode:
+            clc  ;clear carry
+            xce  ;exchange carry and e bit.
+
+                            e
+    Flags Affected --mx/b---c
+                   e from previous carry flag.
+                   c from previous emulation flag.
+                   m native mode flag only. switching to native
+                     65816 mode sets to one.
+                   x x is a native mode flag only.
+                   b brk is an emulation 6502 flag only. it is set
+                     to 1 to become the x flag in native mode
+
+Addressing Mode              Syntax        Opcode   Bytes  Cycles
+----------------------------------------------------------------------
+  Implied                      XCE            FB      1       2
+----------------------------------------------------------------------
+
+TOC
+
+  ------------------------------------------------------------------------
+
+Appendix B:Composite Instruction List
+
+  ------------------------------------------------------------------------
+
+  ------------------------------------------------------------------------
+
+Opcode Mnemonic  Addressing Mode              Bytes Cycles| Reference
+=====================================================================
+   00      BRK     Stack/Interrupt                2**     7 | 9
+   01      ORA     DP Indexed Indirect,X          2       6 | 1,2
+   02      COP     Stack/Interrupt                2**     7 | 9
+   03      ORA     Stack Relative                 2       4 | 1
+   04      TSB     Direct Page                    2       5 | 2,5
+   05      ORA     Direct Page                    2       3 | 1,2
+   06      ASL     Direct Page                    2       5 | 2,5
+   07      ORA     Direct Page Indirect Long      2       6 | 1,2
+   08      PHP     Stack (Push)                   1       3 |
+   09      ORA     Immediate                      2*      2 | 1
+   0A      ASL     Accumulator                    1       2 |
+   0B      PHD     Stack (Push)                   1       4 |
+   0C      TSB     Absolute                       3       6 | 5
+   0D      ORA     Absolute                       3       4 | 1
+   0E      ASL     Absolute                       3       6 | 5
+   0F      ORA     Absolute Long                  4       5 | 1
+   10      BPL     Program Counter Relative       2       2 | 7,8
+   11      ORA     DP Indirect Indexed,Y          2       5 | 1,2,3
+   12      ORA     Direct Page Indirect           2       5 | 1,2
+   13      ORA     SR Indirect Indexed,Y          2       7 | 1
+   14      TRB     Direct Page                    2       5 | 2,5
+   15      ORA     Direct Page Indexed,X          2       4 | 1,2
+   16      ASL     Direct Page Indexed,X          2       6 | 2,5
+   17      ORA     DP Indirect Long Indexed,Y     2       6 | 1,2
+   18      CLC     Implied                        1       2 |
+   19      ORA     Absolute Indexed,Y             3       4 | 1,3
+   1A      INC     Accumulator (INA)              1       2 |
+   1B      TCS     Implied                        1       2 |
+   1C      TRB     Absolute                       3       6 | 5
+   1D      ORA     Absolute Indexed,X             3       4 | 1,3
+   1E      ASL     Absolute Indexed,X             3       7 | 5,6
+   1F      ORA     Absolute Long Indexed,X        4       5 | 1
+   20      JSR     Absolute                       3       6 |
+   21      AND     DP Indexed Indirect,X          2       6 | 1,2
+   22      JSR     Absolute Long                  4       8 |
+   23      AND     Stack Relative                 2       4 | 1
+   24      BIT     Direct Page                    2       3 | 1,2
+   25      AND     Direct Page                    2       3 | 1,2
+   26      ROL     Direct Page                    2       5 | 2,5
+   27      AND     Direct Page Indirect Long      2       6 | 1,2
+   28      PLP     Stack (Pull)                   1       4 |
+   29      AND     Immediate                      2*      2 | 1
+   2A      ROL     Accumulator                    1       2 |
+   2B      PLD     Stack (Pull)                   1       5 |
+   2C      BIT     Absolute                       3       4 | 1
+   2D      AND     Absolute                       3       4 | 1
+   2E      ROL     Absolute                       3       6 | 5
+   2F      AND     Absolute Long                  4       5 | 1
+   30      BMI     Program Counter Relative       2       2 | 7,8
+   31      AND     DP Indirect Indexed,Y          2       5 | 1,2,3
+   32      AND     Direct Page Indirect           2       5 | 1,1
+   33      AND     SR Indirect Indexed,Y          2       7 | 1
+   34      BIT     Direct Page Indexed,X          2       4 | 1,2
+   35      AND     Direct Page Indexed,X          2       4 | 1,2
+   36      ROL     Direct Page Indexed,X          2       6 | 2,5
+   37      AND     DP Indirect Long Indexed,Y     2       6 | 1,2
+   38      SEC     Implied                        1       2 |
+   39      AND     Absolute Indexed,Y             3       4 | 1,3
+   3A      DEC     Accumulator                    1       2 |
+   3B      TSC     Implied                        1       2 |
+   3C      BIT     Absolute Indexed,X             3       4 | 1,3
+   3D      AND     Absolute Indexed,X             3       4 | 1,3
+   3E      ROL     Absolute Indexed,X             3       7 | 5,6
+   3F      AND     Absolute Long Indexed,X        4       5 | 1
+   40      RTI     Stack/RTI                      1       6 | 9
+   41      EOR     DP Indexed Indirect,X          2       6 | 1,2
+   42      WDM                                    2|16      |
+   43      EOR     Stack Relative                 2       4 | 1
+   44      MVP     Block Move                     3         | 13
+   45      EOR     Direct Page                    2       3 | 1,2
+   46      LSR     Direct Page                    2       5 | 2,5
+   47      EOR     Direct Page Indirect Long      2       6 | 1,2
+   48      PHA     Stack (Push)                   1       3 | 1
+   49      EOR     Immediate                      2*      2 | 1
+   4A      LSR     Accumulator                    1       2 |
+   4B      PHK     Stack (Push)                   1       3 |
+   4C      JMP     Absolute                       3       3 |
+   4D      EOR     Absolute                       3       4 | 1
+   4E      LSR     Absolute                       3       6 | 5
+   4F      EOR     Absolute Long                  4       5 | 1
+   50      BVC     Program Counter Relative       2       2 | 7,8
+   51      EOR     DP Indirect Indexed,Y          2       5 | 1,2,3
+   52      EOR     Direct Page Indirect           2       5 | 1,2
+   53      EOR     SR Indirect Indexed,Y          2       7 | 1
+   54      MVN     Block Move                     3         | 13
+   55      EOR     Direct Page Indexed,X          2       4 | 1,2
+   56      LSR     Direct Page Indexed,X          2       6 | 2,5
+   57      EOR     DP Indirect Long Indexed,Y     2       6 | 1,2
+   58      CLI     Implied                        1       2 |
+   59      EOR     Absolute Indexed,Y             3       4 | 1,3
+   5A      PHY     Stack (Push)                   1       3 | 10
+   5B      TCD     Implied                        1       2 |
+   5C      JMP     Absolute Long                  4       4 |
+   5D      EOR     Absolute Indexed,X             3       4 | 1,3
+   5E      LSR     Absolute Indexed,X             3       7 | 5,6
+   5F      EOR     Absolute Long Indexed,X        4       5 | 1
+   60      RTS     Stack (RTS)                    1       6 |
+   61      ADC     DP Indexed Indirect,X          2       6 | 1,2,4
+   62      PER     Stack (PC Relative Long)       3       6 |
+   63      ADC     Stack Relative                 2       4 | 1,4
+   64      STZ     Direct Page                    2       3 | 1,2
+   65      ADC     Direct Page                    2       3 | 1,2,4
+   66      ROR     Direct Page                    2       5 | 1
+   67      ADC     Direct Page Indirect Long      2       6 | 1,4
+   68      PLA     Stack (Pull)                   1       4 | 1
+   69      ADC     Immediate                      2*      2 | 1,4
+   6A      ROR     Accumulator                    1       2 |
+   6B      RTL     Stack (RTL)                    1       6 |
+   6C      JMP     Absolute Indirect              3       5 | 11,12
+   6D      ADC     Absolute                       3       4 | 1,4
+   6E      ROR     Absolute                       3       6 | 5
+   6F      ADC     Absolute Long                  4       5 | 1,4
+   70      BVS     Program Counter Relative       2       2 | 7,8
+   71      ADC     DP Indirect Indexed,Y          2       5 | 1,2,3,4
+   72      ADC     Direct Page Indirect           2       5 | 1,2,4
+   73      ADC     SR Indirect Indexed,Y          2       7 | 1,4
+   74      STZ     Direct Page Indexed,X          2       4 | 1,2
+   75      ADC     Direct Page Indexed,X          2       4 | 1,2,4
+   76      ROR     Direct Page Indexed,X          2       6 | 2,5
+   77      ADC     DP Indirect Long Indexed,Y     2       6 | 1,2,4
+   78      SEI     Implied                        1       2 |
+   79      ADC     Absolute Indexed,Y             3       4 | 1,3,4
+   7A      PLY     Stack (Pull)                   1       4 | 10
+   7B      TDC     Implied                        1       2 |
+   7C      JMP     Absolute Indexed Indirect      3       6 |
+   7D      ADC     Absolute Indexed,X             3       4 | 1,3,4
+   7E      ROR     Absolute Indexed,X             3       7 | 5,6
+   7F      ADC     Absolute Long Indexed,X        4       5 | 1,4
+   80      BRA     Program Counter Relative       2       3 | 8
+   81      STA     DP Indexed Indirect,X          2       6 | 1,2
+   82      BRL     Program Counter Relative Long  3       4 |
+   83      STA     Stack Relative                 2       4 | 1
+   84      STY     Direct Page                    2       3 | 2,10
+   85      STA     Direct Page                    2       3 | 1,2
+   86      STX     Direct Page                    2       3 | 2,10
+   87      STA     Direct Page Indirect Long      2       6 | 1,2
+   88      DEY     Implied                        1       2 |
+   89      BIT     Immediate                      2*      2 | 1
+   8A      TXA     Implied                        1       2 |
+   8B      PHB     Stack (Push)                   1       3 |
+   8C      STY     Absolute                       3       4 | 10
+   8D      STA     Absolute                       3       4 | 1
+   8E      STX     Absolute                       3       4 | 10
+   8F      STA     Absolute Long                  4       5 | 1
+   90      BCC     Program Counter Relative       2       2 | 7,8
+   91      STA     DP Indirect Indexed,Y          2       6 | 1,2
+   92      STA     Direct Page Indirect           2       5 | 1,2
+   93      STA     SR Indirect Indexed,Y          2       7 | 1
+   94      STY     Direct Page Indexed,X          2       4 | 2,10
+   95      STA     Direct Page Indexed,X          2       4 | 1,2
+   96      STX     Direct Page Indexed,Y          2       4 | 2,10
+   97      STA     DP Indirect Long Indexed,Y     2       6 | 1,2
+   98      TYA     Implied                        1       2 |
+   99      STA     Absolute Indexed,Y             3       5 | 1
+   9A      TXS     Implied                        1       2 |
+   9B      TXY     Implied                        1       2 |
+   9C      STZ     Absolute                       3       4 | 1
+   9D      STA     Absolute Indexed,X             3       5 | 1
+   9E      STZ     Absolute Indexed,X             3       5 | 1
+   9F      STA     Absolute Long Indexed,X        4       5 | 1
+   A0      LDY     Immediate                      2+      2 | 10
+   A1      LDA     DP Indexed Indirect,X          2       6 | 1,2
+   A2      LDX     Immediate                      2+      2 | 10
+   A3      LDA     Stack Relative                 2       4 | 1
+   A4      LDY     Direct Page                    2       3 | 2,10
+   A5      LDA     Direct Page                    2       3 | 1,2
+   A6      LDX     Direct Page                    2       3 | 2,10
+   A7      LDA     Direct Page Indirect Long      2       6 | 1,2
+   A8      TAY     Implied                        1       2 |
+   A9      LDA     Immediate                      2*      2 | 1
+   AA      TAX     Implied                        1       2 |
+   AB      PLB     Stack (Pull)                   1       4 |
+   AC      LDY     Absolute                       3       4 | 10
+   AD      LDA     Absolute                       3       4 | 1
+   AE      LDX     Absolute                       3       4 | 10
+   AF      LDA     Absolute Long                  4       5 | 1
+   B0      BCS     Program Counter Relative       2       2 | 7,8
+   B1      LDA     DP Indirect Indexed,Y          2       5 | 1,2,3
+   B2      LDA     Direct Page Indirect           2       5 | 1,2
+   B3      LDA     SR Indirect Indexed,Y          2       7 | 1
+   B4      LDY     Direct Page Indexed,X          2       4 | 2,10
+   B5      LDA     Direct Page Indexed,X          2       4 | 1,2
+   B6      LDX     DP Indexed,Y                   2       4 | 2,10
+   B7      LDA     DP Indirect Long Indexed,Y     2       6 | 1,2
+   B8      CLV     Implied                        1       2 |
+   B9      LDA     Absolute Indexed,Y             3       4 | 1,3
+   BA      TSX     Implied                        1       2 |
+   BB      TYX     Implied                        1       2 |
+   BC      LDY     Absolute Indexed,X             3       4 | 3,10
+   BD      LDA     Absolute Indexed,X             3       4 | 1,3
+   BE      LDX     Absolute Indexed,Y             3       4 | 3,10
+   BF      LDA     Absolute Long Indexed,X        4       5 | 1
+   C0      CPY     Immediate                      2+      2 | 10
+   C1      CMP     DP Indexed Indirect,X          2       6 | 1,2
+   C2      REP     Immediate                      2       3 |
+   C3      CMP     Stack Relative                 2       4 | 1
+   C4      CPY     Direct Page                    2       3 | 2,10
+   C5      CMP     Direct Page                    2       3 | 1,2
+   C6      DEC     Direct Page                    2       5 | 2,5
+   C7      CMP     Direct Page Indirect Long      2       6 | 1,2
+   C8      INY     Implied                        1       2 |
+   C9      CMP     Immediate                      2*      2 | 1
+   CA      DEX     Implied                        1       2 |
+   CB      WAI     Implied                        1       3 | 15
+   CC      CPY     Absolute                       3       4 | 10
+   CD      CMP     Absolute                       3       4 | 1
+   CE      DEC     Absolute                       3       6 | 5
+   CF      CMP     Absolute Long                  4       5 | 1
+   D0      BNE     Program Counter Relative       2       2 | 7,8
+   D1      CMP     DP Indirect Indexed,Y          2       5 | 1,2,3
+   D2      CMP     Direct Page Indirect           2       5 | 1,2
+   D3      CMP     SR Indirect Indexed,Y          2       7 | 1
+   D4      PEI     Stack (Direct Page Indirect)   2       6 | 2
+   D5      CMP     Direct Page Indexed,X          2       4 | 1,2
+   D6      DEC     Direct Page Indexed,X          2       6 | 2,5
+   D7      CMP     DP Indirect Long Indexed,Y     2       6 | 1,2
+   D8      CLD     Implied                        1       2 |
+   D9      CMP     Absolute Indexed,Y             3       4 | 1,3
+   DA      PHX     Stack (Push)                   1       3 | 10
+   DB      STP     Implied                        1       3 | 14
+   DC      JMP     Absolute Indirect Long         3       6 |
+   DD      CMP     Absolute Indexed,X             3       4 | 1,3
+   DE      DEC     Absolute Indexed,X             3       7 | 5,6
+   DF      CMP     Absolute Long Indexed,X        4       5 | 1
+   E0      CPX     Immediate                      2+      2 | 10
+   E1      SBC     DP Indexed Indirect,X          2       6 | 1,2,4
+   E2      SEP     Immediate                      2       3 |
+   E3      SBC     Stack Relative                 2       4 | 1,4
+   E4      CPX     Direct Page                    2       3 | 2,10
+   E5      SBC     Direct Page                    2       3 | 1,2,4
+   E6      INC     Direct Page                    2       5 |
+   E7      SBC     Direct Page Indirect Long      2       6 | 1,2,4
+   E8      INX     Implied                        1       2 |
+   E9      SBC     Immediate                      2*      2 |
+   EA      NOP     Implied                        1       2 |
+   EB      XBA     Implied                        1       3 |
+   EC      CPX     Absolute                       3       4 | 10
+   ED      SBC     Absolute                       3       4 | 1,4
+   EE      INC     Absolute                       3       6 | 5
+   EF      SBC     Absolute Long                  4       5 | 1,4
+   F0      BEQ     Program Counter Relative       2       2 | 7,8
+   F1      SBC     DP Indirect Indexed,Y          2       5 | 1,2,3,4
+   F2      SBC     Direct Page Indirect           2       5 | 1,2,4
+   F3      SBC     SR Indirect Indexed,Y          2       7 | 1,4
+   F4      PEA     Stack (Absolute)               3       5 |
+   F5      SBC     Direct Page Indexed,X          2       4 | 1,2,4
+   F6      INC     Direct Page Indexed,X          2       6 | 2,5
+   F7      SBC     DP Indirect Long Indexed,Y     2       6 | 1,2,4
+   F8      SED     Implied                        1       2 |
+   F9      SBC     Absolute Indexed,Y             3       4 | 1,3,4
+   FA      PLX     Stack (Pull)                   1       4 | 10
+   FB      XCE     Implied                        1       2 |
+   FC      JSR     Absolute Indexed Indirect      3       8 |
+   FD      SBC     Absolute Indexed,X             3       4 | 1,3,4
+   FE      INC     Absolute Indexed,X             3       7 | 5,6
+   FF      SBC     Absolute Long Indexed,X        4       5 | 1,4
+=====================================================================
+
+*  Add 1 if m=0 (16 bit memory/accumulator).
+** Opcode is 1 byte, but program counter value pushed onto stack is
+   incremented by 2 allowing for optional signature byte.
++  Add 1 byte if x=0 (16-bit index registers).
+1  Add 1 cycle if m=0 (16-bit memory/accumulator).
+2  Add 1 cycle if low bye of Direct Page (zero page) register
+   is other than zero (DL<>0).
+3  Add 1 cycle if adding index crosses a page boundary.
+4  Add 1 cycle if CPU is 65C02 and d=1 (decimal mode. 65C02 only).
+5  Add 2 cycles if m=0 (16-bit memory/accumulator).
+6  Subtract 1 cycle if CPU is 65C02 and no page boundary crossed.
+7  Add 1 cycle if branch is taken.
+8  Add 1 more cycle if branch taken crosses page boundary on 6502,
+   65C02, or 65816/65082's emulation mode (e=1).
+9  Add 1 cycle for 65802/65816 native mode (e=0).
+10 Add 1 cycle if x=0 (16-bit index registers).
+11 Add 1 cycle if CPU is 65C02.
+12 6502: if low byte of operand is $FF (ie. operand is $xxFF): yields
+   incorrect result.
+13 7 cycles per byte moved.
+14 Uses 3 cycles to shut the processor down; additional cycles are
+   required by reset to restart CPU.
+15 Uses 3 cycles to shut the processor down; additional cycles are
+   required by interrupt to restart it.
+16 Byte and cycle counts subject to change in future processors which
+   expand WDM into 2-byte opcode portions of instructions of varying
+   lengths.
+
+TOC
+
+  ------------------------------------------------------------------------
+
+========================================================================
+  ------------------------------------------------------------------------
+
+=====================
+Appendix C: IC Pinouts
+=====================
+
+           /=============\                     /=============\
+       VP  I1          40I RES            Vss  I1          40I RES
+      RDY  I2          39I VDA            RDY  I2          39I o2 (OUT)
+    ABORT  I3          38I M/X       o1 (OUT)  I3          38I SO
+      IRQ  I4          37I o2 (IN)        IRQ  I4          37I o2 (IN)
+       ML  I5          36I BE              NC  I5          36I NC
+      NMI  I6          35I E              NMI  I6          35I NC
+      VPA  I7          34I R/W           SYNC  I7          34I R/W
+      VDD  I8          33I D0/BA0         Vdd  I8          33I D0
+       A0  I9  W65C816 32I D1/BA1          A0  I9   6502   32I D1
+       A1  I10         31I D2/BA2          A1  I10         31I D2
+       A2  I11         30I D3/BA3          A2  I11         30I D3
+       A3  I12         29I D4/BA4          A3  I12         29I D4
+       A4  I13         28I D5/BA5          A4  I13         28I D5
+       A5  I14         27I D6/BA6          A5  I14         27I D6
+       A6  I15         26I D7/BA7          A6  I15         26I D7
+       A7  I16         25I A15             A7  I16         25I A15
+       A8  I17         24I A14             A8  I17         24I A14
+       A9  I18         23I A13             A9  I18         23I A13
+      A10  I19         22I A12            A10  I19         22I A12
+      A11  I20         21I Vss            A11  I20         21I Vss
+           \=============/                     \=============/
+
+Notes:
+   ML: Memory Lock line (pin 5) is asserted low during the execution of
+       the read-modify-write (asl,dec,inc,lsr,rol,ror,trb, and tsb
+       instructions to inform other ics that the bus may not be claimed
+       yet.
+
+   VP: Vector Pull is asserted whenever any of the hardware vector
+       address's are being accessed during an IRQ.
+
+ Abort:  An input.  When asserted caused the current instruction to be
+         aborted.
+
+   VPA/VDA.  Valid Program Address and Valid Data Address.  These two
+             signals extend on the 6502 SYNC line - to better handle
+             DMA schemes.
+
+       VPA   VDA
+        0     0  -Internal Operation
+        0     1  -Valid program address
+        1     0  -Valid data address
+        1     1  -Opcode fetch
+
+    M/X: Memory and Index lines.  These signals are multiplexed on pin
+         38.  M is available during phase zero and X during Phase one.
+         These two signals reflect the contents of the status register
+         m and x flags, allowing other devices to decode opcode fetches.
+
+    E: Emulation pin.  This signal reflects the state of the processors
+       emulation bit (E).
+
+TOC
+
+  ------------------------------------------------------------------------
+
+===================================================================
+44 PIN PLCC Pinout.
+
+                    A
+                    B
+                    O               R           0
+            M   I   R   R   V   V   E   V   M   2
+            L   R   T   D   P   S   S   D   /   I   B
+            B   Q   B   Y   B   S   B   A   X   N   E
+           /----I---I---I---I---I---I---I---I---I---I-\
+          / 6   5   4   3   2  1  44  43  42  41  40 I
+    NMIB I 7                                       39 - E
+     VPA I 8                                       38 - R/WB
+     VDD I 9                                       37 - VDD
+      A0 I 10                                      36 - D0/BA0
+      A1 I 11                                      35 - D1/BA1
+     VSS I 12               W65C816S               34 - D2/BA2
+      A2 I 13                                      33 - D3/BA3
+      A3 I 14                                      32 - D4/BA4
+      A4 I 15                                      31 - D5/BA5
+      A5 I 16                                      30 - D6/BA6
+      A6 I 17                                      29 - D7/BA7
+         I 18  19  20  21  22  23  24  25  26  27  28 I
+         \--l---l---l---l---l---l---l---l---l---l---l-/
+            A   A   A   A   A   V   V   A   A   A   A
+            7   8   9   1   1   S   S   1   1   1   1
+                        0   1   S   S   2   3   4   5
+
+                   44 pin W65C816S PLCC Pinout
+
+
+TOC
+
+           -----------------------------------------------------
+
+          Send Email
+
+Last updated on: Tuesday, 23-Dec-1997 23:51:46 CST 92

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+
+	Interrupt Processing Sequence
+
+
+The interrupt processing sequence is initiated as the direct result of hard-
+vare Abort, Interrupt Request, Non-Maskable Interrupt, or Reset inputs.
+The interrupt sequence can also be initiated as a result of the Break or
+Co-Processor instructions within the software. The following listings
+describe the function of each cycle in the interrupt processing sequence:
+
+
+Hardware Interrupt /ABORT, /IRQ, /NMI, /RES Inputs
+
+Cycle No.
+ E = 0 E = 1 Address  Data   R/W  SYNC VDA VPA  VP Description
+
+   1     1    PC        X     1    1    1   1   1  Internal Operation
+   2     2    PC        X     1    0    0   0   1  Internal Operation
+   3    [1]    S       PB     0    0    1   0   1  Write PB to Stack, S-1ÑS
+   4     3     S     PCH [2] 0[3]  0    1   0   1  Write PCH to Stack, S-1ÑS
+   5     4     S     PCL 12] 0[3]  0    1   0   1  Write PCL to Stack, S-1ÑS
+   6     5     S      P [4]  0[3]  0    1   0   1  Write P to Stack, S-1ÑS
+   7     6    VL      (VL)    1    0    1   0   0  Read Vector Low Byte,
+							 0->PD, 1->P1, OO->PB
+   8     7    VH      (VH)    1    0    1   0   0  Read Vector High 8yte
+
+
+Software Interrupt - BRK, COP Instructions
+
+Cycle No.
+ E = 0 E = 1 Address  Data   R/W  SYNC VDA VPA  VP Description
+   1     1   PC-2       X     1    1    1   1   1  Opcode
+   2     2   PC-1       X     1    0    0   1   1  Signature
+   3    111    S       PB     0    0    1   0   1  Write PB to Stack, S-1ÑS
+   4     3     S       PCH    0    0    1   0   1  Write PCH to Stack, S-1 - S
+   5     4     S       PCL    0    0    1   0   1  Write PCL to Stack, S-1ÑS
+   6     5     S        P     0    0    1   0   1  Write P to Stack, S-1ÑS
+   7     6    VL      (VL)    1    0    1   0   0  Read Vector Low Byte,
+							 0ÑPo, 1ÑPl, 00ÑPB
+   8     7    VH      (VH)    1    0    1   0   0  Read Vector High Byte
+
+Notes:
+	[1] Delete this cycle in Emulation mode.
+	[2] Abort writes address of aborted opcode.
+	[3] R/W remains in the high state during Reset.
+	[4] In Emulation mode, bit 4 written to stack is changed to 0.
+
+
+
+	Table 3. Vector Locations
+
+				Emulation   Native	Priority
+	Name	Source		(E = 1)	    (E = 0)	Level
+
+	ABORT	Hardware	00FFF8,9    00FFE8,9	 2
+	BRK	Software	00FFFE,F    00FFE6,7	N/A
+	COP	Software	00FFF4,5    00FFE4,5	N/A
+	IRQ	Hardware	00FFFE,F    00FFEE,F	 4
+	NMI	Hardware	00FFFA,B    00FFEA,B	 3
+	RES	Hardware	00FFFC.D    00FFFC,D	 1
+

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files/docs/snes/Qaddress.txt

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+Addressing mode quick reference
+By Qwertie (QwertMan@hotmail.com)
+
+I lifted this straight from my emulator code, which I tend to comment heavily :)
+
+Please correct me if any of this is wrong...
+
+// ADDRESSING MODES - several categories, one mode from each category can be combined
+// None of the instructions can use all combinations, and certain combinations are
+// never used with any instruction.
+	// Used to calculate memory address:
+	//   Absolute: Argument is two bytes and specifies a memory location
+	//     + Long: Argument is three bytes instead             opcode $addr
+	//   Direct: Argument is one byte; memory address formed by adding D.
+	//     Bank is always 0, unless indirect addressing is also used, in
+	//     which case the bank is the program bank.            opcode <$addr
+	//   Stack Relative: Argument is one byte, which is added to the stack pointer
+	//     to find the final address.                          opcode $addr,S
+	// Indexed addressing:
+	//   Indexed: Memory location argument is added to X or Y to get the final
+	//     memory location.                                    opcode $addr,X or Y
+	//   Note that certain indexed addressing modes only work with the X register
+	//     or only with the Y register.
+	//
+	// Note! The above addressing mode specifiers are used only to specify the
+	// size of the argument and how it is used.  The specifiers DO NOT SPECIFY
+	// anything about the actual memory location being referenced.
+	// For example, suppose the Absolute Indexed mode is used.  This means that
+	// the argument to the opcode is 16 bits and will be added to an index
+	// register.  It does not, however, mean that the value at the calculated
+	// memory location will be a 16-bit value.  The size of the value at the memory
+	// location is determined by either:
+	//   a. whether the processor is in 16-bit mode (and whether E=0), or
+	//   b. if indirect addressing is used, whether the Long Indirect mode is used.
+	//
+	// Indirect addressing:
+	//   Indirect: Uses indirection (pointers).  In other words, after the memory
+	//     location is found and the contents are loaded, the contents are used as
+	//     a SECOND memory location and the value at the second memory location is
+	//     used in the operation.                              opcode ($addr)
+	//     + Direct Long: Normally, the pointer found at the specified location
+	//       will be two bytes.  If Direct Indirect Long is used, the pointer
+	//       at the memory address found will be a three-byte long address.
+	//                                                         opcode [$addr]
+	// Indexed Indirect (preindexed; (arg,x)) vs. Indirect Indexed (postindexed;
+	// (arg),x): remember, these two are different!
+	//
+	// Stack relative addressing: denoted by arg,s, the address is calculated by
+	//   adding the argument value to the stack pointer.  Always accesses bank 0,
+	//   since the stack is always in bank 0.
+// There is also two more modes, which are never used with any other specifiers:
+	// Implied: Opcode has no arguments
+	// Immediate: The argument specifies an actual constant value to be used,
+	//   rather than a memory address. [opcode #$XX or #$XXXX]
+
+Vector Locations:
+In Emulation Mode:      In Native Mode:
+00.FFFE  /IRQ or BRK    00.FFEE  /IRQ
+00.FFFC  /RESET         00.FFEC  (Unused)
+00.FFFA  /NMI           00.FFEA  /NMI
+00.FFF8  /ABORT         00.FFE8  /ABORT
+00.FFF6  (Unused)       00.FFE6  BRK
+00.FFF4  CSP            00.FFE4  CSP
+-The location after the one listed holds the high byte of the address
+-CSP (Call system procedure) is same as the COP mnemonic

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files/docs/snes/SNES-ROM.TXT

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+
+             ______  _____        _____    _______       ___  ___
+            /   __/ /. _  \   ___/  __/   |____   \___  /.  \/   \
+            \___ .\//  |.  \ / . \__ .\    |.    _/   \//        .\
+           /.     \\   |:  .\  __/    \\   || |  .\ !  \     \/.   \
+           \______ /___|____/____\____ /   |__|   \\___/____||:     \
+             By Mind Rape                      \___/         |______/
+             v1.5 (C) Damaged Cybernetics 1994-95
+
+
+   This document main goal is show where one can find the SNES ROM
+   information.  Most of this information was collected thru hacking
+   the rom to death and help from Norm/Yoshi/chp.
+
+   License codes are taken from SU and probably incorrect.
+
+   Source? None here, if you are going to screw with the bin,
+   you probably know what you are doing (HOPEFULLY).
+
+   If you have any questions, comments,corrections, additional information,
+   you can either find me on IRC as (MindRape) or you can send me email
+   (much prefered) mind@primenet.com.  Also if you write anything
+   interesting then send it to me!
+
+   You may distribute this document freely, but you may not change
+   the information here and redistribute.  If you use this information
+   please credit me.  You steal this information and say you did it,
+   you know it's a LIE and there you are.
+
+=[SNES ROM Makeup]===========================================================
+
+ROM Title     : 21 Bytes
+
+  * Titles are all in upper case
+  * Japanese titles are in high ascii values
+    good rule of thumb if you can't read the title and
+    it's country code is Japan and your American,
+    you probably can't play it. :>
+
+Rom Makeup    : 7654 3210
+                0000-0000
+                |__| |__|
+                |    |
+                |    |___Bank Size 0001 = HiROM   (64K Banks Mode 21)
+                |                  0000 = Low Rom (32K Banks Mode 20)
+                |
+                |________ROM Speed 0111 = Fast Rom
+                                   0000 = Slow Rom
+
+                                   * Could someone give the correct
+                                   * speeds of the ROMs?  I got
+                                   * conflicting answers.
+
+
+ROM Type      :  1 Byte
+
+  Hex   ROM Type
+  ---------------------
+   00   ROM
+   01   ROM/RAM
+   02   ROM/SRAM
+   03   ROM/DSP1
+   04   ROM/DSP1/RAM
+   05   ROM/DSP1/SRAM
+   06   FX
+
+   * SRAM = Save Ram
+   * DSP1 = Nintendo's 1st generation of DSP (Math coprocessor)
+   * FX   = RISC based math coprocessor
+            Only a couple of games support the FX Chip, Star Fox
+            is the most well known one.
+
+
+ROM Size      : 1 BYTE
+
+  Hex   Size
+  --------------
+   08    2 Mbit
+   09    4 Mbit
+   0A    8 Mbit
+   0B   16 Mbit
+   0C   32 Mbit
+
+  * As of this documentation 32MBit ROMs are the largest that
+    Nintendo currently uses.  Rumors of a 40+ kart are around,
+    but cannot be verified.
+
+  * 8MBit ROMs are the most common in the entire library of
+    SNES karts
+
+  * ROMs are always multiples 2, thus 2MBit ROMs are the smallest
+    Space Invaders (c) Taito is a 2MBit ROM (Japan only)
+
+  * Easy way to calc rom size without a lookup table
+
+      1 << (ROM_SIZE - 7) MBits
+
+      ie.   8Mbit ROMs = 0Ah = 10d
+            1 << (0A-7) = 8 Mbit
+
+SRAM Size      : 1 BYTE
+
+  Hex   Size
+  --------------
+   00   No SRAM
+   01   16 Kbit
+   02   32 Kbit
+   03   64 Kbit
+
+    * 64Kbit is the largest SRAM size that Nintendo currently uses.
+    * 256Kbit is standard for most copiers.
+
+    * Easy way to calc SRAM Size without a lookup table
+
+        1 << (3+SRAM_BYTE) Kbits
+
+        ie. 16Kbit = 01
+            1 << (3+1) = 16
+
+
+COUNTRY CODE  : 1 BYTE
+
+  Hex    Country                 Video Mode
+  ------------------------------------------
+   00    Japan                   (NTSC)
+   01    USA                     (NTSC)
+   02    Europe, Oceania, Asia    (PAL)
+   03    Sweden                   (PAL)
+   04    Finland                  (PAL)
+   05    Denmark                  (PAL)
+   06    France                   (PAL)
+   07    Holland                  (PAL)
+   08    Spain                    (PAL)
+   09    Germany, Austria, Switz  (PAL)
+   10    Italy                    (PAL)
+   11    Hong Kong, China         (PAL)
+   12    Indonesia                (PAL)
+   13    Korea                    (PAL)
+
+  * Country Codes are from SU.INI, could someone verify these?
+
+LICENSE       : 1 BYTE
+     0 <Invalid License Code>
+     1 Nintendo
+     5 Zamuse
+     8 Capcom
+     9 HOT B
+    10 Jaleco
+    11 STORM (Sales Curve) (1)
+    15 Mebio Software
+    18 Gremlin Graphics
+    21 COBRA Team
+    22 Human/Field
+    24 Hudson Soft
+    26 Yanoman
+    28 Tecmo (1)
+    30 Forum
+    31 Park Place Productions / VIRGIN
+    33 Tokai Engeneering (SUNSOFT?)
+    34 POW
+    35 Loriciel / Micro World
+    38 Enix
+    40 Kemco (1)
+    41 Seta Co.,Ltd.
+    45 Visit Co.,Ltd.
+    53 HECT
+    61 Loriciel
+    64 Seika Corp.
+    65 UBI Soft
+    71 Spectrum Holobyte
+    73 Irem
+    75 Raya Systems/Sculptured Software
+    76 Renovation Pruducts
+    77 Malibu Games (T*HQ Inc.) / Black Pearl
+    79 U.S. Gold
+    80 Absolute Entertainment
+    81 Acclaim
+    82 Activision
+    83 American Sammy
+    84 GameTek
+    85 Hi Tech
+    86 LJN Toys
+    90 Mindscape
+    93 Technos Japan Corp. (Tradewest)
+    95 American Softworks Corp.
+    96 Titus
+    97 Virgin Games
+    98 Maxis
+   103 Ocean
+   105 Electronic Arts
+   107 Laser Beam
+   110 Elite
+   111 Electro Brain
+   112 Infogrames
+   113 Interplay
+   114 LucasArts
+   115 Sculptured Soft
+   117 STORM (Sales Curve) (2)
+   120 THQ Software
+   121 Accolade Inc.
+   122 Triffix Entertainment
+   124 Microprose
+   127 Kemco (2)
+   130 Namcot/Namco Ltd. (1)
+   132 Koei/Koei! (second license?)
+   134 Tokuma Shoten Intermedia
+   136 DATAM-Polystar
+   139 Bullet-Proof Software
+   140 Vic Tokai
+   143 I'Max
+   145 CHUN Soft
+   146 Video System Co., Ltd.
+   147 BEC
+   151 Kaneco
+   153 Pack in Video
+   154 Nichibutsu
+   155 TECMO (2)
+   156 Imagineer Co.
+   160 Wolf Team
+   164 Konami
+   165 K.Amusement
+   167 Takara
+   169 Technos Jap. ????
+   170 JVC
+   172 Toei Animation
+   173 Toho
+   175 Namcot/Namco Ltd. (2)
+   177 ASCII Co. Activison
+   178 BanDai America
+   180 Enix
+   182 Halken
+   186 Culture Brain
+   187 Sunsoft
+   188 Toshiba EMI/System Vision
+   189 Sony (Japan) / Imagesoft
+   191 Sammy
+   192 Taito
+   194 Kemco (3) ????
+   195 Square
+   196 NHK
+   197 Data East
+   198 Tonkin House
+   200 KOEI
+   202 Konami USA
+   205 Meldac/KAZe
+   206 PONY CANYON
+   207 Sotsu Agency
+   209 Sofel
+   210 Quest Corp.
+   211 Sigma
+   214 Naxat
+   216 Capcom Co., Ltd. (2)
+   217 Banpresto
+   219 Hiro
+   221 NCS
+   222 Human Entertainment
+   223 Ringler Studios
+   224 K.K. DCE / Jaleco
+   226 Sotsu Agency
+   228 T&ESoft
+   229 EPOCH Co.,Ltd.
+   231 Athena
+   232 Asmik
+   233 Natsume
+   234 King/A Wave
+   235 Atlus
+   236 Sony Music
+   238 Psygnosis / igs
+   243 Beam Software
+   244 Tec Magik
+   255 Hudson Soft
+
+  * License Codes are from SU.INI, could someone verify these?
+
+  * I believe the # of licenses is low.  Is it possible that
+    License and Country codes are used in conjuction to produce
+    that many more licenses?
+
+VERSION - 1 byte
+
+  * The Version is interpeted this way.
+    1.?? - (thanks to yoshi for the correction)
+
+CHECKSUM COMPLEMENT - 2 bytes the complement of the checksum :>
+
+  The bits are reversed of the CHECKSUM
+
+CHECKSUM            - 2 bytes Checksum of the bin
+
+  * Anyone know how the checksum is calculated for the ROM?
+
+NMI/VBL Vector     - 2 bytes                            - OFFSET 81FAh  (lowrom)
+                                                          OFFSET 101FAh (hirom)
+
+RESET Vector       - 2 bytes where to start our code at - OFFSET 81FCh  (lowrom)
+                                                        - OFFSET 101FAh (hirom)
+  * 8000h is common for Low Roms
+
+=[READING THE CORRECT BIN INFORMATION]==================================
+
+ The bin information can be found in 2 possible places,
+
+    a) End of the 1st 32K bank (Low ROM)  (81c0h/w 512 byte header)
+    b) End of the 1st 64K bank (HiROM)    (101c0h/w 512 byte header)
+
+ You could use UCON's method (author chp).
+
+ The method is as followed:
+
+ UCON's method is to OR the Checksum and the Complement.  If the
+ resulting value is FFFFh, then we found the correct location of
+ to extract rest of the data out.  HOWEVER!  This fails on several
+ karts, such as Castle Wolfenstien 3D and Super Tetris 3 for example.
+
+ Reason being is that not all developers put the correct complement
+ or bother even to implement it.  I would suspect!  That this maybe
+ a ploy to keep other developers out of the bin, for if they can't
+ find the reset vector, disassembling becomes a bit difficult.
+
+=[Other Information on SNES?]================================================
+
+ Famicom Development FTP Site
+   busop.cit.wayne.edu - pub/famidev
+
+ Yoshi's SNES Documentation 2.3
+
+   This is considered the BEST source of SNES hardware information,
+   and the most complete!
+
+   busop.cit.wayne.edu - pub/famidev/incoming/sndoc230.lzh
+
+=[w0rd!]=====================================================================
+
+w0rd to all following console dudes
+
+GoosE_,yoshi,sir jinx,chp,SHORYUKEN,_bubsy,felon,archimede
+rugalz,SinZ,dragonz,procyon,royce,hoodlem,bri_acid,kamikitty,
+norm,ZillionZ Members,grayarea,Victor,drunkfux(h0h0h0h0),dmessiah,
+piratendo
+
+<insert your favorite group(s) greet here> (heh)
+
+Later Mind Rape

+ 971 - 0
files/docs/snes/SNES.DOC

@@ -0,0 +1,971 @@
+=-=-=
+SNES Documentation v1.3: Written by Yoshi of Digital Exodus. 
+=-=-=
+1)    Memory Map.
+	 i) "Main" memory map.
+	ii) Additional info.
+2)    SNES Color explaination.
+3)    SNES DMA Memory Map and explaination.
+4)    SNES Graphics (tiles) explaination.
+5)    SNES Screen mode definitions.
+6)    SNES OAM/Sprite explaination.
+7)    Magicom Disk registers and Memory controller locations.
+69)   About the author...
+FF)   Greetings, Thanx, etc...
+=-=-=
+1)    Memory Map.
+	 i) "Main" memory map.
+-----------                              
+	Just so you know... the R and/or W's on the left side before the             
+	memory location mean [R]eadable and/or [W]riteable. I don't know
+	what happens if you try to read from the write-only registers:
+	I think you get bogus data, but that's about it.
+-----------                              
+ W   |$2100: Screen display register.
+			x000bbbb
+					x: 0 = Screen on.
+					   1 = Screen off.
+				   bbbb: 0-$F = Brightness of screen.
+
+			*** If you increment $2100 so the register goes up
+			    to $xF (x being whatever), you can make the
+			    screen "fade in". Make -SURE- you do this only
+			    during the VBlank period! If you don't, the screen
+			    goes totally wacko! The 'GS programmers like myself
+			    call it "Syncing to the VBL". 
+-----------                              
+ W   |$2101: OAM (Sprite) sizes.
+			sssnnbbb
+					s: Size. 
+					n: Name selection (upper 4k word address).
+					b: Base selection (8k word segment address).
+
+			*** The sizes are defined as follows:
+					000: 8x8 or 16x16
+					001: 8x8 or 32x32
+
+			*** I've never used this register, nor sprites.
+			    Check Section 6 for information
+			    which was not done by me: If you understand
+			    it better than I do, good deal.
+-----------                              
+ W   |$2102: Address of OAM (Sprites).
+			???????? | ????????  
+			
+			*** This register i've never used. All I know is
+			    that it's a -WORD- in length, not a byte.
+-----------                              
+ W   |$2104: Data for OAM (Sprites).
+			????????
+
+			*** I've never used this register. It's like $210D:
+			    You have to store a value in it twice.
+-----------                              
+ W   |$2105: Screen mode.
+			abcdfeee
+					a: Plane 3 tile size.
+					b: Plane 2 tile size.
+					c: Plane 1 tile size.
+					d: Plane 0 tile size.
+						0 = 8x8 tiles.
+						1 = 16x16 tiles.
+					e: MODE definition. 
+					f: Make Plane 2 take highest priority.
+-----------                              
+ W   |$2106: Screen pixelation (aka. MOSAIC) register.
+			xxxxabcd
+					x: 0-$F = Pixel size.
+					a: Affect plane 3.
+					b: Affect plane 2.
+					c: Affect plane 1.
+					d: Affect plane 0.
+
+			*** Just like $2100, this only works during VBlank.
+			    I recommend you setup what planes you want to
+			    affect at the start of the program, then to
+			    make them change, do the following:
+					LDA #$03    ; Affect planes 0 and 1.
+					STA TempReg1
+					STA $2106
+					JSR WaitVBlank
+					LDA TempReg1
+				 Loop STA $2106
+					CLC
+					ADC #$10
+					CMP #$F3
+					BNE Loop
+-----------                              
+ W   |$2107: Plane 0 VRAM location register.
+			xxxxxxab
+					x: Address of VRAM location.
+				     ab: Virtual screen size selection.
+
+		  *** The virtual screen size dealy goes like this:
+			32x32 to 32x64 to 64x32 to 64x64. Visually,
+			you only see 32x32(x25) at once unless you
+			change the ACTUAL screen size.
+
+			*** The way I use this register is pretty simple.
+			    Lets say the VRAM is in $2000... Therefore,
+			    we'd go like this:
+					LDA #$20
+					STA $2107
+-----------                              
+ W   |$2108: Plane 1 VRAM location register.
+ W   |$2109: Plane 2 VRAM location register.
+ W   |$210A: Plane 3 VRAM location register.
+			*** All of these follow the same definition as $2107.
+-----------                              
+ W   |$210B: Tile VRAM location register.
+			aaaabbbb
+					a: Location of tiles for Plane 1.
+					b: Location of tiles for Plane 0.
+
+			***  The way you use this register is fairly neat.
+			     Since you only have a nybble to work with (which
+			     ranges from $0-F only) your Tile location can
+			     only be $0000 to $F000. You can't have an address
+			     such as $5F91 or $1C4A which holds your tile
+			     data. You just can't have it. :-)
+
+-----------                              
+ W   |$210C: Tile VRAM location register.
+			ccccdddd
+					c: Location of tiles for Plane 3.
+					d: Location of tiles for Plane 2.
+
+			*** Same stats for $210B go for this one; 'cept the
+			    plane registers are different.
+-----------                              
+ W   |$210D: Plane 0 X-scroll register.
+			*** This register is really funky. You have to write
+			    to it twice in a row (each piece of data being
+			    1 byte). The register is setup as the following:
+			    - You store the first 8 bits (the first byte) which
+				ranges from $00 to $FF. After you store this
+				value, you have to store the next 3 bits in the
+				same register.
+			*** The following code demonstrates how to move plane 0
+			    left:
+					LDA Plane0X
+					DEC
+					STA Plane0X
+					STA $210D
+					STZ $210D
+			    If you make that into a loop by itself, the result
+			    is the plane keeps scrolling left forever; it even
+			    wraps around back to the start.
+
+		  *** Note: I've been told this is a nasty way to do it
+			    because MODE 7 uses 13 bits of the above,
+			    while the rest use 10. I'm not taking care of
+			    the MSB. :-(
+
+-----------                              
+ W   |$210E: Plane 0 Y-Scroll register.
+ W   |$210F: Plane 1 X-Scroll register.
+ W   |$2110: Plane 1 Y-Scroll register.
+ W   |$2111: Plane 2 X-Scroll register.
+ W   |$2112: Plane 2 Y-Scroll register.
+ W   |$2113: Plane 3 X-Scroll register.
+ W   |$2114: Plane 3 Y-Scroll register.
+			*** All of these follow the same definition as $210D.
+-----------                              
+ W   |$2115: Video port control.
+		  *** If you store the following listed values in this register,
+			the following happens:
+
+		$80: H/L increment which determines if the address will be
+		     incremented after it reads/writes to/from $2118 and
+		     $2139, or $2119 and $213A.
+
+ W   |$2116: Video port address. 
+			*** 16 bit VRAM address.
+	$2117: Video port address (continued, due to 16 bits).
+ W   |$2118: Video port data. 
+			*** Data register for writing VRAM data.
+	$2119: Video port data.
+		  *** Same as above.
+-----------                              
+ W   |$211A: MODE 7 Information register.
+			xy????ab
+					a: Horizontal or Vertical flip. 
+					b: Horizontal or Vertical flip.
+					x: Landscape repeat type.
+					y: Landscape repeat type.
+
+			*** I have not the SLIGHTEST idea what the hell
+			    the original author means by this. If someone
+			    can explain it, tell me.
+-----------                              
+ W   |$211B: COS (COSIN) rotate angle / X Expansion.
+ W   |$211C: SIN (SIN) rotate angle / X Expansion.
+ W   |$211D: SIN (SIN) rotate angle / Y Expansion.
+ W   |$211E: COS (COSIN) rotate angle / Y Expansion.
+ W   |$211F: 13 bit address for the center of Rotate X.
+ W   |$2120: 13 bit address for the center of Rotate Y.
+
+			*** All above things i've never used, nor do I
+			    have any explainations on them. Use them at
+			    your own risk, or until I get info on 'em.
+
+			*** $211F and $2120 are like $210D: You have to
+			    write a byte to them twice.
+-----------                              
+ W   |$2121: Color # (or pallete) selection register.
+			xxxxxxxx
+					x: Color # ($00-$FF).
+ 
+			*** This register is probably one of the most simple
+			    registers I know of to use. You simply store the
+			    # of the color you want to modify before writing
+			    to $2122. This register is autoincrementing, so
+			    you don't have to "LDA #$01, STA $2121, LDA #$02,
+			    STA $2121, LDA #$03..." and so on...
+			    Code is as follows:
+					STZ $2121   ; Start at color 0.
+					STZ $2122   ; Color #0 = 00 00
+					STZ $2122
+					LDA #$FF    ; Color #1 = 7F FF (white).
+					STA $2122
+					LDA #$7F
+					STA $2122
+					LDA #$1F    ; Color #2 = 00 1F (red).
+					STA $2122
+					STZ $2122
+-----------                              
+ W   |$2122: Color data register.
+			xxxxxxxx
+					x: Value of color.
+
+			*** Color on the SNES is trippy; it's 15 bit. Check
+			    Section 2 on how the SNES colors are setup. Some
+			    example code I listed for $2121... Anyways, this
+			    register is like $210D (plane X-scroll) and those
+			    types: You have to store the value in it twice.
+			    For instance: If you wanted the color white (which
+			    is $7FFF in SNES-color), you would have to do the
+			    following:
+					LDA [whatever color #]
+					STA $2121
+					LDA #$FF    ; We first store the "lower half"
+					STA $2122
+					LDA #$7F    ; Then the upper...
+					STA $2122
+			    It's really not that hard, but it'll take some
+			    getting used to :-) Remember, check Section 2 on
+			    how the SNES does it's color, and for tile-setup,
+			    check Section 4.
+-----------                              
+ W   |$212C: Playfield/Sprite-enable register.
+			abcdefgh
+					a: Plane 3 enable (for Sprites).
+					b: Plane 2 enable (for Sprites).
+					c: Plane 1 enable (for Sprites).
+					d: Plane 0 enable (for Sprites).
+					e: Enable plane 3.
+					f: Enable plane 2.
+					g: Enable plane 1.
+					h: Enable plane 0.
+			*** This register allows you to enable which planes
+			    you want to put sprites on (to move or etc.) and
+			    to scroll, or other neato things. If you wanna
+			    use all 4 planes, but no sprites, shove $0F into
+			    this register. If you want to use all the planes,
+			    but want sprites on planes 1 and 3, you would shove
+			    $AF into this register. It's very easy to do.
+-----------                              
+ W   |$2133: Screen mode register. 
+			????ab?c
+					a: Interlace Y.
+					b: Overscan.
+					c: Interlace X.
+
+			*** To be blatently honest, I have -NO IDEA- what
+			    this register does; I don't understand what
+			    Corsair & Dax meant by Interlace and Overscan.
+			    If someone can explain this register to me, i'd
+			    be very grateful :-).
+-----------                              
+ R   |$2139: VRAM port data (reading).
+	$213A: "                       "
+----------- 
+??   |$2140       *** These are the audio registers. 'never used 'em.
+??   |$2141           Try shoving data into them; who knows, if you get
+??   |$2142           music sometime, then you know you're on the right
+??   |$2143           track. :-)
+-----------                              
+??   |$4200: Counter Enable.
+			??yx???a
+					a: Joypad-read Enable (1 = Readable).
+					x: Horizontal Counter Enable.
+					y: Vertical Counter Enable.
+-----------                              
+??   |$4201: 8 bit parallel data.
+
+			*** This is the expansion bus for the Famicom.
+-----------                              
+RW   |$420B: DMA enable register.
+			abcdefgh
+					a: DMA #7.
+					b: DMA #6.
+					c: DMA #5.
+					d: DMA #4.
+					e: DMA #3.
+					f: DMA #2.
+					g: DMA #1.
+					h: DMA #0.
+
+			*** I've personally never used DMA for anything. I hope
+			    someone out there has, and can tell me how to use
+			    it. :-)
+-----------                              
+??   |$420D: Memory select.
+			???????x
+					x: Fast/Normal ROM flip.
+				  0 = Normal.
+				  1 = Fast.
+-----------
+R    |$4210: VBL register.
+			x???????
+					x: VBlank period
+					   1 = On.
+					   0 = Off.
+
+			*** This is probably the most important register
+			    you should work with. Without it, you die,
+			    and other things happen. :-) The following
+			    routine allows you to sync to the VBL/wait
+			    for the VBL to pass by so you can do your work:
+			    -       LDA $4210
+				    AND #$80
+			            BEQ -
+				    LDA $4210
+
+			    From a programmers' standpoint, the following
+			    code should do the EXACT SAME as the above,
+			    but faster. NOTE thou, that it doesn't. I
+			    think the timing is off, that's why it doesn't
+			    work right. But, here-goes:
+
+			    -       LDA $4210
+				    BPL -
+				    LDA $4210
+-----------                              
+??   |$4211: ?????.
+			x???????
+					x: IRQ Enable flag (1: Enabled).
+
+			*** I don't even know the DESCRIPTION of the reg-
+			    ister! :-)
+-----------                              
+RW   |$4212: Joypad-ready register.
+			???????x
+					x: Ready-state bit (1: Ready).
+
+			*** I'm not sure how this register is setup; all I know
+			    is how to use it. Code is as follows:
+					PadLoop LDA $4212
+						  AND #$01
+						  BNE PadLoop
+			    This waits for the joypad to become ready to read.
+-----------                              
+RW   |$4218: Joypad #0 register (1 out of 2).
+			abcd0000
+					a:    0 = A button not pressed.
+						1 = A button pressed.
+					b:    0 = X button not pressed.
+						1 = X button pressed.
+					c:    0 = Top-left button not pressed.
+						1 = Top-left button pressed.
+					d:    0 = Top-right button not pressed.
+						1 = Top-right button pressed.
+			*** These are self-explainitory. To find out the
+			    status of each bit, just AND #$ for that bit...
+			    The code for checking is the following:
+					LDA $4218
+					AND #$80    ; Is the A button pressed?
+					BNE YesA    ; Button pressed (bit is 1).
+					LDA $4218
+					AND #$40    ; Is button X pressed?
+					BNE YesX    ; Button pressed (bit is 1).
+					LDA $4218
+					AND #$10    ; Is the top-right button pressed?
+					BNE YesTopR ; Button pressed (bit is 1).
+			    ...and so on. It's very simple.
+			*** Note: The Corsair & Dax document was -WRONG-.
+				    It took me a good hour or two to find this
+				    out, so I decided i'd better write down the
+				    CORRECT way to do things).
+-----------                              
+RW   |$4219: Joypad #0 register (2 out of 2).
+			abcdefgh
+					a:    0 = B button not pressed.
+						1 = B button pressed.
+					b:    0 = Y button not pressed.
+						1 = Y button pressed.
+					c:    0 = Select button not pressed.
+						1 = Select button pressed.
+					d:    0 = Start button not pressed.
+						1 = Start button pressed.
+					e:    0 = Up not pressed.
+						1 = Up pressed.
+					f:    0 = Down not pressed.
+						1 = Down pressed.
+					g:    0 = Left not pressed.
+						1 = Left pressed.
+					h:    0 = Right not pressed.
+						1 = Right pressed.
+			*** Same as $4218... Some demo code follows:
+					LDA $4219
+					AND #$80    ; Is the B button pressed?
+					BNE YesB    ; Button pressed (bit is 1).
+					LDA $4219
+					AND #$04    ; Is Down pressed?
+					BNE YesDown ; Button pressed (bit is 1).
+					LDA $4219
+					AND #$02    ; Is Left pressed?
+					BNE YesLeft ; Button pressed (bit is 1).
+-----------                              
+RW   |$421A: Joypad #1 register (1 out of 2).
+RW   |$421B: Joypad #1 register (2 out of 2).
+RW   |$421C: Joypad #2 register (1 out of 2).
+RW   |$421D: Joypad #2 register (2 out of 2).
+RW   |$421E: Joypad #3 register (2 out of 2).
+RW   |$421F: Joypad #3 register (2 out of 2).
+				*** Setup is the same as $4218 and $4219.
+=-=-=
+1)    Memory Map
+	ii) Additional info.
+-----------                              
+RW   |$FFC0: Cartridge title.
+RW   |$FFD6: ROM/RAM Info on cart..
+RW   |$FFD7: ROM Size.
+RW   |$FFD8: RAM Size.
+RW   |$FFD9: Maker ID Code.
+RW   |$FFDB: Version #.
+RW   |$FFDC: Checksum complement.
+RW   |$FFDE: Checksum.
+RW   |$FFEA: NMI vector/VBL Interrupt.
+RW   |$FFEC: Reset vector.
+
+			*** With SMC (Magicom) files the offset is $7e00 less
+			    than above.
+			*** I've never actually used this information before:
+			    This could be SMC header only; but then why would
+			    there be memory locations for such? Strange. I'll
+			    leave the information I put in up to SNESASM v1.05.
+			    I use the psuedo-ops NAM, VER, and other things.
+
+=-=-=
+2)    SNES Color explaination.
+-----------                              
+	Oh BOY! So you're interested in finding out how the SNES does
+	it's color (via $2122), right? Well here ya go...
+
+	The SNES has a strange way of doing color (atleast that i've
+	seen in my lifetime). Color is 15 bit; each "RGB" value (red,
+	green, and blue) has 5 bits a piece.
+
+	When it comes to putting data into $2122, the format (in binary)
+	is the following (I put them into each byte):
+				0bbbbbgg gggrrrrr
+				|
+				|_ Someone needs to tell me what this bit
+				   -REALLY- is. I've just been told to set
+				   it to 0...
+	We guess that the Japanese didn't like the idea of putting them
+	in the "standard" order of R, G, then B: but instead wanted them
+	in alphabetical order. Silly! :-).
+
+	The way -I- do my color conversions is on a calculator... Just
+	plug in the bits you want to set in binary, then let the calc.
+	convert it into hexadecimal. It's pretty easy; or you can be
+	a Studly Programmer (hehehe) and do it in your head.
+
+	A quick color chart:          $7FFF: White  (0111 1111 1111 1111)
+						$001F: Red    (0000 0000 0001 1111)
+						$03E0: Green  (0000 0011 1110 0000)
+						$7C00: Blue   (0111 1100 0000 0000)
+						$7C1F: Purple (0111 1100 0001 1111)
+						$7FE0: Aqua   (0111 1111 1110 0000)
+						$03FF: Yellow (0000 0011 1111 1111);
+	Well there you have it. It's pretty simple after you get the hang
+	of it; when using the SNES, you get REALLY good with binary math:
+	You'll find this out after working with the machine for awhile.
+
+=-=-=
+3)    DMA Memory Map and explaination.
+-----------                              
+??   |$43x0: DMA Control register (??? Not sure ???).
+ W   |$43x1: DMA Destination register.
+			$18 = Video Port access.
+			$22 = Color pallete access.
+
+			*** This gives access to only some of the video chip.
+			    registers. Hell if I know which ones.
+-----------                              
+ W   |$43x2: Source address.
+			*** THIS REGISTER IS A WORD IN LENGTH ***
+			*** The document I have says:
+			    "lo-hi  16 lowest bits". Who knows... 
+-----------                              
+ W   |$43x4: Source bank address.
+			*** The document I have says:
+			    "8 highest bits". 
+-----------                              
+ W   |$43x5: Transfer size register.
+			*** Same as above:
+			    "lo-hi". 
+-----------                              
+	All the "x"s represent the DMA # (ranging from 0 to 7).
+	DMA #0: $4300-$4305.
+	DMA #1: $4310-$4315.
+	......
+	DMA #7: $4370-$4375.
+=-=-=
+4)    SNES Graphics (tiles) explaination.
+-----------                              
+	This is probably the most requested section of the document for
+	people whom are starting out on the SNES and want to learn just
+	how in the hell the SNES -DOES- do it's graphics.
+
+	There's so much to explain!!!
+
+	The SNES does it's graphics in tiles (surprise surprise!).
+
+	There are different MODEs on the SNES; the most famous being
+	is MODE 7. Alas: Most people think using $2106 is MODE 7 ($2106
+	is for screen pixelation: Where the pixels get "larger". Look 
+	in Section 1 for an explaination of this register).
+				*** THIS IS NOT MODE 7!!! ***. 
+	So the next time the pixels get really "big" (almost making them
+	look like IBM PC 320x200x256 mode :-)), and your friend says "WOW!
+	MODE 7 is COOL," punch 'em in the nose for me. Just kidding.
+
+	Also, another thing I should mention: Bitplanes are NOT THE SAME
+	AS PLANES. Planes are like "screens." You can scroll a plane, but
+	not a bitplane. Bitplanes are put ONTO a plane, which can be
+	scrolled any direction.
+
+	I'll be explaining MODE 1. MODE 7 is too tough for me to
+	explain, since you end up losing colors and other screwy things...
+	Check Section-5 for a mode-# list.
+	
+MODE   #/Playfields    MaxColor/Tile   Palettes        Colors
+---------------------------------------------------------------------------
+0      4               4               8               16
+1      3               16/16/4 (HUH?)  8               128
+	
+	MODE 0 is good for geometric shapes (if you were going to rotate
+	a wireframe cube), basic star scrolls, or a very "bland" text
+	scroller.
+
+	Let's start with MODE 1.
+
+	MODE 1 is best for really basic things: Star scrollers, text
+	scrolls, geometric (non detailed) art, or line drawings; it's
+	only 16 colors/bitplane, and there's only 4 bitplanes to play
+	with.
+
+	What you need is 4 bitplanes of data. You don't -HAVE- to
+	use 4 bitplanes... You can use 1 bitplane if you want, but
+	you only get 16 colors (NO!!! :-)).
+
+	You also need a plane map: You can't just have the predefined
+	graphics data and thats it: You have to "setup the plane" to
+	tell it what tile goes where.
+	
+	For demonstration purposes, i'll use code to explain it.
+
+-----------                              
+	The "lda #$0000" "tcd" transfers the DP location pointer to
+	where the scratchpad RAM is. This makes things go much faster,
+	because DP is always faster than normal RAM (yay for DP!!!)
+	
+	The other part puts where the location of the data in the
+	binary/image is into two DP locations: font and font2.
+
+font  equ $00     ; Direct page equates.
+font2 equ font+1
+	
+	sei
+	phk          
+	plb          
+	clc
+	xce
+	rep #$30     
+	lda #$0000   
+	tcd
+	lda #charset
+	sta font
+	lda #charset2
+	sta font2
+-----------                              
+	The following code tells the SNES where the actual data
+	is in VRAM memory.
+				     
+	lda #$10                ; Plane 0 text @ VRAM $1000. 
+	sta $2107               
+	
+	lda #$02                ; Tiles for Plane 0 @ VRAM $2000.
+	sta $210b               
+-----------                              
+	The following code actually MOVES the data in the binary/image
+	into the SNES's VRAM.
+
+	sep #$20
+	ldx #$2000              ; This puts the data sent thru $2118 and 
+					; $2119 into VRAM $2000.
+	stx $2116
+	ldy #$0000
+-     lda (font),y            ; Get bitplane 0 data (font)
+	sta $2118               ; ... and store it in bitplane 0.
+	lda (font2),y           ; Get bitplane 1 data (font2)
+	sta $2119               ; ... and store it in bitplane 1...
+	stz $2118               ; I don't want to use bitplane 2 and 3,
+	stz $2119               ; so I store zeros here. You could put
+					; more font data in there if you wanted.
+	iny
+	cpy #$0200        
+	bne -
+	
+	ldx #$1000              ; This puts the data sent thru $2118 and              
+	stx $2116               ; $2119 into VRAM $1000.
+	ldx #$0000
+-     lda TEXT,x              ; Get the character from TEXT...
+	and #$3f                ; AND #$3F because we only want the first
+					; 64 characters in the font.
+	sta $2118               ; 
+	stz $2119               ; Check near the end of this Section for
+					; an explaination on what the actual bits
+					; do instead of just storing 0 there all
+					; the time.
+	inx
+	cpx #$0400
+	bne -            
+-----------                              
+	Here's the actual data names (charset, charset2, and TEXT).
+	My new source has them in dcb % statements to make the font
+	more readable: The first time I did this, I had to convert
+	the binary stuff I wrote on paper into hex, then put them
+	into decent hex statements in an orderly fashion.
+
+charset 
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'@'  
+	dcb     $00,$3c,$66,$7e,$66,$66,$66,$00 ;'A'
+	dcb     $00,$7c,$66,$7c,$66,$66,$7c,$00 ;'B'
+	dcb     $00,$3c,$66,$60,$60,$66,$3c,$00 ;'C'
+	dcb     $00,$78,$6c,$66,$66,$6c,$78,$00 ;'D'
+	dcb     $00,$7e,$60,$78,$60,$60,$7e,$00 ;'E'
+	dcb     $00,$7e,$60,$78,$60,$60,$60,$00 ;'F'
+	dcb     $00,$3c,$66,$60,$6e,$66,$3c,$00 ;'G'
+	dcb     $00,$66,$66,$7e,$66,$66,$66,$00 ;'H'
+	dcb     $00,$3c,$18,$18,$18,$18,$3c,$00 ;'I'
+	dcb     $00,$1e,$0c,$0c,$0c,$6c,$38,$00 ;'J'
+	dcb     $00,$6c,$78,$70,$78,$6c,$66,$00 ;'K'
+	dcb     $00,$60,$60,$60,$60,$60,$7e,$00 ;'L'
+	dcb     $00,$63,$77,$7f,$6b,$63,$63,$00 ;'M'
+	dcb     $00,$66,$76,$7e,$7e,$6e,$66,$00 ;'N'
+	dcb     $00,$3c,$66,$66,$66,$66,$3c,$00 ;'O'
+	dcb     $00,$7c,$66,$66,$7c,$60,$60,$00 ;'P'
+	dcb     $00,$3c,$66,$66,$66,$3c,$0e,$00 ;'Q'
+	dcb     $00,$7c,$66,$66,$7c,$6c,$66,$00 ;'R'
+	dcb     $00,$3e,$60,$3c,$06,$66,$3c,$00 ;'S'
+	dcb     $00,$7e,$18,$18,$18,$18,$18,$00 ;'T'
+	dcb     $00,$66,$66,$66,$66,$66,$3c,$00 ;'U'
+	dcb     $00,$66,$66,$66,$66,$3c,$18,$00 ;'V'
+	dcb     $00,$63,$63,$6b,$7f,$77,$63,$00 ;'W'
+	dcb     $00,$66,$3c,$18,$3c,$66,$66,$00 ;'X'
+	dcb     $00,$66,$66,$3c,$18,$18,$18,$00 ;'Y'
+	dcb     $00,$7e,$0c,$18,$30,$60,$7e,$00 ;'Z'
+	dcb     $08,$00,$00,$00,$00,$00,$00,$00 ;'['    
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'\'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;']'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'^'
+	dcb     $00,$08,$00,$00,$00,$00,$00,$00 ;'_'  
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;' '  
+	dcb     $00,$7E,$7E,$3C,$18,$00,$18,$00 ;'!'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'"'
+	dcb     $80,$80,$80,$80,$80,$80,$80,$80 ;'#'
+	dcb     $FC,$FE,$FF,$F7,$F7,$FF,$FE,$FC ;'$'
+	dcb     $3E,$42,$4E,$5C,$5C,$4E,$42,$3E ;'%'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$01 ;'&'
+	dcb     $00,$00,$00,$07,$00,$00,$00,$00 ;'''
+	dcb     $00,$04,$08,$08,$08,$08,$04,$00 ;'('
+	dcb     $00,$20,$10,$10,$10,$10,$20,$00 ;')'
+	dcb     $08,$08,$08,$F8,$08,$08,$08,$08 ;'*'
+	dcb     $10,$10,$10,$1F,$10,$10,$10,$10 ;'+'
+	dcb     $10,$10,$20,$C0,$00,$00,$00,$00 ;','
+	dcb     $00,$00,$00,$FF,$00,$00,$00,$00 ;'-'
+	dcb     $00,$00,$00,$00,$00,$18,$18,$00 ;'.'
+	dcb     $00,$00,$00,$FF,$80,$80,$80,$80 ;'/'  
+	dcb     $00,$3c,$66,$6e,$76,$66,$3c,$00 ;'0'
+	dcb     $00,$18,$38,$18,$18,$18,$7e,$00 ;'1'
+	dcb     $00,$7c,$06,$0c,$30,$60,$7e,$00 ;'2'
+	dcb     $00,$7e,$06,$1c,$06,$66,$3c,$00 ;'3'
+	dcb     $00,$0e,$1e,$36,$7f,$06,$06,$00 ;'4'
+	dcb     $00,$7e,$60,$7c,$06,$66,$3c,$00 ;'5'
+	dcb     $00,$3e,$60,$7c,$66,$66,$3c,$00 ;'6'
+	dcb     $00,$7e,$06,$0c,$0c,$0c,$0c,$00 ;'7'
+	dcb     $00,$3c,$66,$3c,$66,$66,$3c,$00 ;'8'
+	dcb     $00,$3c,$66,$3e,$06,$66,$3c,$00 ;'9'
+	dcb     $00,$00,$00,$03,$04,$08,$08,$08 ;':' 
+	dcb     $00,$80,$80,$F0,$80,$80,$00,$00 ;';'
+	dcb     $80,$80,$80,$FF,$00,$00,$00,$00 ;'<'
+	dcb     $00,$00,$00,$C0,$20,$10,$10,$10 ;'='
+	dcb     $08,$08,$04,$03,$00,$00,$00,$00 ;'>'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'?'
+
+charset2 
+	dcb     $00,$3C,$4E,$5E,$5E,$40,$3C,$00 ;'@'  
+	dcb     $00,$3c,$66,$7e,$66,$66,$66,$00 ;'A'
+	dcb     $00,$7c,$66,$7c,$66,$66,$7c,$00 ;'B'
+	dcb     $00,$3c,$66,$60,$60,$66,$3c,$00 ;'C'
+	dcb     $00,$78,$6c,$66,$66,$6c,$78,$00 ;'D'
+	dcb     $00,$7e,$60,$78,$60,$60,$7e,$00 ;'E'
+	dcb     $00,$7e,$60,$78,$60,$60,$60,$00 ;'F'
+	dcb     $00,$3c,$66,$60,$6e,$66,$3c,$00 ;'G'
+	dcb     $00,$66,$66,$7e,$66,$66,$66,$00 ;'H'
+	dcb     $00,$3c,$18,$18,$18,$18,$3c,$00 ;'I'
+	dcb     $00,$1e,$0c,$0c,$0c,$6c,$38,$00 ;'J'
+	dcb     $00,$6c,$78,$70,$78,$6c,$66,$00 ;'K'
+	dcb     $00,$60,$60,$60,$60,$60,$7e,$00 ;'L'
+	dcb     $00,$63,$77,$7f,$6b,$63,$63,$00 ;'M'
+	dcb     $00,$66,$76,$7e,$7e,$6e,$66,$00 ;'N'
+	dcb     $00,$3c,$66,$66,$66,$66,$3c,$00 ;'O'
+	dcb     $00,$7c,$66,$66,$7c,$60,$60,$00 ;'P'
+	dcb     $00,$3c,$66,$66,$66,$3c,$0e,$00 ;'Q'
+	dcb     $00,$7c,$66,$66,$7c,$6c,$66,$00 ;'R'
+	dcb     $00,$3e,$60,$3c,$06,$66,$3c,$00 ;'S'
+	dcb     $00,$7e,$18,$18,$18,$18,$18,$00 ;'T'
+	dcb     $00,$66,$66,$66,$66,$66,$3c,$00 ;'U'
+	dcb     $00,$66,$66,$66,$66,$3c,$18,$00 ;'V'
+	dcb     $00,$63,$63,$6b,$7f,$77,$63,$00 ;'W'
+	dcb     $00,$66,$3c,$18,$3c,$66,$66,$00 ;'X'
+	dcb     $00,$66,$66,$3c,$18,$18,$18,$00 ;'Y'
+	dcb     $00,$7e,$0c,$18,$30,$60,$7e,$00 ;'Z'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'[' 
+	dcb     $09,$09,$00,$00,$00,$00,$00,$00 ;'\'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;']'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'^'
+	dcb     $00,$08,$00,$00,$00,$00,$00,$00 ;'_'  
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;' '  
+	dcb     $00,$7E,$7E,$3C,$18,$00,$18,$00 ;'!'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'"'
+	dcb     $80,$80,$80,$80,$80,$80,$80,$80 ;'#'
+	dcb     $FC,$FE,$FF,$F7,$F7,$FF,$FE,$FC ;'$'
+	dcb     $3E,$42,$4E,$5C,$5C,$4E,$42,$3E ;'%'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$01 ;'&'
+	dcb     $00,$00,$00,$07,$00,$00,$00,$00 ;'''
+	dcb     $00,$04,$08,$08,$08,$08,$04,$00 ;'('
+	dcb     $00,$20,$10,$10,$10,$10,$20,$00 ;')'
+	dcb     $08,$08,$08,$F8,$08,$08,$08,$08 ;'*'
+	dcb     $10,$10,$10,$1F,$10,$10,$10,$10 ;'+'
+	dcb     $10,$10,$20,$C0,$00,$00,$00,$00 ;','
+	dcb     $00,$00,$00,$FF,$00,$00,$00,$00 ;'-'
+	dcb     $00,$00,$00,$00,$00,$18,$18,$00 ;'.'
+	dcb     $00,$00,$00,$FF,$80,$80,$80,$80 ;'/'  
+	dcb     $00,$3c,$66,$6e,$76,$66,$3c,$00 ;'0'
+	dcb     $00,$18,$38,$18,$18,$18,$7e,$00 ;'1'
+	dcb     $00,$7c,$06,$0c,$30,$60,$7e,$00 ;'2'
+	dcb     $00,$7e,$06,$1c,$06,$66,$3c,$00 ;'3'
+	dcb     $00,$0e,$1e,$36,$7f,$06,$06,$00 ;'4'
+	dcb     $00,$7e,$60,$7c,$06,$66,$3c,$00 ;'5'
+	dcb     $00,$3e,$60,$7c,$66,$66,$3c,$00 ;'6'
+	dcb     $00,$7e,$06,$0c,$0c,$0c,$0c,$00 ;'7'
+	dcb     $00,$3c,$66,$3c,$66,$66,$3c,$00 ;'8'
+	dcb     $00,$3c,$66,$3e,$06,$66,$3c,$00 ;'9'
+	dcb     $00,$00,$00,$03,$04,$08,$08,$08 ;':' 
+	dcb     $00,$80,$80,$F0,$80,$80,$00,$00 ;';'
+	dcb     $80,$80,$80,$FF,$00,$00,$00,$00 ;'<'
+	dcb     $00,$00,$00,$C0,$20,$10,$10,$10 ;'='
+	dcb     $08,$08,$04,$03,$00,$00,$00,$00 ;'>'
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'?'
+
+TEXT  dcb     " THIS IS YOUR ENTIRE SCREEN     "
+	dcb     " HERE... IF YOU REMOVE ONE OF   "
+	dcb     " THE LINES WHICH IS BLANK, THE  "
+	dcb     " SCREEN ENDS UP BEING FUNKY     "
+	dcb     " DOWN AT THE BOTTOM OF THE      "
+	dcb     " SCREEN.                        "
+	dcb     "                                "
+	dcb     " SO MAKE SURE YOU ALWAYS LEAVE  "
+	dcb     " ALL OF THIS TEXT THINGS IN!    "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "         YOSHI THE DINO         "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "                                "
+	dcb     "********************************"
+	dcb     "                                "
+	dcb     "                                "
+-----------                              
+	Well there's some code for those whom want to rip it :-).
+	
+	I hope I haven't confused you yet: If I have, go back and re-read
+	the code. I've been working with the SNES for awhile, so I under-
+	stand a little more than a beginner.
+
+	You're probably wondering how the heck the following line ends
+	up being an "@" on your TV, or whatever you have your SNES
+	hooked up to.
+
+	Lets look at charset and charset2.
+
+charset 
+	dcb     $00,$00,$00,$00,$00,$00,$00,$00 ;'@'  
+
+charset2 
+	dcb     $00,$3C,$4E,$5E,$5E,$40,$3C,$00 ;'@'  
+
+	Convert charsets hex-statements into binary. Consider each
+	new "$xx" statement a new pixel line. Tile size is 8x8.
+
+	00000000          = $00
+	00000000          = $00
+	00000000          = $00
+	00000000          = $00
+	00000000          = $00
+	00000000          = $00
+	00000000          = $00
+	00000000          = $00
+
+	Convert charset2s hex-statements into binary. 
+
+	00000000          = $00
+	00111100          = $3C
+	01001110          = $4E
+	01011110          = $5E
+	01011110          = $5E
+	01000000          = $40
+	00111100          = $3C
+	00000000          = $00
+
+	*NOW* do you see the at-symbol? (and yes, I -DID- draw all
+	of the font by hand. It took me HOURS, but I did it).
+
+	You're probably now asking: "Well, that tells me how to define
+	where a pixel IS: but how do I define it's color?"
+
+	This is the fun part. It's sort-of hard to explain:
+	If you have a 0 for bitplane 0, a 0 for bitplane 1, a 0 for
+	bitplane 2, and a 0 for bitplane 3, you get the color 0.
+		i.e.: 0000 = Color #0
+			||||___________Bitplane 0
+			|||__________Bitplane 1
+			||_________Bitplane 2
+			|________Bitplane 3
+
+	So, think about a 0 for bitplane 0, a 1 for bitplane 1 & 2
+	and a 0 for bitplane 3.
+		i.e.: 0110 = Color #6
+			||||___________Bitplane 0
+			|||__________Bitplane 1
+			||_________Bitplane 2
+			|________Bitplane 3
+
+	This is probably the best explaination i've ever seen done about
+	SNES pixel-color definition, so don't plan on seeing one any
+	better anytime soon :-).
+
+	Anyway, the result above gives you the color # per pixel; it's
+	fairly interesting... it's like an "overlay" type of method.
+
+	I mentioned in the source above that you should check near the
+	end of the Section for info on why I "stz $2119". Well, here's
+	why: The bits in the tile-data are fairly "silly": The tile
+	"character" itself is 10 bits, while the other 6 are "fun bits,"
+	as I call them. Here's the explaination:
+		    yx?cccNN | NNNNNNNN
+						y: Flip the tile vertically.
+						x: Flip the tile horiztonally.
+						?: Dunno! Set it to 1 and find out. 
+						c: Pallete # (0-7).
+						N: Character itself.
+						
+	So, I STZ there: Yes, I leave the top bits "unset," which means
+	you could get messed up data, but as far as I have checked, the
+	SNES has "clear memory" when you start it up: So the bits I don't
+	zero-out should be zeros anyways! :-) If you want to set them,
+	feel free to do so! The results of flipping Y and X are sortof
+	fun to play with. "To read this scrolly, you must stand on your
+	head" :-)
+=-=-=
+5)    SNES Screen mode definitions.
+-----------                              
+MODE   # of bitplanes  Colors per plane  Palletes      Max. # of colors
+---------------------------------------------------------------------------
+0      2               4               8               32
+1      4               16              8               128
+2      ?               ???             ?               ??? 
+3      8               256             1               256
+4      ?               ???             ?               ??? 
+5      ?               ???             ?               ??? 
+6      ?               16              8               128 (Interlaced mode)
+7      ?               256             1               256 (Yes, MODE 7)
+---------------------------------------------------------------------------
+
+	The parms which have "?" or "???" mean I don't know what they REALLY
+	are: I got a document which explained them, but it was bogus: It
+	said a 16 color mode had -1- bitplane. Weird... I'm not even sure
+	about MODE 6. But, we know what MODE 7 is, even if I'm not sure how
+	many bitplanes it DOES use (the doc says 1, I say 8).
+
+	I've tested MODE 0 and 1 myself. MODE 3 I might test in the future,
+	but i've never had the desire to draw up 8 bitplanes of data by
+	hand ( I don't have a SNES-graphics-generator for the PC! :-( ).
+=-=-=
+6)    SNES OAM/Sprite explaination.
+-----------                              
+	The sprites use a lookup table that contains info on their X and
+	Y position on the screen, their size, if they're flipped horizontally
+	or vertically, their color, and the actual character.
+
+	The format you need to make the table in is as follows:
+
+Size  Address/Offset          Explaination
+---------------------------------------------------------------------------
+*** SPRITE 0 ***
+BYTE  0                      
+					xxxxxxxx
+							x: X location.
+BYTE  1                       
+					yyyyyyyy
+							y: Y location.
+WORD  2+3         
+				  abcdeeex | xxxxxxxx
+							a: Vertical flip.
+							b: Horizontal flip.
+							c: Playfield priority.
+							d: Playfield priority.
+							e: Pallete #.
+							x: Character #.
+*** SPRITE 0 ***
+BYTE  4                       
+					xxxxxxxx
+							x: X location.
+BYTE  5                       
+					yyyyyyyy
+							y: Y location.
+....... and so on .......
+---------------------------------------------------------------------------
+	Continue this table all the way down to sprite #127 (the 128th
+	sprite).
+	
+	Don't think you're

BIN
files/docs/snes/SNESKART.doc


BIN
files/docs/snes/SNESKart-TurtleGroupInc..pdf


+ 1379 - 0
files/docs/snes/SNESMAP2.TXT

@@ -0,0 +1,1379 @@
+ADDRESS  : $2100

+NAME     : INIDISP

+CONTENTS : INITIAL SETTINGS FOR SCREEN

+

+	D7	BLANKING:

+			FORCED BLANKING, 0:NON-BLANKING,1:BLANKING.

+

+        D6-D4   ---

+

+        D3-D0   FADE IN/OUT:

+			0000-DARKEST,1111-BRIGHTEST.

+

+

+ADDRESS  : $2101

+NAME     : OBSEL

+CONTENTS : OBJECT SIZE & OBJECT DATA AREA DESIGNATION

+

+	D7-D5	SIZE SELECT:

+			D7 D6 D5   0   1  (SIZE LARGE/SMALL)

+			 0  0  0   8  16

+			 0  0  1   8  32

+			 0  1  0   8  64

+			 0  1  1  16  32

+			 1  0  0  16  64

+			 1  0  1  32  64 (DOTS.)

+

+	D4-D3	NAME SELECT

+			THE UPPER 4K-WORD OUT OF THE AREA (8K-WORD)

+			DESIGNATED BY "OBJECT BASE ADDRESS" IS ASSIGNED

+			AS THE BASE AREA, AND THE AREA OF THE LOWER 4K-

+			WORD COMBINED WITH ITS BASE AREA CAN BE

+			SELECTED. (SEE APPENDIX 1 & 2)

+

+	D2-D0	NAME BASE SELECT (UPPER-3 BIT)

+			DESIGNATE THE SEGMENT (8K-WORD) ADDRESS WHICH

+			THE OBJ DATA IS STORED IN VRAM.	(APPENDIX 1 & 2)

+

+

+ADDRESS  : $2102/$2103

+NAME     : OAMADDL/OAMADDH

+CONTENTS : ADDRESS FOR ACCESSING OAM

+

+	D7-D0	OAM ADDRESS (A7-A0)				2102H

+

+	D7	OAM PRIORITY ROTATION				2103H

+	D6-D1	---

+	D0	OAM ADDRESS MSB (A8)

+

+          THIS IS THE INITIAL ADDRESS TO BE SET IN ADVANCE WHEN READING

+	  READING FROM THE OAM OR WRITING TO THE OAM.

+

+          BY WRITING "1" TO D7 OF REGISTER <2103H> AND SETTING THE OAM-

+	  ADDRESS THE OBJ FOR THE ADDRESS SET HAS HIGHEST PRIORITY.

+

+          THE ADDRESS WHICH HAS BEEN SET JUST BEFORE EVERY FIELD

+	  (BEGINNING OF V-BLANK) WILL BE SET AGAIN TO REGISTERS <2102H>

+	  <2103H> AUTOMATICALLY. BUT, THE ADDRESS CAN NOT BE SET

+	  AUTOMATICALLY DURING FORCED BLANK PERIOD.

+

+

+ADDRESS  : $2104

+NAME     : OAMDATA

+CONTENTS : DATA FOR OAM WRITE

+

+	D7-D0	OAM DATA (LOW,HIGH)

+

+          THIS IS THE OAM DATA TO BE WRITTING AT ANY ADDRESS OF THE OAM.

+	  (SEE APPENDIX-3)

+

+          AFTER REGISTER <2102H> OR <2103H> IS ACCESSED, THE DATA MUST

+	  BE WRITTEN IN THE ORDER OF LOWER 8-BIT & UPPER 8-BIT OF REGISTER

+	  <2104H>.

+

+          THE DATA CAN BE WRITTEN ONLY DURING V-BLANK OR FORCED BLANK

+	  PERIOD.

+

+

+ADDRESS  : $2105

+NAME     : BGMODE

+CONTENTS : BG MODE & CHARACTER SIZE SETTINGS

+

+	D7-D4	BG SIZE DESIGNATION (BG4-BG1)

+			0:   8 x  8 DOT/CHARACTER

+			1:  16 x 16 DOT/CHARACTER

+

+	D3	HIGHEST PRIORITY DESIGNATION FOR BG-3 IN MODE 1

+			0: OFF (SEE APPENDIX-16)

+			1: ON

+

+	D2-D0	BG SCREEN MODE SELECT (SEE APPENDIX-5)

+

+

+ADDRESS  : $2106

+NAME     : MOSAIC

+CONTENTS : SIZE & SCREEN DESIGNATION FOR MOSAIC DISPLAY

+

+	D7-D4	MOSAIC SIZE (SEE APPENDIX-6)

+			1111 - LARGEST, 0000 - SMALLEST.

+

+	D3-D0	MOSAIC ENABLE (BG4-B1)

+			0: OFF

+			1: ON

+

+

+ADDRESS  : $2107/$2108/$2109/$210A

+NAME     : BG1SC/BG2SC/BG3SC/BG4SC

+CONTENTS : ADDRESS FOR STORING SC-DATA OF EACH BG & SC SIZE DESIGNATION

+

+	D7-D2	SC BASE ADDRESS

+			DESIGNATE THE SEGMENT WHICH BG-SC IN THE VRAM

+			IS STORED. (1K-WORD/SEGMENT)

+

+	D1-D0	SC SIZE

+			DESIGNATE BACKGROUND SCREEN SIZE (APPENDIX-18 & 19)

+			0 0  0 0    1 0  0 0    0 1  0 1    1 1  0 1

+			     0 0         1 1         0 1         2 3

+

+

+ADDRESS  : $210B/$210C

+NAME     : BG12NBA/BG34NBA

+CONTENTS : BG CHARACTER DATA ARE DESIGNATION

+

+	D7-D4	BG2 BASE ADDRESS				210BH

+	D3-D0	BG1 BASE ADDRESS

+

+	D7-D4	BG4 BASE ADDRESS				210CH

+	D3-D0	BG3 BASE ADDRESS

+

+          BACKGROUND NAME BASE ADDRESS (UPPER 4-BIT), SEGMENT ADDRESS

+	  IN THE VRAM WHERE BG CHARACTER DATA IS STORED. (4K-WORD/SEGMENT)

+

+

+ADDRESS  : $210D/$210E/$210F/$2110/$2111/$2112/$2113/$2114

+NAME     : BG1HOFS/BG1VOFS/BG2HOFS/BG2VOFS/BG3HOFS/BG3VOFS/BG4HOFS/BG4VOFS

+CONTENTS : H/V SCROLL VALUE DESIGNATION FOR BG

+

+	D7-D0	H-OFFSET (LOW,HIGH)				HOFS

+

+	D7-D0	V-OFFSET (LOW,HIGH)				VOFS

+

+          10 BIT MAXIMUM (0-1023) CAN BE DESIGNATED FOR H/V SCROLL VALUE.

+	  [THE SIZE OF 13-BIT MAXIMUM (-4096->4095) CAN BE DESIGNATED IN

+	  MODE 7] (SEE APPENDIX-8 & 9)

+

+          BY WRITING TO THE REGISTER TWICE, THE DATA CAN BE SET IN ORDER

+	  OF LOW & HIGH.

+

+

+ADDRESS  : $2115

+NAME     : VMAIN

+CONTENTS : VRAM ADDRESS INCREMENT VALUE DESIGNATION

+

+	D7	H/L INC (WORD OR BYTE VRAM ACCESS)

+

+			DESIGNATE THE INCREMENT TIMING FOR THE ADDRESS

+			0: THE ADDRESS WILL BE INCREASED AFTER THE DATA HAS

+			   BEEN WRITTEN TO REGISTER <2118H> OR THE DATA

+			   HAS BEEN READ FROM REGISTER <2139H>.

+			   THIS WILL RESULT IN BYTE VRAM ACCESS, I.E. FOR

+			   MODE 7 TILE MAP CHANGE.

+

+			1: THE ADDRESS WILL BE INCREASED AFTER THE DATA HAS

+			   BEEN WRITTEN TO REGISTER <2119H> OR THE DATA

+			   HAS BEEN READ FROM REGISTER <213AH>.

+			   THIS WILL RESULT IN WORD VRAM ACCESS, I.E. FOR

+			   MODE 1 TILE MAP CHANGE.

+

+	D6-D4	---

+

+	D3-D2	FULL GRAPHIC (G1 & G0)

+

+	D1-D0	SC INCREMENT (I1 & I0)

+

+

+	G1 G0 I1 I0 | INCREMENT VALUE

+	----------------------------

+	 0  1  0  0 | INCREMENT BY 8 FOR 32 TIMES (2-BIT FORMATION)

+	 1  0  0  0 | INCREMENT BY 8 FOR 64 TIMES (4-BIT FORMATION)

+	 1  1  0  0 | INCREMENT BY 8 FOR 128 TIMES (8-BIT FORMATION)

+	 0  0  0  0 | ADDRESS INCREMENTS 1 BY 1

+	 0  0  0  1 | ADDRESS INCREMENTS 32 BY 32

+	 0  0  1  0 | ADDRESS INCREMENTS 64 BY 64

+	 0  0  1  1 | ADDRESS INCREMENTS 128 BY 128

+

+

+ADDRESS  : $2116/$2117

+NAME     : VMADDL/VMADDH

+CONTENTS : ADDRESS FOR VRAM READ

+

+	D7-D0	VRAM ADDRESS (LOW)				2116H

+	D7-D0	VRAM ADDRESS (HIGH)				2117H

+

+          THIS IS THE INITIAL ADDRESS FOR READING FROM THE VRAM OR WRITING

+	  TO THE VRAM.

+

+          THE DATA IS READ OR WRITTEN BY THE ADDRESS SET INITIALLY, AND

+	  EVERY TIME THE DATA IS READ THE ADDRESS WIL BE INCREASED

+	  AUTOMATICALLY.

+

+          THE VALUE TO BE INCREASED IS DETERMINED BY "SC INCREMENT" OF

+	  REGISTER <2115H> AND THE SETTING VALUE OF THE "FULL GRAPHIC".

+

+

+ADDRESS  : $2118/$2119

+NAME     : VMDATAL/VMDATAH

+CONTENTS : DATA FOR VRAM WRITE

+

+	D7-D0	VRAM DATA (LOW)					2118H

+	D7-D0	VRAM DATA (HIGH)				2119H

+

+          THIS IS THE SCREEN DATA AND CHARACTER DATA (BG & OBJ), WHICH

+	  CAN WRITE AT ANY ADDRESS OF THE VRAM.

+

+          ACCORDING TO THE SETTING OF REGISTER <2115H> "H/L INC.", THE

+	  DATA CAN BE WRITTEN TO THE VRAM AS FOLLOWS:

+

+	H/L INC  |  WRITE TO REGISTER  |  OPERATION

+        --------------------------------------------------------------

+	    0    |  WRITE TO <2118H>   |  THE DATA IS WRITTEN TO LOWER 8BIT

+	         |  ONLY.              |  OF THE VRAM & THE ADDRESS WILL BE

+		 |                     |  INCREASED AUTOMATICALLY.

+	    1    |  WRITE TO <2119H>   |  THE DATA IS WRITTEN TO UPPER 8BIT

+	         |  ONLY.              |  OF THE VRAM & THE ADDRESS WILL BE

+	         |                     |  INCREASED AUTOMATICALLY.

+	    0    |  WRITE IN ORDER OF  |  WHEN THE DATA IS SET IN THE ORDER

+	         |  <2119H> & <2118H>  |  OF UPPER & LOWER THE ADDRESS WILL

+	         |                     |  BE INCREASED.

+	    1    |  WRITE IN ORDER OF  |  WHEN THE DATA IS SET IN THE ORDER

+	         |  <2118H> & <2119H>  |  OF LOWER & UPPER THE ADDRESS WILL

+	         |                     |  BE INCREASED.

+

+	NOTE:	THE DATA CAN ONLY BE WRITTEN DURING V-BLANK OR FORCED BLANK

+	~~~~~	PERIOD.

+

+

+ADDRESS  : $211A

+NAME     : M7SEL

+CONTENTS : INITIAL SETTING IN SCREEN MODE-7

+

+	D7-D6	SCREEN OVER (O1 & O0)

+			PROCESS MADE IF THE SCREEN TO BE DISPLAYED IS

+			OUTSIDE OF THE SCREEN AREA. (SEE BELOW)

+

+	D5-D2	---

+

+	D1-D0	SCREEN FLIP (V/H)

+			0: NORMAL

+			1: FLIPPED

+

+	O1 O0  |  PROCESS OUT OF AREA

+        --------------------------------------------------------------

+	 0  0  |  SCREEN REPETITION IF OUTSIDE OF SCREEN AREA

+	 1  0  |  CHARACTER 0x00 REPETITION IF OUTSIDE OF SCREEN AREA

+	 1  1  |  OUTSIDE OF THE SCREEN AREA IS THE BACK DROP SCREEN IN

+	       |  SINGLE COLOR

+

+

+ADDRESS  : $211B/$211C/$211D/$211E/$211F/$2120

+NAME     : M7A/M7B/M7C/M7D/M7X/M7Y

+CONTENTS : ROTATION/ENLARGEMENT/REDUCTION IN MODE-7, CENTER COORDINATE

+	   SETTINGS & MULTIPLICAND/MULTIPLIER SETTINGS OF COMPLEMENTARY

+	   MULTIPLICATION.

+

+	D7-D0	MATRIX PARAMETER A (LOW[MP7-MP0],HIGH[MP15-MP8])211BH

+	D7-D0	MATRIX PARAMETER B (LOW[MP7-MP0],HIGH[MP15-MP8])211CH

+	D7-D0	MATRIX PARAMETER C (LOW[MP7-MP0],HIGH[MP15-MP8])211DH

+	D7-D0	MATRIX PARAMETER D (LOW[MP7-MP0],HIGH[MP15-MP8])211EH

+

+          THE 8-BIT DATA SHOULD BE WRITTEN TWICE IN THE ORDER OF LOWER &

+	  UPPER. THEN, THE PARAMETER OF ROTATION, ENLARGEMENT AND REDUCTION

+	  SHOULD BE SET BY ITS 16-BIT AREA.

+

+          THE VALUE DOWN TO A DECIMAL POINT SHOULD BE SET TO THE LOWER

+	  8-BIT. THE MOST SIGNIFICANT BIT OF THE UPPER 8-BIT IS FOR THE

+	  SIGNED BIT. (MP15 IS THE SIGNED BIT. THERE IS A DECIMAL POINT

+	  BETWEEN M7 & M8)

+

+          FORMULA FOR ROTAION/ENLARGEMENT/REDUCTION (SEE APPENDIX-13)

+

+		/ X2 \   / A B \ / X1-X0 \   / X0 \

+		|    | = |     | |       | + |    |

+		\ Y2 /   \ C D / \ Y1-Y0 /   \ Y0 /

+

+	  A=COS(GAMMA)*(1/ALPHA), B=SIN(GAMMA)*(1/ALPHA)

+	  C=-SIN(GAMMA)*(1/BETA), D=COS(GAMMA)*(1/BETA)

+

+	  	GAMMA: ROTATION ANGLE

+	  	ALPHA: REDUCTION RATES FOR X(H)

+	  	BETA : REDUCTION RATES FOR Y(V)

+		X0&Y0: CENTER COORDINATE

+		X1&Y1: DISPLAY COORDINATE

+		X2&Y2: COORDINATE BEFORE CALCULATION

+

+          SET THE VALUE OF "A" TO REGISTER <211BH>. IN THE SAME WAY,

+	  SET "B-D" TO THE REGISTERS <211CH>-<211EH>.

+

+	* THE COMPLEMENTARY MULTIPLICATION (16BIT X 8BIT) CAN BE DONE BY

+	  USING REGISTERS <211BH> <211C>.

+	  WHEN SETTING 16 BIT DATA TO REGISTER <211BH> AND 8BIT DATA TO

+	  REGISTER <211CH>, THE MULTIPLICATION RESULT CAN BE INDICATED

+	  RAPIDLY BY READING REGISTERS <2134H>-<2136H>.

+

+	D7-D0	CENTER POSITION X0 (LOW[X7-X0],HIGH[X12-X8])	211FH

+	D7-D0	CENTER POSITION Y0 (LOW[Y7-X0],HIGH[Y12-X8])	2120H

+

+          THE CENTER COORDINATE (X0,Y0) FOR ROTATION/ENLARGEMENT/REDUCTION

+	  CAN BE DESIGNATED BY THIS REGISTER.

+

+          THE COORDINATE VALUE OF X0 & Y0 CAN BE DESIGNATED BY 13-BIT

+	  (COMPLEMENT OF 2).

+

+          THE REGISTER REQUIRES THAT THE LOWER 8-BIT IS SET FIRST AND THE

+	  UPPER 5-BIT IS SET. THEREFORE, 13-BIT DATA IN TOTAL CAN BE SET.

+

+

+ADDRESS  : $2121

+NAME     : CGADD

+CONTENTS : ADDRESS FOR CG-RAM WRITE

+

+	D7-D0	CG-RAM ADDRESS

+

+          THIS IS THE INITIAL ADDRESS FOR READING FROM THE CG-RAM OR

+	  WRITING TO THE CG-RAM

+

+          THE DATA IS READ BY THE ADDRESS SET INITIALLY, AND EVERY TIME

+	  THE DATA IS READ OR WRITTEN THE ADDRESS WILL BE INCREASED

+	  AUTOMATICALLY.

+

+

+ADDRESS  : $2122

+NAME     : CGDATA

+CONTENTS : DATA FOR CG-RAM WRITE

+

+	D7-D0	CG-RAM DATA (LOW[D7-D0],HIGH[D14-D8])

+

+          THIS IS THE COLOR GENERATER DATA TO BE WRITTEN AT ANY ADDRESS

+	  OF THE CG-RAM.

+

+          THE MAPPING OF BG1-BG4 AND OBJ DATA IN CG-RAM WILL BE DETERMINED,

+	  WHICH IS PERFORMED BY EVERY MODE SELECTED BY "BG MODE" OF

+	  REGISTER <2105H>. (SEE APPENDIX-14)

+

+          THERE AREA THE COLOR DATA OF 8-PALETTES FOR EACH SCREEN OF

+	  BG1-BG4. THE PALETTE SELECTION IS DETERMINED BY 3-BIT OF THE

+	  SC DATA "COLOR"

+

+          BECAUSE THE CG-RAM DATA IS 15-BIT/WORD, IT IS NECESSARY TO SET

+	  LOWER 8-BIT FIRST TO THIS REGISTER AND THE THE UPPER 7-BIT.

+	  WHEN BOTH LOWER & UPPER ARE SET, THE ADDRESS WILL BE INCREASED

+	  BY 1 AUTOMATICALLY.

+

+	NOTE:	AFTER THE ADDRESS IS SET, THE DATA SHOULD BE WRITTEN FROM

+	~~~~~	THE LOWER AS WELL AS THE OAM.

+

+	NOTE:	THE DATA CAN BE WRITTEN ONLY DURING H/V BLANK OR FORCED-

+	~~~~~	BLANK PERIOD.

+

+

+ADDRESS  : $2123/$2124/$2125

+NAME     : W12SEL/W34SEL/WOBJSEL

+CONTENTS : WINDOW MASK SETTINS (BG1-BG4, OBJ, COLOR)

+

+	D7	BG2 WINDOW-2 ENABLE				2123H

+			0: OFF

+			1: ON

+

+	D6	BG2 WINDOW-2 IN/OUT

+			THE WINDOW MASK AREA CAN BE DESIGNATED WHETHER

+			INSIDE OR OUTSIDE OF THE FRAME DESIGNATED BY THE

+			WINDOW POSITION.

+			0: IN

+			1: OUT

+

+	D5	BG2 WINDOW-1 ENABLE

+	D4	BG2 WINDOW-1 IN/OUT

+	D3	BG1 WINDOW-2 ENABLE

+	D2	BG1 WINDOW-2 IN/OUT

+	D1	BG1 WINDOW-1 ENABLE

+	D0	BG1 WINDOW-1 IN/OUT

+

+	D7	COLOR WINDOW-2 ENABLE				2125H

+	D6	COLOR WINDOW-2 IN/OUT

+	D5	COLOR WINDOW-1 ENABLE

+	D4	COLOR WINDOW-1 IN/OUT

+	D3	OBJ WINDOW-2 ENABLE

+	D2	OBJ WINDOW-2 IN/OUT

+	D1	OBJ WINDOW-1 ENABLE

+	D0	OBJ WINDOW-1 IN/OUT

+

+          THE COLOR WINDOW IS A WINDOW FOR MAIN & SUB SCREEN (IT IS

+	  RELATED TO REGISTER <2130H>.

+

+

+ADDRESS  : $2126/$2127/$2128/$2129

+NAME     : WH0/WH1/WH2/WH3

+CONTENTS : WINDOW POSITION DESIGNATION (SEE APPENDIX-15)

+

+	D7-D0	WINDOW PPOSITION

+

+	H0,H2	LEFT POSITION DESIGNATION

+	H1,H3	RIGHT POSITION DESIGNATION

+

+	NOTE:	IF "LEFT POSITION SETTING VALUE > RIGHT POSITION VALUE"

+	~~~~~	IS ASSUMED, THERE WILL BE NO RANGE OF THE WINDOW.

+

+

+ADDRESS  : $212A/$212B

+NAME     : WBGLOG/WOBJLOG

+CONTENTS : MASK LOGIC SETTINGS FOR WINDOW-1 & 2 ON EACH SCREEN

+

+	D7-D6	BG4 D1/D0					212AH

+	D5-D4	BG3 D1/D0

+	D3-D2	BG2 D1/D0

+	D1-D0	BG1 D1/D0

+

+	D7-D4	---						212BH

+	D3-D2	COLORWINDOW D1/D0

+	D1-D0	OBJWINDOW D1/D0

+

+		D1 D0  |  LOGIC

+	        ------------------

+		 0  0  |  OR

+		 0  1  |  AND

+		 1  0  |  XOR

+		 1  1  |  XNOR

+

+	NOTE:	"IN/OUT" OF REGISTERS <2123H>-<2125H> BECOMES THE

+	~~~~~	"NOT-LOGIC" FOR EACH WINDOW-1 & WINDOW-2.

+

+

+ADDRESS  : $212C

+NAME     : TM

+CONTENTS : MAIN SCREEN, DESIGNATION

+

+

+	D7-D5	---

+	D4	OBJ

+	D3	BG4

+	D2	BG3

+	D1	BG2

+	D0	BG1

+

+	MAIN SCREEN DESIGNATION:

+

+		DESIGNATE THE SCREEN (BG1-BG4, OBJ) TO BE DISPLAYED

+		AS THE MAIN SCREEN. DESIGNATE THE SCREEN TO BE ADDED

+		FOR THE SCREEN ADDITION/SUBTRACTION

+

+			0: DISABLE

+			1: ENABLE

+

+

+ADDRESS  : $212D

+NAME     : TS

+CONTENTS : SUB SCREEN DESIGNATION

+

+	D7-D5	---

+	D4	OBJ

+	D3	BG4

+	D2	BG3

+	D1	BG2

+	D0	BG1

+

+	SUB SCREEN DESIGNATION:

+

+		DESIGNATE THE SCREEN (BG1-BG4, OBJ) TO BE DISPLAYED

+		AS SUB SCREEN. DESIGNATE THE ADDITION/SUBTRACTION

+		SCREEN AT THE POINT WHEN THE SCREEN ADDITION/SUBTRACTION

+		IS FUNCTIONING.

+

+			0: DISABLE

+			1: ENABLE

+

+	* WHEN THE SCREEN ADDITION/SUBTRACTION IS FUNCTIONING, THE SUB

+	  SCREEN IS A SCREEN TO BE ADDED OR SUBTRACTED AGAINST THE MAIN

+	  SCREEN.

+

+

+ADDRESS  : $212E

+NAME     : TMW

+CONTENTS : WINDOW MASK DESIGNATION FOR MAIN SCREEN

+

+

+ 	D7-D5	---

+	D4	OBJ

+	D3	BG4

+	D2	BG3

+	D1	BG2

+	D0	BG1

+

+	WINDOW MASK DESIGNATION FOR MAIN SCREEN:

+

+		IN THE WINDOW AREA DESIGNATED BY REGISTER <2123H>-<2129H>,

+		THE SCREEN TO BE DISPLAYED CAN BE DESIGNATED, WHICH IS

+		SELECTED AMONG THE MAIN SCREEN DESIGNATED BY REGISTER

+		<212CH>.

+

+			0: DISABLE

+			1: ENABLE

+

+

+ADDRESS  : $212F

+NAME     : TSW

+CONTENTS : WINDOW MASK DESIGNATION FOR SUB SCREEN

+

+ 	D7-D5	---

+	D4	OBJ

+	D3	BG4

+	D2	BG3

+	D1	BG2

+	D0	BG1

+

+	WINDOW MASK DESIGNATION FOR SUB SCREEN:

+

+		IN THE WINDOW AREA DESIGNATED BY REGISTER <2123H>-<2129H>,

+		THE SCREEN TO BE DISPLAYED CAN BE DESIGNATED, WHICH IS

+		SELECTED AMONG THE SUB SCREEN DESIGNATED BY REGISTER

+		<212CH>.

+

+			0: DISABLE

+			1: ENABLE

+

+	* WHEN THE SCREEN ADDITION/SUBTRACTION IS FUNCTIONING, THE SUB

+	  SCREEN IS A SCREEN TO BE ADDED OR SUBTRACTED AGAINST THE MAIN

+	  SCREEN.

+

+

+ADDRESS  : $2130

+NAME     : CGWSEL

+CONTENTS : INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION

+

+	D7-D6	MAIN SW (M1/M0)

+	D5-D4	SUB SW (S1/S0)

+	D3-D2	---

+	D1	CC ADD ENABLE, FIXED COLOR ADDITION/SUBTRACTION ENABLE

+			DESIGNATE WHETHER 2 KINDS OF THE DATA SHOULD

+			BE ADDED/SUBTRACTED EACH OTHER OR NOT, WHICH ARE

+			THE FIXED COLOR SET BY REGISTER <2132H>, AND

+			THE COLOR DATA WHICH IS SET TO CGRAM.

+				0: ADDITION/SUBTRACTION FOR FIXED COLOR

+				1: ADDITION/SUBTRACTION FOR SUB SCREEN

+

+	D0	DIRECT SELECT (SEE APPENDIX-14)

+			THE VRAM DATA (COLOR & CHARACTER DATA) BECOME THE

+			COLOR DATA DIRECTLY. [ONLY WHEN MODE-3,4 & 7]

+				0: DISABLE

+				1: ENABLE

+

+

+	M1(S1) M0(S0)  |  NORMAL DISPLAY IS:

+	--------------------------------------------------------------

+	  0      0     |  ALL THE TIME

+	  0      1     |  INSIDE WINDOW ONLY

+	  1      0     |  OUTSIDE WINDOW ONLY

+	  1      1     |  ALL THE TIME

+

+

+ADDRESS  : $2131

+NAME     : CGADSUB

+CONTENTS : ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN,

+	   OBJ & BACKGROUND COLOR

+

+	D7	COLOR DATA ADDITION/SUBTRACTION SELECT

+			DESIGNATE THE SELECTION EITHER OF THE ADDITION

+			OR THE SUBTRACTION MODE.

+				0: ADDITION MODE SELECT

+				1: SUBTRACTION MODE SELECT

+

+	D6	"1/2 OF COLOR DATA" DESIGNATION

+			WHEN THE COLOR CONSTANT ADDITION/SUBTRACTION OR THE

+			SCREEN ADDITION/SUBTRACTION IS PERFORMED, DESIGNATE

+			WHETHER THE RGB RESULT IN THE ADDITION/SUBTRACTION

+			AREA SHOULD BE "1/2" OR NOT. HOWEVER, IN THE BACK

+			COLOR CONSTANT AREA ON THE SUB SCREEN, IT DOES NOT

+			BECOME "1/2"

+				0: DISABLE

+				1: ENABLE

+	D5	BACK

+	D4	OBJ

+	D3	BG4

+	D2	BG3

+	D1	BG2

+	D0	BG1

+			COLOR DATA ADDITION/SUBTRACTION ENABLE

+				0: DISABLE

+				1: ENABLE

+

+

+ADDRESS  : $2132

+NAME     : COLDATA

+CONTENTS : FIXED COLOR DATA FOR FIXED COLOR ADDITION/SUBTRACTION

+

+	D7	BLUE

+	D6	GREEN

+	D5	RED

+			BIT FOR SELECTING DESIRED COLOR

+

+	D4-D0	COLOR BRILLIANCE DATA

+			SET THE COLOR CONSTANT DATA FOR COLOR CONSTANT

+			ADDITION/SUBTRACTION

+

+	* R/G/B BRIGHTNESS SHOULD BE SET BY THE DATA OF EACH 5-BIT.

+

+		[EXAMPLE]	RED   : C0H, 3FH (B=00H, G=00H, R=1FH)

+				GREEN : A0H, 5FH (B=00H, G=1FH, R=00H)

+				BLUE  : 60H, 9FH (B=1FH, G=00H, R=00H)

+				WHITE : FFH

+				BLACK : 00H

+

+

+ADDRESS  : $2133

+NAME     : SETINI

+CONTENTS : SCREEN INITIAL SETTING

+

+	D7	EXTERNAL SYNCHRONIZATION

+			IT IS USED FOR SUPER IMPOSE AND ETC. NORMALLY,

+			"0" SHOULD BE WRITTEN.

+

+	D6	EXTBG MODE (SCREEN EXPAND)

+			ENABLE THE DATA SUPPLIED FROM THE EXTERNAL LSI.

+			FOR THE SFX, ENABLE WHEN THE SCREEN WITH PRIORITY

+			IS USED ON MODE-7.

+

+	D5-D4	---

+

+	D3	HORIZONTAL PSEUDO 512 MODE

+			512 IMAGINARY RESOLUTION (HORIZONTAL CAN BE MADE

+			BY SHIFTING THE SUBSCREEN HALF DOT TO THE LEFT.)

+				0: DISABLE

+				1: ENABLE

+

+	D2	BG V-DIRECTION DISPLAY

+			SWITCH THE DISPLAY LINE OF A FIELD TO 224 LINE OR

+			239 LINE. (IN CASE OF INTERALACE IT WILL BE

+			DOUBLED DOT.)

+				0: 224 LINE

+				1: 239 LINE

+

+	D1	OBJ V-DIRECTION DISPLAY

+			IN THE INTERLACE MODE, SELECT EITHER OF 1-DOT PER

+			LINE OR 1-DOT REPEATED EVERY 2-LINES. IF "1" IS

+			WRITTEN, THE OBJ SEEMS REDUCED HALF VERTICALLY IN

+			APPEARANCE.

+

+	D0	SCANNING

+			INTERLACE/NON-INTERLACE SELECTION (IT RELATES TO

+			<2105H>.

+				0: NON INTERLACE

+				1: INTERLACE

+

+

+ADDRESS  : $2134/$2135/$2136

+NAME     : *MPYL/*MPYM/*MPYH

+CONTENTS : MULTIPLICATION RESULT

+

+	D7-D0	MPY (LOW)					2134H

+	D7-D0	MPY (MID)					2135H

+	D7-D0	MPY (HIGH)					2136H

+

+          THIS IS A MULTIPLICATION RESULT (COMPLEMENT OF 2) CAN BE READ

+	  BY SETTING 16-BIT TO REGISTER <211BH> AND SETTING 8 BIT TO

+	  REGISTER <211CH>

+

+

+ADDRESS  : $2137

+NAME     : *SLHV

+CONTENTS : SOFTWARE LATCH FOR H/V COUNTER

+

+	D7-D0	SOFT LATCH FOR H/V COUNTER

+

+          THIS IS A REGISTER, WHICH GENERATE THE PULSE FOR LATCHING THE H/V

+	  COUNTER VALUE.

+

+          THE H/V COUNTER VALUE AT THE POINT WHEN REGISTER <2137H> IS READ

+	  CAN BE LATCHED. THE DATA WHICH WAS READ IS MEANINGLESS DATA.

+

+          THE H/V COUNTER VALUE LATCHED CAN BE REFFERED BY REGISTERS

+	  <213CH> & <213DH>.

+

+

+ADDRESS  : $2138

+NAME     : OAMDATAREAD (name differs from SNES manual)

+CONTENTS : READ DATA FROM OAM

+

+	D7-D0	OAM DATA (LOW,HIGH)

+

+          THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF

+	  THE OAM.

+

+         WHEN THE ADDRESS IS SET TO REGISTER <2102H><2103H> AND REGISTER

+	  <2138H> IS ALSO ACCESSED THE DATA CAN BE READ IN THE ORDER OF

+	  LOW 8-BIT/HIGH 8-BIT.

+	  AFTERWARD, THE ADDRESS WILL BE INCREASED AUTOMATICALLY, AND THE

+	  DATA OF THE NEXT ADDRESS CAN BE READ.

+

+	NOTE:	THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED

+	~~~~~	BLANK PERIOD.

+

+

+ADDRESS  : $2139/$213A

+NAME     : VMDATALREAD/VMDATAHREAD (names differ from SNES manual)

+CONTENTS : READ DATA FROM VRAM

+

+	D7-D0	VRAM DATA (LOW)					2139H

+	D7-D0	VRAM DATA (HIGH)				213AH

+

+          THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF

+	  THE VRAM.

+

+          THE INITIAL ADDRESS SHOULD BE SET BY REGISTERS <2116H> AND

+	  <2117H>. THE DATA CAN BE READ BY THE ADDRESS WHICH HAS BEEN SET

+	  INITIALLY.

+

+          WHEN READING THE DATA CONTINOUSLY, THE FIRST DATA FOR THE ADDRESS

+	  INCREMENT SHOULD BE READ AS A DUMMY DATA AFTER THE ADDRESS HAS

+	  BEEN SET.

+

+          QUANTITY TO BE INCREASED WILL BE DETERMINED BY "SC INCREMENT" OF

+	  REGISTER <2115H> AND THE SETTING VALUE OF THE "FULL GRAPHIC".

+

+	NOTE:	THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED

+	~~~~~	BLANK PERIOD.

+

+

+ADDRESS  : $213B

+NAME     : CGDATAREAD (name differs from SNES manual)

+CONTENTS : READ DATA FROM CG-RAM

+

+	D7-D0	CG DATA (LOW,HIGH)

+

+          THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF

+	  THE CG-RAM.

+

+          THE INITIAL ADDRESS SHOULD BE SET BY REGISTER <2121H>. THE LOWER

+	  8-BIT IS READ FIRST, AND THE THE UPPER 7-BIT WILL BE READ BY

+	  ACCESSING THIS REGISTER. THE CURRENT ADDRESS WILL BE INCREASED

+	  TO THE NEXT ADDRESS AT THE SAME TIME THE UPPER 7-BIT IS READ.

+

+	NOTE:	THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED

+	~~~~~	BLANK PERIOD.

+

+

+ADDRESS  : $213C/$213D

+NAME     : *OPHCT/*OPVCT

+CONTENTS : H/V COUNTER DATA BY EXTERNAL OR SOFTWARE LATCH

+

+	D7-D0	OUTPUT DATA OF H-COUNTER [9-BIT]		213CH

+	D7-D0	OUTPUT DATA OF V-COUNTER [9-BIT]		213DH

+

+          THE H/V COUNTER IS LATCHED BY READING REGISTER <2137H>, AND ITS

+	  H/V COUNTER VALUE CAN BE READ BY THIS REGISTER.

+

+          THE H/V COUNTER IS ALSO LATCHED BY THE EXTERNAL LATCH, AND ITS

+	  VALUE CAN BE READ BY THIS REGISTER.

+

+          IF REGISTER <213CH> OR <213DH> IS READ AFTER REGISTER <213FH> HAS

+	  BEEN READ, THE LOWER 8-BIT DATA WILL BE READ FIRST, AND THEN THE

+	  UPPER 1-BIT WILL BE READ BY READING THE REGISTER.

+

+

+ADDRESS  : $213E

+NAME     : *STAT77

+CONTENTS : PPU STATUS FLAG & VERSION NUMBER

+

+	D7	TIME OVER  \

+	D6	RANGE OVER /

+			OBJ DISPLAY STATUS (ON A HORIZONTAL LINE)

+			RANGE: 	WHEN QUANTITY OF THE OBJ (REGARDLESS OF

+				THE SIZE) BECOMES 33 PCS OR MORE, "1"

+				WILL BE SET.

+			TIME:	WHEN QUANTITY OF THE OBJ WHICH IS CONVERTED

+				TO "8 x 8-SIZE" IS 35 PCS OR MORE, "1"

+				WILL BE SET.

+

+	D5	MASTER/SLAVE MODE SELECT. LSI MODE (NORMALLY "0" IS SET.)

+

+	D4	---

+

+	D3-D0	5C77	VERSION NUMBER

+

+	NOTE:	THE FLAG WILL BE RESET AT THE END OF THE V-BLANK PERIOD.

+	~~~~~

+

+

+ADDRESS  : $213F

+NAME     : *STAT78

+CONTENTS : PPU STATUS FLAG & VERSION NUMBER

+

+	D7	FIELD

+			THIS IS A STATUS FLAG, WHICH INDICATED WHETHER 1ST

+			FIELD IS SCANNED OR 2ND FIELD IS SCANNED IN INTER-

+			LACE MODE. (THE DEFINITION IS DIFFERENT FROM THE

+			FIELD OF NTSC.)

+				0: 1ST FIELD

+				1: 2ND FIELD

+

+	D6	EXTERNAL LATCH FLAG

+			WHEN THE EXTERNAL SIGNAL (LIGHT PEN, ETC.) IS

+			APPLIED, IT ENABLES TO LATCH THE H/V COUNTER VALUE.

+

+	D5	---

+

+	D4	NTSC/PAL MODE

+				0: NTSC

+				1: PAL

+

+	D3-D0	5C78 VERSION NUMBER

+

+	NOTE:	WHEN THIS REGISTER IS READ, REGISTERS <213CH><213DH> WILL

+	~~~~~	BE INITIALIZED INDIVIDUALLY IN THE ORDER OF LOW & HIGH.

+

+

+ADDRESS  : $2140/$2141/$2142/$2143

+NAME     : APUI00/APUI01/APUI02/APUI03

+CONTENTS : COMMUNICATION PORT WITH APU

+

+	D7-D0	APU I/O PORT

+

+          THIS PORT PROVIDES MORE REGISTERS FOR THE PURPOSE OF IN/OUT,

+	  WHICH ARE 8 REGISTERS IN TOTAL IN THE APU. THEREFORE, THE

+	  DIFFERENT REGISTER WILL BE ACCESSED, WHETHER READING OR

+	  WRITING FOR THE SAME ADDRESS.

+

+          SEE "APU MANUAL" FOR THE DETAILS OF THE COMMUNICATION METHOD.

+

+

+ADDRESS  : $2180

+NAME     : WMDATA

+CONTENTS : DATA TO CONSECUTIVLEY READ FROM AND WRITE TO WRAM

+

+	D7-D0	WORK RAM DATA

+

+          DATA TO CONSECUTIVLEY READ FROM AND WRITE TO WRAM

+

+          DATA IS READ AND WRITTEN AT ADDRESS SET BY REGISTER <2181H>-<2183H>,

+	  AND ADDRESS AUTOMATICALLY INCREASES EACH TIME DATA IS READ OR WRITTEN.

+

+

+ADDRESS  : $2181/$2182/$2183

+NAME     : WMADDL/WMADDM/WMADDH

+CONTENTS : ADDRESS TO CONSECUTIVELY READ AND WRITE WRAM

+

+	D7-D0	WRAM DATA (LOW)					2181H

+	D7-D0	WRAM DATA (MID)					2182H

+   	D0	WRAM DATA (HIGH)				2183H

+

+          ADDRESS TO BE SET BEFORE WRAM IS CONSECUTIVLEY READ OR WRITTEN.

+

+          A0 TROUGH A16 AT REGISTER <2181H>-<2183H> IS LOWER 17 BIT ADDRESS

+	  TO SHOW ADDRESS $7E0000-$7FFFFF IN MEMORY.

+

+

+ADDRESS  : $4200

+NAME     : NMITIMEN

+CONTENTS : ENABLE FLAG FOR V-BLANK, TIMER INTERRUPT & JOY CONTROLLER READ

+

+	D7	NMI ENABLE

+			ENABLE NMI AT THE POINT WHEN V-BLANK BEGINS

+			(WHEN POWER IS TURNED ON OR THE RESET SIGNAL IS

+			APPLIED, IT WILL BE "0".)

+				0: NMI DISABLED

+				1: NMI ENABLED

+

+	D6	---

+

+	D5-D4	TIMER ENABLE (V-EN/H-EN)

+

+	D3-D1	---

+

+	D0	JOY-C ENABLE

+			0: DISABLE AUTOMATIC READING OF THE JOY-CONTROLLER.

+			1: ENABLE AUTOMATIC READING OF THE JOY-CONTROLLER.

+

+	V-EN H-EN  |  FUNCTION

+	--------------------------------------------------------

+	   0    0  |  DISABLE BOTH H & V

+	   0    1  |  ENABLE H ONLY, IRQ APPLIED BY H-COUNT TIMER VALUE DESIGNATED

+	   1    0  |  ENABLE V ONLY, IRQ APPLIED BY V-COUNT TIMER VALUE DESIGNATED

+	   1    1  |  ENABLE BOTH V & H, IRQ APPLIED BY BOTH H & V COUNT TIMER VAL

+	           |  DESIGNATED.

+

+	* READING THE DATA CAN BE STARTED AT THE BEGINNING OF V-BLANK

+	  PERIOD, BUT IT TAKES ABOUT FOR 3 OR 4 SCANNING PERIOD UNTIL

+	  COMPLETION OF READING.

+

+

+ADDRESS  : $4201

+NAME     : WRIO

+CONTENTS : PROGRAMMABLE I/O PORT (OUT-PORT)

+

+	D7-D0	I/O PORT

+

+          THIS IS A PROGRAMMABLE I/O PORT (OUT-PORT). THE WRITTEN DATA

+	  WILL BE OUTPUT DIRECTLY FROM THE OUT-PORT.

+

+          WHEN THIS IS USED AS A INPORT. "1" SHOULD BE WRITTEN TO THE

+	  PARTICULAR BIT WHICH WILL BE USED AS IN PORT. THE INPUT CAN

+	  BE READ BY REGISTER <4213H>.

+

+

+ADDRESS  : $4202/$4203

+NAME     : WRMPYA/WRMPYB

+CONTENTS : MULTIPLIER & MULTIPLICAND BY MULTIPLICATION

+

+	D7-D0	MULTIPLICAND-A					4202H

+	D7-D0	MULTIPLIER-B					4203H

+

+          THIS IS A REGISTER, WHICH CAN SET A MULITPLICAND (A) AND A

+	  MULTIPLIER (B) FOR ABSOLUTE MULTIPLICATION OF

+	  "A (8-BIT) * B (8-BIT)=C (16-BIT)"

+

+          A PRODUCT (C) CAN BE READ BY REGISTERS <4216H><4217H>

+

+          SET IN THE ORDER OF (A) AND (B). THE OPERATION WILL START AS

+	  SOON AS (B) HAS BEEN SET, AND IT WILL BE COMPLETED RIGHT AFTER

+	  8-MACHINE CYCLE PERIOD.

+

+          ONCE THE DATA OF THE A-REGISTER IS SET, IT WILL NOT BE DESTROYED

+	  UNTIL NEW DATA IS SET.

+

+

+ADDRESS  : $4204/$4205/$4206

+NAME     : WRDIVL/WRDIVH/WRDIVB

+CONTENTS : DIVISOR & DIVIDEND DIVIDE

+

+	D7-D0	MULTIPLIER-C (LOW)				4204H

+	D7-D0	MULTIPLIER-C (HIGH)				4205H

+	D7-D0	DIVISOR-B					4206H

+

+          THIS IS A REGISTER, WHICH CAN SET A DIVIDEND (C) AND A DIVISOR (B)

+	  FOR ABSOLUTE DIVIDE OF

+	  "C (16-BIT) / B (8-BIT)=A (16-BIT)"

+

+          THE DIVISOR (A) CAN BE READ BY REGISTERS <4214H><4215H>, AND THE

+	  REMAINDER CAN ALSO BE READ BY REGISTERS <4216H><4217H>.

+

+          SET IN THE ORDER OF (C) AND (B). THE OPERATION WILL START AS SOON

+	  AS (B) HAS BEEN SET, AND IT WILL BE COMPLETED RIGHT AFTER 16-

+	  MACHINE CYCLE PERIOD.

+

+          ONCE THE DATA OF THE A-REGISTER IS SET, IT WILL NOT BE DESTROYED

+	  UNTIL NEW DATA IS SET.

+

+

+ADDRESS  : $4207/$4208

+NAME     : HTIMEL/HTIMEH

+CONTENTS : H-COUNT TIMER SETTINGS

+

+	D7-D0	H COUNT TIMER (H7-H0)				4207H

+

+	D7-D1	---

+	D0	H COUNT TIMER (H8)				4208H

+

+          THIS IS A REGISTER, WHICH CAN SET THE H-COUNT TIMER VALUE.

+

+          THE SETTING VALUE SHOULD BE FROM 0 THROUGH 339, WHICH IS COUNTED

+	  FROM THE FAR LEFT ON THE SCREEN.

+

+          HWEN THE COORDINATE COUNTER BECOMES THE COUNT VALUE SET, THE IRQ

+	  WILL BE APPLIED. AND AT THE SAME TIME. "1" WILL BE WRITTEN TO

+	  "TIMER IRQ" OF REGISTER <4211H>. (READ RESET)

+	  ENABLE/DISABLE OF THE INTERRUPT WILL BE DETERMINED BY SETTING

+	  REGISTER <4200H>

+

+	* THIS CONTINOUS COUNTER IS RESET EVERY SCANNING LINE, THEREFORE

+	  ONCE THE COUNT VALUE IS SET, IT IS POSSIBLE TO APPLY THE IRQ

+	  EVERY TIME THE SCANNING LINE COMES TO THE SAME HORIZONTAL

+	  POSITION ON THE SCREEN.

+

+

+ADDRESS  : $4209/$420AH

+NAME     : VTIMEL/VTIMEH

+CONTENTS : V-COUNT TIMER SETTINGS

+

+	D7-D0	V COUNT TIMER (V7-V0)				4209H

+

+	D7-D1	---

+	D0	V COUNT TIMER (V8)				420AH

+

+          THIS IS A REGISTER, WHICH CAN SET THE V-COUNT TIMER VALUE.

+

+          THE SETTING VALUE SHOULD BE FROM 0 THROUGH 261(262), WHICH IS

+	  COUNTED FROM THE FAR TOP OF THE SCREEN. [THE LINE NUMBER DESCRIBED

+	  IS DIFFERENT FROM THE ACTUAL LINE NUMBER ON THE SCREEN.]

+

+          HWEN THE COORDINATE COUNTER BECOMES THE COUNT VALUE SET, THE IRQ

+	  WILL BE APPLIED. AND AT THE SAME TIME. "1" WILL BE WRITTEN TO

+	  "TIMER IRQ" OF REGISTER <4211H>. (READ RESET)

+	  ENABLE/DISABLE OF THE INTERRUPT WILL BE DETERMINED BY SETTING

+	  REGISTER <4200H>

+

+	* THIS IS A CONTINOUS COUNTER SAME AS H-COUNTER, AND IT WILL BE

+	  RESET EVERY TIME 262(263) LINE ARE SCANNED. ONCE THE COUNT

+	  VALUE IS SET, IT IS POSSIBLE TO APPLY THE IRQ EVERY TIME THE

+	  SCANNING LINE COMES TO THE SAME VERTICAL LINE ON THE SCREEN.

+

+

+ADDRESS  : $420B

+NAME     : MDMAEN

+CONTENTS : CHANNEL DESIGNATION FOR GENERAL PURPOSE DMA & TRIGGER (START)

+

+	D7-D0	GENERAL PURPOSE CH7-CH0 ENABLE

+

+          THE GENERAL PURPOSE DMA CONSISTS OF 8-CHANNELS IN TOTAL.

+

+          THIS REGISTER IS USED TO DESIGNATE THE CHANNEL OUT OF 8-CHANNELS.

+

+          THE CHANNEL WHICH SHOULD BE USED CAN BE DESIGNATED BY WRITING "1"

+	  TO THE BIT OF THIS CHANNEL. AS SOON AS "1" IS WRITTEN TO THE

+	  BIT (AFTER A FEW CYCLES PASSED), THE GENERAL PURPOSE DMA TRANSFER

+	  WILL BE STARTED.

+

+          WHEN THE GENERAL PURPOSE DMA OF THE DESIGNATED CHANNEL IS

+          COMPLETED, THE FLAG WILL BE CLEARED.

+

+	NOTE:	BECAUSE THE DATA AREA (REGISTER <4300>-) OF EACH CHANNEL

+	~~~~~	IS HELD IN COMMON WITH THE DATA OF EACH H-DMA CHANNEL, THE

+		CHANNEL DESIGNATED BY THE H-DMA CHANNEL DESIGNATION

+		REGISTER <420CH> CAN NOT BE USED.

+		(IT IS PROHIBITED TO WRITE "1" TO THE BIT OF THE CHANNEL)

+		THEREFORE, 8 CHANNELS (CH0-CH7) SHOULD BE ASSIGNED BY THE

+		H-DMA AND THE GENERAL PURPOSE DMA)

+

+	NOTE:	IF THE H-BLANK COME DURING THE OPERATION OF THE GENERAL

+	~~~~~	PURPOSE DMA AND THE H-DMA IS STARTED, THE GENERAL PURPOSE

+		DMA WILL BE DISCONTINUED IN THE MIDDLE, AND RE-STARTED RIGHT

+		AFTER THE H-DMA IS COMPLETE.

+

+	NOTE:	IF 2 OR MORE CHANNELS ARE DESIGNATED, THE DMA TRANSFER WILL

+	~~~~~	BE PERFORMED CONTINOUSLY ACCORDING TO THE PRIORITY DESCRIBED

+		IN APPENDIX-1.

+		AND ALSO, THE CPU STOPS OPERATION UNTIL ALL THE GENERAL

+		PURPOSE DMA ARE COMPLETED.

+

+

+ADDRESS  : $420C

+NAME     : HDMAEN

+CONTENTS : CHANNEL DESIGNATION FOR H-DMA

+

+	D7-D0	H-DMA CH7-DH0 ENABLE

+

+          THE H-DMA CONSISTS OF 8-CHANNELS IN TOTAL

+

+          THIS REGISTER IS USED TO DESIGNATE THE CHANNEL OUT OF 8-CHANNELS

+

+          THE CHANNEL WHICH SHOULD BE USED CAN BE DESIGNATED BY WRITING

+	  "1" TO THE BIT OF THIS CHANNEL. AS SOON AS H-BLANK BEGINS (AFTER

+	  A FEW CYCLES PASSED), THE H-DMA TRANSFER WILL BE STARTED.

+

+	NOTE:	ONCE THIS FLAG IS SET, IT WILL NOT BE DESTROYED (CLEARED)

+	~~~~~	UNTIL NEW DATA IS SET. THEREFORE, THE INITIAL SETTINGS ARE

+		DONE AUTOMATICALLY EVERY FIELD, AND THE SAME TRANSFER

+		PATTERN WILL BE REPEATED.

+		AND ALSO, THE FLAG IS SET OUT OF V-BLANK PERIOD, THE DMA-

+		TRANSFER WILL BE PERFORMED PROPERLY FROM NEXT SCREEN FRAME.

+

+

+ADDRESS  : $420D

+NAME     : MEMSEL

+CONTENTS : ACCESS CYCLE DESIGNATION IN MEMORY (2) AREA

+

+	D7-D1	---

+	D0	ACCESS CYCLE DESIGNATION IN MEMORY (2) AREA

+			0: 2.68MHz ACCESS CYCLE

+			1: 3.58MHz ACCESS CYCLE (ONLY WHEN HIGH SPEED

+						 MEMORY IS USED.)

+

+          MEMORY (2) SHOWS THE ADDRESS (8000H-FFFFH) OF THE BANK (80H-BFH)

+	  AND ALL THE ADDRESS OF THE BANK (C0H-FFH).

+

+          WHEN POWER IS TURNED ON OR THE RESET SIGNAL IS APPLIED IT BECOMES

+	  "0".

+

+          HIGH SPEED MEMORY REQUIERS 120NS OR FASTER EPROMS.

+

+

+ADDRESS  : $4210

+NAME     : *RDNMI

+CONTENTS : NMI FLAG BY V-BLANK & VERSION NUMBER

+

+	D7	NMI FLAG BY V-BLANK

+			WHEN "1" IS WRITTEN TO "NMI ENABLE" OF REGISTER

+			<4200H>, THIS FLAG WILL SHOW NMI STATUS.

+				0: NMI STATUS IS "DISABLE"

+				1: NMI STATUS IS "ENABLE"

+

+	D6-D4	---

+

+	D3-D0	5A22 VERSION NUMBER

+

+	* "1" IS SET TO THIS FLAG AT BEGINNING OF V-BLANK, AND "0" IS

+	  SET AT END OF V-BLANK. ALSO, IT CAN BE SET BY READING THIS

+	  REGISTER.

+

+	NOTE:	IT IS NECESSARY TO RESET BY READING THIS FLAG DURING

+	~~~~~	NMI PROCESSING. (SEE APPENDIX-3)

+

+

+ADDRESS  : $4211

+NAME     : *TIMEUP

+CONTENTS : IRQ FLAG BY H/V COUNT TIMER

+

+	D7	IRQ FLAG BY H/V COUNT TIMER

+			[IN CASE THE TIME ENABLE IS SET BY "TIMER ENABLE"

+			OF REGISTER <4200H>] AS SOON AS H/V COUNTER TIMER

+			BECOMES THE COUNT VALUE SET, IRQ WILL BE APPLIED

+			AND "1" WILL BE SET TO THIS FLAG.

+			THIS FLAG IS "READ-RESET".

+

+	D6-D0	---

+

+	* EVEN IF V-EN="0" AND H-EN="0" ARE SET BY "TIMER ENABLE" OF

+	  REGISTER <4200H>, THIS FLAG WILL BE RESET.

+		0: EITHER H/V COUNTER IS IN ACTIVE OR DISABLE.

+		1: H/V COUNT TIMER IS TIME UP.

+

+

+ADDRESS  : $4212

+NAME     : HVBJOY

+CONTENTS : H/V BLANK FLAG & JOY CONTROLLER ENABLE FLAG

+

+	D7	V-BLANK PERIOD FLAG

+			0: OUT OF V-BLANK PERIOD

+			1: IN V-BLANK PERIOD

+

+	D6	H-BLANK PERIOD FLAG

+			0: OUT OF H-BLANK PERIOD

+			1: IN H-BLANK PERIOD

+

+	D5-D1	---

+

+	D0	JOY CONTROLLER ENABLE FLAG

+			THIS FLAG SHOWS THE TIMING TO READ THE DATA OF THE

+			JOY CONTROLLER. (HOWEVER, IT IS LIMITED TO THE CASE

+			WHICH THE "JOY-C ENABLE" OF REGISTER <4200H> IS SET

+			TO "1".

+

+

+ADDRESS  : $4213

+NAME     : *RDIO

+CONTENTS : PROGRAMMABLE I/O PORT (IN-PORT)

+

+	D7-D0	I/O PORT

+

+          THIS IS A PROGRAMMABLE I/O PORT (IN PORT). THE DATA WHICH IS SET

+	  TO THE IN-PORT SHOULD BE READ DIRECTLY.

+

+          THE BIT WHICH "1" IS WRITTEN BY REGISTER <4201H> IS USED AS THE

+	  IN PORT.

+

+

+ADDRESS  : $4114/$4115

+NAME     : *RDDIVL/*RDDIVH

+CONTENTS : QUOTIENT OF DIVIDE RESULT

+

+	D7-D0	QUOTENT-A (LOW)					4114H

+	D7-D0	QUOTENT-A (HIGH)				4115H

+

+          THIS IS A QUOTENT (A), WHICH IS A RESULT FOR ABSOLUTE DIVIDE OF

+	  "C (16-BIT) / B (8-BIT) = A (16-BIT)".

+

+          DIVIDEND (C) AND DIVISOR (B) ARE SET BY REGISTERS <4204H>-<4206H>.

+

+

+ADDRESS  : $4216/$4217

+NAME     : *RDMPYL/*RDMPYH

+CONTENTS : PRODUCT OF MULTIPLICATION RESULT OR REMAINDER OF DIVIDE RESULT

+

+	D7-D0	PRODUCT-C [MUL] / REMAINDER [DIV] (LOW)		4216H

+	D7-D0	PRODUCT-C [MUL] / REMAINDER [DIV] (HIGH)	4217H

+

+	(1) IN CASE OF MULTIPLICATION

+          THIS IS A PRODUCT (C) WHICH IS A RESULT FOR ABSOLUTE

+	  MULTIPLICATION OF "A (8-BIT) * B (8-BIT) = C (16-BIT)".

+

+          A MULTIPLICAND (A) AND A MULTIPLIER (B) ARE SET BY REGISTERS

+	  <4202H> & <4203H>.

+

+	(2) IN CASE OF DIVIDE

+          THIS IS THE REMAINDER, WHICH IS A RESULT FOR THE ABSOLUTE

+	  DIVIDE OF "C (16-BIT) / B (8-BIT) = A (16-BIT)".

+

+          A DIVIDEND (C) AND DIVISOR (B) ARE SET BY THE REGISTERS

+	  <4204H><4205H> & <4206H>.

+

+

+ADDRESS  : $4218/$4219/$421A/$421B/$421C/$421D/$421E/$421F

+NAME     : JOY1L/JOY1H/JOY2L/JOY2H/JOY3L/JOY3H/JOY4L/JOY4H

+CONTENTS : DATA FOR JOY CONTROLLER I, II, III & IV

+

+	D7	X BUTTON					LOW

+	D6	Y BUTTON

+	D5	TL BUTTON

+	D4	TR BUTTON

+	D3-D0	----

+

+	D7	A BUTTON					HIGH

+	D6	B BUTTON

+	D5	SELECT BUTTON

+	D4	START BUTTON

+	D3	UP

+	D2	DOWN

+	D1	LEFT

+	D0	RIGHT

+

+          REGISTERS <4016H><4017H> CAN BE USED THE SAME AS THE FAMILY

+	  COMPUTER.

+

+	4016H-RD

+		D0 : DATA FOR CONTROLLER I

+		D1 : DATA FOR CONTROLLER III

+	4016H-WR

+		OUT0,OUT1,OUT2

+	4017H-RD

+		D0 : DATA FOR CONTROLLER II

+		D1 : DATA FOR CONTROLLER IV

+

+	NOTE:	WHETHER THE STANDARD JOY CONTROLLERS ARE CONNECTED TO THE

+	~~~~~	SFX OR NOT CAN BE REFFERED BY READING 17TH BIT OF <4016H>

+		AND <4017H> (SEE PAGE 22).

+			0: CONNECTED

+			1: NOT CONNECTED

+

+

+ADDRESS  : $43X0 (X: CHANNEL NUMBER 0-7)

+NAME     : DMAPX

+CONTENTS : PARAMETER FOR DMA TRANSFER

+

+	D7	TRANSFER ORIGINATION DESIGNATION (SEE APPENDIX-1)

+			TRANSFER DIRECTION  A-BUS -> B-BUS

+			                    B-BUS -> A-BUS DESIGNATION

+				0: A-BUS -> B-BUS (CPU MEMORY -> PPU)

+				1: B-BUS -> A-BUS (PPU -> CPU MEMORY)

+

+	D6	TYPE DESIGNATION (H-DMA ONLY)

+			ADDRESSING MODE DESIGNATION WHEN ACCESSING THE

+			DATA (SEE APPENDIX-2).

+				0: ABSOLUTE ADDRESSING

+				1: INDIRECT ADDRESSING

+

+	D5	---

+

+	D4-D3	FIXED ADDRESS FOR A-BUS & AUTOMATIC INC./DEC. SELECT.

+			D3	0: AUTOMATIC ADDRESS INCREMENT/DECREMENT

+				1: FIXED ADDRESS <TO BE USED WHEN CLEARING

+				   VRAM ETC.>

+			D4	0: AUTOMATIC INCREMENT

+				1: AUTOMATIC DECREMENT (IN CASE "0" IS

+				   WRITTEN TO D3)

+

+	D2-D0	DMA TRANSFER WORD SELECT

+			GENERAL PURPOSE DMA: B-ADDRESS CHANGE METHOD

+

+				D2 D1 D0  | ADDRESS TO BE WRITTEN

+				---------------------------------

+				 0  0  0  | 1-ADDRESS

+				 0  0  1  | 2-ADDRESS (VRAM ETC.)   L,H

+				 0  1  0  | 1-ADDRESS

+				 0  1  1  | 2-ADDRESS (WRITE TWICE) L,L,H,H

+				 1  0  0  | 4-ADDRESS               L,H,L,H

+

+			H-DMA: THE NUMBER OF BYTE TO BE TRANSFERED PER LINE

+			AND WRITE METHOD DESIGNATION

+

+				D2 D1 D0  | ADDRESS TO BE WRITTEN

+				---------------------------------

+				 0  0  0  | 1-ADDRESS                     (1)

+				 0  0  1  | 2-ADDRESS (VRAM ETC.)  L,H    (2)

+				 0  1  0  | WRITE TWICE            L,L    (1)

+				 0  1  1  | 2-ADDRESS/WRITE TWICE  L,L,H,H(2)

+				 1  0  0  | 4-ADDRESS              L,H,L,H(4)

+

+

+ADDRESS  : $43X1 (X: CHANNEL NUMBER 0-7)

+NAME     : BBADX

+CONTENTS : B-BUS ADDRESS FOR DMA

+

+	D7-D0	B-ADDRESS

+

+          THIS IS A REGISTER, WHICH CAN SET THE ADDRESS OF B-BUS.

+

+          WHETHER THIS IS THE ADDRESS OF THE "TRANSFER DESTINATION" OR

+	  THE ADDRESS OF THE "TRANSFER ORIGINATION" CAN BE DETERMINED BY

+	  D7 (TRANSFER ORIGINATION) OF REGISTER <4300H>.

+

+	* WHEN THE H-DMA IS PERFORMED, IT WILL BE ADDRESS OF "TRANSFER

+	  DESTINATION".

+

+

+ADDRESS  : $43X2/$43X3/$43X4 (X: CHANNEL NUMBER 0-7)

+NAME     : A1TXL/A1TXH/A1BX

+CONTENTS : TABLE ADDRESS OF A-BUS FOR DMA <A1 TABLE ADDRESS>

+

+	D7-D0	A1 TABLE ADDRESS (LOW)				43X2H

+	D7-D0	A1 TABLE ADDRESS (HIGH)				43X3H

+	D7-D0	A1 TABLE BANK					43X4H

+

+          THIS IS A REGISTER, WHICH CAN SET THE ADDRESS OF A-BUS

+

+          WHETHER THIS IS THE ADDRESS OF THE "TRANSFER DESTINATION" OR

+	  THE ADDRESS OF THE "TRANSFER ORIGINATION" CAN BE DETERMINED BY

+	  D7 (TRANSFER ORIGINATION) OF REGISTER <4300H>.

+	  "0" SHOULD BE WRITTEN TO D7 EXCEPT A SPECIAL CASE.

+

+          IN THE H-DMA MODE, THE ADDRESS OF THE TRANSFER ORIGINATION IS

+	  DESIGNATED BY THIS ADDRESS, THE DATA (APPENDIX-2) MUST BE

+	  SET BY THE ABSOLUTE ADDRESSING MODE OR THE INDIRECT ADDRESSING

+	  MODE.

+

+          THIS ADDRESS BECOMES THE BASIC ADDRESS ON THE A-BUS DURING DMA

+	  TRANSFER PERIOD, AND THE ADDRESS WILL BE INCREASED OR DECREASED

+	  BASED ON THIS ADDRESS. (WHEN THE GENERAL PURPOSE DMA IS PERFORMED

+	  IT WILL BE DECREASED.)

+

+

+ADDRESS  : $43X5/$43X6/$43X7 (X: CHANNEL NUMBER 0-7)

+NAME     : DASXL/DASXH/DASBX

+CONTENTS : DATA ADDRESS STORE BY H-DMA & NUMBER OF BYTE TO BE TRANSFERED

+	   SETTINGS BY GENERAL PURPOSE DMA

+

+	D7-D0	DATA ADDRESS (LOW) 			 H-DMA	43X5H

+		NUMBER OF BYTES TO BE TRANSFERED (LOW)	GP-DMA

+

+	D7-D0	DATA ADDRESS (HIGH)			 H-DMA	43X6H

+		NUMBER OF BYTES TO BE TRANSFERED (HIGH) GP-DMA

+

+	D7-D0	DATA BANK					43X7H

+

+          IN CASE OF H-DMA

+		THIS IS A REGISTER WHICH THE INDIRECT ADDRESS WILL BE

+		STORED AUTOMATICALLY IN THE INDIRECT ADDRESSING MODE.

+		THE INDIRECT ADDRESS MEANS THE DATA ADDRESS DESCRIBED

+		ON APPENDIX-2. IT IS NOT NECESSARY TO READ OR WRITE

+		DIRECTLY BY THE CPU EXCEPT IN SPECIAL CASES.

+

+          IN CASE OF GENERAL PURPOSE DMA

+		THIS IS THE REGISTER, WHICH CAN SET THE NUMBER OF BYTE

+		TO TRANSFER OR TO BE TRANSFERED. HOWEVER, THE NUMBER OF

+		BYTE "0000H" MEANS "10000H".

+

+

+ADDRESS  : $43X8/$43X9 (X: CHANNEL NUMBER 0-7)

+NAME     : A2AXL/A2AXH

+CONTENTS : TABLE ADDRESS OF A-BUS BY DMA < A2 TABLE ADDRESS

+

+	D7-D0	A2 TABLE ADDRESS (LOW)				43X8H

+	D7-D0	A2 TABLE ADDRESS (HIGH)				43X9H

+

+          THESE ARE THE ADDRESSES, WHICH ARE USED TO ACCESS THE CPU & RAM,

+	  AND IT WILL BE INCREASED AUTOMATICALLY. (SEE APPENDIX-2)

+

+          THE DATA OF THESE REGISTERS ARE USED AS THE BASIC ADDRESS WHICH

+	  IS THE ADDRESSS SET BY THE "A1 TABLE ADDRESS". AFTERWARDS,

+	  BECAUSE IT WILL BE INCREASED OR DECREASED AUTOMATICALLY, IT IS

+	  NECESSARY TO SET THE ADDRESS INTO THIS REGISTER BY THE CPU

+	  DIRECTLY.

+

+	FOLLOWING APPLY TO H-DMA ONLY:

+		HOWEVER, IF THE DATA WHICH IS TRANSFERED NEED TO BE CHANGED

+		BY FORCE, IT CAN BE DONE BY SETTING THE CPU MEMORY ADDRESS

+		TO THIS REGISTER. AND ALSO, THE ADDRESS OF THE CPU WHICH IS

+		ACCESSED CURRENTLY WILL BE CHANGED BY READING THIS REGISTER.

+

+

+ADDRESS  : $43XA (X: CHANNEL NUMBER 0-7)

+NAME     : NTRLX

+CONTENTS : THE NUMBER OF LINES TO BE TRANSFERED BY H-DMA›0;31;40m

+

+	D7	CONTINUE

+	D6-D0	NUMBER OF LINES TO BE TRANSFERED

+

+          THIS IS A REGISTER WHICH SHOWS NUMBER OF LINES FOR H-DMA TRANSFER

+	  (SEE APPENDIX-2)

+

+          THE NUMBER OF LINES WRITTEN TO THE CPU MEMORY WILL BE THE BASIC

+	  NUMBER OF LINE, IT IS NOT NECESSARY TO SET THE ADDRESS INTO

+          THIS REGISTER DIRECTLY.

+

+


+ 92 - 0
files/docs/snes/SNESMNEM.TXT

@@ -0,0 +1,92 @@
+add  add adress for all instruction fetches 
+adc  add memory to accumulator with carry 
+and  'and' memory with accumulator 
+asl  arithmic shift left 1 bit (memory or accumulator) 
+bcc  branch on carry clear C=0 
+bcs  branch on carry set C=1 
+beq  branch if equal Z=1 
+bit  bit test 
+bmi  branch if result is negative N=1 
+bne  branch if not equal Z=0 
+bpl  branch if result is plus N=0 
+bra  branch always 
+brk  force break 
+brl  branch always long 
+bvc  branch on overflow clear V=0 
+bvs  branch on overflow set V=1 
+clc  clear carry flag C=0 
+cld  clear decimal mode D=0 
+cli  clear interrupt disable bit I=0 
+clv  clear overflow flag V=0 
+cmp  compare memory and accumulator 
+cop  coprocessor 
+cpx  compare memory and index x 
+cpy  compare memory and index y 
+dec  decrement memory or accumulator by one 
+dex  decrement index x by one 
+dey  decrement index y by one 
+eor  exclusive 'or' memory with accumulator 
+inc  increment memory or accumulator by one 
+inx  increment index x by one 
+iny  increment index y by one 
+jml  jump long other banks possible 
+jmp  jump to location in same bank 
+jsl  jump to subroutine long 
+jsr  jump to subroutine in same bank 
+lda  load accumulator with memory 
+ldx  load index x with memory 
+ldy  load index y with memory 
+lsr  logical shift right by one bit (memory or accu) 
+mvn  move block negative (uses x,y,a) 
+mvp  move block positive (uses x,y,a) 
+nop  no operation 
+ora  'or' memory with accumulator 
+pea  push effective adres (or data) on stack 
+pei  push effective indirect adres on stack 
+per  push effective program counter relative adres on stack 
+pha  push accumulator on stack 
+phb  push data bank register on stack 
+phd  push direct register on stack 
+phk  push program bank register on stack 
+php  push processor status on stack 
+phx  push index register x on stack 
+phy  push index register y on stack 
+pla  pull accumulator from stack 
+plb  pull data bank register from stack 
+pld  pull direct register from stack 
+plp  pull processor status from stack 
+plx  pull index x from stack 
+ply  pull index y from stack 
+rep  reset processor status bits 
+rol  rotate left one bit (memory or accu) 
+ror  rorate right one bit (memory or accu) 
+rti  return from interrupt 
+rtl  return from subroutine long 
+rts  return from subroutine 
+sbc  subtract memory from accumulator with borrow 
+sec  set carry flag C=1 
+sed  set decimal mode D=1 
+sei  set interrupt disable status I=1 
+sep  set processor status bits 
+sta  store accumulator in memory 
+stp  stop the clock (only reset will help) 
+stx  store index x in memory 
+sty  store index y in memory 
+stz  store zero in memory 
+tad  (tcd) transfer accumulator to direct register 
+tas  (tcs) transfer accumulator to stack pointer register 
+tax  transfer accumulator to index x 
+tay  transfer accumulator to index y 
+tda  (tdc) transfer direct register to accumulator 
+trb  test and reset bit 
+tsa  (tsc) transfer stack pointer register to accumulator 
+tsb  test and set bit 
+tsx  transfer stack pointer register to index x 
+txa  transfer index x to accumulator 
+txs  transfer index x to stack pointer register 
+txy  transfer index x to index y 
+tya  transfer index y to accumulator 
+tyx  transfer index y to index x 
+wai  wait for interrupt 
+xba  exchange accumulator high and low 8 bits 
+xce  exchange carry and emulation bits 

+ 129 - 0
files/docs/snes/SNESMem.txt

@@ -0,0 +1,129 @@
+                      +=-=-=-=-=-=-=-=-=-=-=+
+                      | SNES Memory Mapping |
+                      |    By: ]SiMKiN[     |
+                      |         v2.0        |
+                      +=-=-=-=-=-=-=-=-=-=-=+
+
+
+• FastROM's can execute at 3.58Mhz
+• SlowROM's can only execute 2.68Mhz
+
+  • The SNES lets you access ROM through bank $00 onwards and bank 
+    $80 onwards such that locations $00:8000 and $80:8000 are congruent,
+    (they access the same locations.)
+  • When accessing bank $00 onwards the 65816 runs at 2.68Mhz. However, 
+    when accessing bank $80 onwards the 65816 can run at 2.68Mhz or 
+    3.58Mhz depending on how you set bit 0 of $420D.
+
+  • This Document Contains Information Regarding ROM's upto 32mbit.
+    If you have any information regarding ROM's above 32mbit please send
+    E-Mail to 'simkin@innocent.com'
+
++======================================================================+
+| Mode 20: LoROM Memory Model (32k Banks)                              |
+| ---------------------------------------                              |
+|  • $80-$ef : $8000-$ffff                                             |
+|              Mirrored to $00-6f                                      |
+|  • $f0-$ff : $8000-$ffff                                             |
++=========+=============+====================================+=========+
+| Bank    | Offset      | Definition                         | Shadow  |
++=========+=============+====================================+=========+
+| $00-$2f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | RESERVED                           | $00-$3f |
+|         | $8000-$ffff | (Mode 20 ROM)                      | ------- |
++---------+-------------+------------------------------------+---------+
+| $30-$3f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | RESERVED                           | ------- |
+|         | $8000-$ffff | (Mode 20 ROM)                      | $80-$bf |
++---------+-------------+------------------------------------+---------+
+| $40-$6f | $0000-$7fff | RESERVED                           | ------- |
+|         | $8000-$ffff | (Mode 20 ROM)                      | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $70-$77 | $0000-$ffff | (Mode 20 SRAM) 256KBytes           | ------- |
++---------+-------------+------------------------------------+---------+
+| $78-$7d | $0000-$ffff | RESERVED                           | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7e   | $0000-$1fff | LowRAM                             | $00-$3f |
+|         | $2000-$7fff | HighRAM                            | ------- |
+|         | $8000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7f   | $0000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+| $80-$ef | $0000-$ffff | Mirror of $00-$6f                  | $00-$6f |
++---------+-------------+------------------------------------+---------+
+| $f0-$ff | $0000-$7fff | RESERVED                           | ------- |
+|         | $8000-$ffff | (Mode 20 ROM)                      | ------- |
++=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
+
++======================================================================+
+| Mode 21: HiROM Memory Model (64k Banks)                              |
+| ---------------------------------------                              |
+|  • $C0-$ff : $0000-$ffff                                             |
+|              High Parts ONLY '($8000-$ffff)' are Shadowed to $00-3f  |
++=========+=============+====================================+=========+
+| Bank    | Offset      | Definition                         | Shadow  |
++=========+=============+====================================+=========+
+| $00-$2f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | RESERVED                           | $00-$3f |
+|         | $8000-$ffff | (Mode 21 ROM) from $C0-$EF         | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $30-$3f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | (Mode 21 SRAM) 256KBytes           | ------- |
+|         | $8000-$ffff | (Mode 21 ROM) from $C0-$EF         | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $40-$6f | $0000-$7fff | (Mode 21 ROM) from $C0-$EF         | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $70-$77 | $0000-$ffff | (Mode 20 SRAM) 256KBytes           | ------- |
++---------+-------------+------------------------------------+---------+
+| $78-$7d | $0000-$ffff | RESERVED                           | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7e   | $0000-$1fff | LowRAM                             | $00-$3f |
+|         | $2000-$7fff | HighRAM                            | ------- |
+|         | $8000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7f   | $0000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+| $80-$bf | $0000-$ffff | Mirror of $00-$3f                  | $00-$3f |
++---------+-------------+------------------------------------+---------+
+| $c0-$ff | $0000-$ffff | (Mode 21 ROM)                      | ------- |
++=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
+
+• ROM: The SNES ROM Image
+• RAM: The SNES Work Memory (WRAM)
+       LowRAM, HighRAM, & Expanded RAM 
+       All together = 128 Kilo-Bytes
+• SRAM: Save RAM (Extra RAM added by Cart)
+        The SNES only utilizes 256 Kilo-bits
+        However 256 Kilo-Bytes are provided.
+
+• APU: Audio Processing Unit
+       SPC700, Inside which has a DSP   
+• PPU: Picture Processing Unit
+       PPU1: 5c77-01
+       PPU2: 5c78-03
+
+• SFX: Super FX Cart Chip, by Nintendo
+• DSP: Digital Signal Processing Cart Chip
+       a.k.a. 'NEC mUPD77C25'
+
+• Shadow: "Congruent Bank".  Same meaning as Mirror.
+
+          _____________________________________________________
+       .o(_Thanx to: zsKnight, Lord Esnes, Y0SHi, and MintaBoo_)o.
+

+ 82 - 0
files/docs/snes/SNESMem2.txt

@@ -0,0 +1,82 @@
+                      +=-=-=-=-=-=-=-=-=-=-=+
+                      | SNES Memory Mapping |
+                      |    By: ]SiMKiN[     |
+                      |         v1.0        |
+                      +=-=-=-=-=-=-=-=-=-=-=+
+
+
+• LoROM: Mode 20
+• HiROM: Mode 21
+
+• FastROM's can execute at 3.58Mhz
+• SlowROM's can only execute 2.68Mhz
+
+  • The SNES lets you access ROM through bank $00 onwards and bank 
+    $80 onwards such that locations $00:8000 and $80:8000 are congruent,
+    (they access the same locations.)
+  • When accessing bank $00 onwards the 65816 runs at 2.68Mhz. However, 
+    when accessing bank $80 onwards the 65816 can run at 2.68Mhz or 
+    3.58Mhz depending on how you set bit 0 of $420D.
+
++=========+=============+====================================+=========+
+| Bank    | Offset      | Definition                         | Shadow  |
++=========+=============+====================================+=========+
+| $00-$2f | $0000-$1fff | LowRAM, each bank is shadowed      | $00-$3f |
+|         |             | From bank $7e                      |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | Reserved?                          | $00-$3f |
+|         | $8000-$ffff | (Mode 20, 21 - ROM)                | ------- |
++---------+-------------+------------------------------------+---------+
+| $30-$3f | $0000-$1fff | LowRAM, each bank is shadowed      | $00-$3f |
+|         |             | From bank $7e                      |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | (Mode 21 - SRAM) 256KBytes         | ------- |
+|         | $8000-$ffff | (Mode 20, 21 - ROM)                | ------- |
++---------+-------------+------------------------------------+---------+
+| $40-$6f | $0000-$7fff | (Mode 21 - ROM)                    | ------- |
+|         | $8000-$ffff | (Mode 20, 21 - ROM)                | ------- |
++---------+-------------+------------------------------------+---------+
+| $70-$77 | $0000-$ffff | (Mode 20, 21 - SRAM) 256KBytes     | ------- |
++---------+-------------+------------------------------------+---------+
+| $78-$7d | $0000-$ffff | Never Used                         | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7e   | $0000-$1fff | LowRAM                             | $00-$3f |
+|         |             | Shadowed to banks $00-$3f          | ------- |
+|         | $2000-$7fff | HighRAM                            | ------- |
+|         | $8000-$ffff | Expanded Ram                       | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7f   | $0000-$ffff | More Expanded RAM                  | ------- |
++---------+-------------+------------------------------------+---------+
+| $80-$ef | $0000-$ffff | Mirror of $00-$6f                  | $00-$6f |
++---------+-------------+------------------------------------+---------+
+| $f0-$ff | $0000-$ffff | (Mode 21 - ROM)                    | ------- |
++=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
+
+• ROM: The SNES ROM Image
+• RAM: The SNES Work Memory (WRAM)
+       LowRAM, HighRAM, & Expanded RAM 
+       All together = 128 Kilo-Bytes
+• SRAM: Save RAM (Extra RAM added by Cart)
+        The SNES only utilizes 256 Kilo-bits
+        However 256 Kilo-Bytes are provided.
+
+• APU: Audio Processing Unit
+       SPC700, Inside which has a DSP   
+• PPU: Picture Processing Unit
+       PPU1: 5c77-01
+       PPU2: 5c78-03
+
+• SFX: Super FX Cart Chip, by Nintendo
+• DSP: Digital Signal Processing Cart Chip
+       a.k.a. 'NEC mUPD77C25'
+
+• Shadow: "Congruent Bank". Same meaning as Mirror.
+
+          _________________________________________________
+       .o(_Thanx to: Y0SHi, zsKnight, MrGrim, and MintaBoo_)o.

+ 35 - 0
files/docs/snes/SNESROM.PIN

@@ -0,0 +1,35 @@
+Here's the pinout to a 4Mbit/*Mbit mask Rom used in SNES carts as I've
+deduced from various specs and actual testing.
+
+1	A17   ------\__/------	+5v	32	
+2	A18   |		     |	*OE	31
+3	A15			A19	30
+4	A12			A14	29
+5	A7			A13	28
+6	A6			A8	27
+7	A5			A9	26
+8	A4			A11	25
+9	A3			A16	24
+10	A2			A10	23
+11	A1			*CE	22
+12	A0			D7	21
+13	D0			D6	20
+14	D1			D5	19
+15	D2			D4	18
+16	GND  |---------------|	D3	17
+
+The design approximates std EPROM/SRAM pinouts except for the upper address
+lines (A16-A19), and OE which sits where VPP or PRGM usually is for an EPROM.
+This pinout approximates Fujitsu's tentative mask ROM pinouts (a package
+called GAMEMEDC.ZIP seems to base itself on this and is consequently wrong). 
+Nintendo uses Fujitsu chips in some carts, but from my testing and card-edge
+pinouts provided by other users, I conclude that Fujitsu must have modified
+the designs. 
+
+NOTE!: Card-edge pin #40, address line 15 (A15) is not used by any cart I've
+seen. And ROM pin #3 (see above) that I've determined to be A15 is connected
+to card-edge pin#41, labeled on many pinouts schems as A16..not A15!!!
+Would some one please verify this inconsistency.
+
+PS: How many Megabits can the Snes address?
+

+ 373 - 0
files/docs/snes/SNES_Lockout.txt

@@ -0,0 +1,373 @@
+
+             Disabling the Super NES/Super Famicom "Lockout Chip"
+             ====================================================
+			     (rev. 0.5 27-Dec-97)
+
+[Expert summary: disconnect CIC pin 4]
+
+This document is copyright © 1997 by Mark Knibbs <mark_k@iname.com>. The latest
+version, and several other console-related documents, should be available at:
+                  http://www.netcomuk.co.uk/~markk/index.html
+The direct URL for this file is:
+          http://www.netcomuk.co.uk/~markk/Consoles/SNES_Lockout.txt
+
+You are explicitly permitted to include the *unmodified* document on web sites,
+FTP sites and the like. But it is best to simply link to the document on my web
+page, as this means that you automatically pick up any changes made.
+
+If you have any comments, suggestions or questions about this document, please
+contact me. If you would like to perform a similar modification to your NES 8-
+bit console, you should see:
+           http://www.netcomuk.co.uk/~markk/Consoles/NES_Lockout.txt
+
+
+
+Revision History
+----------------
+0.1   27-Jul-97   First release.
+0.2   19-Aug-97   Added information about another PCB revision and the lockout
+                  chip used in U.S./Japanese consoles.Various other small
+                  changes.
+0.3   21-Aug-97   Added information about later model U.S. console (PCB
+                  revision SNS-CPU-GPM-01). Added section about removing a game
+                  pak with power on. Other minor changes.
+0.4   22-Sep-97   Changed email address and web URLs. Added "Possible
+                  Incompatibilities" section.
+0.5   27-Dec-97   Added step describing how to dissipate stored charge in the
+                  console before opening it. Added paragraph on precautions
+                  against static electricity. Added pointer to my SNES 50/60Hz
+                  modification document. Minor edits and changes.
+
+
+
+Introduction
+------------
+This document details a simple modification that you can perform on your Super
+NES or Super Famicom 16-bit video game console in order to disable the "lockout
+chip" protection system. The "lockout chip" system means that no PAL games can
+be played on an unmodified U.S. or Japanese console, or vice versa.
+
+If you have a PAL model Super NES, I strongly recommend that you also fit a
+switch to change between 50Hz and 60Hz modes. 60Hz mode runs games full-screen,
+at the correct speed (20% faster than the usual PAL speed). Additionally, more
+recent games (e.g. Super Mario All-Stars, Super Metroid) contain code to check
+for 60Hz. So it is not usually possible to run, say, the Japanese version of
+such a game on a PAL console. Details of this modification, and an accompanying
+picture, can be found at:
+                  http://www.netcomuk.co.uk/~markk/index.html
+
+
+The procedure given here should work for ANY model Super NES or Super Famicom,
+both NTSC and PAL versions. As of this writing I have only applied the
+modification to two UK model PAL Super NES consoles.
+
+Why might you want to do this? Well, I can think of a few reasons:
+· You own a PAL Super NES, and currently have to use a clumsy "universal
+  adapter" to be able to use American or Japanese games - with this
+  modification you are able to directly use Japanese cartridges, and can use
+  American games either by cutting a larger hole for the cartridge, or using
+  an extension adapter (you can use your old universal adapter for this - you
+  will no longer need to plug in the second "domestic" cartridge);
+· You own illicit or unlicensed games which can't be played on your console (I
+  have seen a counterfeit Street Fighter II cartridge which contains no lockout
+  chip, and thus normally requires that a universal adapter be used);
+· If you own an American model console, you can make it run almost every SNES
+  game by removing the tabs behind the cartridge slot, disabling the lockout
+  chip, and fitting a 50Hz/60Hz switch. If you have a PAL or Japanese console,
+  you will need to file away the cartridge slot in order to accomodate the
+  larger U.S. cartridges, if you want to be able to directly run every game.
+
+
+If you perform this procedure on your console, PLEASE LET ME KNOW WHETHER IT
+WORKS! I want to update this document so that it's applicable to as many
+consoles as possible. Please also tell me which PCB revision your console has
+(e.g. "SHVC-CPU-01"), the model (e.g. "SNS-001"), serial number, and the date
+code stamped on the label underneath (e.g. "9313"). I don't anticipate there
+being many relevant differences between different SNES models, though. I would
+welcome any comments you have about this document. Send them to the email
+address given above.
+
+
+If you are interested in the operation of the lockout chip and Nintendo's
+history in general, you might like to read David Sheff's book "Game Over", and
+consult U.S. patents 4,799,635 and/or 5,070,479. Indeed, I obtained the
+information necessary to carry out this modification from one of the patents.
+
+
+
+Background
+----------
+Before the NES was first released in the U.S.A., Nintendo developed a system
+for preventing the use of unauthorised software with it. Much counterfeit
+software had apparently been produced for their Famicom (Family Computer)
+system, and Nintendo wanted to avoid this happening for the NES.
+
+Another benefit (to Nintendo) of the system was that legal third-party
+development was severely hindered. Only Nintendo licensees could buy the
+lockout chips, one of which was fitted inside every game cartridge. Licensees
+were apparently charged around US$9 for each chip, in addition to having to pay
+steep royalties. Nintendo patented the lockout chip concept, and copyrighted
+the code contain within it.
+
+Nintendo also used the lockout system to provide "territorial protection". This
+means that you can't use a U.K. or European NES game in a U.S. console, for
+example.
+
+Nintendo used exactly the same system for the Super NES. American and Japanese
+consoles use identical lockout chips. You can run Japanese games on an American
+console by simply removing two plastic tabs from behind the cartridge slot.
+
+PAL versions of the Super NES use a different lockout chip. So PAL cartridges
+cannot be played on an American or Japanese machine, or vice versa. Many
+companies produced "universal adapters" to get around this problem. Typically,
+these have two cartridge slots. You put the foreign game in one, and a domestic
+game in the other. The adapter uses the lockout chip from the domestic game to
+enable the foreign game to be played.
+
+
+
+How the Lockout System Works
+----------------------------
+This is a very brief, simplified description. Consult Nintendo's patent for
+detailed information.
+
+Functionally identical chips are fitted in the console and inside every game
+cartridge. (For the SNES, the chips are packaged differently - the one inside
+the console is surface-mounted, and the one in game cartridges is usually a
+normal DIL package.)
+
+Depending on whether a certain pin (pin 4) of the chip is grounded or at +5V,
+the chip functions as either a lock or as a key. Inside the console, pin 4 of
+the lockout chip is at +5V (lock), and inside the game cartridge pin 4 is at 0V
+(key).
+
+When you switch on the console, the CPU and PPU chips are held in a reset
+state. The two lockout chips talk to each other. Since they are identical, they
+should be saying exactly the same thing at exactly the same time. Each chip
+compares its output with that of its counterpart. If they match, the lock chip
+releases the reset state of the console, and the game can start. The two chips
+still talk to each other, and if their outputs ever differ, the lock chip
+causes the console to reset, and the key chip (inside the game cartridge) may
+use the chip select lines of the cartridge ROM chips to disable the ROMs.
+
+The lockout chip is in fact a 4-bit microprocessor with its own internal ROM
+and RAM. The program it runs was called "10NES" for the NES version of the
+chip.
+
+
+
+How the Modification Works
+--------------------------
+This depends on changing the lock device to think that it's actually a key. If
+both devices are configured to be the same type (i.e., both keys), to quote
+Nintendo's patent "an unstable state takes place and no operations are
+performed at all." This means that the two chips will do nothing. So the
+console will not be reset, and the key device will not disable the cartridge
+ROM chips.
+
+To carry out the modification you need to disconnect pin 4 of the lockout chip,
+and connect this pin to ground (0V) instead. (In fact, it seems that you only
+need to disconnect the pin.)
+
+Whilst coming up with this method, I considered two other possible ways of
+achieving the result. I have not tried either of these, and I would be
+interested to hear if they work. If you feel like doing one of these, contact
+me for pinout information. The first involves connecting the lockout chip's
+input to its own output. Thus it may always think that its counterpart chip is
+present. The second involves simply disconnecting the chip's clock input.
+
+
+
+Performing the Modification
+---------------------------
+Whilst the modification is very simple, if you have not used a soldering iron
+before I suggest that you ask someone who has some experience with soldering
+and electronics in general to help you. Maybe your local TV repair person will
+be willing to do it for you, if you provide a copy of this document and a
+screwdriver for opening the Super NES case.
+
+Game consoles, in common with most modern electronic devices are VERY SENSITIVE
+TO STATIC ELECTRICITY. Ideally, wear a grounding strap and work on a conductive
+surface when modifying your console. Avoid wearing clothes containing man-made
+fibres, which are prone to static (e.g. nylon). As far as possible, avoid
+touching component leads or PCB tracks. Handle the board by its edges.
+
+Print out and read this document several times before opening your console.
+
+
+You will need the following:
+
+· A screwdriver suitable for opening the Super NES case. The screws are special
+  tamperproof screws, referred to as "System Zero" or "Line Head System". A
+  suitable screwdriver can be obtained from a company called MCM Electronics in
+  the USA (http://www.mcmelectronics.com/) or from RS Components in the UK.
+
+· A crosshead screwdriver suitable for removing some screws inside the Super
+  NES (a "No. 1" bit will be suitable).
+
+· A low power grounded soldering iron with a fine bit and some desoldering
+  braid.
+
+· A thin needle or similar implement.
+
+· A pair of sharp scissors.
+
+
+When removing screws, make sure you remember which type goes in which hole!
+Here are step-by-step instructions:
+
+ 1. Turn off the console and remove all leads attached to it (AC adapter,
+    controller, A/V lead, etc.). After doing this, turn the power switch on for
+    a couple of seconds and then off again. This dissipates any stored charge
+    inside; you may see the power LED light for a moment as you do this. IT IS
+    *VERY IMPORTANT* THAT YOU DO THIS! YOU RISK DAMAGING YOUR CONSOLE IF YOU
+    DO NOT!
+
+ 2. Turn the console upside-down, and remove the six screws from the base. Turn
+    it back over, and lift off the upper part of the case. Position the console
+    so that it is facing you.
+
+ 3. Remove the eject lever. Pull up the right-hand side of the metal rod and
+    slide it out, then remove the lever and spring.
+
+ 4. Remove the two screws which secure the power switch to the casing. Lift up
+    the switch so that you can get at the screw below.
+
+ 5. Gently remove the ribbon cable which leads to the controller socket PCB
+    from the connector at the front of the PCB.
+
+    You do not need to do this if you have a late revision console. You can
+    identify this by the fact that there are only two screws holding down the
+    shielding, and you can see that the ribbon cable does not interfere with
+    removal of the shielding.
+
+ 6. Now unscrew the metal shielding from in front of the cartridge slot. The
+    exact details of this step depend on which revision PCB your console has. I
+    will give specifics for the three variants that are known to me.
+
+    · For early consoles, which can be identified by the separate plug-in sound
+      module "SHVC-SOUND", there are six screws to remove from the shielding,
+      including the two which are on either side of the cartridge slot. (After
+      removing the shielding, you may see "SHVC-CPU-01" printed on the PCB if
+      you have a U.S. or Japanese console.)
+
+    · For later consoles, which have no separate sound module, there are four
+      screws to remove. (You may see "SNSP-CPU-02" printed on the PCB after
+      removing the shielding for a PAL console.)
+
+    · For still later consoles, there are two screws to remove. For this type
+      of console, there is no need to remove the controller ribbon cable. (You
+      may see "SNS-CPU-GPM-01" printed on the PCB after removing the shielding
+      for a U.S. model console.)
+
+ 7. Carefully lift up the metal shielding. The edges may be quite sharp. You
+    will see various chips. There is more than one type of SNES PCB. Earlier
+    models can be distinguished because the sound hardware is contained in a
+    separate plug-in module labelled "SHVC-SOUND" (towards the rear right of
+    the console). Later revisions integrated this onto the main PCB.
+
+    The position of the lockout chip depends on which kind of PCB your console
+    has. For a U.S. model console with separate sound module, PCB revision
+    "SHVC-CPU-01", the lockout chip is labelled U8 on the PCB, and says:
+				   F411
+				   © 1990
+				  Nintendo
+    It is located just behind the reset switch.
+
+    For a later revision PAL console with integrated sound, PCB revision
+    "SNSP-CPU-02", the lockout chip is labelled U8 on the PCB, and says:
+				   F413A
+				   © 1992
+				  Nintendo
+    It is located towards the front left of the PCB, near the power switch.
+
+    For a still later revision U.S. console, PCB revision "SNS-CPU-GPM-01", the
+    lockout chip is labelled U8 on the PCB, and says:
+				   F411A
+				   © 1990
+				  Nintendo
+    It is located behind and to the left of the reset switch.
+
+ 8. Locate pin 4 of the lockout chip. The pins at each corner are numbered on
+    the PCB. Just count along from pin 1 to find pin 4.
+
+ 9. Use the desoldering braid and soldering iron to remove some of the solder
+    from pin 4. It may help to cut the end of the braid into a "V" shape, so
+    that you don't inadvertently desolder any adjacent pins. Position the end
+    of the braid over where pin 4 meets the PCB, and briefly press down on this
+    with the soldering iron bit. You should see that some solder has been
+    "sucked into" the braid.
+    
+    Using the needle, apply a gentle levering action to the pin as you
+    momentarily touch the soldering iron to it. The pin should come away from
+    the PCB. Carefully pull it up using the tip of the needle as a lever, so
+    that the end is a couple of millimetres away from the PCB.
+
+10. That's it! You can optionally solder a short length of wire between pin 4
+    and 0V. Pin 9 of the lockout chip is at 0V, so you could connect these two
+    pins. Alternatively, you may wish to add a switch; see the "Possible
+    Incompatibilities" section below.
+
+11. It is a good idea to test the console before putting it back together. Rest
+    the power switch on its mounting and connect the AC adapter, controller,
+    video lead and a game pak. Switch the console on. If all has gone well, the
+    display should appear as usual. Turn the console off, and insert a foreign
+    game pak (i.e., a U.S. or Japanese game pak if you have a PAL console; PAL
+    game pak if you have a U.S. or Japanese console). Turn the console off and
+    remove all attachments (AC adapter, etc.). Turn the power switch on and
+    then off.
+
+12. Put the console back together. The procedure is the reverse of steps 2 to 7
+    above. You may find fitting the eject lever tricky. If so, put the metal
+    rod through the lever, and put the spring on the left end of this, so that
+    the outwards-pointing end of the spring is downwards. The outwards-pointing
+    end should be the longer of the two. Ease the spring and lever into
+    position, ensuring that the end of the spring goes into the recess in the
+    casing. Now carefully move the other end of the spring back until it is in
+    the recess in the lever.
+
+
+
+Possible Incompatibilities
+--------------------------
+A few very recent titles may be incompatible with this modification. One
+example is PAL "Street Fighter Alpha 2", used with a PAL SNES whose lockout
+chip has been disabled. The graphics were reported to be corrupted in some way.
+There is also reported to be more than one version of "Super Mario RPG", one of
+which may be incompatible.
+
+I know why this is. One explanation might be that Nintendo changed the lockout-
+related circuitry inside the cartridges, to detect the "deadlock" situation
+caused by disabling the console's lockout chip, and interfere with normal use
+of the game in this case.
+
+To solve this problem, and allow at least all domestic titles to be played, you
+can fit a DPST switch to pin 4 of the lockout chip. Connect the middle switch
+terminal to pin 4, and the other two terminals to +5V and ground respectively.
+Then, with the switch in one position the lockout chip will be disabled, and in
+the other it will operate as normal. Contact me if you are unsure of how to do
+this.
+
+
+
+At Your Own Risk!
+-----------------
+There are some interesting things which can be done now that the lockout chip
+is disabled. If you try the following, it is at your own risk. Be aware that
+removing a game pak while the console is on may damage your console or your
+game pak.
+
+If your SNES has an "eject prevention lever", you will have to try this before
+fitting the case back on. (To see whether your console has one, open the game
+pak shutter, and move the power switch. If you see a piece of plastic move out
+when the switch is in the "on" position, that is the eject prevention lever.
+Nintendo removed this from later U.S. models of the SNES, at least.)
+
+Plug in a game pak; "Street Fighter II" is a suitable one. Turn on the console,
+and wait until some music starts playing. Now carefully remove the game pak,
+without turning off the console first. You should find that the display blanks,
+but the music keeps playing until the end of the tune! This is because the
+sound processor has its own RAM, and the music code is loaded into this. So
+music continues to play even after removing the game pak.
+
+---

+ 302 - 0
files/docs/snes/SWC.TXT

@@ -0,0 +1,302 @@
+                
+                   E.V.O.L.U.T.I.O.N.   A.U.S.T.R.A.L.I.A.
+o                o        o
+               /\                /\      /\           ___o               ___o
+o_____________/  \_ _______o    /  \    /  \_________|   |____________o |   |
+\      __    /   / |\       \  /  ./  __\   \    _   \   |\       \   \ |  .|
+ \ \__/_/___/  ./  |/\  /\  .\/  o/  |  .\   \___\)  .) .|/\  /\   \ \ \|  o|
+ /\_______//  o/   /   / /  o/  O/___|  o|\   \  /  o/  o/   / /  o/ .\ \  O|
+/   /_/  O/  O/|  (   (_/  O/   /_)   ) O|_)   )/  O/|  (   (_/  O/  o|\    |
+\    ____/_________\   \___/_________/________//   / |___\_______/|  O| \___|
+_\   \______________\   \_____________________/   /               |   |______
+_________________________________________________/ Poise/RaZoR PC |__________
+
+   Presents : The Super Wild Card & Super Magicom Programmers Handbook.
+
+   Typed by : MicroChip/Evolution/Submission
+   
+   Call the Evolution WHQ on : Southern Cross BBS (SNES/MD/PC/AMIGA)
+                               --> +61-3-428-9359 (2 Nodes Ringdown)
+
+                                  
+ ***************************************************************************
+
+
+HardWare Specifcations & Features
+---------------------------------
+
+
+1) DRAM - 28Mega Bits Maximum Available
+2) SRAM - 256k (Battery Backup)
+3) ROM - 128k (Firmware)
+4) Floppy Drive Interface -
+   * Motorola MCS3201 Chip (NEC 765A Compatible)
+   * Compatible with IBM PC/AT & XT Disk Drive System
+   * Suports 3.5" & 5.25" Flopy Disk Drive.
+   * DB-25 Female Connector (non-standard)
+   * Supports only Non-DMA mode (polling)
+5) Parallel Port Interface -
+   * 8 bits input, 4 bits output, 1 bit handshake.
+   * DB-25 Female Connector
+   * Use Male to Male DB-25 Connector to connect to PC's Parallel Port
+6) Core Chip -
+   * Altera EP1810 Chip (First Generation)
+   * Front Far East FC9203 Chip (Currently Shipping)
+   * Front Far East FC9304 Chip (Not Avilable)
+7) Versions -
+   Ver.  Bios-Name   Core    Mode21   Saver   Description
+   'A'   Magicom     EP1810  No       Yes     External Drive
+   'B'   Wild Card   EP1810  Yes      Yes     External or Bulid-in DD
+   'C'   Wild Card   FC9203  Yes      Yes     External or Bulid-in DD
+   'D'   Wild Card   FC9304  Yes      Yes     (Under Development)
+   'E'   Wild Card   EP1810  Yes      No      Magic Drive Adapter
+   'F'   Wild Card   FC9203  Yes      No      Magic Drive Adapter
+
+
+SoftWare Specifications & Features
+----------------------------------
+
+1) Registers -
+
+   [Floppy Drive I/O]
+   C000R : Input Register
+           Bit 7 - MCS3201 IRQ Signal
+           Bit 6 - Drive 'Index' Signal (Disk Insert Check)
+   C002W : Digital Output Register
+   C004R : Main Status Register
+   C005RW: Data Register
+   C007R : Digital Input Register
+   C007W : Disk Control Register
+   * Consult the MCS3201 Data Sheet for more detailed information.
+
+   [Parallel I/O]
+   C008R : Bit 07 : Parallel Data Input (reading this register will
+                                         reverse the busy flag)
+   C008W : Bit 03 : Parallel Data Output
+           Bit 00 :  0=Mode 20, 1=Mode 21 (DRAM Mapping)
+           Bit 01 :  0=Mode 1, 1=Mode 2 (SRAM Mapping)
+
+   C009R : Busy Flag, Bit 7 (EP1810 Version)
+   C000R : Busy Flag, Bit 5 (FC9203 Version)
+
+   [Page Select]
+   E000W : Memory Page 0
+   E001W : Memory Page 1
+   E002W : Memory Page 2
+   E003W : Memory Page 3
+
+   [Mode Select]
+   E004W : System Mode 0 (Bios Mode, Power On Default)
+   E004W : System Mode 0 (Play Cartridge)
+   E004W : System Mode 0 (Cartridge Emulation 1)
+   E004W : System Mode 0 (Cartridge Emulation 2)
+
+   [Others]
+   
+   E008W : 44256 Dram Type (For 2,4,6,8 Mega Dram Card.
+   E009W : 441000 Dram Type (For 8,16,24,32 Mega Dram Card)
+
+   E00CW : Enable cartridge page mapping at A000FFF (Sys Mode 0)
+           Disable cartridge page mapping at bank 205F,A0 (Sys Mode 2,3)
+   E00DW : Enable SRAM page mapping at A000FFF (Sys Mode 0)
+           Enable cartridge mapping at Bank 205F,A0 (Sys Mode 2,3) 
+           
+   * The bank address of the above registers is 007D,80.
+   * The above registers are available only in System Mode 0 (BIOS Mode)
+   * [Mode Select] registers also available in System Mode 2.
+
+2) Memory Mapping -
+
+   [System Mode 0]
+   bb2000B3FFFRW : SRAM or Cartridge page mapping, bb=407D,C0 
+   bb8000B9FFFRW : DRAM page mapping, bb=007D,80
+   bbA000bBFFFRW : SRAM or Cartridge page mapping, bb=007D,90
+   bbC000W : I/O Registers, bb=007D,80 (Registers)
+   bbE000bFFFFR  : ROM Page mapping, bb=01 (Firmware)
+
+   * 1 Page = 8k Bytes, 1 Bank = 4 pages
+   * bb:000F = 4 Mega Bytes
+   * bb:001F = 8 Mega Bytes
+   * bb:002F = 12 Mega Bytes
+   * bb:003F = 16 Mega Bytes
+
+   [System Mode 1]
+   bb0000b7FFFR : Cartridge Mapping, bb=407D,C0 (Mode 21)
+   bb8000bFFFFR : Cartridge Mapping, bb=007d,80 (Mode 20,21)
+
+   [System Mode 2]
+   bb0000b7FFFR : DRAM Mapping, bb=407D,C00 (Mode 21)
+   bb8000BFFFFR : DRAM Mapping, bb=0070,800 (Mode 20,21)
+   70800070FFFFRW : SRAM Mode 1 Mapping
+   306000307FFFRW : SRAM Mode 2 Mapping, Page 0
+   316000317FFFRW : SRAM Mode 2 Mapping, Page 1
+   326000327FFFRW : SRAM Mode 2 Mapping, Page 2
+   336000337FFFRW : SRAM Mode 2 Mapping, Page 3
+
+   * bbE004bE007W : Mode Select Registers, bb=007D,80
+
+   [System Mode 3]
+   bb0000b7FFFR : DRAM Mapping, bb=406F,C0 (Mode 21)
+   bb8000BFFFFR : DRAM Mapping, bb=006F,80 (Mode 20,21)
+   70800070FFFFRW : SRAM Mode 1 Mapping
+   306000307FFFRW : SRAM Mode 2 Mapping, Page 0
+   316000317FFFRW : SRAM Mode 2 Mapping, Page 1
+   326000327FFFRW : SRAM Mode 2 Mapping, Page 2
+   336000337FFFRW : SRAM Mode 2 Mapping, Page 3
+
+   * Mode 21 - Even DRAM is mapped to bb0000b7FFF
+               Odd  DRAM is mapped to bb8000bFFFF
+
+
+3) Parallel I/O Protocol - 
+
+   [Protocol used in PC]
+                                 
+   * Byte Output procedure:
+       Wait Busy Bit = 1           Status Port Bit 7  (Hex n79,n7D)
+       Write One Bytes             Data Latch         (Hex n78,n7C)
+       Reverse Strobe bit          Control Port Bit 0 (Hex n7a,n7E)
+
+   * Byte Input procedure:
+       Wait Busy Bit = 0           Status Port Bit 7  (Hex n79.n7D)
+       Read Low 4 bits of byte     Status Port Bit 36 (Hex n79.n7D)
+       Reverse Strobe bit          Control Port Bit 0 (Hex n7A.n7E)
+       Wait Bust Bit = 0           Status PortBit 7   (Hex n79.n7D)
+       Read High 4 Bits of byte    Status Port Bit 36 (Hex n79.n7D)
+       Reverse Strobe Bit          Control Port Bit 0 (Hex n7A.n7E)
+
+    * 5 Types of Commands
+
+    * Command length = 9 bytes
+
+    * Command Format:
+      Byte 1  D5              ID Code 1
+      Byte 2  AA              ID Code 2
+      Byte 3  96              ID Code 3
+      Byte 4  00|01|04|05|06  Command Code
+      Byte 5  A1              Low Byte of Address
+      Byte 6  AH              High Bytes of Address
+      Byte 7  LL              Low Byte of Data Length
+      Byte 8  LH              High Byte of data Length
+      Byte 9  CC              Checksum = 81^Byte4^Byte5^Byte6^Byte7^Byte8
+     
+     * Command [00] : Download Data
+       a1,ah = Address
+       11,1h = Data Length
+       Output Data after Command
+     
+     * Command [01] : Upload Data
+       a1,ah = Address
+       11,1h = Data Length
+       Input Data after Command 
+       
+     * Command [04] : Force SFC Program to JMP  
+       a1,ah = address
+
+     * Command [05] : Set Memory Page Number
+       a1 Bit 1 = Page Number
+       a1 Bit27 + ah Bit 1 = Bank Number
+
+     * Command [06] : SUB Function
+       a1 = 0  Initial Device
+       a1 = 1  Play Game in DRAM
+       a1 = 2  Play Cartridge
+
+
+Password Format
+---------------
+
+1) Description -
+   Use the Data in the password to replace the data in the memory
+   at the offset address (according to the game file)
+
+2) Format 1 -
+   * Game Doctor Gold Finger Format
+   * 20 bits address space assigment
+   * 3 data bytes per string
+   * [Gaaaaaddddddccc]
+     'G'    = Means Game Doctor Format 
+     aaaaa  = Offser address of game file (Excluding 512 bytes header)
+     dddddd = 3 data Bytes (If the second ot the third data is '00',
+                            this means that the data is uncganged in
+                            the second of third byte)
+     ccc    = Checksum (Not used in SWC and SMC)
+
+3) Format 2 -
+   * 'FFE' Format
+   * 24 bit address space assigment
+   * 1 to 36 data bytes per string
+   * No Checksum
+   * [nnaaaaaadd....]
+     nn     = Data bytes length
+     aaaaaa = Offset Address of Game file (excluding 512 bytes header)
+     dd.... = nn Bytes data (Should be nn*2 Characters)
+
+File Header
+-----------
+
+1) Created by JSI/Front Far East
+
+2) 512 Bytes Length
+
+3) Byte
+    0   - Low Byte of 8k-Bytes page Counts
+    1   - High Byte of 8k-Bytes page Counts
+    2   - Emulation Mode Select
+          Bit 7 6 5 4 3 2 1
+              x             : 1=Run in Mode 0 (Jump $8000)
+                x           : 0=Last File of the Game (Multi-File)
+                  x         : 0=Mode 1, 1=Mode 2 (SRAM Mapping)
+                    x       : 0=Mode 20, 1=Mode 21 (DRAM Mapping)
+                        x   : 0=Run in Mode 3, 1=Run in Mode 2 (JMP Reset)
+                          x : 0=Disable, 1=Enable (external cartridge
+                              memory image at Bank 205F,A0 System Mode 2,3)
+    8   - File ID Code 1 (Should be 'AA')
+    9   - File ID Code 2 (Should be 'BB')
+    10  - Check this byte if ID 1 & 2 Match
+          02 : Magic Griffin Game File (PC Engine)
+          03 : Magic Griffin SRAM Data File
+          04 : SWC & SMC Game File (SNES)
+          05 : SWC & SMC Password, SRAM data, Saver Data File.
+          06 : SMD Game File (Megadrive)
+          07 : SMD SRAM Data File
+    37  - Reserved (Should be 00)
+    11511 - Reserved (Should be 00)
+
+
+  ****************************** The End ***********************************
+
+
+Personal Greetings go to:
+
+Ice/ATX - See ya at the Rave!
+Krayzi/PE - Stop pulling those pipes.
+Krimsym - See ya at Insanity!
+VIking Child/Submission - Use a condom next time!
+Ginnie/Razor - PC's RULE - NOT!
+TV & Revenger/Submission - Why an A4000?
+Poise/Razor - Where's my text screen??
+Itec/Submission - Lets get TCC going again? 
+Mixer/Mel - See ya at Kentucky!
+WormEater & RAM - Call my board!
+Kirk/Anthrox - How ya going Pete? Will Call ya soon!
+Mat - Speed kills - NOT!
+Choronzon - Let me see ya trade!
+Sweet Thing - Thanx for the support!
+Woody & Sandman - Call my bbs you lazy bastards.. hehe
+Cameo - I want a pre-release...
+Rotox - Call me..
+Mr. IRQ - Dove' il mio manuale?
+Jacknife - Thanx for the Support Dude!
+And to all my friends I have forgotten about coz I am tired!
+
+Group Greetings go to:
+
+Submission, Magical, Anthrox, Paradox, Razor, Fairlight, BSL, Elitendo, 
+PE, Quartex, Skid Row and to all others I missed! 
+
+NOTE: If any Australian's wish to purchase a Super Wild Card they are
+      asked to call (03) 883-0297 (24hour paging service)............
+
+
+

BIN
files/docs/snes/SWC.ZIP


+ 1216 - 0
files/docs/snes/Sneskart.txt

@@ -0,0 +1,1216 @@
+                               SNES Kart v1.6
+           The most complete guide to a SNES cartridge worldwide
+
+                            .                 .
+
+                              ______ ______ .
+
+                           .:_\_ .  \\_ .__\_::.
+
+                        . .::./ ./  // ./__ .:::. .
+
+                           :_<_____/<______>_:.
+
+                           .                 .
+
+                       Damaged Cybernetics Australia
+
+      It is a crime to redistribute this document in a commercial
+
+      venture of any kind without permission or a licensing agreement.
+
+      Contact us via email for more information on licensing.
+
+      This is freely distributable for non-commercial use, however we
+
+      require that you acknowledge the following:
+
+   SNES Kart 1.6 Copyright (c) 1995-1996 DiskDude. All rights reserved.
+
+                                  [Image]
+
+None of the information contained in this text comes from any confidential
+source. It was obtained from various sources on the Internet, but also the
+product of my own investigation. Refer to the Acknowledgements section at
+the end of this text.
+
+Use this information for your own use, I will not take any responsibility
+for your actions. All copyrights and trademarks are owned by their
+respective owners, even if not acknowledged, no infringements intended.
+
+I wrote this because all of this information is scattered in small files
+everywhere, if existing at all, most of it outdated. This is an attempt to
+conveniently bring all of the information to one place, and as up-to-date
+as possible. If you find this useful, tell me! I love positive feedback.
+
+                                  Contents
+
+ Pin Layouts                            Cheat Device Decoding
+
+    * What is the cartridge pin            * Pro Action Replay (hardware)
+      layout?                              * Gold Finger (software)
+    * What is the ROM pin layout?          * Game Genie (hardware)
+    * What is the DSP1 pin layout?         * Converting between CPU
+    * What is the MAD-1 and its pin          addresses and ROM addresses
+      layout?                              * Easily converting between
+    * What is the pin layout of the          codes
+      16kbit SRAM most commonly used
+      by Nintendo?                      SNES Copiers
+
+ Cartridge Addressing Schemes              * What are copiers?
+                                           * Super Wild Card (SWC) header
+    * LoROM cartridges                       information
+    * HiROM cartridges                     * Pro Fighter (FIG) header
+                                             format
+ Embedded Cartridge Information            * Game Doctor file name format
+                                           * Super Wild Card parallel port
+    * Game title (21 bytes)                  I/O protocol
+    * ROM makeup (1 byte)
+    * ROM type (1 byte)                 ROM Protection Schemes
+    * ROM size (1 byte)
+    * SRAM size (1 byte)                   * SlowROM checks
+    * Country (1 byte)                     * PAL/NTSC checks
+    * License (1 byte)                     * SRAM size checks
+    * Game Version (1 byte)
+    * Inverse ROM Checksum (2 bytes)    IPS Patch Format
+    * ROM Checksum (2 bytes)
+    * Non Maskable Interrupt / VBL      Acknowledgements
+      Vector (2 bytes)
+    * Reset Vector (2 bytes)
+    * How do I know if the ROM is
+      HiROM or LoROM?
+
+                                Pin Layouts
+
+What is the cartridge pin layout?
+
+If the SNES doesn't detect the CIC while power is on, then it will not
+continue to read the cartridge. Further details of this are not known to
+me.
+
+               Super FX   01   32
+
+                          02   33
+
+                          03   34
+
+                          04   35
+
+                    GND   05   36   GND
+
+F                   A11   06   37   A12
+
+r                   A10   07   38   A13
+
+o                    A9   08   39   A14
+
+n                    A8   09   40   A15
+
+t                    A7   10   41   BA0
+
+                     A6   11   42   BA1
+
+o                    A5   12   43   BA2
+
+f                    A4   13   44   BA3
+
+                     A3   14   45   BA4
+
+c                    A2   15   46   BA5
+
+a                    A1   16   47   BA6
+
+r                    A0   17   48   BA7
+
+t                  /IRQ   18   49   /CS
+
+                     D0   19   50   D4
+
+                     D1   20   51   D5
+
+                     D2   21   52   D6
+
+                     D3   22   53   D7
+
+                    /RD   23   54   /WR
+
+      CIC out data (p1)   24   55   CIC out data (p2)
+
+       CIC in data (p7)   25   56   CIC in clock (p6)
+
+                  RESET   26   57   nc
+
+                    Vcc   27   58   Vcc
+
+                          28   59
+
+                          29   60
+
+                          30   61
+
+             Left audio   31   62   Right audio
+
+LoROM:    32kbyte pages/banks (A15 not used - assumed high)
+
+HiROM:    64kbyte pages/banks
+
+BA0-BA7 switch between a possible 256 banks/pages.
+
+LoROM data is stored in the upper 32kbytes of the possible 64kbyte
+bank/page (A15 is assumed high). Using 64kbyte pages, the SNES can address
+a huge 16Mbytes or 128Mbits!
+
+According to a SNES memory map, LoROM games can be as large as 16Mbit while
+HiROM games are limited to 32Mbit... what about the 48Mbit game floating
+around?
+
+What is the ROM pin layout?
+
+This pin layout was taken from a Donkey Kong Country 2 cartridge and seems
+to be consistent with all their mask ROMs (some are 32pin, others 36pin).
+
+               A20             Vcc
+
+               A21             A22
+
+               A17   01   32   Vcc
+
+               A18   02   31   /OE
+
+               A15   03   30   A19
+
+               A12   04   29   A14
+
+                A7   05   28   A13
+
+                A6   06   27   A8
+
+                A5   07   26   A9
+
+                A4   08   25   A11
+
+                A3   09   24   A16
+
+                A2   10   23   A10
+
+                A1   11   22   /CS
+
+                A0   12   21   D7
+
+                D0   13   20   D6
+
+                D1   14   19   D5
+
+                D2   16   18   D4
+
+               Vss   16   17   D3
+
+What is the DSP1 pin layout?
+
+This was taken from a hacked Pilotwings cartridge with a switch on it -
+possibly to select between HiROM and LoROM DSP1 games. I'm not 100% sure
+that the following is correct or complete though.
+
+               Vcc   01   28   Vcc
+
+               Vcc   02   27   A14 (A12 - used for HiROM?)
+
+                nc   03   26   /CS
+
+                nc   04   25   /RD
+
+                nc   05   24   /WR
+
+                D0   06   23   ?
+
+                D1   07   22   ?
+
+                D2   08   21   Vcc
+
+                D3   09   20   Vcc
+
+                D4   10   19   Vcc
+
+                D5   11   18   Vcc
+
+                D6   12   17   GND
+
+                D7   13   16   /RESET (inverted RESET- SNES slot)
+
+                D8   14   15   CLOCK?
+
+If you can verify/correct this, it would be greatly appreciated.
+
+What is the MAD-1 and its pin layout?
+
+The MAD-1 stands for Memory Address Decoder revision 1. It is used on the
+Donkey Kong Country (1 and 2) cartridge and possibly other cartridges in
+order to address one or two ROMs and a static RAM.
+
+               /HI   01   16   /LO
+
+               /SE   02   15   A13
+
+                     03   14   A14
+
+               /RE   04   13   BA5
+
+               Vcc   05   12   A15
+
+               Vcc   06   11   /CS (p49 SNES slot)
+
+               Vcc   07   10   Vcc
+
+               GND   08   09   RESET (p26 SNES slot)
+
+/RE - /CS on a 32Mbit ROM (possibly for MAD-1a only)
+
+/LO - /CS on ROM1 (lower 16mbit)
+
+/HI - /CS on ROM2 (upper 16mbit)
+
+/SE - /CS on Static RAM
+
+What is the pin layout of the 16kbit SRAM most commonly used by Nintendo?
+
+It seems that Nintendo uses this SRAM in many of their games, mainly
+because it is very cheap, only $A5 (retail) - much cheaper for Nintendo who
+buys millions of them. It can address up to 2048 bytes or 16kbits.
+
+                A7   01   24   Vcc
+
+                A6   02   23   A8
+
+                A5   03   22   A9
+
+                A4   04   21   /WE
+
+                A3   05   20   /OE
+
+                A2   06   19   A10
+
+                A1   07   18   /CS
+
+                A0   08   17   D7
+
+                D0   09   16   D6
+
+                D1   10   15   D5
+
+                D2   11   14   D4
+
+               Vss   12   13   D3
+
+                        Cartridge Addressing Schemes
+
+    LoROM cartridges:                HiROM cartridges:
+
+    read ROM   /RD, /CS, RESET low   read ROM   /CS, /RD, RESET low
+
+               /WR high                         /WR high
+
+    read SRAM  /CS, /RD low          read SRAM  /RD low
+
+               RESET, /WR high                  RESET, /WR, /CS high
+
+               A15, BA4, BA5 high               A13, A14, BA5 high
+
+    write SRAM /CS, /WR low          write SRAM /WR low
+
+               RESET, /RD high                  RESET, /RD, /CS high
+
+               A15, BA4, BA5 high               A13, A14, BA5 high
+
+Would anyone like to verify this?
+
+                       Embedded Cartridge Information
+
+Most of the information in this section was obtained from Mindrape's SNES
+ROM, available from http://www.futureone.com/~damaged/.
+
+All values are in decimal unless specified with a trailing 'h'.
+
+The starting offset for this information is located at the end of the first
+page:
+
+LoROM: offset 32704
+
+HiROM: offset 65472
+
+Game title (21 bytes)
+
+The title is in upper case on most games.
+
+ROM makeup (1 byte)
+
+Upper nibble (4 bits):
+
+Value ROM speed
+
+  0   SlowROM (200ns)
+
+  3   FastROM (120ns)
+
+Lower nibble (4 bits):
+
+Value Bank size
+
+  0   LoROM (32kb banks)
+
+  1   HiROM (64kb banks)
+
+ROM type (1 byte)
+
+Byte ROM type
+
+ 0   ROM only
+
+ 1   ROM and RAM
+
+ 2   ROM and Save RAM
+
+ 3   ROM and DSP1 chip
+
+ 4   ROM, RAM and DSP1 chip
+
+ 5   ROM, Save RAM and DSP1 chip
+
+ 19  ROM and Super FX chip
+
+227  ROM, RAM and GameBoy data
+
+246  ROM and DSP2 chip
+
+ROM size (1 byte)
+
+Byte ROM size
+
+ 8    2 MegaBits
+
+ 9    4 MegaBits
+
+ 10   8 MegaBits
+
+ 11  16 MegaBits
+
+ 12  32 MegaBits
+
+At the time of writing, the largest SNES game is 48Mbit, while 8Mbit
+cartridges are the most common. There are cartridge sizes of 10Mbit,
+12Mbit, 20Mbit and 24Mbit, which are reported as 16Mbit, 16Mbit, 16Mbit and
+32Mbit respectively.
+
+Another way of calculating the ROM size is: 1 shl (ROMbyte-7) MegaBits
+
+SRAM size (1 byte)
+
+Byte SRAM size
+
+ 0   (none)
+
+ 1   16 KiloBits
+
+ 2   32 KiloBits
+
+ 3   64 KiloBits
+
+64 KiloBit SRAM's are the largest Nintendo uses (except DOOM?), while most
+copiers have 256 kiloBits on-board.
+
+Another way of calculating the SRAM size is: 1 shl (SRAMbyte+3) KiloBits
+
+Country (1 byte)
+
+Byte Country                               Video system
+
+ 0   Japan                                 NTSC
+
+ 1   USA                                   NTSC
+
+ 2   Australia, Europe, Oceania and Asia   PAL
+
+ 3   Sweden                                PAL
+
+ 4   Finland                               PAL
+
+ 5   Denmark                               PAL
+
+ 6   France                                PAL
+
+ 7   Holland                               PAL
+
+ 8   Spain                                 PAL
+
+ 9   Germany, Austria and Switzerland      PAL
+
+ 10  Italy                                 PAL
+
+ 11  Hong Kong and China                   PAL
+
+ 12  Indonesia                             PAL
+
+ 13  Korea                                 PAL
+
+License (1 byte)
+
+ Byte Company                             Byte Company
+
+  1   Nintendo                            131  Lozc
+
+  3   Imagineer-Zoom                      132  Koei
+
+  5   Zamuse                              134  Tokuma Shoten Intermedia
+
+  6   Falcom                              136  DATAM-Polystar
+
+  8   Capcom                              139  Bullet-Proof Software
+
+  9   HOT-B                               140  Vic Tokai
+
+  10  Jaleco                              142  Character Soft
+
+  11  Coconuts                            143  I''Max
+
+  12  Rage Software                       144  Takara
+
+  14  Technos                             145  CHUN Soft
+
+  15  Mebio Software                      146  Video System Co., Ltd.
+
+  18  Gremlin Graphics                    147  BEC
+
+  19  Electronic Arts                     149  Varie
+
+  21  COBRA Team                          151  Kaneco
+
+  22  Human/Field                         153  Pack in Video
+
+  23  KOEI                                154  Nichibutsu
+
+  24  Hudson Soft                         155  TECMO
+
+  26  Yanoman                             156  Imagineer Co.
+
+  28  Tecmo                               160  Telenet
+
+  30  Open System                         164  Konami
+
+  31  Virgin Games                        165  K.Amusement Leasing Co.
+
+  32  KSS                                 167  Takara
+
+  33  Sunsoft                             169  Technos Jap.
+
+  34  POW                                 170  JVC
+
+  35  Micro World                         172  Toei Animation
+
+  38  Enix                                173  Toho
+
+  39  Loriciel/Electro Brain              175  Namco Ltd.
+
+  40  Kemco                               177  ASCII Co. Activison
+
+  41  Seta Co.,Ltd.                       178  BanDai America
+
+  45  Visit Co.,Ltd.                      180  Enix
+
+  49  Carrozzeria                         182  Halken
+
+  50  Dynamic                             186  Culture Brain
+
+  51  Nintendo                            187  Sunsoft
+
+  52  Magifact                            188  Toshiba EMI
+
+  53  Hect                                189  Sony Imagesoft
+
+  60  Empire Software                     191  Sammy
+
+  61  Loriciel                            192  Taito
+
+  64  Seika Corp.                         194  Kemco
+
+  65  UBI Soft                            195  Square
+
+  70  System 3                            196  Tokuma Soft
+
+  71  Spectrum Holobyte                   197  Data East
+
+  73  Irem                                198  Tonkin House
+
+  75  Raya Systems/Sculptured Software    200  KOEI
+
+  76  Renovation Products                 202  Konami USA
+
+  77  Malibu Games/Black Pearl            203  NTVIC
+
+  79  U.S. Gold                           205  Meldac
+
+  80  Absolute Entertainment              206  Pony Canyon
+
+  81  Acclaim                             207  Sotsu Agency/Sunrise
+
+  82  Activision                          208  Disco/Taito
+
+  83  American Sammy                      209  Sofel
+
+  84  GameTek                             210  Quest Corp.
+
+  85  Hi Tech Expressions                 211  Sigma
+
+  86  LJN Toys                            214  Naxat
+
+  90  Mindscape                           216  Capcom Co., Ltd.
+
+  93  Tradewest                           217  Banpresto
+
+  95  American Softworks Corp.            218  Tomy
+
+  96  Titus                               219  Acclaim
+
+  97  Virgin Interactive Entertainment    221  NCS
+
+  98  Maxis                               222  Human Entertainment
+
+ 103  Ocean                               223  Altron
+
+ 105  Electronic Arts                     224  Jaleco
+
+ 107  Laser Beam                          226  Yutaka
+
+ 110  Elite                               228  T&ESoft
+
+ 111  Electro Brain                       229  EPOCH Co.,Ltd.
+
+ 112  Infogrames                          231  Athena
+
+ 113  Interplay                           232  Asmik
+
+ 114  LucasArts                           233  Natsume
+
+ 115  Parker Brothers                     234  King Records
+
+ 117  STORM                               235  Atlus
+
+ 120  THQ Software                        236  Sony Music Entertainment
+
+ 121  Accolade Inc.                       238  IGS
+
+ 122  Triffix Entertainment               241  Motown Software
+
+ 124  Microprose                          242  Left Field Entertainment
+
+ 127  Kemco                               243  Beam Software
+
+ 128  Misawa                              244  Tec Magik
+
+ 129  Teichio                             249  Cybersoft
+
+ 130  Namco Ltd.                          255  Hudson Soft
+
+Game Version (1 byte)
+
+The version is stored as version 1.VersionByte and must be less than 128.
+i.e. Less than 1.128.
+
+Inverse ROM Checksum (2 bytes)
+
+This is the same as XORing the two checksum bytes. i.e. The checksum bits
+are inversed.
+
+ROM Checksum (2 bytes)
+
+The checksum is a 16bit word with the lower 8bits stored first, followed by
+the upper 8bits.
+
+The checksum is calculated by dividing the ROM into 4Mbit chunks then
+adding all the bytes in these chunks together. Once you have the checksum
+for each chunk, add them together and take the lower 32bits of the result.
+
+With a non-standard image size, you do not get it equally divisible by
+4Mbit (excluding 2Mbit images). e.g. 10Mbit = 4Mbit + 4Mbit + 2Mbit chunks.
+
+Therefore, you must create a 4Mbit chunk from what is left over. Using the
+same example, you would add the checksum of the following chunks to get the
+ROM checksum:
+
+                      4Mbit + 4Mbit + (2Mbit + 2Mbit)
+                                     or
+                        4Mbit + 4Mbit + (2 x 2Mbit)
+
+Non Maskable Interrupt / VBL Vector (2 bytes)
+
+LoROM: at offset 33274
+
+HiROM: at offset 66042
+
+Reset Vector (2 bytes)
+
+Where to start the ROM code.
+
+LoROM: at offset 33276
+
+HiROM: at offset 66042 [correction by Qwertie: 66044?]
+
+How do I know if the ROM is HiROM or LoROM?
+
+When you OR the checksum bytes of a disk image and the inverse checksum
+bytes, the result should be FFFF hex. Therefore, to detect whether an image
+is HiROM or LoROM, you must read those bytes, OR them, and see if they
+equal FFFF hex.
+
+The ROM's type depends at which location the OR'd bytes equal FFFF hex. If
+it isn't found at either location, then the other way of checking is to see
+at which location the title contains uppercase alphanumeric characters.
+(But this fails with most Japanese cartridges)
+
+Why don't you use the ROM Makeup Byte? You can, and some utilities do, but
+some utilities allow you to change this byte, so incorrect results may
+occur.
+
+For the actual ROM, the embedded cartridge information is stored at the
+same position for both LoROM and HiROM. In this case, you must use the ROM
+Makeup Byte or read a 64kb page and see if both 32kb chunks (upper and
+lower 32kb) are the same. If they are the same, it is LoROM (32kb pages -
+A15 is not used, the data repeats itself) otherwise it is HiROM.
+
+As a general rule of thumb, if you can't detect which ROM type it is,
+default to LoROM, as these are the most common of cartridges.
+
+                           Cheat Device Decoding
+
+We'll start with the easiest first then work our way down. These codes work
+by replacing a byte at a specific location in the ROM.
+
+E.g. In the game F-Zero, at a particular position in the ROM, there is a
+number 3 indicating 3 lives to start off with. What a cheat code will do is
+replace this byte with, let's say, the number 9, so now when the game is
+run, the player starts off with 9 lives.
+
+Pro Action Replay (hardware)
+
+Code format:        AAAAAADD            (8 digits)
+
+A - Address
+
+D - Data
+
+These codes are in Hex, the address being a CPU address, not a direct ROM
+location (more about this later).
+
+Gold Finger (software)
+
+Code format:        AAAAADDDDDDCCW      (14 digits)
+
+A - Address
+
+D - Data
+
+C - Checksum
+
+W - What to change (DRAM or SRAM)
+
+This code was designed for the copiers, and are straight Hex characters.
+Therefore the Address is a ROM address, not a CPU address. Data bytes are
+arranged in 2 characters (2 D's per byte), which allows for 3 bytes. If a
+byte is not being used, it is denoted by 'XX'. I have never seen a code
+with three unused bytes - what's the point of one anyhow?
+
+The address (A's) is a base address. The first data byte (D's) is to be
+placed at this address. The second at address+1, the third at address+2 (if
+to be used, that is, if they are not 'XX').
+
+To calculate the checksum you must take the A's and D's, add a zero (0) to
+the front of the shortened code, then divide into block's of 2 hex digits
+(bytes). Add these hex digits together (2 characters per hex digit) then
+minus 160 hex (352 decimal). Now AND this number by FF hex (255 decimal) to
+get the lower 8 bits (byte). Convert this number to hex and you have your
+checksum (C's).
+
+W tells the copier whether to replace the byte in the DRAM (ROM image) or
+the SRAM (Saved game static RAM) of the copier.
+
+Value of W  Where to place byte
+
+    0       DRAM (ROM image)
+
+    1       SRAM (Saved game image)
+
+The rec.games.video FAQ specifies that there may be non- standard values of
+2, 8, A, C, F for W, which may be converted to 0. I personally have only
+seen Gold Finger codes with W = 0.
+
+Game Genie (hardware)
+
+Code format:        DDAA-AAAA      (8 digits)
+
+A - Address
+
+D - Data
+
+This is the most difficult code to decipher out of the lot. It is as
+follows:
+
+First take the code in the form xxxx-xxxx and take out the dash ('-') to
+form xxxxxxxx. Convert these characters (Genie Hex) to normal hex
+characters using the following table:
+
+Genie Hex:    D  F  4  7  0  9  1  5  6  B  C  8  A  2  3  E
+
+Normal  Hex:  0  1  2  3  4  5  6  7  8  9  A  B  C  D  E  F
+
+The first two characters is the data byte in Hex. Now take the other 6
+following characters (encoded address) and put it into it's binary form of
+24 bits.
+
+Now take each bit of the encoded address and rearrange to form the real
+address:
+
+24bit encoded address: ijklqrst opabcduv wxefghmn
+
+8bit encoded data:     ABCDEFGH
+
+Rearrange as:
+
+24bit address             : 8bit data
+
+abcdefgh ijklmnop qrstuvwx: ABCDEFGH
+
+MSB                    LSB  MSB  LSB
+
+Bit 23 of the encoded address (bit 15 of the real address) is always 1. The
+reason being that the SNES CPU address must be 1 for it to access the ROM.
+
+Converting between CPU addresses and ROM addresses
+
+This is very easy once you understand how it is done. To convert from a CPU
+address to a ROM address, all you need to do is remove bit 15. By doing
+this, I don't mean just setting it to 0. I mean by removing it, then moving
+all bits after it down one.
+
+e.g. ROMaddress = (CPUaddress and 7FFFh) or ((CPUaddress and FF0000h) shl 1)
+
+Therefore, to convert from a ROM address to a CPU address, you must insert
+a high bit into position 15 (bit 15).
+
+e.g. CPUaddress = (ROMaddress and 7FFFh) or ((ROMaddress and 7F8000h) shr 1) or 8000h
+
+Easily converting between codes
+
+I have made available two DOS programs with source code on my WWW pages
+which allow you to convert between Game Genie and Gold Finger codes. These
+are available freely from http://www.parodius.com/~diskdude/CartDisk/.
+
+Note: Because the Gold Finger can only address upto 8Mbit of game data,
+while other codes can address upto 64Mbit of game data, some Game Genie and
+Action Replay codes may not be converted to Gold Finger.
+
+                                SNES Copiers
+
+What are copiers?
+
+A copier is a device which sits on top of the SNES and allows you to backup
+your cartridges as well as play your backed up games. It does this by
+storing the ROM image of a cartridge to floppy disks via a 1.44Mb disk
+drive. Most copiers also include a parallel PC port interface, allowing
+your PC to control the unit and store images on your hard drive.
+
+Copier's contain DRAM from 1 Megabyte to 16 Megabytes, 8MegaBits to
+128MegaBits respectively. This is the reason why they are so expensive.
+
+It is legal to own and use a copier for your own personal backup of
+cartridges which you legally own in this point in time, although it is
+illegal to distribute this copy (only one copy is allowed). This may vary
+depending on where you live.
+
+If you wish to make your own "home brew" copier for the SNES, and other
+consoles, more information can be found at
+http://www.parodius.com/~diskdude/CartDisk/.
+
+Super Wild Card (SWC) header information
+
+The SWC (Super Wild Card) image format consists of a 512 byte header. It's
+layout is as follows (set unused bytes to 00h):
+
+Offset Function
+
+  0    Lower 8 bits of size word
+
+  1    Upper 8 bits of size word
+
+  2    Image information byte
+
+  8    SWC header identifier (set to AAh)
+
+  9    SWC header identifier (set to BBh)
+
+ 10    SWC header identifier (set to 04h)
+
+The size word is calculated by multiplying the image size, not game size
+(in MegaBits) by 16. e.g. Image is 4 Mbits, so size word would be 4*16=64.
+
+Image information byte (in the form of 76543210):
+
+Bit  Description
+
+7    1 - Run program in Mode 0 (JMP $8000)
+
+     0 - Run program in Mode 1 (JMP RESET Vector)
+
+6    1 - Multi image (there is another split file to follow)
+
+     0 - Not multi image (no more split files to follow)
+
+5    1 - SRAM memory mapping Mode 21 (HiROM)
+
+     0 - SRAM memory mapping Mode 20
+
+4    1 - DRAM memory mapping Mode 21 (HiROM)
+
+     0 - DRAM memory mapping Mode 20
+
+3/2  00: 256kbit SRAM
+
+     01: 65kbit SRAM
+
+     10: 16kbit SRAM
+
+     11: no SRAM
+
+1/0  reserved
+
+Pro Fighter (FIG) header format
+
+This format is similar to the SWC. It consists of a 512byte header who's
+layout is as follows (set unused bytes to 00h):
+
+Offset Function
+
+  0    Lower 8 bits of size word
+
+  1    Upper 8 bits of size word
+
+  2    40h - Multi image
+
+       00h - Last image in set (or single image)
+
+  3    80h - if HiROM
+
+       00h - if LoROM
+
+  4    If using DSP1 microchip:
+
+           FDh - If using SRAM (SRAM size>0)
+
+           47h - If no SRAM (SRAM size=0)
+
+       77h - If not using DSP1 and no SRAM (SRAM size=0)
+
+  5    If using DSP1 microchip:
+
+           82h - If using SRAM (SRAM size>0)
+
+           83h - If no SRAM (SRAM size=0)
+
+       83h - If not using DSP1 and no SRAM (SRAM size=0)
+
+Game Doctor file name format
+
+The Game Doctor does not use a 512 byte header like the SWC, instead it
+uses specially designed filenames to distinguish between multi files. I'm
+not sure if it used the filename for information about the size of the
+image though.
+
+Usually, the filename is in the format of: SFXXYYYZ.078
+
+Where SF means Super Famicon, XX refers to the size of the image in Mbit.
+If the size is only one character (i.e. 2, 4 or 8 Mbit) then no leading "0"
+is inserted.
+
+YYY refers to a catalogue number in Hong Kong shops identifying the game
+title. (0 is Super Mario World, 1 is F- Zero, etc). I was told that the
+Game Doctor copier produces a random number when backing up games.
+
+Z indicates a multi file. Like XX, if it isn't used it's ignored.
+
+A would indicate the first file, B the second, etc. I am told 078 is not
+needed, but is placed on the end of the filename by systems in Asia.
+
+e.g. The first 16Mbit file of Donkey Kong Country (assuming it is cat. no.
+475) would look like: SF16475A.078
+
+Super Wild Card parallel port I/O protocol
+
+I was given this information a while ago. It is supposed to be direct from
+the company which makes SWC's and I have included this information because
+a few people have been asking for it. If you have similar information for
+other backup devices, it would be appreciated if you could send it to me.
+
+      [PROTOCOL USED IN PC]
+
+      * BYTE OUTPUT PROCEDURE
+
+          WAIT BUSY BIT = 1           STATUS PORT BIT7   (HEX n79, n7D)
+
+          WRITE ONE BYTE              DATA LATCH         (HEX n78, n7C)
+
+          REVERSE STROBE BIT          CONTROL PORT BIT0  (HEX n7A, n7E)
+
+      * BYTE INPUT PROCEDURE
+
+          WAIT BUSY BIT = 0           STATUS PORT BIT7   (HEX n79, n7D)
+
+          READ LOW 4 BITS OF BYTE     STATUS PORT BIT3-6 (HEX n79, n7D)
+
+          REVERSE STROBE BIT          CONTROL PORT BIT0  (HEX n7A, n7E)
+
+          WAIT BUSY BIT = 0           STATUS PORT BIT7   (HEX n79, n7D)
+
+          READ HIGH 4 BITS OF BYTE    STATUS PORT BIT3-6 (HEX n79, n7D)
+
+          REVERSE STROBE BIT          CONTROL PORT BIT0  (HEX n7A, n7E)
+
+      * 5 TYPES OF COMMAND
+
+      * COMMAND LENGTH = 9 BYTES.
+
+      * COMMAND FORMAT
+
+        BYTE 1   D5               ID CODE 1
+
+        BYTE 2   AA               ID CODE 2
+
+        BYTE 3   96               ID CODE 3
+
+        BYTE 4   00|01|04|05|06   COMMAND CODE
+
+        BYTE 5   al               LOW BYTE OF ADDRESS
+
+        BYTE 6   ah               HIGH BYTE OF ADDRESS
+
+        BYTE 7   ll               LOW BYTE OF DATA LENGTH
+
+        BYTE 8   lh               HIGH BYTE OF DATA LENGTH
+
+        BYTE 9   cc               CHECKSUM = 81^BYTE4^BYTE5^BYTE6^BYTE7^BYTE8
+
+      * COMMAND [00] : DOWNLOAD DATA
+
+        al, ah = ADDRESS
+
+        ll, lh = DATA LENGTH
+
+        OUTPUT DATAS AFTER COMMAND
+
+      * COMMAND [01] : UPLOAD DATA
+
+        al, ah = ADDRESS
+
+        ll, lh = DATA LENGTH
+
+        INPUT DATAS AFTER COMMAND
+
+      * COMMAND [04] : FORCE SFC PROGRAM TO JMP
+
+        al, ah = ADDRESS
+
+      * COMMAND [05] : SET MEMORY PAGE NUMBER
+
+        al BIT0-1 = PAGE NUMBER
+
+        al BIT2-7 + ah BIT0-1 = BANK NUMBER
+
+      * COMMAND [06] : SUB FUNCTION
+
+        al = 0  INITIAL DEVICE
+
+        al = 1  PLAY GAME IN DRAM
+
+        al = 2  PLAY CARTRIDGE
+
+                           ROM Protection Schemes
+
+This section details ways of bypassing the FastROM, PAL/NTSC and SRAM size
+checks implemented in many SNES games in order to stop people backing them
+up using copiers.
+
+Note: You don't necessarily have to find and replace all strings to remove
+the check(s).
+
+SlowROM checks
+
+Most cartridges these days use 120ns ROM in order to get the most out of
+the ageing SNES. However, there are still many copiers around which emulate
+ROM at speeds of 200ns meaning they cannot backup the newer cartridges
+correctly.
+
+Changing the ROM code to bypass the SlowROM check, found in many, but not
+all FastROM games, allows many people with SlowROM copiers to backup
+FastROM games.
+
+To patch a ROM and bypass the SlowROM check, you must find any of the
+following strings in the image and replace it with the patch string: (all
+codes in hex)
+
+Search for          Replace with
+
+A9 01 8D 0D 42      A9 00 8D 0D 42
+
+A9 01 8E 0D 42      A9 00 8E 0D 42
+
+A2 01 8D 0D 42      A2 00 8D 0D 42
+
+A2 01 8E 0D 42      A2 00 8E 0D 42
+
+A9 01 00 8D 0D 42   A9 00 00 8D 0D 42
+
+A9 01 8F 0D 42 00   A9 00 8F 0D 42 00
+
+PAL/NTSC checks
+
+Most SNES games have code which detects which video system the cartridge is
+being played on and refuses to run if not in the right mode. This is to
+stop people from buying games from other countries before they are released
+locally.
+
+To bypass the PAL/NTSC check the following patterns must be found and
+replaced with the ones specified: (all codes in hex)
+
+Search for                Replace with
+
+3F 21 29 10 C9 10 F0      3F 21 29 10 C9 10 80
+
+3F 21 89 10 C9 10 F0      3F 21 89 10 C9 10 80
+
+3F 21 29 10 F0            3F 21 29 10 80
+
+3F 21 00 89 10 F0         3F 21 00 89 10 80
+
+3F 21 00 29 10 F0         3F 21 00 29 10 80
+
+3F 21 89 10 00 F0         3F 21 89 10 00 80
+
+3F 21 29 10 00 F0         3F 21 29 10 00 80
+
+AD 3F 21 29 10 00 D0      AD 3F 21 29 10 00 80
+
+AF 3F 21 00 29 10 D0      AF 3F 21 00 29 10 80
+
+AF 3F 21 00 29 10 00 D0   AF 3F 21 00 29 10 00 EA EA
+
+AD 3F 21 29 10 D0         AD 3F 21 29 10 EA EA
+
+AD 3F 21 29 10 F0         AD 3F 21 29 10 80
+
+AD 3F 21 89 10 D0         AD 3F 21 89 10 80
+
+AD 3F 21 29 10 C9 00 F0   AD 3F 21 29 10 C9 00 80
+
+AF 3F 21 00 29 10 00 F0   AF 3F 21 00 29 10 00 80
+
+AF 3F 21 00 89 10 00 F0   AF 3F 21 00 89 10 00 80
+
+SRAM size checks
+
+Some SNES games check to see how much SRAM is connected to the SNES as a
+form of copy protection. As most copiers have 256kbits standard, the game
+will know it's running on a backup unit and stop to prevent people copying
+the games. However, the newer copiers get around this detection somehow.
+
+To disable the SRAM size check in a ROM image, search for the following and
+replace as appropriate.
+
+Note: All codes are in hex, although 'xx' means anything, while a comma
+means search for either of the two or more (enclosed in brackets).
+
+Search for     (8F, 9F) xx xx 70 (CF, DF) xx xx 70 D0
+
+Replace with   (8F, 9F) xx xx 70 (CF, DF) xx xx 70 EA EA (if SRAM size of game = 64kbit)
+
+               (8F, 9F) xx xx 70 (CF, DF) xx xx 70 80  (if SRAM size of game <> 64kbit)
+
+Search for     (8F, 9F) xx xx (30, 31, 32, 33) (CF, DF) xx xx (30, 31, 32, 33) D0
+
+Replace with   (8F, 9F) xx xx (30, 31, 32, 33) (CF, DF) xx xx (30, 31, 32, 33) 80
+
+Search for     (8F, 9F) xx xx (30, 31, 32, 33) (CF, DF) xx xx (30, 31, 32, 33) F0
+
+Replace with   (8F, 9F) xx xx (30, 31, 32, 33) (CF, DF) xx xx (30, 31, 32, 33) EA EA
+
+Search for     (8F, 9F) xx xx (30, 31, 32, 33) AF xx xx (30, 31, 32, 33) C9 xx xx D0
+
+Replace with   (8F, 9F) xx xx (30, 31, 32, 33) AF xx xx (30, 31, 32, 33) C9 xx xx 80
+
+Many thanks to Chp for making his uCON v1.41 source publicly available,
+from which these patterns came.
+
+                              IPS Patch Format
+
+This patch format is used a lot for patching SNES ROM images. Therefore I
+have included it's format in this text. For a more detailed explanation of
+the IPS format, please visit the Damaged Cybernetics WWW pages
+http://www.futureone.com/~damaged/.
+
+The format is as follows:
+
+   Description                    Size
+
+IPS file identifier            5 bytes (characters PATCH)
+
+Offset in file to place patch  3 bytes
+
+Number of bytes in patch       2 bytes (allows 65535 patch bytes)
+
+Patch byte(s)                  (specified by 'No. of bytes in patch')
+
+        .                              .
+
+        .                              .
+
+Start again, looking           3 bytes (characters EOF)
+
+for new offset, unless
+
+and EOF is found.
+
+Sample IPS file contents with 2 offset points:
+
+PATCHooonn?ooonn?EOF
+
+o - Offset in file
+
+n - Number of bytes in patch
+
+? - Data byte(s) (n number of bytes)
+
+                              Acknowledgements
+
+The following people have contributed to this text, whether they know it or
+not. Many thanks to them for their wonderful contribution(s).
+
+ Donald Moore   (moore@futureone.com)
+ Chp            (ronaldm@netcom.com)
+ Thomas Rolfes  (Thomas_Rolfes@ms.maus.de)
+ Jeremy Chadwick(yoshi@parodius.com)
+ Nigel Bryant   (nbb@essex.ac.uk)
+
+Also used for the creation of this text was the rec.games.video Frequently
+Asked Questions (FAQ) file; a FAQ with a huge amount of information on
+consoles in general.
+
+                                  [Image]
+
+                   Special thanks to Mark for the midi!
+                                  [Image]
+
+Questions, comments or complaints can be sent to DiskDude via e-mail.
+Copyright © 1995-1996 DiskDude of Damaged Cybernetics. All rights reserved.
+
+Last updated 1st January 1997
+
+Damaged Cybernetics is not connected or affiliated with any mentioned
+company in any way. The opinions of Damaged Cybernetics do not reflect the
+views of the various companies mentioned here. Companies and all products
+pertaining to that company are trademarks of that company. Please contact
+that company for trademark and copyright information.

+ 48 - 0
files/docs/snes/Snesmath.txt

@@ -0,0 +1,48 @@
+From:     vic@physci.psu.edu (Vic Ricker)
+To:       "Super Famicom Development Group" <famidev@busop.cit.wayne.edu>
+Subject:  Re: Multiplying/Dividing?
+Date:     Sun, 26 Dec 93 16:29:09 EST
+
+Take a look at this:
+
+
+    Address: $4202/$4203
+       Name: WRMPYA/WRMPYB
+Description: Multiplier and multiplicand
+
+
+  D7   D6   D5   D4   D3   D2   D1   D0
+
+|           MULTIPLICAND-A              |       $4202
+|_______________________________________|
+
+  D7   D6   D5   D4   D3   D2   D1   D0
+
+|            MULTIPLIER-B               |       $4203
+|_______________________________________|
+
+
+These registers perform absolute multiplication by multiplying
+multiplicand A by multiplier B and return product C which can be read
+from $4216/$4217 RDMPY.
+
+Set register A, then B.  After the B register is set, it will take 8
+machine cycles for the multiplication to be completed.
+
+* The A register will not be destroyed by the multiplication process.
+^^^ does not refer to the accumulator. it means the multiplicand
+
+Also, there is 8/16 multiply that shares the mode 7 matrix registers:
+set 16 bit multiplier to $211b and 8 bit multiplicand to $211c the 24
+bit product will be placed in $2134-$2136.
+
+The shift-add routine is a great way to multiply.  I'm suprised that
+so many so-called assembly programmers don't know how to do it.
+Regardless of how fast it is, the hardware stuff blows it away.
+
+There is also a hardware divide:
+
+$4204/4205 is the 16 bit dividend, $4206 is the 8bit divisor, the
+quotient will be put in $4214, and the remainder in $4216/4217.
+
+ANy questions, lemme know.

+ 343 - 0
files/docs/snes/Snesrom.txt

@@ -0,0 +1,343 @@
+
+             ______  _____        _____    _______       ___  ___
+            /   __/ /. _  \   ___/  __/   |____   \___  /.  \/   \
+            \___ .\//  |.  \ / . \__ .\    |.    _/   \//        .\
+           /.     \\   |:  .\  __/    \\   || |  .\ !  \     \/.   \
+           \______ /___|____/____\____ /   |__|   \\___/____||:     \
+             By Mind Rape                      \___/         |______/
+             v1.5 (C) Damaged Cybernetics 1994-95
+
+
+   This document main goal is show where one can find the SNES ROM
+   information.  Most of this information was collected thru hacking
+   the rom to death and help from Norm/Yoshi/chp.
+
+   License codes are taken from SU and probably incorrect.
+
+   Source? None here, if you are going to screw with the bin,
+   you probably know what you are doing (HOPEFULLY).
+
+   If you have any questions, comments,corrections, additional information,
+   you can either find me on IRC as (MindRape) or you can send me email
+   (much prefered) mind@primenet.com.  Also if you write anything
+   interesting then send it to me!
+
+   You may distribute this document freely, but you may not change
+   the information here and redistribute.  If you use this information
+   please credit me.  You steal this information and say you did it,
+   you know it's a LIE and there you are.
+
+=[SNES ROM Makeup]===========================================================
+
+ROM Title     : 21 Bytes
+
+  * Titles are all in upper case
+  * Japanese titles are in high ascii values
+    good rule of thumb if you can't read the title and
+    it's country code is Japan and your American,
+    you probably can't play it. :>
+
+Rom Makeup    : 7654 3210
+                0000-0000
+                |__| |__|
+                |    |
+                |    |___Bank Size 0001 = HiROM   (64K Banks Mode 21)
+                |                  0000 = Low Rom (32K Banks Mode 20)
+                |
+                |________ROM Speed 0111 = Fast Rom
+                                   0000 = Slow Rom
+
+                                   * Could someone give the correct
+                                   * speeds of the ROMs?  I got
+                                   * conflicting answers.
+
+
+ROM Type      :  1 Byte
+
+  Hex   ROM Type
+  ---------------------
+   00   ROM
+   01   ROM/RAM
+   02   ROM/SRAM
+   03   ROM/DSP1
+   04   ROM/DSP1/RAM
+   05   ROM/DSP1/SRAM
+   06   FX
+
+   * SRAM = Save Ram
+   * DSP1 = Nintendo's 1st generation of DSP (Math coprocessor)
+   * FX   = RISC based math coprocessor
+            Only a couple of games support the FX Chip, Star Fox
+            is the most well known one.
+
+
+ROM Size      : 1 BYTE
+
+  Hex   Size
+  --------------
+   08    2 Mbit
+   09    4 Mbit
+   0A    8 Mbit
+   0B   16 Mbit
+   0C   32 Mbit
+
+  * As of this documentation 32MBit ROMs are the largest that
+    Nintendo currently uses.  Rumors of a 40+ kart are around,
+    but cannot be verified.
+
+  * 8MBit ROMs are the most common in the entire library of
+    SNES karts
+
+  * ROMs are always multiples 2, thus 2MBit ROMs are the smallest
+    Space Invaders (c) Taito is a 2MBit ROM (Japan only)
+
+  * Easy way to calc rom size without a lookup table
+
+      1 << (ROM_SIZE - 7) MBits
+
+      ie.   8Mbit ROMs = 0Ah = 10d
+            1 << (0A-7) = 8 Mbit
+
+SRAM Size      : 1 BYTE
+
+  Hex   Size
+  --------------
+   00   No SRAM
+   01   16 Kbit
+   02   32 Kbit
+   03   64 Kbit
+
+    * 64Kbit is the largest SRAM size that Nintendo currently uses.
+    * 256Kbit is standard for most copiers.
+
+    * Easy way to calc SRAM Size without a lookup table
+
+        1 << (3+SRAM_BYTE) Kbits
+
+        ie. 16Kbit = 01
+            1 << (3+1) = 16
+
+
+COUNTRY CODE  : 1 BYTE
+
+  Hex    Country                 Video Mode
+  ------------------------------------------
+   00    Japan                   (NTSC)
+   01    USA                     (NTSC)
+   02    Europe, Oceania, Asia    (PAL)
+   03    Sweden                   (PAL)
+   04    Finland                  (PAL)
+   05    Denmark                  (PAL)
+   06    France                   (PAL)
+   07    Holland                  (PAL)
+   08    Spain                    (PAL)
+   09    Germany, Austria, Switz  (PAL)
+   10    Italy                    (PAL)
+   11    Hong Kong, China         (PAL)
+   12    Indonesia                (PAL)
+   13    Korea                    (PAL)
+
+  * Country Codes are from SU.INI, could someone verify these?
+
+LICENSE       : 1 BYTE
+     0 <Invalid License Code>
+     1 Nintendo
+     5 Zamuse
+     8 Capcom
+     9 HOT B
+    10 Jaleco
+    11 STORM (Sales Curve) (1)
+    15 Mebio Software
+    18 Gremlin Graphics
+    21 COBRA Team
+    22 Human/Field
+    24 Hudson Soft
+    26 Yanoman
+    28 Tecmo (1)
+    30 Forum
+    31 Park Place Productions / VIRGIN
+    33 Tokai Engeneering (SUNSOFT?)
+    34 POW
+    35 Loriciel / Micro World
+    38 Enix
+    40 Kemco (1)
+    41 Seta Co.,Ltd.
+    45 Visit Co.,Ltd.
+    53 HECT
+    61 Loriciel
+    64 Seika Corp.
+    65 UBI Soft
+    71 Spectrum Holobyte
+    73 Irem
+    75 Raya Systems/Sculptured Software
+    76 Renovation Pruducts
+    77 Malibu Games (T*HQ Inc.) / Black Pearl
+    79 U.S. Gold
+    80 Absolute Entertainment
+    81 Acclaim
+    82 Activision
+    83 American Sammy
+    84 GameTek
+    85 Hi Tech
+    86 LJN Toys
+    90 Mindscape
+    93 Technos Japan Corp. (Tradewest)
+    95 American Softworks Corp.
+    96 Titus
+    97 Virgin Games
+    98 Maxis
+   103 Ocean
+   105 Electronic Arts
+   107 Laser Beam
+   110 Elite
+   111 Electro Brain
+   112 Infogrames
+   113 Interplay
+   114 LucasArts
+   115 Sculptured Soft
+   117 STORM (Sales Curve) (2)
+   120 THQ Software
+   121 Accolade Inc.
+   122 Triffix Entertainment
+   124 Microprose
+   127 Kemco (2)
+   130 Namcot/Namco Ltd. (1)
+   132 Koei/Koei! (second license?)
+   134 Tokuma Shoten Intermedia
+   136 DATAM-Polystar
+   139 Bullet-Proof Software
+   140 Vic Tokai
+   143 I'Max
+   145 CHUN Soft
+   146 Video System Co., Ltd.
+   147 BEC
+   151 Kaneco
+   153 Pack in Video
+   154 Nichibutsu
+   155 TECMO (2)
+   156 Imagineer Co.
+   160 Wolf Team
+   164 Konami
+   165 K.Amusement
+   167 Takara
+   169 Technos Jap. ????
+   170 JVC
+   172 Toei Animation
+   173 Toho
+   175 Namcot/Namco Ltd. (2)
+   177 ASCII Co. Activison
+   178 BanDai America
+   180 Enix
+   182 Halken
+   186 Culture Brain
+   187 Sunsoft
+   188 Toshiba EMI/System Vision
+   189 Sony (Japan) / Imagesoft
+   191 Sammy
+   192 Taito
+   194 Kemco (3) ????
+   195 Square
+   196 NHK
+   197 Data East
+   198 Tonkin House
+   200 KOEI
+   202 Konami USA
+   205 Meldac/KAZe
+   206 PONY CANYON
+   207 Sotsu Agency
+   209 Sofel
+   210 Quest Corp.
+   211 Sigma
+   214 Naxat
+   216 Capcom Co., Ltd. (2)
+   217 Banpresto
+   219 Hiro
+   221 NCS
+   222 Human Entertainment
+   223 Ringler Studios
+   224 K.K. DCE / Jaleco
+   226 Sotsu Agency
+   228 T&ESoft
+   229 EPOCH Co.,Ltd.
+   231 Athena
+   232 Asmik
+   233 Natsume
+   234 King/A Wave
+   235 Atlus
+   236 Sony Music
+   238 Psygnosis / igs
+   243 Beam Software
+   244 Tec Magik
+   255 Hudson Soft
+
+  * License Codes are from SU.INI, could someone verify these?
+
+  * I believe the # of licenses is low.  Is it possible that
+    License and Country codes are used in conjuction to produce
+    that many more licenses?
+
+VERSION - 1 byte
+
+  * The Version is interpeted this way.
+    1.?? - (thanks to yoshi for the correction)
+
+CHECKSUM COMPLEMENT - 2 bytes the complement of the checksum :>
+
+  The bits are reversed of the CHECKSUM
+
+CHECKSUM            - 2 bytes Checksum of the bin
+
+  * Anyone know how the checksum is calculated for the ROM?
+
+NMI/VBL Vector     - 2 bytes                            - OFFSET 81FAh  (lowrom)
+                                                          OFFSET 101FAh (hirom)
+
+RESET Vector       - 2 bytes where to start our code at - OFFSET 81FCh  (lowrom)
+                                                        - OFFSET 101FAh (hirom)
+  * 8000h is common for Low Roms
+
+=[READING THE CORRECT BIN INFORMATION]==================================
+
+ The bin information can be found in 2 possible places,
+
+    a) End of the 1st 32K bank (Low ROM)  (81c0h/w 512 byte header)
+    b) End of the 1st 64K bank (HiROM)    (101c0h/w 512 byte header)
+
+ You could use UCON's method (author chp).
+
+ The method is as followed:
+
+ UCON's method is to OR the Checksum and the Complement.  If the
+ resulting value is FFFFh, then we found the correct location of
+ to extract rest of the data out.  HOWEVER!  This fails on several
+ karts, such as Castle Wolfenstien 3D and Super Tetris 3 for example.
+
+ Reason being is that not all developers put the correct complement
+ or bother even to implement it.  I would suspect!  That this maybe
+ a ploy to keep other developers out of the bin, for if they can't
+ find the reset vector, disassembling becomes a bit difficult.
+
+=[Other Information on SNES?]================================================
+
+ Famicom Development FTP Site
+   busop.cit.wayne.edu - pub/famidev
+
+ Yoshi's SNES Documentation 2.3
+
+   This is considered the BEST source of SNES hardware information,
+   and the most complete!
+
+   busop.cit.wayne.edu - pub/famidev/incoming/sndoc230.lzh
+
+=[w0rd!]=====================================================================
+
+w0rd to all following console dudes
+
+GoosE_,yoshi,sir jinx,chp,SHORYUKEN,_bubsy,felon,archimede
+rugalz,SinZ,dragonz,procyon,royce,hoodlem,bri_acid,kamikitty,
+norm,ZillionZ Members,grayarea,Victor,drunkfux(h0h0h0h0),dmessiah,
+piratendo
+
+<insert your favorite group(s) greet here> (heh)
+
+Later Mind Rape

+ 34 - 0
files/docs/snes/Swchead.txt

@@ -0,0 +1,34 @@
+This file was given to me by one of my friends from #emu, I can't remember who
+it was. I believe it was taken from the person's SWC game manual, so it should
+be accurate.
+
+	-avatar_Z - http://mana.nfinity.com/node99
+------------------------------------------------------------------------------
+
+byte 0	 - numbers of block (low byte)
+byte 1   - numbers of block (high byte)
+
+     total numbers of block = (byte1 * 256) + byte0
+
+byte 2	 - program execution mode
+
+   bit: 76543210
+        X            : 0, reserved
+         X           : 0=no more split file, the last fule
+                       1=search for next split file
+          X          : SRAM memory mapping,
+                       0=mode20, 1=mode21
+           X         : program memory mapping,
+                       0=mode20, 1=mode21
+            XX       : SRAM mode (size),
+                       00=256K, 01=64K, 10=16K, 11=off
+              XX     : 00, reserved
+
+byte 3~7  - 00, reserved
+byte 8    - aa, file id
+byte 9    - bb, file id
+byte 10   - file type
+            04: program
+            05: battery back-up data
+            08: real-time save data
+byte 11~511  - 00, reserved

BIN
files/docs/snes/U12675EJ7V0DS00.pdf


BIN
files/docs/snes/board_cpld_01.png


BIN
files/docs/snes/book1.pdf


BIN
files/docs/snes/book2.pdf


+ 227 - 0
files/docs/snes/csr-code.txt

@@ -0,0 +1,227 @@
+_________________________________________________________________________
+\_____________________   _______________________________________________/
+       _________  ___|!  | ________  
+      /   __   | /   /:  ||   __   \ -%*]  THE HOLE /  LSD USHQ!  [*%-
+  o _(___( |!  |/   /|o  ||   |_)___) 
+     /\    |:  /   __    ||!  ______/ SYSOPS: OLDMAN, ETRON, HIGHLANDER
+    o  o   |o (   (  |   ||:  |_)   ) D-MAN, ZANDOR
+__________ |   \___\ |___||o  _____/_______________________      __
+\________ \|___|__________|___|____/ ______________________>    (__)
+ ________\________      ____________/__________          _        _
+ \  __  !| |   | /__/\__\ |   |   \  __   __   \    __  _)\      (_)
+  \ \|  :|_|   |/ \ OO / \|  !|____\ \|!  |_)___)   \ \/  o\     O
+   \/|   ___   /  /_\/_\  \  :|\   \\/|:  ______/    ) /|\__). o
+    /    | |! (     \/     ) o|_)   )/ o  |_)   )   /_/\___/
+   /_____| |:  \__________/________//__   _____/            
+ __________|o  |______________________|   |____
+/______________________________________________\
+
+          Node1               Node2                Node3
+         PRIVATE         419-899-2754           419-899-2765
+                           RINGDOWN
+ <-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=->
+                        This file was leeched from:
+ ..THE..
+   _______/\_______    /\____    /\_________/\  _____/\/\_______/\______
+  /       \____    \  /  \   \  /  \   ______/\/    /  \____    \____   \
+ // __|___  /  |    \/    \   \/   /   ___/___   __/    \/  |    \   |   \
+/   \__   \/      __/      \      /   |   |  /   |/      \     __/   |   \\
+\      |  /    \   \__ /\   \__  /    |   | /  __/   /\   \ \   \|_  |    /
+ \________\____|\    /__/\    / /\________| \__\    /\____/_|\    /______/
+                 \  /     \  /\/-rAt            \  /          \  /
+<---- --- - ---- -\/--- ---\/---- ---- ------ -- \/-- - - --- -\/---- ---->
+          Q.U.A.R.T.E.X  MEGA HQ (AMIGA+CONSOLE) & H.Y.B.R.I.D (IBM)
+
+            Uploaded at: 02:36:04 on: 23-Apr-93 By: RAMRAIDER           
+
+ <-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=->
+;       Welcome to the first installment of "How to code SNES"
+; This first volume will show you how to make a simple text intro. It uses
+;mode 0 graphics with no DMAs (Horizontal or General) and is the simplest
+;type of intro you can make. We're starting small so you can easily understand
+;what to do. Other future volumes will contain other graphic modes,
+;Horizontal DMA (HDMA, the SNES version of an amiga copperlist), General DMA,
+;Interrupts, and a brief section on Sound. Originally we were going to release
+;the full Super Famicom Programmer's Manual but believe it or not, this manual
+;a pile of garbage. Contrary to the popular belief that we always had the
+;manual, this is NOT true. The White Knight happened to meet a very cool
+;guy at the CEBIT in Germany and has gotten the manual 2 weeks ago!
+;Yes! What you have seen from us before was true coding. We started out
+;by hacking and working our way to the top. We didn't wait until we bought
+;a manual. In fact, the manual was sent to us for FREE! This book isn't
+;worth paying for!
+
+
+ If White Knight had contacted us anytime in the last 6 months he could of had
+ a manual - instead he took the huff at Quattro's attitude.
+
+ 
+;Let's clear up a few misunderstandings about that SNES manual!
+; 
+;1) This book does NOT teach you assembly language!!
+;   It would help if you knew a little before trying to code this machine!
+;
+;2) This book was not written such as other reference guides you can find in
+;   a store, like Mapping the Amiga, or even Mapping the C64.
+;   It tells you barely and confusingly what the registers do. Period.
+;
+;3) This book is about 148 pages long and that includes the Sound Section.
+;   Some have said it was the size of a phone book. Unless live in
+;   Mud Hole, Kentucky this is NOT the case!
+
+
+ I dont know what fuckin manual you have got but mine is 300 pages and
+ includes a full section on the assembler as well.
+ The manual is a good reference manual, the english is a bit confusing but
+ it works well.  It is not an idiots guide to the SNES, but it aint intended
+ as this - only veteran coders are supposed to have it.
+ 
+ 
+;You cannot do this! $c000 is ROM and you can not write to ROM!
+;To write to ram, simply write to any address between $0000-$1fff.
+;If you need more memory you will find plenty at bank $7e and $7f
+;These 2 banks contain memory from $0000-$ffff. These 2 banks each contain
+;64k ofram totalling 128k for your own use!
+;If you need to write to these directly, just use the LONG STA command
+;example:
+;sta $7ec000
+; 
+;This will write to bank $7e at address $c000!
+
+
+ dont forget there is only 120k at the top of memory the other 8k is mapped 
+ through the whole memory map at 0-$1fff.
+
+
+;You will notice when looking at the source code something very strange.
+;Some registers are written to twice in a row! This because some registers
+;need more than one 8 bit info, such as the scroll X registers. In these
+;registers you can enter any number between $0-$07ff, but they are written
+;as two 8 bit numbers, one right after another.
+;example:
+; 
+;lda #$07
+;sta $210d
+;lda #$00
+;sta $210d
+; 
+;This writes #$0007 to $210d, plane 0 scroll x register.
+
+
+
+	why not use the efficient method
+
+	lda	#$7
+	sta	$210d
+	stz	$210d
+
+
+;The Super NES system has it own graphics processor. This requires its own
+;ram to read/write graphics data.  This ram can only be accessed through
+;certain registers such as $2118 + $2119.  To access Video Ram you MUST
+;turn off the video or you must be in screen blank (horizontal or vertical).
+;This is one of the downsides of the SNES.
+;Video Ram allows the storage of map planes and tile graphics.
+;VRAM is only 64k long and can not be used as regular ram. You can not
+;program in it, it is a separate unit!
+
+
+ you can store wotevere ya want in vram, programs if ya want!!!!
+
+ you can put data in at anytime u like not just the blank times - less time
+ available outside of the blanks though..
+ 
+ apart from these little quotes of critism, not bad, a good idea would
+ be nice to see some intros that aren't lame - I thought they would
+ improve but the last few have been so shite it aint tru, i'm sure as we 
+ ripped music 12 months ago, other peeps would be able to do it by now
+ and put it in intros.
+
+ I find it funny that PAN-HANDLE goes on about going the Klan and killing
+ a Nigger, I thought White Knight was slightly tainted in that direction,
+ so when ya gonna kill him then??? Leave the nogs for now and get those
+ bone-idle curry peddlers.................
+
+ hehehe rant rant rant - MAKE A EFFORT ON THE SNES DONT JUST PUT A PISS
+ SIMPLE INTRO OUT - PUSH THE FUCKIN MACHINE>>>>>>>>>>>>>>>>>>>>>
+
+ Corsair..........
+
+ Additional note about the source code :
+
+ A "veteran coder" would take one look at it and tell you it is inefficent.
+
+RamRaider at the keys now :
+
+If you really want to code on the SNES and need help from professionals :
+
+Call The GRaVEYARD BBS QUARTEX MEGA-HQ  +44-YOU-KNOW-IT, which has just
+started running a developers conference to help promote professional coding.
+
+Peeps In Charge : Corsair & Dax 
+
+Peep who pesters and Leaves stupid msgs about cheese : RamRaider!
+
+Two Points :
+
+1. SNASM for the 68k and 65816 (SNES) cracked will be available for
+   download from the above BBS in the developers conference.
+   It will be uploaded there and no where else. Unless someone spreads
+   it for the glory. 
+2. We also have the latest SNES manual with F/X, DSP1, DSP2 etc notes.
+   It is less than a week old.
+
+PS.  If ya take offence from this Text then fuck off.
+     Spelling Mistkes are Copyright.
+
+PPS. We do not give a shit wot ya think, and if ya take it the wrong way
+     Then fuck you!
+
+Quick greet from RamRaider to Beast/QTX, fuking southern wanker!! hahaha
+
+And also to Dax who seems to be working FAR too HARD.
+
+BBS Ads to follow this wonderfully Piece of text :
+ <-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=->
+
+                        This file was leeched from:
+ ..THE..
+   _______/\_______    /\____    /\_________/\  _____/\/\_______/\______
+  /       \____    \  /  \   \  /  \   ______/\/    /  \____    \____   \
+ // __|___  /  |    \/    \   \/   /   ___/___   __/    \/  |    \   |   \
+/   \__   \/      __/      \      /   |   |  /   |/      \     __/   |   \\
+\      |  /    \   \__ /\   \__  /    |   | /  __/   /\   \ \   \|_  |    /
+ \________\____|\    /__/\    / /\________| \__\    /\____/_|\    /______/
+                 \  /     \  /\/-rAt            \  /          \  /
+<---- --- - ---- -\/--- ---\/---- ---- ------ -- \/-- - - --- -\/---- ---->
+          Q.U.A.R.T.E.X  MEGA HQ (AMIGA+CONSOLE) & H.Y.B.R.I.D (IBM)
+ <-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=->
+                                                     [A¡RaDDer v3.1 By A¡Rcø]
+
+------------------------------------------------------------------------------
+                   CaLL THe øNe aND øNLY PLeaSuRE DøME
+------------------------------------------------------------------------------
+
+     |  ____   _       _____   _____   _____   ___|\   _____   _____  |
+  ___|_/  _¬\_/¬|    _/   __\_/ _  ¬\_/ ____\_/   | \_/   _¬\_/   __\_|__ _
+    ø:    |  |  |    |    |_\|  |    |  |___\|    |  |    | _|    |_\_:ø__
+     :    |  |  |   _|   __/ |  _    |\__    |    |  |    _ \_   __/ _|__ _
+     :    |  |  |__/¬|   ¬|_/|  |    |\_|    |    |  |    |  |   ¬|_/ :ø
+     :    |  |  |    |    |  |  |    |  |    |    |  |    |  |    |   :
+     :    |  |  |    |    |  |  |    |  |    |    |  |    |  |    |   :
+     :    |  |  |    |    |  |  |    |  |    |    |  |    |  |    |   :
+     :    ¬ _|  |    |    |  |  |    |  |    |    |  |    |  |    |   :
+     :   __/ |  |    |    |  |  |    |  |    |    |  |    |  |    |   :
+     :   ¬|  |  |    |    |  |  |    |  |    |    |  |    |  |    |   :
+  _ø_:_   |  |  ¬    |    ¬  |  |    |  ¬    |    ¬  |    |  |    ¬  _:_ø_
+     | \__|  ¯\_____/¯\_____/¯\ |___/¯\_____/¯\_____/¯\___| /¯\_____/ |
+     |                         \|                         |/          |-rS!
+                                  °° DD ° OO ° MM ° EE °°    
+     NøDE 1(DHST):+43-XXXX-XXXX                  NøDE 2(HST):+43-XXXX-XXXX
+
+                           DiaMøNDS & RuST euRøPeaN HQ
+                    ----------------------------------------
+                          aMiGa / SNeS / GeNeSiS / iBM
+
+        SYSøPS: [-STE\/E/D&R-],BøøN KiD/D&R,eTRøN&JøKer,eDø,CeViN KeY
+

+ 160 - 0
files/docs/snes/dma.txt

@@ -0,0 +1,160 @@
+From:     LAY@uk.tele.nokia.fi
+To:       "Super Famicom Development Group" <famidev@busop.cit.wayne.edu>
+Subject:  RE: Assorted questions...
+
+>> 2) I asked a question before about HDMA, and I got replies saying that
+>>    it has something to do with the horizontal interrupt or horizontal
+>>    blank time (I forget which).  Later on I saw people talking about
+>>    HDMA "channels".  Could someone please tell me what the "channels"
+>>    are used for, or are they another name for a register or a memory
+>>    storage location?
+
+It's probably best to start by explaning "normal" DMA. The SNES
+supports 8 DMA channels which allow data to be copied to VRAM
+extremely quickly, bypassing the 65c816 processor. Each channel
+consists of the following registers.
+
+    Byte    $43?0    DMA channel ? control register
+    Byte    $43?1    DMA channel ? destination
+    Word    $43?2    DMA channel ? source address offset
+    Byte    $43?4    DMA channel ? source address bank
+    Word    $43?5    DMA channel ? transfer bytes
+
+    where ? is 0..7
+
+A value of $01 written to the DMA channel control register at
+$43?0 indicates that we're using "normal" DMA. The graphics
+register destination is formed by using $21 as the high byte
+of the address and using the byte specified at $43?1 as the
+low byte. Hence you can DMA to any of the graphics registers
+between $2100..$21FF.
+
+There is also a DMA control register.
+
+    Byte    $420B    DMA control register
+
+Here bit 0 enables channel 0, bit 1 enables channel 1 etc...
+
+For example, suppose I wanted to copy a 32 x 32 character
+screen map (ie. $800 bytes) from location $18000 in ROM into
+location $0000 of VRAM. I could do this using DMA channel 0
+with the following code (A is 8-bits, X & Y are 16-bits).
+
+    ldx.w #$0000    ; set VRAM pointer to $0000
+    stx $2116
+    lda #$01        ; control value for "normal" DMA
+    sta $4300
+    lda #$18        ; dma to $2118
+    sta $4301
+    ldx.w #$8000    ; source offset
+    stx $4302
+    lda #$01        ; source bank
+    sta $4304
+    ldx.w #$0800    ; number of bytes
+    stx $4305
+    lda #$01        ; enable DMA channel 0
+    sta $420B
+
+And that's all there is to it. After completion of the last
+instruction "sta $420B" the $800 bytes at $18000 will have
+been copied into VRAM at location $0000.
+
+HDMA allows you to use any combination of these DMA channels
+to modify graphics registers just before the start of every
+horizontal scan line.
+
+To use HDMA you have to write a value of $00 or $02 to the
+DMA channel control register at $43?0 to indicate "horizontal"
+DMA. Writing $00 indicates a byte is to be DMA'd each scan
+line, writing $02 indicates a word. The DMA channel destination
+at $43?1 works just as before with "normal" DMA. The source
+address offset and bank registers at $43?2 & $43?4 will point
+to a HDMA table. The transfer bytes register at $43?5 is not
+used.
+
+The format of the HDMA table depends on the value you have
+written to the DMA channel control register. If you have
+written $00 then a byte will be written to the selected
+graphics register each scan line. The table should have the
+following format.
+
+hdma_table
+    Byte n ; number of bytes that follow (7-bit value 0..127)
+    Byte value_1, value_2, value_3 ... value_n
+    Byte n ; number of bytes that follow (7-bit value 0..127)
+    Byte value_1, value_2, value_3 ... value_n
+    .
+    etc
+    .
+    Byte 0 ; ends list
+
+The table is made up of a number of entries. The first byte
+in each entry is a count on the number of bytes that follow.
+The table is terminated by a 0 entry.
+
+If you have written $02 to the DMA channel control register
+then a word will be written to the selected graphics register
+each scan line. The table should have the following format.
+
+hdma_table
+    Byte n ; # times to repeat next word (7-bit value 0..127)
+    Word value
+    Byte n ; # times to repeat next word (7-bit value 0..127)
+    Word value
+    .
+    etc
+    .
+    Byte 0 ; ends list
+
+The table is made up of a number of entries. The first byte of
+each entry indicates the number of times the following word is
+to be repeated. The table is terminated by a 0 entry.
+
+The only other thing you'll need to know is that there is a
+HDMA control register.
+
+    Byte    $420C    HDMA control register
+
+This is the same format as the DMA control register at $420B,
+ie. bit 0 enables HDMA channel 0, bit 1 enables channel 1 etc...
+
+For example, suppose halfway down the screen I want to scroll
+graphics plane 0 left by 128 pixels.
+
+    lda #$02        ; word format HDMA (count, word)
+    sta $4300
+    lda #$0D        ; plane 0 x-scroll at $210D
+    sta $4301
+    ldx.w #hdma_table&$FFFF ; hdma table offset
+    stx $4302
+    lda #hdma_table/$10000 ; hdma table bank
+    sta $4304
+    lda #$01        ; enable HDMA channel 0
+    sta $420c
+
+    .
+    .
+    .
+
+hdma_table
+    dc.b 112       ; for first 112 scan lines
+    dc.w 0         ; set plane 0 x-scroll to 0
+    dc.b 1         ; on next scan line
+    dc.w 128       ; set plane 0 x-scroll to 128
+    dc.b 0
+
+You can use HDMA channels in combination, ie. you could use HDMA
+channel 0 to select a colour register and HDMA channel 1 to write
+the RGB data for that colour register.
+
+I don't have access to any of the official Nintendo documentation 
+so I may not have entirely understood everything about HDMA but 
+this is a much as I've been able to work out. Maybe there are other
+(H)DMA modes too?
+
+I'll should have put a simple HDMA demo with source code on the
+busop.cit.wayne.edu ftp site (in pub/famidev/incoming/hdmademo.zip).
+
+Hope that helps.
+
+Paul.

+ 759 - 0
files/docs/snes/fairligh.txt

@@ -0,0 +1,759 @@
+                        This fine text file came from...
+
+              /\____     __/\____           /\ _______/\__/\________
+             / __  //\   \_\/___ \  /\      \// _____/ /_/ /__  _  /
+         ___/ /__\//  \  /\  __/ / / / ___/\_/ /_   / /_/ /  / / \/ 
+         \_/ /__/ / /\ \/ / / __/ / /  \_/ // /_ \ / /_  /  / /     
+         _/ /    / /  \ \/__\ \__/ /_/\ / // /_/ / \/ / /  / /      
+         \_/[SP] \/   /\_____\ \_\____/ \/ \__  /    / /   \/       
+                      \/      \/            _/ /     \/             
+                                            \_/			    
+                                                               S.H.Q
+                          Far Out Multi Node System
+                          					
+        Node1 +46-46-133489   Node2 +46-46-133482   Node3 +46-46-133424
+								
+    If you want to read this then download it!  No free loaders here!!
+									
+··············································································
+-------->      a SMaSHiNG 100% SUPER NiNTENDo oNLY SYSTEM        <----------
+   ___/\____/\____    /\______    /\       /\_____/\__________  /\  /\
+   \____   / __   \  /   __   \  /  \ /\  /     _    ______   \/  \/  \
+    / _/ _/  _/\/\ \/   / /\   \/   // / /   /\//   /   / /\   \ _ \   \
+   /  \  \_     \ \    /  \/       /_\ \/   /  /   /   /  \/   /  \    /
+   \  /\  /______\ \  /\______/\___  /\____/   \  /\  /\__________/\  /
+    \/  \/          \/             \/           \/  \/              \/
+---------> +46-431-51557 ----- SYSoP: SY-KLoNE - CoSYSoP: HiTMaN <-----------
+
+; Corsair presents an example of how to drive the hardware - basically I used this intro
+
+; cos everyone knows how it looks and thus it seemed a good bit of code to do..
+
+; the comments outside the hardware stuff are a bit sparse - i'm not teaching you how
+
+; Fairlight write code , just their use of hardware!!
+
+;
+
+; questions as usual leave on GRAVEYARD, Treasure Island or Oasis..
+
+;
+
+
+
+
+
+Start Of Intro From Fairlight
+
+------------------------------------------------
+
+00E000 78                     SEI			; disable irq ints  
+
+00E001 A9 8F                  LDA #$8F			;
+
+00E003 8D 00 21               STA Screen_Fader		; turn screen on at full brightness
+
+00E006 9C 00 42               STZ $4200			;
+
+00E009 9C 0C 42               STZ Start_DMA_Hi		; disable all 8 DMA channels
+
+00E00C 9C 0B 42               STZ Start_DMA_Lo		;
+
+00E00F 18                     CLC 			;
+
+00E010 FB                     XCE 			; place in native (16 bit) mode
+
+00E011 C2 30                  REP #$30			; set x,y,a all to 16 bit
+
+00E013 A9 00 00               LDA #$0000		; 
+
+00E016 5B                     TCD 			; set direct register to bank zero
+
+00E017 64 07                  STZ $07			; clear memory loc. 7
+
+00E019 A9 20 00               LDA #$0020		;
+
+00E01C 85 0B                  STA $0B			; set $0b.w = $0020
+
+00E01E E2 20                  SEP #$20			; set accum. to 8 bit
+
+00E020 A9 80                  LDA #$80			;
+
+00E022 8D 15 21               STA Video_Port_Control	; initialise Video Port Controller
+
+00E025 A2 00 10               LDX #$1000		;
+
+00E028 8E 16 21               STX Video_Port_Address	; Point Vram Pointer To $1000
+
+
+
+00E02B A9 5B                  LDA #$5B        		;
+
+00E02D 85 0D                  STA $0D         		; Copies $5bx8 bytes of char
+
+00E02F A2 00 00               LDX #$0000      		; data into Video Ram via the port
+
+outer_loop:						; thus giving 2
+
+00E032 A0 08 00               LDY #$0008      		;
+
+inner_loop:						;
+
+00E035 BD D3 E2               LDA CHAR_SET,X  		; .: Character set for intro
+
+00E038 8D 18 21               STA Video_Port_Lo		;    and FLT logo.
+
+00E03B 9C 19 21               STZ Video_Port_Hi		;
+
+00E03E E8                     INX             		;
+
+00E03F 88                     DEY             		;
+
+00E040 D0 F3                  BNE inner_loop   		;
+
+00E042 C6 0D                  DEC $0D         		;
+
+00E044 D0 EC                  BNE outer_loop   		;
+
+
+
+00E046 9C 05 21               STZ $2105			; clear Video Reg. unknown
+
+00E049 A9 04                  LDA #$04        		; set Playfield 0 To $400 and 32x32 chars
+
+00E04B 8D 07 21               STA Playfield_0_Addr	; 
+
+00E04E A9 08                  LDA #$08        		; set Playfield 1 to $800 and 32x32 chars
+
+00E050 8D 08 21               STA Playfield_1_Addr	;
+
+00E053 A9 11                  LDA #$11        		; Set Playfield 0+1 Tile Addr To $100
+
+00E055 8D 0B 21               STA Tile01_Vram_Addr	;
+
+
+
+00E058 A2 07 00               LDX #$0007      		;
+
+00E05B 9E 0D 21               STZ Plane_0_Scroll_X,X	; Clear All The Scroll Pointers
+
+00E05E 9E 0D 21               STZ Plane_0_Scroll_X,X 	;
+
+00E061 CA                     DEX 			;
+
+00E062 10 F7                  BPL $00E05B		;
+
+
+
+00E064 A2 07 00               LDX #$0007		;
+
+00E067 9E 23 21               STZ $2123,X		; Clear Video Registers $2123-$212a
+
+00E06A CA                     DEX 			;
+
+00E06B 10 FA                  BPL $00E067		;
+
+
+
+00E06D A9 03                  LDA #$03			;
+
+00E06F 8D 2C 21               STA Playfield_Enable	; Enable playfields 0 & 1
+
+00E072 A2 04 00               LDX #$0004		;
+
+00E075 9E 2D 21               STZ $212D,X		; Clear Video Registers $212d-$2130
+
+00E078 CA                     DEX 			;
+
+00E079 10 FA                  BPL $00E075		;
+
+
+
+00E07B 9C 33 21               STZ Interlace_Flags	; Disable Interlace Mode
+
+00E07E A9 04                  LDA #$04			;
+
+00E080 9C 16 21               STZ Video_Port_Address	; Set Video Port Address to $400
+
+00E083 8D 17 21               STA Video_Port_Address+1	;
+
+00E086 A9 80                  LDA #$80			;
+
+00E088 8D 15 21               STA Video_Port_Controller	; Initialise Video Controller
+
+
+
+00E08B A2 00 08               LDX #$0800		;
+
+00E08E 9C 19 21               STZ Video_Port_Data+1	; Clear $800 bytes of Vram from $400 upwards
+
+00E091 CA                     DEX             		;
+
+00E092 D0 FA                  BNE $00E08E		;
+
+
+
+00E094 A2 AB E5               LDX #$E5AB      		; Display Text From $e5ab on..
+
+00E097 20 3E E2               JSR DO_TEXT     		; 
+
+00E09A A9 08                  LDA #$08			;
+
+00E09C 9C 16 21               STZ Video_Port_Address	; Set Video Port Address to $800 
+
+00E09F 8D 17 21               STA Video_Port_Address+1	; 
+
+00E0A2 9C 15 21               STZ Video_Port_Controller	; Clear Video Port Controller
+
+
+
+00E0A5 A2 00 00               LDX #$0000		;
+
+00E0A8 BD 91 E6               LDA $E691,X     		; Copy $a0 bytes down into Vram location
+
+00E0AB 8D 18 21               STA Video_Port_Data	; $800 onwards
+
+00E0AE E8                     INX 			; 
+
+00E0AF E0 A0 00               CPX #$00A0		;
+
+00E0B2 D0 F4		      BNE $E0A8			;
+
+
+
+00E0B4 A9 20		      LDA #$20			;
+
+00E0B6 8D 18 21               STA Video_Port_Data	; Fill One Screen Worth of VRAM with 
+
+00E0B9 E8                     INX 			; spaces
+
+00E0BA E0 00 04               CPX #$400			;
+
+00E0BD D0 F7		      BNE $E0B6			;
+
+
+
+00E0BF A9 A8		      LDA #$A8			;
+
+00E0C1 8D 00 0C               STA $0C00			; $c00 = $a8
+
+00E0C4 8D 00 0D               STA $0D00			; $d00 = $a8
+
+
+
+00E0C7 A9 21                  LDA #$21			;
+
+00E0C9 A2 00 00               LDX #$0000		; set $c01-$c028 = $21
+
+00E0CC 9D 01 0C               STA $0C01,X		;
+
+00E0CF E8                     INX 			; ie set up the color pointer table
+
+00E0D0 E0 28 00               CPX #$0028		;
+
+00E0D3 D0 F7		      BNE $E0CC			;
+
+
+
+00E0D5 A9 F8		      LDA #$F8			;
+
+00E0D6 F8                     SED 			; set decimal flag on
+
+00E0D7 9D 01 0C               STA $0C01,X		;
+
+00E0DA A9 01                  LDA #$01			; set more low memory
+
+00E0DC 9D 02 0C               STA $0C02,X		;
+
+00E0DF E8                     INX 			;
+
+00E0E0 E0 A0 00               CPX #$00A0		; and further color palette set-up
+
+00E0E3 D0 F7		      BNE $E0DC			;
+
+
+
+00E0E5 9e 02 0C		      STZ $C02,X		;
+
+00E0E8 A9 0B                  LDA #$0B			;
+
+00E0EA A2 00 00               LDX #$0000		; set even more low memory 
+
+00E0ED 9D 01 0D               STA $0D01,X		; - seems to set it to $b and then clear it??
+
+00E0F0 E8                     INX 			;
+
+00E0F1 9E 01 0D               STZ $0D01,X		;
+
+00E0F4 1A                     INC A			; pallete data set up
+
+00E0F5 E8                     INX 			;
+
+00E0F6 E0 28 00               CPX #$0028		;
+
+00E0F9 D0 F2		      BNE $E0ED			;
+
+
+
+00E0FB 9D 01 0D		      STA $0D01,X               ;   
+
+00E0FE E8                     INX 			;
+
+00E0FF 9E 01 0D               STZ $0D01,X		;
+
+00E102 3A                     DEC A			; and more 'irelevant' low mem stuff
+
+00E103 E8                     INX 			;
+
+00E104 E0 50                  CPX #$0050		; more palette data set-up
+
+00E107 D0 F2                  BNE $E0FB			;
+
+
+
+00E109 A9 F8		      LDA #$F8			;
+
+00E10B 9D 01 0D               STA $0D01,X		;
+
+00E10E A9 FF                  LDA #$FF			; and more 'irelevant' low mem stuff
+
+00E110 9D 02 0D               STA $0D02,X		;
+
+00E113 E8                     INX 			; more palette data set-up
+
+00E114 E0 40 01               CPX #$0140		;
+
+00E117 D0 F7		      BNE $E109			;
+
+00E119 9E 02 0D		      STZ $D02,X		;
+
+
+
+00E11C 9C 0C 42               STZ DMA_Enable		; Disable all DMA channels
+
+00E11F 9C 10 43               STZ DMA_Control_1		;
+
+00E122 A9 02                  LDA #$02       		; set up control regs for channel 1+2
+
+00E124 8D 20 43               STA DMA_Control_2		;
+
+00E127 A9 21                  LDA #$21       		; Select pallete pointer + color for
+
+00E129 8D 11 43               STA DMA_Destination_1	; DMA dump destination
+
+00E12C 1A                     INC A          		;
+
+00E12D 8D 21 43               STA DMA_Destination_2	;
+
+00E130 A2 00 0C               LDX #$0C00     		;
+
+00E133 8E 12 43               STX DMA_Source_Addr_1	; Palette numbers from $0c00 
+
+00E136 A2 00 0D               LDX #$0D00     		;
+
+00E139 8E 22 43               STX DMA_Source_Addr_2	; Palette data from $0d00
+
+00E13C 9C 14 43               STZ DMA_Source_Bank_1	;
+
+00E13F 9C 24 43               STZ DMA_Source_Bank_2	;
+
+00E142 A9 06                  LDA #$06			; turn on DMA channels 1+2
+
+00E144 8D 0C 42               STA DMA_Enable		;
+
+
+
+00E147 A9 0F                  LDA #$0F			; turn off screen
+
+00E149 8D 00 21               STA Screen_Fader		;
+
+00E14C A9 01                  LDA #$01			;
+
+00E14E 8D 00 42               STA $4200			; errmm
+
+00E151 20 C1 E1               JSR Pad_Poll_Hi		; Wait for poll hi
+
+00E154 9C 21 21               STZ Palette_Color_Pointer ; 
+
+00E157 9C 22 21               STZ Palette_Color_Data	; set background to black
+
+00E15A 9C 22 21               STZ Palette_Color_Data	;
+
+00E15D 4C 97 E1               JMP $00E197
+
+------------------------------------------------
+
+00E160 20 C1 E1               JSR Pad_Poll_Hi		; wait for poll hi
+
+00E163 20 13 E2               JSR PROC_B
+
+
+
+00E166 AD 12 42               LDA Pad_Poll		; Wait until a button has been
+
+00E169 4A                     LSR A			; pressed
+
+00E16A B0 FA                  BCS $00E166		;
+
+
+
+00E16C 20 CD E1               JSR PROC_A		;
+
+00E16F A9 F0                  LDA #$F0			;
+
+00E171 25 0A                  AND $0A			;
+
+00E173 F0 46                  BEQ $00E1BB		;
+
+00E175 5C 00 80 00            JMP GAME			; and run the game..
+
+------------------------------------------------
+
+00E179 A9 01                  LDA #$01			;
+
+00E17B A2 01 00               LDX #$0001		;
+
+00E17E 20 C1 E1               JSR Pad_Poll_Hi		;
+
+00E181 8D 06 21               STA Pixelation		;
+
+00E184 20 C7 E1               JSR Pad_Poll_Lo		;
+
+00E187 CA                     DEX 			;
+
+00E188 10 F4                  BPL $00E17E		;
+
+00E18A 18                     CLC 			;
+
+00E18B 69 10                  ADC #$10			;
+
+00E18D C9 01                  CMP #$01			;
+
+00E18F D0 EA                  BNE $00E17B		;
+
+
+
+00E191 20 40 E2               JSR $00E240		;
+
+00E194 20 C7 E1               JSR Pad_Poll_Lo		;
+
+
+
+00E197 20 C1 E1               JSR Pad_Poll_Hi		; wait for b7 pad_poll to go hi.
+
+00E19A 20 13 E2               JSR PROC_B		;
+
+
+
+00E19D A9 F1                  LDA #$F1       		;
+
+00E19F A2 01 00               LDX #$0001		; 'Reverse Pixelate' the text into vision
+
+00E1A2 20 C1 E1               JSR Pad_Poll_Hi   	;
+
+00E1A5 8D 06 21               STA Pixelation		;
+
+00E1A8 20 C7 E1               JSR Pad_Poll_Lo    	;
+
+00E1AB CA                     DEX            		;
+
+00E1AC 10 F4                  BPL $00E1A2    		;
+
+00E1AE 38                     SEC            		;
+
+00E1AF E9 10                  SBC #$10       		;
+
+00E1B1 C9 F1                  CMP #$F1       		;
+
+00E1B3 D0 EA                  BNE $00E19F    		;
+
+
+
+00E1B5 20 C1 E1               JSR Pad_Poll_Hi		;
+
+00E1B8 9C 06 21               STZ Pixelation 		; set pixels to normal.
+
+00E1BB 20 C7 E1               JSR Pad_Poll_Lo		;
+
+00E1BE 4C 60 E1               JMP $00E160		; and jump into the main loop
+
+------------------------------------------------
+
+00E1C1 2C 12 42 Pad_Poll_Hi   BIT Pad_Poll		; wait until bit 7 of pad_ready goes hi
+
+00E1C4 10 FB                  BPL Pad_Poll_Hi		;
+
+00E1C6 60                     RTS			;
+
+------------------------------------------------
+
+00E1C7 2C 12 42 Pad_Poll_Lo   BIT Pad_Poll		;
+
+00E1CA 30 FB                  BMI Pad_Poll_Lo       	; wait until bit 7 of pad_ready goes lo
+
+00E1CC 60                     RTS 			;
+
+------------------------------------------------
+
+00E1CD C2 20    PROC_A        REP #$20			; 16 bit accum.
+
+00E1CF A2 00 00               LDX #$0000		;
+
+
+
+00E1D2 A9 FF 7F               LDA #$7FFF		;
+
+00E1D5 E4 0B                  CPX $0B			;
+
+00E1D7 F0 07                  BEQ $00E1E0		; set up table of $7fff in memory
+
+00E1D9 9D B0 0D               STA $0DB0,X		;
+
+00E1DC E8                     INX 			;
+
+00E1DD E8                     INX 			;
+
+00E1DE 80 F5                  BRA $00E1D5		;
+
+00E1E0 A0 00 00               LDY #$0000		; and then follow the table with 5 zeros
+
+00E1E3 B9 C3 E2               LDA $E2C3,Y   		;
+
+
+
+00E1E6 9D B0 0D               STA $0DB0,X		;
+
+00E1E9 C8                     INY 			;
+
+00E1EA C8                     INY 			;
+
+00E1EB E8                     INX 			;
+
+00E1EC E8                     INX 			;
+
+00E1ED C0 10 00               CPY #$0010		;
+
+00E1F0 D0 F1                  BNE $00E1E3		;
+
+
+
+00E1F2 A9 FF 7F               LDA #$7FFF		; and if x<>$90 then add more $7fff's
+
+00E1F5 E0 90 00               CPX #$0090		;
+
+00E1F8 F0 07                  BEQ $00E201		;
+
+00E1FA 9D B0 0D               STA $0DB0,X		;
+
+00E1FD E8                     INX 			;
+
+00E1FE E8                     INX 			;
+
+00E1FF 80 F4                  BRA $00E1F5		;
+
+------------------------------------------------
+
+00E201 A6 07                  LDX $07			; preserve old pad data
+
+00E203 AD 18 42               LDA Pad_0_Data_Lo		; get new data
+
+00E206 85 07                  STA $07			; and store it as the old
+
+00E208 8A                     TXA 			; wop it in accum.
+
+00E209 49 FF FF               EOR #$FFFF		; not the old data
+
+00E20C 25 07                  AND $07			; and then use as a mask on new data
+
+00E20E 85 09                  STA $09			; and then store in 9
+
+00E210 E2 20                  SEP #$20			; and back to 8 bit accum..
+
+00E212 60                     RTS 			; and back..
+
+------------------------------------------------
+
+00E213 9C 15 21 PROC_B        STZ Video_Port_Control	; Reset Video Port
+
+00E216 A9 04                  LDA #$04          	;
+
+00E218 9C 16 21               STZ Video_Port_Addr	; set video ram pointer to $400
+
+00E21B 8D 17 21               STA Video_Port_Addr_Hi	;
+
+00E21E 9C 19 21               STZ Video_Port_Data_Hi	;
+
+00E221 9C 00 43               STZ DMA_Control_0		; reset dma controller #0
+
+00E224 A9 18                  LDA #$18			;
+
+00E226 8D 01 43               STA DMA_Destination_0	; point dma #0 to vram
+
+00E229 A2 00 04               LDX #$0400		;
+
+00E22C 8E 02 43               STX DMA_Source_Addr_0	; copy from address $400 to vram
+
+00E22F 9C 04 43               STZ DMA_Source_Bank_0	;
+
+00E232 A2 00 04               LDX #$0400		; copy $400 bytes into vram
+
+00E235 8E 05 43               STX DMA_Size_0		;
+
+00E238 A9 01                  LDA #$01			; and enable dma #0
+
+00E23A 8D 0B 42               STA DMA_Enable		;
+
+00E23D 60                     RTS 
+
+------------------------------------------------
+
+00E23E 86 00    DO_TEXT       STX $00          		; store text location
+
+00E240 A2 00 04               LDX #$0400       		; set pointer to text
+
+00E243 86 02                  STX $02          		; store text location again
+
+00E245 64 06                  STZ $06			; clear 6
+
+00E247 A2 00 00               LDX #$0000		; 
+
+00E24A B2 00                  LDA ($00)			; get next char
+
+00E24C 30 55                  BMI $00E2A3      		; if bit 7 set then off we go..
+
+00E24E C9 20                  CMP #$20			; is it a space
+
+00E250 90 11                  BCC $00E263      		; branch if less than a space..
+
+00E252 92 02                  STA ($02)        		; store char
+
+00E254 E8                     INX 			;
+
+00E255 E6 00                  INC $00          		; next char
+
+00E257 D0 02                  BNE $00E25B		;
+
+00E259 E6 01                  INC $01			;
+
+00E25B E6 02                  INC $02          		; next dest spot
+
+00E25D D0 EB                  BNE $00E24A		;
+
+00E25F E6 03                  INC $03			; 
+
+00E261 80 E7                  BRA $00E24A		;
+
+------------------------------------------------
+
+00E263 E6 00                  INC $00          		; increment counter 
+
+00E265 D0 02                  BNE $00E269      		; if not end of 255 boundary skip
+
+00E267 E6 01                  INC $01			; increment hi byte of pointer
+
+00E269 48                     PHA 			;
+
+00E26A A9 20                  LDA #$20			;
+
+00E26C E0 20                  CPX #$0020		; 
+
+00E26F F0 0B                  BEQ $E27C			;
+
+00E271 92 02                  STA ($02)			; basically these routines strip
+
+00E273 E8                     INX 			; chars unnecessary and prepare the
+
+00E274 E6 02                  INC $02			; text for output..
+
+00E276 D0 F4                  BNE $00E26C		;
+
+00E278 E6 03                  INC $03			; these lines increment the 16 bit pointer
+
+00E27A 80 F0                  BRA $00E26C		; as 2 8 bit pointers
+
+------------------------------------------------
+
+00E27C 68                     PLA 			;
+
+00E27D A2 00 00               LDX #$0000		;
+
+00E280 E6 06                  INC $06			;
+
+00E282 C5 06                  CMP $06			;
+
+00E284 D0 E3                  BNE $00E269		;
+
+00E286 B2 00                  LDA ($00)			;
+
+00E288 E6 00                  INC $00			;
+
+00E28A D0 02                  BNE $00E28E		;
+
+00E28C E6 01                  INC $01			;
+
+00E28E 85 0D                  STA $0D			;
+
+00E290 64 0E                  STZ $0E			;
+
+00E292 A9 20                  LDA #$20			;
+
+00E294 E4 0D                  CPX $0D			;
+
+00E296 F0 B2                  BEQ $00E24A		;
+
+00E298 92 02                  STA ($02)			;
+
+00E29A E8                     INX 			;
+
+00E29B E6 02                  INC $02			;
+
+00E29D D0 02                  BNE $00E2A1		; and again increment pointer as 2 8 bit
+
+00E29F E6 03                  INC $03			;
+
+00E2A1 80 F1                  BRA $00E294		;
+
+------------------------------------------------
+
+00E2A3 A5 06                  LDA $06			;
+
+00E2A5 C9 20                  CMP #$20			;
+
+00E2A7 F0 19                  BEQ $00E2C2		;
+
+00E2A9 A9 20                  LDA #$20			;
+
+00E2AB E0 20                  CPX #$0020		;
+
+00E2AE F0 0B                  BEQ $E2BB			;
+
+00E2B0 92 02                  STA ($02)			;
+
+00E2B2 E8                     INX 			;
+
+00E2B3 E6 02                  INC $02			;
+
+00E2B5 D0 F4                  BNE $00E2AB		;
+
+00E2B7 E6 03                  INC $03			;
+
+00E2B9 80 F0                  BRA $00E2AB		;
+
+------------------------------------------------
+
+00E2BB A2 00 00               LDX #$0000		;
+
+00E2BE E6 06                  INC $06			;
+
+00E2C0 80 E1                  BRA $00E2A3		;
+
+00E2C2 60                     RTS 			;
+
+------------------------------------------------
+
+
+
+The End..
+
+

+ 151 - 0
files/docs/snes/famitec2.txt

@@ -0,0 +1,151 @@
+Version 1.1
+
+Corrected an error in screen sizes and removed a quesry on sound registers.
+
+
+Corsair + Kari presents the first dox of Fami hardware register
+locations and brief explanation of them..
+
+If you would like to add any info found in this list please leave
+a mail message to Corsair or RamRaider on GRAVEYARD BBS +44-91-5160560
+or anything to do with the FAMICON/SNES..
+
+We have an INTERNET address if ya want it leave true e-mail!
+
+Or better still if ya can get the Programmers handbook (Both) please call
+and leave mail :) , or even the 100,000 quid SCSI SNASM board for FAMICON
+development :)
+
+Also if you want more info contact us the same way..
+
+We are esp looking for contacts to help get to grips with this new platform
+everybody welcome!
+
+Special greetings to Starr/QUARTEX and any other True Console Dude! 
+
+coming soon is some sound chip info........
+
+Memory Map
+~~~~~~~~~~ 
+Bank    Address
+~~~~    ~~~~~~~
+
+ 00-    0000-1fff       Lo RAM  (same as at $7e0000-$7e1fff)
+ 7d     2100-2142(?)    Videochip Registers
+        4300-437f       DMA Registers
+
+        8000-ffff       ROM:This contains 32k block of game ROM.
+                            So, the games are divided to 32k chunks
+                            which locate always at address $8000-$ffff,
+                            but in different banks. This means that the first
+                            32k of game is at $008000-$00ffff and next 32k
+                            is at $018000-$01ffff etc.
+
+ 7e     0000-1fff       Lo RAM (same as always at $0000-$1fff)  \
+        2000-ffff       RAM    \ I'm not sure about              } 128k RAM??
+ 7f     0000-ffff       RAM    / this RAM                       /
+
+ 7f-ff  all             Not used???
+
+$ffec($fffc) contains reset vector and $ffea($fffa) is NMI vector. The NMI is
+actually vertical blank interrupt.
+
+Video Chip
+~~~~~~~~~~
+size    loc.
+~~~~    ~~~~
+  B     2100    Screen fade  x000bbbb   x=screen on/off  b=brightness(0-f)
+  B     2106    Screen Pixelation xxxxbbbb  x=pixel size b=planes to expand
+  B     2107    Plane 0 location in vram  xxxxxxab x=address ab=32/64 width xy
+  B     2108    Plane 1 location in vram  xxxxxxab      as above
+  B     2109    Plane 2 location in vram  xxxxxxab      as above
+  B     210a    Plane 3 location in vram  xxxxxxab      as above
+  B     210b    Tile VRAM address  aaaabbbb a=Playfield 0   b=Playfield 1       
+  B     210c    Tile VRAM address  ccccdddd c=Playfield 2   d=Playfield 3       
+ 2B     210d    Plane 0 scroll x   8+3 bits (0-7ff) put first 8 bits and then
+ 2B     210e    Plane 0 scroll y   8+3 bits  (0-7ff)  3 highest bits
+ 2B     210f    Plane 1 scroll x                as above
+ 2B     2110    Plane 1 scroll y                as above
+ 2B     2111    Plane 2 scroll x                as above
+ 2B     2112    Plane 2 scroll y                as above
+ 2B     2113    Plane 3 scroll x                as above
+ 2B     2114    Plane 3 scroll y                as above
+ B      2115    Video port control
+ W      2116    Video port address (lo-hi)
+ W      2118    Video port data (lo-hi) (address is incremented by 2)
+ B      2121    Palette color nr
+ B      2122    Palette color data
+ B      212C    Playfield Enable xxxxabcd  a-d = playfield number..
+ B      2133    Screen mode  0000ab0c a=Interlace Y  b=Overscan  c=Interlace X??
+     2140-2142  Audio Registers
+
+I/O
+~~~
+W B     420b    Start dma (enable bits) bits: 76543210 = dma nr (8 DMA's)
+R B     4212    Pad ready to be read
+R W     4218    Pad 0 data      76543210 = A-B-Select-Start-U-D-L-R
+        4219                    76543210 = X-Y-Top Left-Top Right-0000
+R W     421a    Pad 1 data              as above 
+R W     421c    Pad 2 data              as above
+R W     421e    Pad 3 data              as above
+
+DMA registers  ($4300-$437f)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  B     43X0    DMA control reg??(not sure!)
+  B     43X1    DMA destination (Access only to some of the video chip
+                    registers ($2100-$21ff)
+                    $18=video port  $22=color palette
+  W     43X2    Source address lo-hi  16 lowest bits
+  B     43X4    Source Bank addr. 8 highest bits
+  W     43X5    Transfer size lo-hi
+
+        X=dma number (0-7)  DMA #0= 4300-4305
+                            DMA #1= 4310-4315 ...
+                            DMA #7= 4370-4375
+
+ Symbols:  size: B=byte long    2B=put 2 bytes    W=word long
+             R=read only  W=write only
+
+Screen Details
+~~~~~~~~~~~~~~
+Famicom Tile format is simple. Each Tile is 4 planes and 8x8 bits.
+32 bytes are used per Tile .
+
+PLANES 1  &  2                  PLANES  3  &    4
+    byte0   byte1                  byte 16   byte 17  
+    byte2   byte3                  byte 18   byte 19
+    byte4   byte5                  byte 20   byte 21
+     .....                              .......
+    byte14  byte15                 byte 30   byte 31
+
+Screen Map
+~~~~~~~~~~
+Famicom can use only Tiles $0-$3ff, max 1024 chars.
+16 bits:   YX?c ccNN NNNN NNNN
+           fedc ba98 7654 3210
+
+  Y = mirror y     X = mirror x   ?=unknown
+  ccc = palette nr (8 palettes)   NN.. = character number
+
+Screen Resolution is normally 32x32 chars but only the first 30 y blocks are 
+visible (until scrolled) - 64 bytes / line
+
+Screen VRAM Location
+~~~~~~~~~~~~~~~~~~~~
+Screen Width 32x32 offset for x,y       0,0   = 0
+
+Screen Width 64x32 offset for x,y       0,0   = 0
+                                        33,0  = $400
+
+Screen Width 32x64 offset for x,y       0,0   = 0
+                                        0,33  = $400 
+
+Screen Width 64x64 offset for x,y       0,0   = 0
+                                        33,0  = $400
+                                        0,33  = $800
+                                        33,33 = $c00
+
+As can be seen if a wider mode is selected the extra height/width follow
+after the main screen in memory.
+
+=============================================================================

+ 45 - 0
files/docs/snes/fastrom.txt

@@ -0,0 +1,45 @@
+From:     LAY@uk.tele.nokia.fi
+To:       "Super Famicom Development Group" <FAMIDEV@BUSOP.CIT.WAYNE.EDU>
+Subject:  The need for speed revisited...
+Date:     Wed, 16 Feb 1994 11:00:49 GMT
+
+I unsubscribed from this mailing list after my suggestion that 
+maybe the processor would run faster when executing from RAM 
+brought responses such as "if you want something to run that 
+fast you should use a PC" which quickly turned into a whole
+barrage of "my Amiga is faster than your PC" mails. Just the 
+sort of comments I was hoping to get from this mailing 
+list... )-: However I'm changing jobs and I don't know whether
+I'll have internet access at my new job, so I'd better make
+the most of it...
+
+So, for anyone like myself who wants to get the most out 
+of their SNES I thought I'd let you know that I've managed to
+run the program in FASTROM which has resulted in a 33% speed
+improvement - the 65816 runs at 3.58Mhz rather than 2.68Mhz.
+This is possible because the ROMs have a faster access time
+- hence the reason I thought it may be possible with RAM which
+typically has faster access times than ROM.
+
+So how's it done?
+
+The SNES lets you access ROM through bank $00 onwards and bank 
+$80 onwards such that locations $008000 and $808000, $008001 and
+$808001, $008002 and $808002 etc... all access the same locations.
+When accessing bank $00 onwards the 65816 runs at 2.68Mhz. However,
+when accessing bank $80 onwards the 65816 can run at 2.68Mhz or 
+3.58Mhz depending on how you set bit 0 of $420D.
+
+So all you have to do is assemble your program so that it
+starts at $808000, make sure you set the programming and 
+data banks to $80 (K and D) and set bit 0 of $420D. You'll 
+also need to mask off the bank part of the run/reset vector 
+and vertical blank interrupt locations. 
+
+Paul.
+
+PS. I also see that the source code for an early version of my 
+GIF2SNES program has made it onto the ftp site by a somewhat
+indirect route (UK->NZ->AUS->USA). If someone wanted
+this source code let me know and I'll post the latest fully
+optimising version.

+ 156 - 0
files/docs/snes/how2code.txt

@@ -0,0 +1,156 @@
+       BASELINE 2091 Presents The First Guide To Coding The SNES
+                    Guide and Source Code by -Pan-
+                         Released on 4/20/93
+
+
+       Welcome to the first installment of "How to code SNES"
+ This first volume will show you how to make a simple text intro. It uses
+mode 0 graphics with no DMAs (Horizontal or General) and is the simplest
+type of intro you can make. We're starting small so you can easily understand
+what to do. Other future volumes will contain other graphic modes,
+Horizontal DMA (HDMA, the SNES version of an amiga copperlist), General DMA,
+Interrupts, and a brief section on Sound. Originally we were going to release
+the full Super Famicom Programmer's Manual but believe it or not, this manual
+a pile of garbage. Contrary to the popular belief that we always had the
+manual, this is NOT true. The White Knight happened to meet a very cool
+guy at the CEBIT in Germany and has gotten the manual 2 weeks ago!
+Yes! What you have seen from us before was true coding. We started out
+by hacking and working our way to the top. We didn't wait until we bought
+a manual. In fact, the manual was sent to us for FREE! This book isn't
+worth paying for!
+ 
+Let's clear up a few misunderstandings about that SNES manual!
+ 
+1) This book does NOT teach you assembly language!!
+   It would help if you knew a little before trying to code this machine!
+
+2) This book was not written such as other reference guides you can find in
+   a store, like Mapping the Amiga, or even Mapping the C64.
+   It tells you barely and confusingly what the registers do. Period.
+
+3) This book is about 148 pages long and that includes the Sound Section.
+   Some have said it was the size of a phone book. Unless live in
+   Mud Hole, Kentucky this is NOT the case!
+ 
+
+So much for the introduction. I personally feel that experience is better
+than a reference guide. Reading a text file does not give you the feel of the
+machine. In the included source file, you will notice that almost every line
+has a description of what it is doing. This is better than telling you the
+registers and letting you fiddle around. You know what it will do, and you
+can see it in action in the assembled output (also included). I suggest
+you examine the source code right after reading this brief introduction on
+how the SNES system operates.
+ 
+The SNES runs on a 65816 processor. This is similar to the 6502, but many
+new instructions are available. You will use the most popular commands
+like LDA, LDX, STA, PHA, PLA, RTS, JMP.. etc etc.   There are some new
+ones but we will get into that subject in the next volume as it is not
+very important right now.
+The 65816 is a 16 bit processor that does 24 bit addressing.
+You can load and store 16 bit numbers, as well as 8 bit. The addressing is
+is different than the 6502 in that it includes a bank. If you have coded on
+the C64 you know that the addressing on the C64 was from $0000-$FFFF.
+That is 16 bit addressing. 24 bit includes 1 extra byte. This one byte
+is the BANK number.  The SNES memory is broken down into fragments of
+32k blocks each. They are addressed from $8000-$FFFF and are stored into
+banks sequentially. If you wanted to access the first ROM byte in memory, 
+the address would be $008000. The first $00 is the bank number, the first
+bank you can access. The $8000 is the 16 bit address. All banks (unless in
+high rom 64k bank memory) start at $8000!
+Remember that you can not write ROM. If you have coded on a C64 you have
+written a routine that looked like this:
+
+lda #$00
+sta $c000
+ 
+You cannot do this! $c000 is ROM and you can not write to ROM!
+To write to ram, simply write to any address between $0000-$1fff.
+If you need more memory you will find plenty at bank $7e and $7f
+These 2 banks contain memory from $0000-$ffff. These 2 banks each contain
+64k ofram totalling 128k for your own use!
+If you need to write to these directly, just use the LONG STA command
+example:
+sta $7ec000
+ 
+This will write to bank $7e at address $c000!
+
+Fair enough. This was only a brief lecture on how the memory works.
+
+ 
+The SNES hardware registers and how the work:
+
+You will notice when looking at the source code something very strange.
+Some registers are written to twice in a row! This because some registers
+need more than one 8 bit info, such as the scroll X registers. In these
+registers you can enter any number between $0-$07ff, but they are written
+as two 8 bit numbers, one right after another.
+example:
+ 
+lda #$07
+sta $210d
+lda #$00
+sta $210d
+ 
+This writes #$0007 to $210d, plane 0 scroll x register.
+
+Using 16 bit data storage will not work for this type of register!
+example:
+
+lda #$0007
+sta $210d
+
+This will not work because it will write #$07 to $210d, then a #$00 to $210e.
+
+Another strange register is the self-incrementing register such as the VRAM
+address registers $2116 and $2117.
+After writing to $2119 (or $2118 in another setting) the VRAM address in
+$2116 and $2117 will be increased. You do not have to do it yourself.
+This can be seen in the Character set (font set) transfer  routine in the 
+source code.
+
+ 
+Introduction to Video RAM (VRAM)
+ 
+The Super NES system has it own graphics processor. This requires its own
+ram to read/write graphics data.  This ram can only be accessed through
+certain registers such as $2118 + $2119.  To access Video Ram you MUST
+turn off the video or you must be in screen blank (horizontal or vertical).
+This is one of the downsides of the SNES.
+Video Ram allows the storage of map planes and tile graphics.
+VRAM is only 64k long and can not be used as regular ram. You can not
+program in it, it is a separate unit!
+
+In this volume we show you how to make a text screen in Mode 0. There are
+8 graphic modes numbered from Mode 0 to Mode 7.   Mode 0 is the most 
+simplistic. It allows only 4 colors per tile, but allows all four 
+planes to be used.
+ 
+A normal video screen on the SNES is 32*32 tiles, which comes out to an
+even 1024 tiles. You can widen the screen but you still may only have
+1024 tiles. There are 2 parts to displaying a graphic on the screen.
+There is the tile graphic data which gives the tile its picture. Then there
+is the Map data. These are individually placed tiles placed on the screen
+to produce an image.
+
+example:
+
+                BBBBB   SSSSS  LL
+                BB  BB SS      LL
+                BBBBB   SSSS   LL
+                BB  BB     SS  LL
+                BBBBB  SSSSS   LLLLLLL
+
+Notice that all the small B's are the same. These woulds be drawn as
+Tile Graphics. They all form together to create the large B image.
+These B's together would be the Map data. The same would go for the S and L.
+
+This is enough info to understand the basics of this 2 color intro.
+This next installment on "How to code SNES" will feature more interesting
+subjects as:
+ 
+ - How the color works
+ - 16 color graphic mode
+ - the entire 65816 instruction set with op-codes
+ - more info on the joypad
+

+ 129 - 0
files/docs/snes/memmap.txt

@@ -0,0 +1,129 @@
+                      +=-=-=-=-=-=-=-=-=-=-=+
+                      | SNES Memory Mapping |
+                      |    By: ]SiMKiN[     |
+                      |         v2.0        |
+                      +=-=-=-=-=-=-=-=-=-=-=+
+
+
+• FastROM's can execute at 3.58Mhz
+• SlowROM's can only execute 2.68Mhz
+
+  • The SNES lets you access ROM through bank $00 onwards and bank 
+    $80 onwards such that locations $00:8000 and $80:8000 are congruent,
+    (they access the same locations.)
+  • When accessing bank $00 onwards the 65816 runs at 2.68Mhz. However, 
+    when accessing bank $80 onwards the 65816 can run at 2.68Mhz or 
+    3.58Mhz depending on how you set bit 0 of $420D.
+
+  • This Document Contains Information Regarding ROM's upto 32mbit.
+    If you have any information regarding ROM's above 32mbit please send
+    E-Mail to 'simkin@innocent.com'
+
++======================================================================+
+| Mode 20: LoROM Memory Model (32k Banks)                              |
+| ---------------------------------------                              |
+|  • $80-$ef : $8000-$ffff                                             |
+|              Mirrored to $00-6f                                      |
+|  • $f0-$ff : $8000-$ffff                                             |
++=========+=============+====================================+=========+
+| Bank    | Offset      | Definition                         | Shadow  |
++=========+=============+====================================+=========+
+| $00-$2f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | RESERVED                           | $00-$3f |
+|         | $8000-$ffff | (Mode 20 ROM)                      | ------- |
++---------+-------------+------------------------------------+---------+
+| $30-$3f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | RESERVED                           | ------- |
+|         | $8000-$ffff | (Mode 20 ROM)                      | $80-$bf |
++---------+-------------+------------------------------------+---------+
+| $40-$6f | $0000-$7fff | RESERVED                           | ------- |
+|         | $8000-$ffff | (Mode 20 ROM)                      | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $70-$77 | $0000-$ffff | (Mode 20 SRAM) 256KBytes           | ------- |
++---------+-------------+------------------------------------+---------+
+| $78-$7d | $0000-$ffff | RESERVED                           | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7e   | $0000-$1fff | LowRAM                             | $00-$3f |
+|         | $2000-$7fff | HighRAM                            | ------- |
+|         | $8000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7f   | $0000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+| $80-$ef | $0000-$ffff | Mirror of $00-$6f                  | $00-$6f |
++---------+-------------+------------------------------------+---------+
+| $f0-$ff | $0000-$7fff | RESERVED                           | ------- |
+|         | $8000-$ffff | (Mode 20 ROM)                      | ------- |
++=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
+
++======================================================================+
+| Mode 21: HiROM Memory Model (64k Banks)                              |
+| ---------------------------------------                              |
+|  • $C0-$ff : $0000-$ffff                                             |
+|              High Parts ONLY '($8000-$ffff)' are Shadowed to $00-3f  |
++=========+=============+====================================+=========+
+| Bank    | Offset      | Definition                         | Shadow  |
++=========+=============+====================================+=========+
+| $00-$2f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | RESERVED                           | $00-$3f |
+|         | $8000-$ffff | (Mode 21 ROM) from $C0-$EF         | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $30-$3f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | (Mode 21 SRAM) 256KBytes           | ------- |
+|         | $8000-$ffff | (Mode 21 ROM) from $C0-$EF         | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $40-$6f | $0000-$7fff | (Mode 21 ROM) from $C0-$EF         | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $70-$77 | $0000-$ffff | (Mode 20 SRAM) 256KBytes           | ------- |
++---------+-------------+------------------------------------+---------+
+| $78-$7d | $0000-$ffff | RESERVED                           | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7e   | $0000-$1fff | LowRAM                             | $00-$3f |
+|         | $2000-$7fff | HighRAM                            | ------- |
+|         | $8000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7f   | $0000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+| $80-$bf | $0000-$ffff | Mirror of $00-$3f                  | $00-$3f |
++---------+-------------+------------------------------------+---------+
+| $c0-$ff | $0000-$ffff | (Mode 21 ROM)                      | ------- |
++=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
+
+• ROM: The SNES ROM Image
+• RAM: The SNES Work Memory (WRAM)
+       LowRAM, HighRAM, & Expanded RAM 
+       All together = 128 Kilo-Bytes
+• SRAM: Save RAM (Extra RAM added by Cart)
+        The SNES only utilizes 256 Kilo-bits
+        However 256 Kilo-Bytes are provided.
+
+• APU: Audio Processing Unit
+       SPC700, Inside which has a DSP   
+• PPU: Picture Processing Unit
+       PPU1: 5c77-01
+       PPU2: 5c78-03
+
+• SFX: Super FX Cart Chip, by Nintendo
+• DSP: Digital Signal Processing Cart Chip
+       a.k.a. 'NEC mUPD77C25'
+
+• Shadow: "Congruent Bank".  Same meaning as Mirror.
+
+          _____________________________________________________
+       .o(_Thanx to: zsKnight, Lord Esnes, Y0SHi, and MintaBoo_)o.
+

+ 151 - 0
files/docs/snes/memory_mapping_and_io.txt

@@ -0,0 +1,151 @@
+Version 1.1
+
+Corrected an error in screen sizes and removed a quesry on sound registers.
+
+
+Corsair + Kari presents the first dox of Fami hardware register
+locations and brief explanation of them..
+
+If you would like to add any info found in this list please leave
+a mail message to Corsair or RamRaider on GRAVEYARD BBS +44-91-5160560
+or anything to do with the FAMICON/SNES..
+
+We have an INTERNET address if ya want it leave true e-mail!
+
+Or better still if ya can get the Programmers handbook (Both) please call
+and leave mail :) , or even the 100,000 quid SCSI SNASM board for FAMICON
+development :)
+
+Also if you want more info contact us the same way..
+
+We are esp looking for contacts to help get to grips with this new platform
+everybody welcome!
+
+Special greetings to Starr/QUARTEX and any other True Console Dude!
+
+coming soon is some sound chip info........
+
+Memory Map
+~~~~~~~~~~ 
+Bank    Address
+~~~~    ~~~~~~~
+
+ 00-    0000-1fff       Lo RAM  (same as at $7e0000-$7e1fff)
+ 7d     2100-2142(?)    Videochip Registers
+        4300-437f       DMA Registers
+
+        8000-ffff       ROM:This contains 32k block of game ROM.
+                            So, the games are divided to 32k chunks
+                            which locate always at address $8000-$ffff,
+                            but in different banks. This means that the first
+                            32k of game is at $008000-$00ffff and next 32k
+                            is at $018000-$01ffff etc.
+
+ 7e     0000-1fff       Lo RAM (same as always at $0000-$1fff)  \
+        2000-ffff       RAM    \ I'm not sure about              } 128k RAM??
+ 7f     0000-ffff       RAM    / this RAM                       /
+
+ 7f-ff  all             Not used???
+
+$ffec($fffc) contains reset vector and $ffea($fffa) is NMI vector. The NMI is
+actually vertical blank interrupt.
+
+Video Chip
+~~~~~~~~~~
+size    loc.
+~~~~    ~~~~
+  B     2100    Screen fade  x000bbbb   x=screen on/off  b=brightness(0-f)
+  B     2106    Screen Pixelation xxxxbbbb  x=pixel size b=planes to expand
+  B     2107    Plane 0 location in vram  xxxxxxab x=address ab=32/64 width xy
+  B     2108    Plane 1 location in vram  xxxxxxab      as above
+  B     2109    Plane 2 location in vram  xxxxxxab      as above
+  B     210a    Plane 3 location in vram  xxxxxxab      as above
+  B     210b    Tile VRAM address  aaaabbbb a=Playfield 0   b=Playfield 1       
+  B     210c    Tile VRAM address  ccccdddd c=Playfield 2   d=Playfield 3       
+ 2B     210d    Plane 0 scroll x   8+3 bits (0-7ff) put first 8 bits and then
+ 2B     210e    Plane 0 scroll y   8+3 bits  (0-7ff)  3 highest bits
+ 2B     210f    Plane 1 scroll x                as above
+ 2B     2110    Plane 1 scroll y                as above
+ 2B     2111    Plane 2 scroll x                as above
+ 2B     2112    Plane 2 scroll y                as above
+ 2B     2113    Plane 3 scroll x                as above
+ 2B     2114    Plane 3 scroll y                as above
+ B      2115    Video port control
+ W      2116    Video port address (lo-hi)
+ W      2118    Video port data (lo-hi) (address is incremented by 2)
+ B      2121    Palette color nr
+ B      2122    Palette color data
+ B      212C    Playfield Enable xxxxabcd  a-d = playfield number..
+ B      2133    Screen mode  0000ab0c a=Interlace Y  b=Overscan  c=Interlace X??
+     2140-2142  Audio Registers
+
+I/O
+~~~
+W B     420b    Start dma (enable bits) bits: 76543210 = dma nr (8 DMA's)
+R B     4212    Pad ready to be read
+R W     4218    Pad 0 data      76543210 = A-B-Select-Start-U-D-L-R
+        4219                    76543210 = X-Y-Top Left-Top Right-0000
+R W     421a    Pad 1 data              as above 
+R W     421c    Pad 2 data              as above
+R W     421e    Pad 3 data              as above
+
+DMA registers  ($4300-$437f)
+~~~~~~~~~~~~~~~~~~~~~~~~~~~~
+  B     43X0    DMA control reg??(not sure!)
+  B     43X1    DMA destination (Access only to some of the video chip
+                    registers ($2100-$21ff)
+                    $18=video port  $22=color palette
+  W     43X2    Source address lo-hi  16 lowest bits
+  B     43X4    Source Bank addr. 8 highest bits
+  W     43X5    Transfer size lo-hi
+
+        X=dma number (0-7)  DMA #0= 4300-4305
+                            DMA #1= 4310-4315 ...
+                            DMA #7= 4370-4375
+
+ Symbols:  size: B=byte long    2B=put 2 bytes    W=word long
+             R=read only  W=write only
+
+Screen Details
+~~~~~~~~~~~~~~
+Famicom Tile format is simple. Each Tile is 4 planes and 8x8 bits.
+32 bytes are used per Tile .
+
+PLANES 1  &  2                  PLANES  3  &    4
+    byte0   byte1                  byte 16   byte 17  
+    byte2   byte3                  byte 18   byte 19
+    byte4   byte5                  byte 20   byte 21
+     .....                              .......
+    byte14  byte15                 byte 30   byte 31
+
+Screen Map
+~~~~~~~~~~
+Famicom can use only Tiles $0-$3ff, max 1024 chars.
+16 bits:   YX?c ccNN NNNN NNNN
+           fedc ba98 7654 3210
+
+  Y = mirror y     X = mirror x   ?=unknown
+  ccc = palette nr (8 palettes)   NN.. = character number
+
+Screen Resolution is normally 32x32 chars but only the first 30 y blocks are 
+visible (until scrolled) - 64 bytes / line
+
+Screen VRAM Location
+~~~~~~~~~~~~~~~~~~~~
+Screen Width 32x32 offset for x,y       0,0   = 0
+
+Screen Width 64x32 offset for x,y       0,0   = 0
+                                        33,0  = $400
+
+Screen Width 32x64 offset for x,y       0,0   = 0
+                                        0,33  = $400 
+
+Screen Width 64x64 offset for x,y       0,0   = 0
+                                        33,0  = $400
+                                        0,33  = $800
+                                        33,33 = $c00
+
+As can be seen if a wider mode is selected the extra height/width follow
+after the main screen in memory.
+
+=============================================================================

+ 139 - 0
files/docs/snes/memory_mapping_overview.txt

@@ -0,0 +1,139 @@
+SNES Memory Mapping
+by
+Duncanthrax of ShadowCraft
+
+Version: 1.0
+Date:	August 28, 1997
+
+Introduction:
+
+This is a little document I'm throwing together as I go. It probably has a few innacuracies, but it's certainly better than nothing. I became frustrated with the lack of solid knowledge and documentation regarding memory in the SNES, all the other maps were very incomplete. So, since I'm building an emulator at the moment, I figured I'd write all this down for posterity.
+
+If you find anything in here that is wrong, or if you have an additions or questions, or suggestions... or if you want to help with the emulator, mail me at:
+
+odin@ccs.neu.edu
+
+Or check out ShadowCraft's web page at:
+
+http://shadowguild.home.ml.org
+
+Have fun, and I hope this is helpful.
+
+*---------------------------------------------------*
+
+SNES Memory Map in LoROM Mode (Mode 0x20):
+
+Bank:	Address:	Purpose:
+-----	--------	--------
+00-3F	0000-1FFF	Shadow RAM
+	2000-5FFF	Hardware Registers
+	6000-7FFF	Expansion RAM
+	8000-FFFF	32k ROM Chunk
+40-7C	0000-7FFF	32k ROM Chunk
+	8000-FFFF	32k ROM Chunk
+7D	0000-FFFF	SRAM
+7E	0000-1FFF	Shadow RAM
+	2000-FFFF	System RAM
+7F	0000-FFFF	System RAM
+
+80-BF	0000-1FFF	Shadow RAM
+	2000-5FFF	Hardware Registers
+	6000-7FFF	Expansion RAM
+	8000-FFFF	32k ROM Chunk
+C0-FC	0000-7FFF	32k ROM Chunk
+	8000-FFFF	32k ROM Chunk
+FD	0000-FFFF	SRAM
+FE	0000-1FFF	Shadow RAM
+	2000-FFFF	System RAM
+FF	0000-FFxx	System RAM
+	FFxx-FFFF	Reset and NMI Vectors
+
+SNES Memory Map in HiROM Mode (Mode 0x21):
+
+Bank:	Address:	Purpose:
+-----	--------	--------
+00-3F	0000-1FFF	Shadow RAM
+	2000-5FFF	Hardware Registers
+	6000-7FFF	SRAM
+	8000-FFFF	32k ROM Chunk
+40-7D	0000-FFFF	64k ROM Chunk
+7E	0000-1FFF	Shadow RAM
+	2000-FFFF	System RAM
+7F	0000-FFFF	System RAM
+
+80-BF	0000-1FFF	Shadow RAM
+	2000-5FFF	Hardware Registers
+	6000-7FFF	SRAM
+	8000-FFFF	32k ROM Chunk
+C0-FE	0000-FFFF	64k ROM Chunk
+FF	0000-FFxx	64k ROM Chunk
+	FFxx-FFFF	Reset and NMI Vectors
+
+*--------------------------------------------*
+
+Now that I've given you the overview of the memory layout, perhaps a little explanation would be in order. We'll start at 00.0000 and work our way up... in LoROM first, then HiROM - to avoid confusion.
+
+00-3F	0000-1FFF	Shadow RAM
+
+What's going on here? Well, this is RAM that is the same in every bank up to and including 7E. It's the first 8k of System RAM. So, if you write 0x42 to 00.1001, you'll read a 0x42 from 7E.1001. Simple, huh?
+
+00-3F	2000-5FFF	Hardware Registers
+
+This is where you do graphics hardware calls, BIOS calls, DMA calls, and all that stuff. There are lots and lots of documents on this, all of them confusing. I may write one later on that clarifies a bunch of stuff, but for now I won't go into greater detail, as this is pretty straightforward... read and write values that interact with hardware.
+
+00-3F	6000-7FFF	Expansion RAM
+
+This is one of those areas in which I draw a blank. I'm not certain where this RAM is supposed to map, whether it is part of system RAM or what. Anybody who wants to clarify the purpose of this area of RAM can feel free. I've seen at least two cartridges that access this area...
+
+00-3F	8000-FFFF	32k ROM Chunk
+40-7C	0000-7FFF	32k ROM Chunk
+	8000-FFFF	32k ROM Chunk
+
+This bears a little explanation. When the LoROM is loaded into memory, this is where it is mapped (in a real SNES it isn't "loaded" at all - just mapped). The first 64 32k chunks are loaded into the upper half of banks 00-3F. Then, you continue at 40, mapping two (2!) 32k chunks in each bank from 40-7C. This should take care of an entire LoROM. I know that theoretically a LoROM could be slightly bigger than this, but I've never seen one that is...
+
+7D	0000-FFFF	SRAM
+
+OK, this is pretty obvious. This is where the battery-backed SRAM on cartridges is mapped. Very simple. Most have 64kb. DOOM, I've heard, has 256kb. Copiers have 256kb. Simple.
+
+7E	0000-1FFF	Shadow RAM
+	2000-FFFF	System RAM
+7F	0000-FFFF	System RAM
+
+Also very simple. This is the SNES's 128k of RAM. There, that was easy, right?
+
+80-FF	0000-FFFF	MIRROR!
+
+The upper area of the SNES's addressing space is for "Fast ROM". Games will use this area instead of the lower area (they're mapped exactly the same) when they want to run faster. The SNES gains 1Mhz of speed this way.
+
+The only thing that is different about the upper area is that the vectors for reset and NMI get stored in the FF.FFxx last 32 bytes...
+
+*-------------------------------------------*
+
+LoROM vs. HiROM!
+
+OK, this is the most interesting part of SNES mapping, and also the part where I'm most likely to get something wrong. As always, if this is incorrect or confusing, let me know!
+
+00-3F	0000-5FFF	Same as LoROM
+
+00-3F	6000-7FFF	8k SRAM Chunk
+
+00-3F	8000-FFFF	32k ROM Chunk
+40-7D	0000-FFFF	64k ROM Chunk
+
+Ok, this is not too hard, with one caveat... the first 64 32k chunks of the HiROM cartridge get loaded into 00-3F, and then it REPEATS FROM THE BEGINNING starting at 40.0000, this time going in 64k chunks until the end of the file. Now, people are about to start yelling about how this doesn't leave room for the last 2 64k chunks of a 32mb ROM. Yes, I know... keep reading.
+
+7E-7F	0000-FFFF	Same as LoROM
+
+Note 7D is no longer the SRAM, which is now in the expansion ram area.
+
+80-FD	0000-FFFF	Same as LoROM
+
+FE-FF	0000-FFFF	64k ROM Chunk
+
+Aha! Here it is... the last two chunks of a 32mb ROM (i.e. Chrono Trigger, etc.) get loaded here. Remember as always that the last 16 bytes are for vectors, and you're all set!
+
+*--------------------------------------------*
+
+Ok kiddies! That was a quick tour through the SNES memory map. Tune in next time for "Dr. Duncanthrax teaches CPU!" - same Bat Time, same Bat Channel!
+
+Fin

+ 129 - 0
files/docs/snes/memory_mapping_table.txt

@@ -0,0 +1,129 @@
+                      +=-=-=-=-=-=-=-=-=-=-=+
+                      | SNES Memory Mapping |
+                      |    By: ]SiMKiN[     |
+                      |         v2.0        |
+                      +=-=-=-=-=-=-=-=-=-=-=+
+
+
+• FastROM's can execute at 3.58Mhz
+• SlowROM's can only execute 2.68Mhz
+
+  • The SNES lets you access ROM through bank $00 onwards and bank 
+    $80 onwards such that locations $00:8000 and $80:8000 are congruent,
+    (they access the same locations.)
+  • When accessing bank $00 onwards the 65816 runs at 2.68Mhz. However, 
+    when accessing bank $80 onwards the 65816 can run at 2.68Mhz or 
+    3.58Mhz depending on how you set bit 0 of $420D.
+
+  • This Document Contains Information Regarding ROM's upto 32mbit.
+    If you have any information regarding ROM's above 32mbit please send
+    E-Mail to 'simkin@innocent.com'
+
++======================================================================+
+| Mode 20: LoROM Memory Model (32k Banks)                              |
+| ---------------------------------------                              |
+|  • $80-$ef : $8000-$ffff                                             |
+|              Mirrored to $00-6f                                      |
+|  • $f0-$ff : $8000-$ffff                                             |
++=========+=============+====================================+=========+
+| Bank    | Offset      | Definition                         | Shadow  |
++=========+=============+====================================+=========+
+| $00-$2f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | RESERVED                           | $00-$3f |
+|         | $8000-$ffff | (Mode 20 ROM)                      | ------- |
++---------+-------------+------------------------------------+---------+
+| $30-$3f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | RESERVED                           | ------- |
+|         | $8000-$ffff | (Mode 20 ROM)                      | $80-$bf |
++---------+-------------+------------------------------------+---------+
+| $40-$6f | $0000-$7fff | RESERVED                           | ------- |
+|         | $8000-$ffff | (Mode 20 ROM)                      | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $70-$77 | $0000-$ffff | (Mode 20 SRAM) 256KBytes           | ------- |
++---------+-------------+------------------------------------+---------+
+| $78-$7d | $0000-$ffff | RESERVED                           | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7e   | $0000-$1fff | LowRAM                             | $00-$3f |
+|         | $2000-$7fff | HighRAM                            | ------- |
+|         | $8000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7f   | $0000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+| $80-$ef | $0000-$ffff | Mirror of $00-$6f                  | $00-$6f |
++---------+-------------+------------------------------------+---------+
+| $f0-$ff | $0000-$7fff | RESERVED                           | ------- |
+|         | $8000-$ffff | (Mode 20 ROM)                      | ------- |
++=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
+
++======================================================================+
+| Mode 21: HiROM Memory Model (64k Banks)                              |
+| ---------------------------------------                              |
+|  • $C0-$ff : $0000-$ffff                                             |
+|              High Parts ONLY '($8000-$ffff)' are Shadowed to $00-3f  |
++=========+=============+====================================+=========+
+| Bank    | Offset      | Definition                         | Shadow  |
++=========+=============+====================================+=========+
+| $00-$2f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | RESERVED                           | $00-$3f |
+|         | $8000-$ffff | (Mode 21 ROM) from $C0-$EF         | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $30-$3f | $0000-$1fff | LowRAM, shadowed from $7e          |   $7e   |
+|         | $2000-$2fff | PPU1, APU                          | $00-$3f |
+|         | $3000-$3fff | SFX, DSP, etc.                     | $00-$3f |
+|         | $4000-$41ff | Controller                         | $00-$3f |
+|         | $4200-$5fff | PPU2, DMA, etc.                    | $00-$3f |
+|         | $6000-$7fff | (Mode 21 SRAM) 256KBytes           | ------- |
+|         | $8000-$ffff | (Mode 21 ROM) from $C0-$EF         | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $40-$6f | $0000-$7fff | (Mode 21 ROM) from $C0-$EF         | $C0-$EF |
++---------+-------------+------------------------------------+---------+
+| $70-$77 | $0000-$ffff | (Mode 20 SRAM) 256KBytes           | ------- |
++---------+-------------+------------------------------------+---------+
+| $78-$7d | $0000-$ffff | RESERVED                           | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7e   | $0000-$1fff | LowRAM                             | $00-$3f |
+|         | $2000-$7fff | HighRAM                            | ------- |
+|         | $8000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+|   $7f   | $0000-$ffff | Expanded RAM                       | ------- |
++---------+-------------+------------------------------------+---------+
+| $80-$bf | $0000-$ffff | Mirror of $00-$3f                  | $00-$3f |
++---------+-------------+------------------------------------+---------+
+| $c0-$ff | $0000-$ffff | (Mode 21 ROM)                      | ------- |
++=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-=-+
+
+• ROM: The SNES ROM Image
+• RAM: The SNES Work Memory (WRAM)
+       LowRAM, HighRAM, & Expanded RAM 
+       All together = 128 Kilo-Bytes
+• SRAM: Save RAM (Extra RAM added by Cart)
+        The SNES only utilizes 256 Kilo-bits
+        However 256 Kilo-Bytes are provided.
+
+• APU: Audio Processing Unit
+       SPC700, Inside which has a DSP   
+• PPU: Picture Processing Unit
+       PPU1: 5c77-01
+       PPU2: 5c78-03
+
+• SFX: Super FX Cart Chip, by Nintendo
+• DSP: Digital Signal Processing Cart Chip
+       a.k.a. 'NEC mUPD77C25'
+
+• Shadow: "Congruent Bank".  Same meaning as Mirror.
+
+          _____________________________________________________
+       .o(_Thanx to: zsKnight, Lord Esnes, Y0SHi, and MintaBoo_)o.
+

+ 1385 - 0
files/docs/snes/mmio.txt

@@ -0,0 +1,1385 @@
+I have no idea where this document came from (EPR? Who knows..), there's no credits anywhere
+or anything... weird.  Anyways, it was really hard with my eyes so I told Wordperfect to convert it
+to  initial caps' since there was no  Capitalize the first word of each line or sentence and leave
+abbreviations the way they are' option.
+     - Qwertie
+
+Address  : $2100
+Name     : Inidisp
+Contents : Initial Settings for Screen
+
+     D7   Blanking:
+               Forced Blanking, 0:non-blanking,1:blanking.
+
+        D6-d4   ---
+
+        D3-d0   Fade In/out:
+               0000-darkest,1111-brightest.
+
+
+Address  : $2101
+Name     : Obsel
+Contents : Object Size & Object Data Area Designation
+
+     D7-d5     Size Select:
+               D7 D6 D5   0   1  (Size Large/small)
+                0  0  0   8  16
+                0  0  1   8  32
+                0  1  0   8  64
+                0  1  1  16  32
+                1  0  0  16  64
+                1  0  1  32  64 (Dots.)
+
+     D4-d3     Name Select
+               The Upper 4k-word Out of the Area (8k-word)
+               Designated by "Object Base Address" is Assigned
+               As the Base Area, and the Area of the Lower 4k-
+               Word Combined with its Base Area Can Be
+               Selected. (See Appendix 1 & 2)
+
+     D2-d0     Name Base Select (Upper-3 Bit)
+               Designate the Segment (8k-word) Address Which
+               The Obj Data is Stored in Vram.    (Appendix 1 & 2)
+
+
+Address  : $2102/$2103
+Name     : Oamaddl/oamaddh
+Contents : Address for Accessing Oam
+
+     D7-d0     Oam Address (A7-a0)                2102h
+
+     D7   Oam Priority Rotation                   2103h
+     D6-d1     ---
+     D0   Oam Address Msb (A8)
+
+          This is the Initial Address to Be Set in Advance When Reading
+       Reading From the Oam Or Writing to the Oam.
+
+          By Writing "1" to D7 of Register <2103h> and Setting the Oam-
+       Address the Obj for the Address Set Has Highest Priority.
+
+          The Address Which Has Been Set Just Before Every Field
+       (Beginning of V-blank) Will Be Set Again to Registers <2102h>
+       <2103h> Automatically. But, the Address Can Not Be Set
+       Automatically During Forced Blank Period.
+
+
+Address  : $2104
+Name     : Oamdata
+Contents : Data for Oam Write
+
+     D7-d0     Oam Data (Low,high)
+
+          This is the Oam Data to Be Writting At Any Address of the Oam.
+       (See Appendix-3)
+
+          After Register <2102h> Or <2103h> is Accessed, the Data Must
+       Be Written in the Order of Lower 8-bit & Upper 8-bit of Register
+       <2104h>.
+
+          The Data Can Be Written Only During V-blank Or Forced Blank
+       Period.
+
+
+Address  : $2105
+Name     : Bgmode
+Contents : Bg Mode & Character Size Settings
+
+     D7-d4     Bg Size Designation (Bg4-bg1)
+               0:   8 X  8 Dot/character
+               1:  16 X 16 Dot/character
+
+     D3   Highest Priority Designation for Bg-3 in Mode 1
+               0: Off (See Appendix-16)
+               1: on
+
+     D2-d0     Bg Screen Mode Select (See Appendix-5)
+
+
+Address  : $2106
+Name     : Mosaic
+Contents : Size & Screen Designation for Mosaic Display
+
+     D7-d4     Mosaic Size (See Appendix-6)
+               1111 - Largest, 0000 - Smallest.
+
+     D3-d0     Mosaic Enable (Bg4-b1)
+               0: Off
+               1: on
+
+
+Address  : $2107/$2108/$2109/$210a
+Name     : Bg1sc/bg2sc/bg3sc/bg4sc
+Contents : Address for Storing Sc-data of Each Bg & Sc Size Designation
+
+     D7-d2     Sc Base Address
+               Designate the Segment Which Bg-sc in the Vram
+               Is Stored. (1k-word/segment)
+
+     D1-d0     Sc Size
+               Designate Background Screen Size (Appendix-18 & 19)
+               0 0  0 0    1 0  0 0    0 1  0 1    1 1  0 1
+                    0 0         1 1         0 1         2 3
+
+
+Address  : $210b/$210c
+Name     : Bg12nba/bg34nba
+Contents : Bg Character Data Are Designation
+
+     D7-d4     Bg2 Base Address                   210bh
+     D3-d0     Bg1 Base Address
+
+     D7-d4     Bg4 Base Address                   210ch
+     D3-d0     Bg3 Base Address
+
+          Background Name Base Address (Upper 4-bit), Segment Address
+       In the Vram Where Bg Character Data is Stored. (4k-word/segment)
+
+
+Address  : $210d/$210e/$210f/$2110/$2111/$2112/$2113/$2114
+Name     : Bg1hofs/bg1vofs/bg2hofs/bg2vofs/bg3hofs/bg3vofs/bg4hofs/bg4vofs
+Contents : H/v Scroll Value Designation for Bg
+
+     D7-d0     H-offset (Low,high)                Hofs
+
+     D7-d0     V-offset (Low,high)                Vofs
+
+          10 Bit Maximum (0-1023) Can Be Designated for H/v Scroll Value.
+       [The Size of 13-bit Maximum (-4096->4095) Can Be Designated in
+       Mode 7] (See Appendix-8 & 9)
+
+          By Writing to the Register Twice, the Data Can Be Set in Order
+       Of Low & High.
+
+
+Address  : $2115
+Name     : Vmain
+Contents : Vram Address Increment Value Designation
+
+     D7   H/l Inc (Word Or Byte Vram Access)
+
+               Designate the Increment Timing for the Address
+               0: the Address Will Be Increased After the Data Has
+                  Been Written to Register <2118h> Or the Data
+                  Has Been Read From Register <2139h>.
+                  This Will Result in Byte Vram Access, I.e. for
+                  Mode 7 Tile Map Change.
+
+               1: the Address Will Be Increased After the Data Has
+                  Been Written to Register <2119h> Or the Data
+                  Has Been Read From Register <213ah>.
+                  This Will Result in Word Vram Access, I.e. for
+                  Mode 1 Tile Map Change.
+
+     D6-d4     ---
+
+     D3-d2     Full Graphic (G1 & G0)
+
+     D1-d0     Sc Increment (I1 & I0)
+
+
+     G1 G0 I1 I0 | Increment Value
+     ----------------------------
+      0  1  0  0 | Increment by 8 for 32 Times (2-bit Formation)
+      1  0  0  0 | Increment by 8 for 64 Times (4-bit Formation)
+      1  1  0  0 | Increment by 8 for 128 Times (8-bit Formation)
+      0  0  0  0 | Address Increments 1 by 1
+      0  0  0  1 | Address Increments 32 by 32
+      0  0  1  0 | Address Increments 64 by 64
+      0  0  1  1 | Address Increments 128 by 128
+
+
+Address  : $2116/$2117
+Name     : Vmaddl/vmaddh
+Contents : Address for Vram Read
+
+     D7-d0     Vram Address (Low)                 2116h
+     D7-d0     Vram Address (High)                2117h
+
+          This is the Initial Address for Reading From the Vram Or Writing
+       To the Vram.
+
+          The Data is Read Or Written by the Address Set Initially, and
+       Every Time the Data is Read the Address Wil Be Increased
+       Automatically.
+
+          The Value to Be Increased is Determined by "Sc Increment" of
+       Register <2115h> and the Setting Value of the "Full Graphic".
+
+
+Address  : $2118/$2119
+Name     : Vmdatal/vmdatah
+Contents : Data for Vram Write
+
+     D7-d0     Vram Data (Low)                         2118h
+     D7-d0     Vram Data (High)                   2119h
+
+          This is the Screen Data and Character Data (Bg & Obj), Which
+       Can Write At Any Address of the Vram.
+
+          According to the Setting of Register <2115h> "H/l Inc.", the
+       Data Can Be Written to the Vram As Follows:
+
+     H/l Inc  |  Write to Register  |  Operation
+        --------------------------------------------------------------
+         0    |  Write to <2118h>   |  the Data is Written to Lower 8bit
+              |  Only.              |  of the Vram & the Address Will Be
+           |                     |  Increased Automatically.
+         1    |  Write to <2119h>   |  the Data is Written to Upper 8bit
+              |  Only.              |  of the Vram & the Address Will Be
+              |                     |  Increased Automatically.
+         0    |  Write in Order of  |  When the Data is Set in the Order
+              |  <2119h> & <2118h>  |  of Upper & Lower the Address Will
+              |                     |  Be Increased.
+         1    |  Write in Order of  |  When the Data is Set in the Order
+              |  <2118h> & <2119h>  |  of Lower & Upper the Address Will
+              |                     |  Be Increased.
+
+     Note:     the Data Can Only Be Written During V-blank Or Forced Blank
+     ~~~~~     Period.
+
+
+Address  : $211a
+Name     : M7sel
+Contents : Initial Setting in Screen Mode-7
+
+     D7-d6     Screen Over (O1 & O0)
+               Process Made If the Screen to Be Displayed is
+               Outside of the Screen Area. (See Below)
+
+     D5-d2     ---
+
+     D1-d0     Screen Flip (V/h)
+               0: Normal
+               1: Flipped
+
+     O1 O0  |  Process Out of Area
+        --------------------------------------------------------------
+      0  0  |  Screen Repetition If Outside of Screen Area
+      1  0  |  Character 0x00 Repetition If Outside of Screen Area
+      1  1  |  Outside of the Screen Area is the Back Drop Screen in
+            |  Single Color
+
+
+Address  : $211b/$211c/$211d/$211e/$211f/$2120
+Name     : M7a/m7b/m7c/m7d/m7x/m7y
+Contents : Rotation/enlargement/reduction in Mode-7, Center Coordinate
+        Settings & Multiplicand/multiplier Settings of Complementary
+        Multiplication.
+
+     D7-d0     Matrix Parameter A (Low[mp7-mp0],High[mp15-mp8])211bh
+     D7-d0     Matrix Parameter B (Low[mp7-mp0],High[mp15-mp8])211ch
+     D7-d0     Matrix Parameter C (Low[mp7-mp0],High[mp15-mp8])211dh
+     D7-d0     Matrix Parameter D (Low[mp7-mp0],High[mp15-mp8])211eh
+
+          The 8-bit Data Should Be Written Twice in the Order of Lower &
+       Upper. Then, the Parameter of Rotation, Enlargement and Reduction
+       Should Be Set by its 16-bit Area.
+
+          The Value Down to A Decimal Point Should Be Set to the Lower
+       8-bit. The Most Significant Bit of the Upper 8-bit is for the
+       Signed Bit. (Mp15 is the Signed Bit. There is A Decimal Point
+       Between M7 & M8)
+
+          Formula for Rotaion/enlargement/reduction (See Appendix-13)
+
+          / X2 \   / A B \ / X1-x0 \   / X0 \
+          |    | = |     | |       | + |    |
+          \ Y2 /   \ C D / \ Y1-y0 /   \ Y0 /
+
+       A=cos(gamma)*(1/alpha), B=sin(gamma)*(1/alpha)
+       C=-sin(gamma)*(1/beta), D=cos(gamma)*(1/beta)
+
+          Gamma: Rotation Angle
+          Alpha: Reduction Rates for X(h)
+          Beta : Reduction Rates for Y(v)
+          X0&y0: Center Coordinate
+          X1&y1: Display Coordinate
+          X2&y2: Coordinate Before Calculation
+
+          Set the Value of "A" to Register <211bh>. In the Same Way,
+       Set "B-d" to the Registers <211ch>-<211eh>.
+
+     * the Complementary Multiplication (16bit X 8bit) Can Be Done by
+       Using Registers <211bh> <211c>.
+       When Setting 16 Bit Data to Register <211bh> and 8bit Data to
+       Register <211ch>, the Multiplication Result Can Be Indicated
+       Rapidly by Reading Registers <2134h>-<2136h>.
+
+     D7-d0     Center Position X0 (Low[x7-x0],High[x12-x8]) 211fh
+     D7-d0     Center Position Y0 (Low[y7-x0],High[y12-x8]) 2120h
+
+          The Center Coordinate (X0,y0) for Rotation/enlargement/reduction
+       Can Be Designated by this Register.
+
+          The Coordinate Value of X0 & Y0 Can Be Designated by 13-bit
+       (Complement of 2).
+
+          The Register Requires That the Lower 8-bit is Set First and the
+       Upper 5-bit is Set. Therefore, 13-bit Data in Total Can Be Set.
+
+
+Address  : $2121
+Name     : Cgadd
+Contents : Address for Cg-ram Write
+
+     D7-d0     Cg-ram Address
+
+          This is the Initial Address for Reading From the Cg-ram Or
+       Writing to the Cg-ram
+
+          The Data is Read by the Address Set Initially, and Every Time
+       The Data is Read Or Written the Address Will Be Increased
+       Automatically.
+
+
+Address  : $2122
+Name     : Cgdata
+Contents : Data for Cg-ram Write
+
+     D7-d0     Cg-ram Data (Low[d7-d0],High[d14-d8])
+
+          This is the Color Generater Data to Be Written At Any Address
+       Of the Cg-ram.
+
+          The Mapping of Bg1-bg4 and Obj Data in Cg-ram Will Be Determined,
+       Which is Performed by Every Mode Selected by "Bg Mode" of
+       Register <2105h>. (See Appendix-14)
+
+          There Area the Color Data of 8-palettes for Each Screen of
+       Bg1-bg4. The Palette Selection is Determined by 3-bit of the
+       Sc Data "Color"
+
+          Because the Cg-ram Data is 15-bit/word, it is Necessary to Set
+       Lower 8-bit First to this Register and the the Upper 7-bit.
+       When Both Lower & Upper Are Set, the Address Will Be Increased
+       By 1 Automatically.
+
+     Note:     After the Address is Set, the Data Should Be Written From
+     ~~~~~     the Lower As Well As the Oam.
+
+     Note:     the Data Can Be Written Only During H/v Blank Or Forced-
+     ~~~~~     Blank Period.
+
+
+Address  : $2123/$2124/$2125
+Name     : W12sel/w34sel/wobjsel
+Contents : Window Mask Settins (Bg1-bg4, Obj, Color)
+
+     D7   Bg2 Window-2 Enable                2123h
+               0: Off
+               1: on
+
+     D6   Bg2 Window-2 In/out
+               The Window Mask Area Can Be Designated Whether
+               Inside Or Outside of the Frame Designated by the
+               Window Position.
+               0: in
+               1: Out
+
+     D5   Bg2 Window-1 Enable
+     D4   Bg2 Window-1 In/out
+     D3   Bg1 Window-2 Enable
+     D2   Bg1 Window-2 In/out
+     D1   Bg1 Window-1 Enable
+     D0   Bg1 Window-1 In/out
+
+     D7   Color Window-2 Enable                   2125h
+     D6   Color Window-2 In/out
+     D5   Color Window-1 Enable
+     D4   Color Window-1 In/out
+     D3   Obj Window-2 Enable
+     D2   Obj Window-2 In/out
+     D1   Obj Window-1 Enable
+     D0   Obj Window-1 In/out
+
+          The Color Window is A Window for Main & Sub Screen (It is
+       Related to Register <2130h>.
+
+
+Address  : $2126/$2127/$2128/$2129
+Name     : Wh0/wh1/wh2/wh3
+Contents : Window Position Designation (See Appendix-15)
+
+     D7-d0     Window Pposition
+
+     H0,h2     Left Position Designation
+     H1,h3     Right Position Designation
+
+     Note:     If "Left Position Setting Value > Right Position Value"
+     ~~~~~     is Assumed, There Will Be No Range of the Window.
+
+
+Address  : $212a/$212b
+Name     : Wbglog/wobjlog
+Contents : Mask Logic Settings for Window-1 & 2 on Each Screen
+
+     D7-d6     Bg4 D1/d0                     212ah
+     D5-d4     Bg3 D1/d0
+     D3-d2     Bg2 D1/d0
+     D1-d0     Bg1 D1/d0
+
+     D7-d4     ---                           212bh
+     D3-d2     Colorwindow D1/d0
+     D1-d0     Objwindow D1/d0
+
+          D1 D0  |  Logic
+             ------------------
+           0  0  |  Or
+           0  1  |  and
+           1  0  |  Xor
+           1  1  |  Xnor
+
+     Note:     "In/out" of Registers <2123h>-<2125h> Becomes the
+     ~~~~~     "Not-logic" for Each Window-1 & Window-2.
+
+
+Address  : $212c
+Name     : Tm
+Contents : Main Screen, Designation
+
+
+     D7-d5     ---
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+
+     Main Screen Designation:
+
+          Designate the Screen (Bg1-bg4, Obj) to Be Displayed
+          As the Main Screen. Designate the Screen to Be Added
+          for the Screen Addition/subtraction
+
+               0: Disable
+               1: Enable
+
+
+Address  : $212d
+Name     : Ts
+Contents : Sub Screen Designation
+
+     D7-d5     ---
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+
+     Sub Screen Designation:
+
+          Designate the Screen (Bg1-bg4, Obj) to Be Displayed
+          As Sub Screen. Designate the Addition/subtraction
+          Screen At the Point When the Screen Addition/subtraction
+          is Functioning.
+
+               0: Disable
+               1: Enable
+
+     * When the Screen Addition/subtraction is Functioning, the Sub
+       Screen is A Screen to Be Added Or Subtracted Against the Main
+       Screen.
+
+
+Address  : $212e
+Name     : Tmw
+Contents : Window Mask Designation for Main Screen
+
+
+     D7-d5     ---
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+
+     Window Mask Designation for Main Screen:
+
+          In the Window Area Designated by Register <2123h>-<2129h>,
+          the Screen to Be Displayed Can Be Designated, Which is
+          Selected Among the Main Screen Designated by Register
+          <212ch>.
+
+               0: Disable
+               1: Enable
+
+
+Address  : $212f
+Name     : Tsw
+Contents : Window Mask Designation for Sub Screen
+
+     D7-d5     ---
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+
+     Window Mask Designation for Sub Screen:
+
+          In the Window Area Designated by Register <2123h>-<2129h>,
+          the Screen to Be Displayed Can Be Designated, Which is
+          Selected Among the Sub Screen Designated by Register
+          <212ch>.
+
+               0: Disable
+               1: Enable
+
+     * When the Screen Addition/subtraction is Functioning, the Sub
+       Screen is A Screen to Be Added Or Subtracted Against the Main
+       Screen.
+
+
+Address  : $2130
+Name     : Cgwsel
+Contents : Initial Settings for Fixed Color Addition Or Screen Addition
+
+     D7-d6     Main Sw (M1/m0)
+     D5-d4     Sub Sw (S1/s0)
+     D3-d2     ---
+     D1   Cc Add Enable, Fixed Color Addition/subtraction Enable
+               Designate Whether 2 Kinds of the Data Should
+               Be Added/subtracted Each Other Or Not, Which Are
+               The Fixed Color Set by Register <2132h>, and
+               The Color Data Which is Set to Cgram.
+                    0: Addition/subtraction for Fixed Color
+                    1: Addition/subtraction for Sub Screen
+
+     D0   Direct Select (See Appendix-14)
+               The Vram Data (Color & Character Data) Become the
+               Color Data Directly. [Only When Mode-3,4 & 7]
+                    0: Disable
+                    1: Enable
+
+
+     M1(s1) M0(s0)  |  Normal Display Is:
+     --------------------------------------------------------------
+       0      0     |  All the Time
+       0      1     |  Inside Window Only
+       1      0     |  Outside Window Only
+       1      1     |  All the Time
+
+
+Address  : $2131
+Name     : Cgadsub
+Contents : Addition/subtraction & Subtraction Designation for Each Screen,
+        Obj & Background Color
+
+     D7   Color Data Addition/subtraction Select
+               Designate the Selection Either of the Addition
+               Or the Subtraction Mode.
+                    0: Addition Mode Select
+                    1: Subtraction Mode Select
+
+     D6   "1/2 of Color Data" Designation
+               When the Color Constant Addition/subtraction Or the
+               Screen Addition/subtraction is Performed, Designate
+               Whether the Rgb Result in the Addition/subtraction
+               Area Should Be "1/2" Or Not. However, in the Back
+               Color Constant Area on the Sub Screen, it Does Not
+               Become "1/2"
+                    0: Disable
+                    1: Enable
+     D5   Back
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+               Color Data Addition/subtraction Enable
+                    0: Disable
+                    1: Enable
+
+
+Address  : $2132
+Name     : Coldata
+Contents : Fixed Color Data for Fixed Color Addition/subtraction
+
+     D7   Blue
+     D6   Green
+     D5   Red
+               Bit for Selecting Desired Color
+
+     D4-d0     Color Brilliance Data
+               Set the Color Constant Data for Color Constant
+               Addition/subtraction
+
+     * R/g/b Brightness Should Be Set by the Data of Each 5-bit.
+
+          [Example] Red   : C0h, 3fh (B=00h, G=00h, R=1fh)
+                    Green : A0h, 5fh (B=00h, G=1fh, R=00h)
+                    Blue  : 60h, 9fh (B=1fh, G=00h, R=00h)
+                    White : Ffh
+                    Black : 00h
+
+
+Address  : $2133
+Name     : Setini
+Contents : Screen Initial Setting
+
+     D7   External Synchronization
+               It is Used for Super Impose and Etc. Normally,
+               "0" Should Be Written.
+
+     D6   Extbg Mode (Screen Expand)
+               Enable the Data Supplied From the External Lsi.
+               For the Sfx, Enable When the Screen with Priority
+               Is Used on Mode-7.
+
+     D5-d4     ---
+
+     D3   Horizontal Pseudo 512 Mode
+               512 Imaginary Resolution (Horizontal Can Be Made
+               By Shifting the Subscreen Half Dot to the Left.)
+                    0: Disable
+                    1: Enable
+
+     D2   Bg V-direction Display
+               Switch the Display Line of A Field to 224 Line Or
+               239 Line. (In Case of Interalace it Will Be
+               Doubled Dot.)
+                    0: 224 Line
+                    1: 239 Line
+
+     D1   Obj V-direction Display
+               In the Interlace Mode, Select Either of 1-dot Per
+               Line Or 1-dot Repeated Every 2-lines. If "1" is
+               Written, the Obj Seems Reduced Half Vertically in
+               Appearance.
+
+     D0   Scanning
+               Interlace/non-interlace Selection (It Relates to
+               <2105h>.
+                    0: Non Interlace
+                    1: Interlace
+
+
+Address  : $2134/$2135/$2136
+Name     : *Mpyl/*mpym/*mpyh
+Contents : Multiplication Result
+
+     D7-d0     Mpy (Low)                     2134h
+     D7-d0     Mpy (Mid)                     2135h
+     D7-d0     Mpy (High)                         2136h
+
+          This is A Multiplication Result (Complement of 2) Can Be Read
+       By Setting 16-bit to Register <211bh> and Setting 8 Bit to
+       Register <211ch>
+
+
+Address  : $2137
+Name     : *Slhv
+Contents : Software Latch for H/v Counter
+
+     D7-d0     Soft Latch for H/v Counter
+
+          This is A Register, Which Generate the Pulse for Latching the H/v
+       Counter Value.
+
+          The H/v Counter Value At the Point When Register <2137h> is Read
+       Can Be Latched. The Data Which Was Read is Meaningless Data.
+
+          The H/v Counter Value Latched Can Be Reffered by Registers
+       <213ch> & <213dh>.
+
+
+Address  : $2138
+Name     : Oamdataread (Name Differs From Snes Manual)
+Contents : Read Data From Oam
+
+     D7-d0     Oam Data (Low,high)
+
+          This is A Register, Which Can Read the Data At Any Address of
+       The Oam.
+
+         When the Address is Set to Register <2102h><2103h> and Register
+       <2138h> is Also Accessed the Data Can Be Read in the Order of
+       Low 8-bit/high 8-bit.
+       Afterward, the Address Will Be Increased Automatically, and the
+       Data of the Next Address Can Be Read.
+
+     Note:     the Data Can Be Read Only During H/v Blank Or Forced
+     ~~~~~     Blank Period.
+
+
+Address  : $2139/$213a
+Name     : Vmdatalread/vmdatahread (Names Differ From Snes Manual)
+Contents : Read Data From Vram
+
+     D7-d0     Vram Data (Low)                         2139h
+     D7-d0     Vram Data (High)                   213ah
+
+          This is A Register, Which Can Read the Data At Any Address of
+       The Vram.
+
+          The Initial Address Should Be Set by Registers <2116h> and
+       <2117h>. The Data Can Be Read by the Address Which Has Been Set
+       Initially.
+
+          When Reading the Data Continously, the First Data for the Address
+       Increment Should Be Read As A Dummy Data After the Address Has
+       Been Set.
+
+          Quantity to Be Increased Will Be Determined by "Sc Increment" of
+       Register <2115h> and the Setting Value of the "Full Graphic".
+
+     Note:     the Data Can Be Read Only During H/v Blank Or Forced
+     ~~~~~     Blank Period.
+
+
+Address  : $213b
+Name     : Cgdataread (Name Differs From Snes Manual)
+Contents : Read Data From Cg-ram
+
+     D7-d0     Cg Data (Low,high)
+
+          This is A Register, Which Can Read the Data At Any Address of
+       The Cg-ram.
+
+          The Initial Address Should Be Set by Register <2121h>. The Lower
+       8-bit is Read First, and the the Upper 7-bit Will Be Read by
+       Accessing this Register. The Current Address Will Be Increased
+       To the Next Address At the Same Time the Upper 7-bit is Read.
+
+     Note:     the Data Can Be Read Only During H/v Blank Or Forced
+     ~~~~~     Blank Period.
+
+
+Address  : $213c/$213d
+Name     : *Ophct/*opvct
+Contents : H/v Counter Data by External Or Software Latch
+
+     D7-d0     Output Data of H-counter [9-bit]        213ch
+     D7-d0     Output Data of V-counter [9-bit]        213dh
+
+          The H/v Counter is Latched by Reading Register <2137h>, and its
+       H/v Counter Value Can Be Read by this Register.
+
+          The H/v Counter is Also Latched by the External Latch, and its
+       Value Can Be Read by this Register.
+
+          If Register <213ch> Or <213dh> is Read After Register <213fh> Has
+       Been Read, the Lower 8-bit Data Will Be Read First, and Then the
+       Upper 1-bit Will Be Read by Reading the Register.
+
+
+Address  : $213e
+Name     : *Stat77
+Contents : Ppu Status Flag & Version Number
+
+     D7   Time Over  \
+     D6   Range Over /
+               Obj Display Status (On A Horizontal Line)
+               Range:    When Quantity of the Obj (Regardless of
+                    The Size) Becomes 33 Pcs Or More, "1"
+                    Will Be Set.
+               Time:     When Quantity of the Obj Which is Converted
+                    To "8 X 8-size" is 35 Pcs Or More, "1"
+                    Will Be Set.
+
+     D5   Master/slave Mode Select. Lsi Mode (Normally "0" is Set.)
+
+     D4   ---
+
+     D3-d0     5c77 Version Number
+
+     Note:     the Flag Will Be Reset At the End of the V-blank Period.
+     ~~~~~
+
+
+Address  : $213f
+Name     : *Stat78
+Contents : Ppu Status Flag & Version Number
+
+     D7   Field
+               This is A Status Flag, Which Indicated Whether 1st
+               Field is Scanned Or 2nd Field is Scanned in Inter-
+               Lace Mode. (The Definition is Different From the
+               Field of Ntsc.)
+                    0: 1st Field
+                    1: 2nd Field
+
+     D6   External Latch Flag
+               When the External Signal (Light Pen, Etc.) Is
+               Applied, it Enables to Latch the H/v Counter Value.
+
+     D5   ---
+
+     D4   Ntsc/pal Mode
+                    0: Ntsc
+                    1: Pal
+
+     D3-d0     5c78 Version Number
+
+     Note:     When this Register is Read, Registers <213ch><213dh> Will
+     ~~~~~     Be Initialized Individually in the Order of Low & High.
+
+
+Address  : $2140/$2141/$2142/$2143
+Name     : Apui00/apui01/apui02/apui03
+Contents : Communication Port with Apu
+
+     D7-d0     Apu I/o Port
+
+          This Port Provides More Registers for the Purpose of In/out,
+       Which Are 8 Registers in Total in the Apu. Therefore, the
+       Different Register Will Be Accessed, Whether Reading Or
+       Writing for the Same Address.
+
+          See "Apu Manual" for the Details of the Communication Method.
+
+
+Address  : $2180
+Name     : Wmdata
+Contents : Data to Consecutivley Read From and Write to Wram
+
+     D7-d0     Work Ram Data
+
+          Data to Consecutivley Read From and Write to Wram
+
+          Data is Read and Written At Address Set by Register <2181h>-<2183h>,
+       And Address Automatically Increases Each Time Data is Read Or Written.
+
+
+Address  : $2181/$2182/$2183
+Name     : Wmaddl/wmaddm/wmaddh
+Contents : Address to Consecutively Read and Write Wram
+
+     D7-d0     Wram Data (Low)                         2181h
+     D7-d0     Wram Data (Mid)                         2182h
+     D0   Wram Data (High)                   2183h
+
+          Address to Be Set Before Wram is Consecutivley Read Or Written.
+
+          A0 Trough A16 At Register <2181h>-<2183h> is Lower 17 Bit Address
+       To Show Address $7e0000-$7fffff in Memory.
+
+
+Address  : $4200
+Name     : Nmitimen
+Contents : Enable Flag for V-blank, Timer Interrupt & Joy Controller Read
+
+     D7   Nmi Enable
+               Enable Nmi At the Point When V-blank Begins
+               (When Power is Turned on Or the Reset Signal is
+               Applied, it Will Be "0".)
+                    0: Nmi Disabled
+                    1: Nmi Enabled
+
+     D6   ---
+
+     D5-d4     Timer Enable (V-en/h-en)
+
+     D3-d1     ---
+
+     D0   Joy-c Enable
+               0: Disable Automatic Reading of the Joy-controller.
+               1: Enable Automatic Reading of the Joy-controller.
+
+     V-en H-en  |  Function
+     --------------------------------------------------------
+        0    0  |  Disable Both H & V
+        0    1  |  Enable H Only, Irq Applied by H-count Timer Value Designated
+        1    0  |  Enable V Only, Irq Applied by V-count Timer Value Designated
+        1    1  |  Enable Both V & H, Irq Applied by Both H & V Count Timer Val
+                |  Designated.
+
+     * Reading the Data Can Be Started At the Beginning of V-blank
+       Period, But it Takes About for 3 Or 4 Scanning Period Until
+       Completion of Reading.
+
+
+Address  : $4201
+Name     : Wrio
+Contents : Programmable I/o Port (Out-port)
+
+     D7-d0     I/o Port
+
+          This is A Programmable I/o Port (Out-port). The Written Data
+       Will Be Output Directly From the Out-port.
+
+          When this is Used As A Inport. "1" Should Be Written to the
+       Particular Bit Which Will Be Used As in Port. The Input Can
+       Be Read by Register <4213h>.
+
+
+Address  : $4202/$4203
+Name     : Wrmpya/wrmpyb
+Contents : Multiplier & Multiplicand by Multiplication
+
+     D7-d0     Multiplicand-a                     4202h
+     D7-d0     Multiplier-b                       4203h
+
+          This is A Register, Which Can Set A Mulitplicand (A) and A
+       Multiplier (B) for Absolute Multiplication of
+       "A (8-bit) * B (8-bit)=c (16-bit)"
+
+          A Product (C) Can Be Read by Registers <4216h><4217h>
+
+          Set in the Order of (A) and (B). The Operation Will Start As
+       Soon As (B) Has Been Set, and it Will Be Completed Right After
+       8-machine Cycle Period.
+
+          Once the Data of the A-register is Set, it Will Not Be Destroyed
+       Until New Data is Set.
+
+
+Address  : $4204/$4205/$4206
+Name     : Wrdivl/wrdivh/wrdivb
+Contents : Divisor & Dividend Divide
+
+     D7-d0     Multiplier-c (Low)                 4204h
+     D7-d0     Multiplier-c (High)                4205h
+     D7-d0     Divisor-b                     4206h
+
+          This is A Register, Which Can Set A Dividend (C) and A Divisor (B)
+       For Absolute Divide of
+       "C (16-bit) / B (8-bit)=a (16-bit)"
+
+          The Divisor (A) Can Be Read by Registers <4214h><4215h>, and the
+       Remainder Can Also Be Read by Registers <4216h><4217h>.
+
+          Set in the Order of (C) and (B). The Operation Will Start As Soon
+       As (B) Has Been Set, and it Will Be Completed Right After 16-
+       Machine Cycle Period.
+
+          Once the Data of the A-register is Set, it Will Not Be Destroyed
+       Until New Data is Set.
+
+
+Address  : $4207/$4208
+Name     : Htimel/htimeh
+Contents : H-count Timer Settings
+
+     D7-d0     H Count Timer (H7-h0)                   4207h
+
+     D7-d1     ---
+     D0   H Count Timer (H8)                 4208h
+
+          This is A Register, Which Can Set the H-count Timer Value.
+
+          The Setting Value Should Be From 0 Through 339, Which is Counted
+       From the Far Left on the Screen.
+
+          Hwen the Coordinate Counter Becomes the Count Value Set, the Irq
+       Will Be Applied. And At the Same Time. "1" Will Be Written to
+       "Timer Irq" of Register <4211h>. (Read Reset)
+       Enable/disable of the Interrupt Will Be Determined by Setting
+       Register <4200h>
+
+     * this Continous Counter is Reset Every Scanning Line, Therefore
+       Once the Count Value is Set, it is Possible to Apply the Irq
+       Every Time the Scanning Line Comes to the Same Horizontal
+       Position on the Screen.
+
+
+Address  : $4209/$420ah
+Name     : Vtimel/vtimeh
+Contents : V-count Timer Settings
+
+     D7-d0     V Count Timer (V7-v0)                   4209h
+
+     D7-d1     ---
+     D0   V Count Timer (V8)                 420ah
+
+          This is A Register, Which Can Set the V-count Timer Value.
+
+          The Setting Value Should Be From 0 Through 261(262), Which is
+       Counted From the Far Top of the Screen. [The Line Number Described
+       Is Different From the Actual Line Number on the Screen.]
+
+          Hwen the Coordinate Counter Becomes the Count Value Set, the Irq
+       Will Be Applied. And At the Same Time. "1" Will Be Written to
+       "Timer Irq" of Register <4211h>. (Read Reset)
+       Enable/disable of the Interrupt Will Be Determined by Setting
+       Register <4200h>
+
+     * this is A Continous Counter Same As H-counter, and it Will Be
+       Reset Every Time 262(263) Line Are Scanned. Once the Count
+       Value is Set, it is Possible to Apply the Irq Every Time the
+       Scanning Line Comes to the Same Vertical Line on the Screen.
+
+
+Address  : $420b
+Name     : Mdmaen
+Contents : Channel Designation for General Purpose Dma & Trigger (Start)
+
+     D7-d0     General Purpose Ch7-ch0 Enable
+
+          The General Purpose Dma Consists of 8-channels in Total.
+
+          This Register is Used to Designate the Channel Out of 8-channels.
+
+          The Channel Which Should Be Used Can Be Designated by Writing "1"
+       To the Bit of this Channel. As Soon As "1" is Written to the
+       Bit (After A Few Cycles Passed), the General Purpose Dma Transfer
+       Will Be Started.
+
+          When the General Purpose Dma of the Designated Channel is
+          Completed, the Flag Will Be Cleared.
+
+     Note:     Because the Data Area (Register <4300>-) of Each Channel
+     ~~~~~     is Held in Common with the Data of Each H-dma Channel, the
+          Channel Designated by the H-dma Channel Designation
+          Register <420ch> Can Not Be Used.
+          (It is Prohibited to Write "1" to the Bit of the Channel)
+          Therefore, 8 Channels (Ch0-ch7) Should Be Assigned by the
+          H-dma and the General Purpose Dma)
+
+     Note:     If the H-blank Come During the Operation of the General
+     ~~~~~     Purpose Dma and the H-dma is Started, the General Purpose
+          Dma Will Be Discontinued in the Middle, and Re-started Right
+          After the H-dma is Complete.
+
+     Note:     If 2 Or More Channels Are Designated, the Dma Transfer Will
+     ~~~~~     Be Performed Continously According to the Priority Described
+          in Appendix-1.
+          And Also, the Cpu Stops Operation Until All the General
+          Purpose Dma Are Completed.
+
+
+Address  : $420c
+Name     : Hdmaen
+Contents : Channel Designation for H-dma
+
+     D7-d0     H-dma Ch7-dh0 Enable
+
+          The H-dma Consists of 8-channels in Total
+
+          This Register is Used to Designate the Channel Out of 8-channels
+
+          The Channel Which Should Be Used Can Be Designated by Writing
+       "1" to the Bit of this Channel. As Soon As H-blank Begins (After
+       A Few Cycles Passed), the H-dma Transfer Will Be Started.
+
+     Note:     Once this Flag is Set, it Will Not Be Destroyed (Cleared)
+     ~~~~~     Until New Data is Set. Therefore, the Initial Settings Are
+          Done Automatically Every Field, and the Same Transfer
+          Pattern Will Be Repeated.
+          And Also, the Flag is Set Out of V-blank Period, the Dma-
+          Transfer Will Be Performed Properly From Next Screen Frame.
+
+
+Address  : $420d
+Name     : Memsel
+Contents : Access Cycle Designation in Memory (2) Area
+
+     D7-d1     ---
+     D0   Access Cycle Designation in Memory (2) Area
+               0: 2.68mhz Access Cycle
+               1: 3.58mhz Access Cycle (Only When High Speed
+                               Memory is Used.)
+
+          Memory (2) Shows the Address (8000h-ffffh) of the Bank (80h-bfh)
+       And All the Address of the Bank (C0h-ffh).
+
+          When Power is Turned on Or the Reset Signal is Applied it Becomes
+       "0".
+
+          High Speed Memory Requiers 120ns Or Faster Eproms.
+
+
+Address  : $4210
+Name     : *Rdnmi
+Contents : Nmi Flag by V-blank & Version Number
+
+     D7   Nmi Flag by V-blank
+               When "1" is Written to "Nmi Enable" of Register
+               <4200h>, this Flag Will Show Nmi Status.
+                    0: Nmi Status is "Disable"
+                    1: Nmi Status is "Enable"
+
+     D6-d4     ---
+
+     D3-d0     5a22 Version Number
+
+     * "1" is Set to this Flag At Beginning of V-blank, and "0" is
+       Set At End of V-blank. Also, it Can Be Set by Reading this
+       Register.
+
+     Note:     it is Necessary to Reset by Reading this Flag During
+     ~~~~~     Nmi Processing. (See Appendix-3)
+
+
+Address  : $4211
+Name     : *Timeup
+Contents : Irq Flag by H/v Count Timer
+
+     D7   Irq Flag by H/v Count Timer
+               [In Case the Time Enable is Set by "Timer Enable"
+               Of Register <4200h>] As Soon As H/v Counter Timer
+               Becomes the Count Value Set, Irq Will Be Applied
+               And "1" Will Be Set to this Flag.
+               This Flag is "Read-reset".
+
+     D6-d0     ---
+
+     * Even If V-en="0" and H-en="0" Are Set by "Timer Enable" of
+       Register <4200h>, this Flag Will Be Reset.
+          0: Either H/v Counter is in Active Or Disable.
+          1: H/v Count Timer is Time Up.
+
+
+Address  : $4212
+Name     : Hvbjoy
+Contents : H/v Blank Flag & Joy Controller Enable Flag
+
+     D7   V-blank Period Flag
+               0: Out of V-blank Period
+               1: in V-blank Period
+
+     D6   H-blank Period Flag
+               0: Out of H-blank Period
+               1: in H-blank Period
+
+     D5-d1     ---
+
+     D0   Joy Controller Enable Flag
+               This Flag Shows the Timing to Read the Data of the
+               Joy Controller. (However, it is Limited to the Case
+               Which the "Joy-c Enable" of Register <4200h> is Set
+               To "1".
+
+
+Address  : $4213
+Name     : *Rdio
+Contents : Programmable I/o Port (In-port)
+
+     D7-d0     I/o Port
+
+          This is A Programmable I/o Port (In Port). The Data Which is Set
+       To the In-port Should Be Read Directly.
+
+          The Bit Which "1" is Written by Register <4201h> is Used As the
+       In Port.
+
+
+Address  : $4114/$4115
+Name     : *Rddivl/*rddivh
+Contents : Quotient of Divide Result
+
+     D7-d0     Quotent-a (Low)                         4114h
+     D7-d0     Quotent-a (High)                   4115h
+
+          This is A Quotent (A), Which is A Result for Absolute Divide of
+       "C (16-bit) / B (8-bit) = A (16-bit)".
+
+          Dividend (C) and Divisor (B) Are Set by Registers <4204h>-<4206h>.
+
+
+Address  : $4216/$4217
+Name     : *Rdmpyl/*rdmpyh
+Contents : Product of Multiplication Result Or Remainder of Divide Result
+
+     D7-d0     Product-c [Mul] / Remainder [Div] (Low)      4216h
+     D7-d0     Product-c [Mul] / Remainder [Div] (High)     4217h
+
+     (1) in Case of Multiplication
+          This is A Product (C) Which is A Result for Absolute
+       Multiplication of "A (8-bit) * B (8-bit) = C (16-bit)".
+
+          A Multiplicand (A) and A Multiplier (B) Are Set by Registers
+       <4202h> & <4203h>.
+
+     (2) in Case of Divide
+          This is the Remainder, Which is A Result for the Absolute
+       Divide of "C (16-bit) / B (8-bit) = A (16-bit)".
+
+          A Dividend (C) and Divisor (B) Are Set by the Registers
+       <4204h><4205h> & <4206h>.
+
+
+Address  : $4218/$4219/$421a/$421b/$421c/$421d/$421e/$421f
+Name     : Joy1l/joy1h/joy2l/joy2h/joy3l/joy3h/joy4l/joy4h
+Contents : Data for Joy Controller I, Ii, Iii & Iv
+
+     D7   X Button                      Low
+     D6   Y Button
+     D5   Tl Button
+     D4   Tr Button
+     D3-d0     ----
+
+     D7   A Button                      High
+     D6   B Button
+     D5   Select Button
+     D4   Start Button
+     D3   Up
+     D2   Down
+     D1   Left
+     D0   Right
+
+          Registers <4016h><4017h> Can Be Used the Same As the Family
+       Computer.
+
+     4016h-rd
+          D0 : Data for Controller I
+          D1 : Data for Controller Iii
+     4016h-wr
+          Out0,out1,out2
+     4017h-rd
+          D0 : Data for Controller Ii
+          D1 : Data for Controller Iv
+
+     Note:     Whether the Standard Joy Controllers Are Connected to the
+     ~~~~~     Sfx Or Not Can Be Reffered by Reading 17th Bit of <4016h>
+          and <4017h> (See Page 22).
+               0: Connected
+               1: Not Connected
+
+
+Address  : $43x0 (X: Channel Number 0-7)
+Name     : Dmapx
+Contents : Parameter for Dma Transfer
+
+     D7   Transfer Origination Designation (See Appendix-1)
+               Transfer Direction  A-bus -> B-bus
+                                   B-bus -> A-bus Designation
+                    0: A-bus -> B-bus (Cpu Memory -> Ppu)
+                    1: B-bus -> A-bus (Ppu -> Cpu Memory)
+
+     D6   Type Designation (H-dma Only)
+               Addressing Mode Designation When Accessing the
+               Data (See Appendix-2).
+                    0: Absolute Addressing
+                    1: Indirect Addressing
+
+     D5   ---
+
+     D4-d3     Fixed Address for A-bus & Automatic Inc./dec. Select.
+               D3   0: Automatic Address Increment/decrement
+                    1: Fixed Address <To Be Used When Clearing
+                       Vram Etc.>
+               D4   0: Automatic Increment
+                    1: Automatic Decrement (In Case "0" is
+                       Written to D3)
+
+     D2-d0     Dma Transfer Word Select
+               General Purpose Dma: B-address Change Method
+
+                    D2 D1 D0  | Address to Be Written
+                    ---------------------------------
+                     0  0  0  | 1-address
+                     0  0  1  | 2-address (Vram Etc.)   L,h
+                     0  1  0  | 1-address
+                     0  1  1  | 2-address (Write Twice) L,l,h,h
+                     1  0  0  | 4-address               L,h,l,h
+
+               H-dma: the Number of Byte to Be Transfered Per Line
+               And Write Method Designation
+
+                    D2 D1 D0  | Address to Be Written
+                    ---------------------------------
+                     0  0  0  | 1-address                     (1)
+                     0  0  1  | 2-address (Vram Etc.)  L,h    (2)
+                     0  1  0  | Write Twice            L,l    (1)
+                     0  1  1  | 2-address/write Twice  L,l,h,h(2)
+                     1  0  0  | 4-address              L,h,l,h(4)
+
+
+Address  : $43x1 (X: Channel Number 0-7)
+Name     : Bbadx
+Contents : B-bus Address for Dma
+
+     D7-d0     B-address
+
+          This is A Register, Which Can Set the Address of B-bus.
+
+          Whether this is the Address of the "Transfer Destination" Or
+       The Address of the "Transfer Origination" Can Be Determined by
+       D7 (Transfer Origination) of Register <4300h>.
+
+     * When the H-dma is Performed, it Will Be Address of "Transfer
+       Destination".
+
+
+Address  : $43x2/$43x3/$43x4 (X: Channel Number 0-7)
+Name     : A1txl/a1txh/a1bx
+Contents : Table Address of A-bus for Dma <A1 Table Address>
+
+     D7-d0     A1 Table Address (Low)                  43x2h
+     D7-d0     A1 Table Address (High)                 43x3h
+     D7-d0     A1 Table Bank                      43x4h
+
+          This is A Register, Which Can Set the Address of A-bus
+
+          Whether this is the Address of the "Transfer Destination" Or
+       The Address of the "Transfer Origination" Can Be Determined by
+       D7 (Transfer Origination) of Register <4300h>.
+       "0" Should Be Written to D7 Except A Special Case.
+
+          In the H-dma Mode, the Address of the Transfer Origination is
+       Designated by this Address, the Data (Appendix-2) Must Be
+       Set by the Absolute Addressing Mode Or the Indirect Addressing
+       Mode.
+
+          This Address Becomes the Basic Address on the A-bus During Dma
+       Transfer Period, and the Address Will Be Increased Or Decreased
+       Based on this Address. (When the General Purpose Dma is Performed
+       It Will Be Decreased.)
+
+
+Address  : $43x5/$43x6/$43x7 (X: Channel Number 0-7)
+Name     : Dasxl/dasxh/dasbx
+Contents : Data Address Store by H-dma & Number of Byte to Be Transfered
+        Settings by General Purpose Dma
+
+     D7-d0     Data Address (Low)             H-dma    43x5h
+          Number of Bytes to Be Transfered (Low)  Gp-dma
+
+     D7-d0     Data Address (High)            H-dma    43x6h
+          Number of Bytes to Be Transfered (High) Gp-dma
+
+     D7-d0     Data Bank                     43x7h
+
+          In Case of H-dma
+          this is A Register Which the Indirect Address Will Be
+          Stored Automatically in the Indirect Addressing Mode.
+          The Indirect Address Means the Data Address Described
+          on Appendix-2. It is Not Necessary to Read Or Write
+          Directly by the Cpu Except in Special Cases.
+
+          In Case of General Purpose Dma
+          this is the Register, Which Can Set the Number of Byte
+          to Transfer Or to Be Transfered. However, the Number of
+          Byte "0000h" Means "10000h".
+
+
+Address  : $43x8/$43x9 (X: Channel Number 0-7)
+Name     : A2axl/a2axh
+Contents : Table Address of A-bus by Dma < A2 Table Address
+
+     D7-d0     A2 Table Address (Low)                  43x8h
+     D7-d0     A2 Table Address (High)                 43x9h
+
+          These Are the Addresses, Which Are Used to Access the Cpu & Ram,
+       And it Will Be Increased Automatically. (See Appendix-2)
+
+          The Data of These Registers Are Used As the Basic Address Which
+       Is the Addresss Set by the "A1 Table Address". Afterwards,
+       Because it Will Be Increased Or Decreased Automatically, it is
+       Necessary to Set the Address Into this Register by the Cpu
+       Directly.
+
+     Following Apply to H-dma Only:
+          However, If the Data Which is Transfered Need to Be Changed
+          by Force, it Can Be Done by Setting the Cpu Memory Address
+          to this Register. And Also, the Address of the Cpu Which is
+          Accessed Currently Will Be Changed by Reading this Register.
+
+
+Address  : $43xa (X: Channel Number 0-7)
+Name     : Ntrlx
+Contents : the Number of Lines to Be Transfered by H-dma›0;31;40m
+
+     D7   Continue
+     D6-d0     Number of Lines to Be Transfered
+
+          This is A Register Which Shows Number of Lines for H-dma Transfer
+       (See Appendix-2)
+
+          The Number of Lines Written to the Cpu Memory Will Be the Basic
+       Number of Line, it is Not Necessary to Set the Address Into
+          This Register Directly.
+
+

+ 74 - 0
files/docs/snes/oam_flags.txt

@@ -0,0 +1,74 @@
+From:     vic@physci.psu.edu (Vic Ricker)
+To:       "Super Famicom Development Group" <famidev@busop.cit.wayne.edu>
+Subject:  Re:  some programming questions
+Date:     Tue, 9 Nov 93 20:20:35 EST
+
+>Hi Folks.
+
+>I need help with a few SNES programming questions... 
+
+>(1) Can anyone tell me how to make noises come out of my SNES?
+
+Insert your favorite cart, power up the TV, switch the snes power to
+ON.. :-)
+
+>(3) Is the sprite position table held in RAM or VRAM? And how
+>    do the 5 address bits in $2101 relate to this location?
+
+The sprite images are stored in VRAM.  The palettes for the sprites
+are stored in CGRAM.  The coordinates and char attributes are stored
+in OAM.
+
+The format of each OBJ is:
+
+OBJ H position: 8 bits
+OBJ V position: 8 bits
+V flip: 1 bit
+H flip: 1 bit
+OBJ priority: 2 bits
+color palette: 3 bits
+character name: 9 bits
+
+there are 128 of these in sequence making 512 bytes then 32 bytes
+follow in the format:
+size: 1 bit
+x msb: 1 bit
+
+there are 128 of these (one for every OBJ) making 32 more bytes.
+
+$2101 is OBJSEL
+
+it chooses the size of sprites to use and also sets the address of the
+images in VRAM.  the top 3 bits chose the size:
+
+000 means 8x8 and 16x16 sprites
+001 8x8 and 32x32
+010 8x8 and 64x64
+011 16x16 and 32x32
+100 16x16 and 64x64
+101 32x32 and 64x64
+
+the other bits are the address in vram of the sprite images.
+
+
+$2102-$2103 is OAMADDL/H
+the lower 9 bits are the address for accessing the OAM. (like $2116
+for VRAM)
+the high bit (15) enables priority rotation (causes OBJ's to change
+priority as to keep them from disappearing totally when time out and range
+over occur.)
+
+$2104 is OAMDATA
+
+it is the write register for the OAM. (like $2118-$2119 for VRAM)
+
+
+$2138 is *OAMDATA
+
+it is the read register for the OAM.
+
+
+Hope this gives you enough to play with.  Most is from memory, I hope
+its all correct. :-)
+
+Lemme know if you have questions.

BIN
files/docs/snes/pilotwings.pdf


+ 343 - 0
files/docs/snes/romformat_overview.txt

@@ -0,0 +1,343 @@
+
+             ______  _____        _____    _______       ___  ___
+            /   __/ /. _  \   ___/  __/   |____   \___  /.  \/   \
+            \___ .\//  |.  \ / . \__ .\    |.    _/   \//        .\
+           /.     \\   |:  .\  __/    \\   || |  .\ !  \     \/.   \
+           \______ /___|____/____\____ /   |__|   \\___/____||:     \
+             By Mind Rape                      \___/         |______/
+             v1.5 (C) Damaged Cybernetics 1994-95
+
+
+   This document main goal is show where one can find the SNES ROM
+   information.  Most of this information was collected thru hacking
+   the rom to death and help from Norm/Yoshi/chp.
+
+   License codes are taken from SU and probably incorrect.
+
+   Source? None here, if you are going to screw with the bin,
+   you probably know what you are doing (HOPEFULLY).
+
+   If you have any questions, comments,corrections, additional information,
+   you can either find me on IRC as (MindRape) or you can send me email
+   (much prefered) mind@primenet.com.  Also if you write anything
+   interesting then send it to me!
+
+   You may distribute this document freely, but you may not change
+   the information here and redistribute.  If you use this information
+   please credit me.  You steal this information and say you did it,
+   you know it's a LIE and there you are.
+
+=[SNES ROM Makeup]===========================================================
+
+ROM Title     : 21 Bytes
+
+  * Titles are all in upper case
+  * Japanese titles are in high ascii values
+    good rule of thumb if you can't read the title and
+    it's country code is Japan and your American,
+    you probably can't play it. :>
+
+Rom Makeup    : 7654 3210
+                0000-0000
+                |__| |__|
+                |    |
+                |    |___Bank Size 0001 = HiROM   (64K Banks Mode 21)
+                |                  0000 = Low Rom (32K Banks Mode 20)
+                |
+                |________ROM Speed 0111 = Fast Rom
+                                   0000 = Slow Rom
+
+                                   * Could someone give the correct
+                                   * speeds of the ROMs?  I got
+                                   * conflicting answers.
+
+
+ROM Type      :  1 Byte
+
+  Hex   ROM Type
+  ---------------------
+   00   ROM
+   01   ROM/RAM
+   02   ROM/SRAM
+   03   ROM/DSP1
+   04   ROM/DSP1/RAM
+   05   ROM/DSP1/SRAM
+   06   FX
+
+   * SRAM = Save Ram
+   * DSP1 = Nintendo's 1st generation of DSP (Math coprocessor)
+   * FX   = RISC based math coprocessor
+            Only a couple of games support the FX Chip, Star Fox
+            is the most well known one.
+
+
+ROM Size      : 1 BYTE
+
+  Hex   Size
+  --------------
+   08    2 Mbit
+   09    4 Mbit
+   0A    8 Mbit
+   0B   16 Mbit
+   0C   32 Mbit
+
+  * As of this documentation 32MBit ROMs are the largest that
+    Nintendo currently uses.  Rumors of a 40+ kart are around,
+    but cannot be verified.
+
+  * 8MBit ROMs are the most common in the entire library of
+    SNES karts
+
+  * ROMs are always multiples 2, thus 2MBit ROMs are the smallest
+    Space Invaders (c) Taito is a 2MBit ROM (Japan only)
+
+  * Easy way to calc rom size without a lookup table
+
+      1 << (ROM_SIZE - 7) MBits
+
+      ie.   8Mbit ROMs = 0Ah = 10d
+            1 << (0A-7) = 8 Mbit
+
+SRAM Size      : 1 BYTE
+
+  Hex   Size
+  --------------
+   00   No SRAM
+   01   16 Kbit
+   02   32 Kbit
+   03   64 Kbit
+
+    * 64Kbit is the largest SRAM size that Nintendo currently uses.
+    * 256Kbit is standard for most copiers.
+
+    * Easy way to calc SRAM Size without a lookup table
+
+        1 << (3+SRAM_BYTE) Kbits
+
+        ie. 16Kbit = 01
+            1 << (3+1) = 16
+
+
+COUNTRY CODE  : 1 BYTE
+
+  Hex    Country                 Video Mode
+  ------------------------------------------
+   00    Japan                   (NTSC)
+   01    USA                     (NTSC)
+   02    Europe, Oceania, Asia    (PAL)
+   03    Sweden                   (PAL)
+   04    Finland                  (PAL)
+   05    Denmark                  (PAL)
+   06    France                   (PAL)
+   07    Holland                  (PAL)
+   08    Spain                    (PAL)
+   09    Germany, Austria, Switz  (PAL)
+   10    Italy                    (PAL)
+   11    Hong Kong, China         (PAL)
+   12    Indonesia                (PAL)
+   13    Korea                    (PAL)
+
+  * Country Codes are from SU.INI, could someone verify these?
+
+LICENSE       : 1 BYTE
+     0 <Invalid License Code>
+     1 Nintendo
+     5 Zamuse
+     8 Capcom
+     9 HOT B
+    10 Jaleco
+    11 STORM (Sales Curve) (1)
+    15 Mebio Software
+    18 Gremlin Graphics
+    21 COBRA Team
+    22 Human/Field
+    24 Hudson Soft
+    26 Yanoman
+    28 Tecmo (1)
+    30 Forum
+    31 Park Place Productions / VIRGIN
+    33 Tokai Engeneering (SUNSOFT?)
+    34 POW
+    35 Loriciel / Micro World
+    38 Enix
+    40 Kemco (1)
+    41 Seta Co.,Ltd.
+    45 Visit Co.,Ltd.
+    53 HECT
+    61 Loriciel
+    64 Seika Corp.
+    65 UBI Soft
+    71 Spectrum Holobyte
+    73 Irem
+    75 Raya Systems/Sculptured Software
+    76 Renovation Pruducts
+    77 Malibu Games (T*HQ Inc.) / Black Pearl
+    79 U.S. Gold
+    80 Absolute Entertainment
+    81 Acclaim
+    82 Activision
+    83 American Sammy
+    84 GameTek
+    85 Hi Tech
+    86 LJN Toys
+    90 Mindscape
+    93 Technos Japan Corp. (Tradewest)
+    95 American Softworks Corp.
+    96 Titus
+    97 Virgin Games
+    98 Maxis
+   103 Ocean
+   105 Electronic Arts
+   107 Laser Beam
+   110 Elite
+   111 Electro Brain
+   112 Infogrames
+   113 Interplay
+   114 LucasArts
+   115 Sculptured Soft
+   117 STORM (Sales Curve) (2)
+   120 THQ Software
+   121 Accolade Inc.
+   122 Triffix Entertainment
+   124 Microprose
+   127 Kemco (2)
+   130 Namcot/Namco Ltd. (1)
+   132 Koei/Koei! (second license?)
+   134 Tokuma Shoten Intermedia
+   136 DATAM-Polystar
+   139 Bullet-Proof Software
+   140 Vic Tokai
+   143 I'Max
+   145 CHUN Soft
+   146 Video System Co., Ltd.
+   147 BEC
+   151 Kaneco
+   153 Pack in Video
+   154 Nichibutsu
+   155 TECMO (2)
+   156 Imagineer Co.
+   160 Wolf Team
+   164 Konami
+   165 K.Amusement
+   167 Takara
+   169 Technos Jap. ????
+   170 JVC
+   172 Toei Animation
+   173 Toho
+   175 Namcot/Namco Ltd. (2)
+   177 ASCII Co. Activison
+   178 BanDai America
+   180 Enix
+   182 Halken
+   186 Culture Brain
+   187 Sunsoft
+   188 Toshiba EMI/System Vision
+   189 Sony (Japan) / Imagesoft
+   191 Sammy
+   192 Taito
+   194 Kemco (3) ????
+   195 Square
+   196 NHK
+   197 Data East
+   198 Tonkin House
+   200 KOEI
+   202 Konami USA
+   205 Meldac/KAZe
+   206 PONY CANYON
+   207 Sotsu Agency
+   209 Sofel
+   210 Quest Corp.
+   211 Sigma
+   214 Naxat
+   216 Capcom Co., Ltd. (2)
+   217 Banpresto
+   219 Hiro
+   221 NCS
+   222 Human Entertainment
+   223 Ringler Studios
+   224 K.K. DCE / Jaleco
+   226 Sotsu Agency
+   228 T&ESoft
+   229 EPOCH Co.,Ltd.
+   231 Athena
+   232 Asmik
+   233 Natsume
+   234 King/A Wave
+   235 Atlus
+   236 Sony Music
+   238 Psygnosis / igs
+   243 Beam Software
+   244 Tec Magik
+   255 Hudson Soft
+
+  * License Codes are from SU.INI, could someone verify these?
+
+  * I believe the # of licenses is low.  Is it possible that
+    License and Country codes are used in conjuction to produce
+    that many more licenses?
+
+VERSION - 1 byte
+
+  * The Version is interpeted this way.
+    1.?? - (thanks to yoshi for the correction)
+
+CHECKSUM COMPLEMENT - 2 bytes the complement of the checksum :>
+
+  The bits are reversed of the CHECKSUM
+
+CHECKSUM            - 2 bytes Checksum of the bin
+
+  * Anyone know how the checksum is calculated for the ROM?
+
+NMI/VBL Vector     - 2 bytes                            - OFFSET 81FAh  (lowrom)
+                                                          OFFSET 101FAh (hirom)
+
+RESET Vector       - 2 bytes where to start our code at - OFFSET 81FCh  (lowrom)
+                                                        - OFFSET 101FAh (hirom)
+  * 8000h is common for Low Roms
+
+=[READING THE CORRECT BIN INFORMATION]==================================
+
+ The bin information can be found in 2 possible places,
+
+    a) End of the 1st 32K bank (Low ROM)  (81c0h/w 512 byte header)
+    b) End of the 1st 64K bank (HiROM)    (101c0h/w 512 byte header)
+
+ You could use UCON's method (author chp).
+
+ The method is as followed:
+
+ UCON's method is to OR the Checksum and the Complement.  If the
+ resulting value is FFFFh, then we found the correct location of
+ to extract rest of the data out.  HOWEVER!  This fails on several
+ karts, such as Castle Wolfenstien 3D and Super Tetris 3 for example.
+
+ Reason being is that not all developers put the correct complement
+ or bother even to implement it.  I would suspect!  That this maybe
+ a ploy to keep other developers out of the bin, for if they can't
+ find the reset vector, disassembling becomes a bit difficult.
+
+=[Other Information on SNES?]================================================
+
+ Famicom Development FTP Site
+   busop.cit.wayne.edu - pub/famidev
+
+ Yoshi's SNES Documentation 2.3
+
+   This is considered the BEST source of SNES hardware information,
+   and the most complete!
+
+   busop.cit.wayne.edu - pub/famidev/incoming/sndoc230.lzh
+
+=[w0rd!]=====================================================================
+
+w0rd to all following console dudes
+
+GoosE_,yoshi,sir jinx,chp,SHORYUKEN,_bubsy,felon,archimede
+rugalz,SinZ,dragonz,procyon,royce,hoodlem,bri_acid,kamikitty,
+norm,ZillionZ Members,grayarea,Victor,drunkfux(h0h0h0h0),dmessiah,
+piratendo
+
+<insert your favorite group(s) greet here> (heh)
+
+Later Mind Rape

+ 1128 - 0
files/docs/snes/romhacking.txt

@@ -0,0 +1,1128 @@
+                       
+                        "THE ROM HACKERS BIBLE v0.2"
+                                  
+                             By SeRiAlKLR
+                         <SeRiAlKLR@usa.net>
+
+                         RomHackers Inc. (c) 1997
+
+
+¸,.�¬=椺²°`¯ ¯`°²º¤æ=- The Rom Hackers Bible -=椺²°`¯ ¯`°²º¤æ=¬�.,¸
+
+
+
+                         TABLE OF CONTENTS
+
+
+  I. Introduction
+      1. Preface
+      2. Introduction
+      3. Disclaimer
+ II. Tools
+      A) Nes Tools
+          1. NESticle
+          2. Hex editor
+          3. Xchar v1
+          4. Xlate v1
+          5. Romhack
+      B) Snes Tools
+          1. Ctool
+          2. Kill Them
+          3. SnesTool
+          4. Xchar v2
+          5. Xlate v2
+          6. CartDisk
+          7.RipGrfx
+III. The process
+      1. The ROM
+      2. Changing graphics
+      3. Changing text
+ IV. The Nintendo 
+      1. General Architecture
+      2. Interrupts
+      3. I/O Ports
+      4. PPU Memory
+      5. Hit/VBlank Bits
+      6. Joysticks
+      7. Sprites
+      8. Memory Mappers
+          a) Sequential
+          b) Konami
+          c) VROM Switch
+          d) 5202 Chip
+          e) Others
+
+      
+ V. Sample walkthrough
+VI. The Big Credits and Thanks section!!
+
+
+¸,.�¬=椺²°`¯ ¯`°²º¤æ=- Section I. -=椺²°`¯ ¯`°²º¤æ=¬�.,¸
+
+
+
+I. Introduction
+---------------
+
+
+A. Preface
+   
+        This document was written due to the general lack of thourough
+rom hacking documents. Although there are a few available they arent as 
+thourough as I needed. Therefore I wrote this to help all "would be"
+rom hackers. I also copied extracts of various text on certain 
+tools, and I added credit to the author's when due, all other text is by
+me and I hope you find this useful. Also I will not cover pasofami hacking
+ due to the fact that ines format is more popular.
+
+
+B. Introduction
+
+        Hacking a ROM in its simplest form is easy. It does, even then,
+require alot of time depending on the complexity of the hack you are
+doing.  For the truly daring you can even learn how to hack the rom
+completely, by this I  mean "change the colors, etc.. even make a whole 
+new game" This information is in chapter IV.
+
+       Using this document you "may" learn how to be a great rom hacker
+although I'm not promissing  anything. The "information" is here, it's
+how you use it that makes the difference. 
+
+
+C. Disclaimer
+
+   1) The author is not responsible for any illegal activities related with
+       this document.
+   2) The author is not affiliated in any way with any programs or
+       companies mentioned within this document.
+   3) The author takes no responsibility in any damage done to your system by
+       running the mentioned programs.
+   3) This document MAY be copied and transmitted electronically, so long as
+       everything included is INTACT and NOT MODIFIED.
+   4) This document MAY NOT be distributed as any hard copy. This includes
+       paper, books, or magazines.
+   5) This document MAY NOT be modified to another format, such as HTML or
+       Adobe's PostScript, without prior written consent by the author.
+   
+
+
+¸,.�¬=椺²°`¯ ¯`°²º¤æ=- Section II. -=椺²°`¯ ¯`°²º¤æ=¬�.,¸
+
+
+
+II. Tools
+---------
+(A) NES ROM HACKING TOOLS
+
+1. NESticle
+
+        To edit patterns, goto the View/Pattern table, then click 
+on a pattern and edit it.Right clicking on a pattern will change 
+its attribute (palette), to aid in drawing. If you wish, you can save 
+the changes with File/Write VROM, and the VROM will be written directly
+to the .NES file, so make back-up copies!!.
+( nesticle homepage http://www2.southwind.net/~bldlust/NESticle.html )
+
+2. Hex editor
+
+        Depending on the rom your hacking it may or may not have
+text in it to edit. Generally use this for simple hacks, but also
+use it for major rom hacking as described later in the document.
+
+3. Xchar 
+        
+        X-Char is a tile data editor for Nintendo systems.  Tile 
+data is both the tile and sprite data of the cartridge.  This
+tool allows the user to modify the data to their liking, it
+sports an easy to use interface, simple enough for even the
+most uninitiated in the ways of ROM editting.  If you can use
+a paint program, you can use this.(Planet X Software)
+Version 2 allows you to edit roms for many emulator formats:
+a) *.nes
+b) *.gb
+c) *.smc
+
+note: It may support more but the above are all that i've tried.
+
+4. Xlate
+
+       what xlate does is take a table file (created by you) of byte 
+equivalencies to characters defined by the rom (companies rarely used ascii 
+standards for their text encoding).  with a normal hexeditor, you can't see 
+jack shit of text in a rom. with xlate, you can manipulate what bytes define
+ the characters, so you can see the text by the way it was meant to be seen 
+in the rom. let's take a segment from ff2j, for example. 
+
+8F AC AA AB B7
+
+under a normal hexeditor (ascii), it would look like crap. ż¬½+ to be exact.
+but as i said, squaresoft didn't use standard ascii codes for their text. 
+8F means F, AC means i, etc.. it's xlate's job to reallign the text codes 
+into something that looks right.
+
+the format for creating a xlate 1.00 table is like this :
+
+<A> <B> <C>
+8F   F   F
+AA   g   g
+AB   h   h
+AC   i   i
+B7   t   t
+...
+
+A: column A is the byte addressed.
+B: column B is the key you press to call the letter in column C.
+C: column C is the text displayed to us while in xlate, in place of the byte 
+in column A.
+
+so, in xlate, when bytes 8F,AC,AA,AB,B7 are addressed, they look like 'Fight
+'. ( Extract from Demi's romhacking text )
+
+
+5. Romhack
+
+      RomHack starts with the File Requester. From there you may choose 
+the rom file you want to see. Actually, you can read ANY file, but RomHack
+comes handy only with roms! Chosen the rom, the main screen displaying a 
+BITwise dump of that rom will pop up. On the bottom of the screen the rom 
+filename is displayed. On the top right, we have: the POSition indicator 
+into the rom (referred to the first pixel shown on the top-left of the 
+screen), the total LENgth of the ROM and the MODulus (or sprites size) value. The modulus
+is very important, since it's the key to display things like character-sets
+and sprites. The Y modulus works togheter with the X one to help display
+graphics with aligned bytes (sprites). The key of sprites dumping is, anyway,
+the SPRITES mode. The sprites mode displays bytes in the following format:
+
+byte 1    byte 9
+byte 2    byte 10
+byte 3    byte 11
+byte 4    byte 12
+byte 5    byte 13
+byte 6    byte 14
+byte 7    byte 15
+byte 8    byte 16
+
+byte 17   byte 25
+byte 18   byte 26
+byte 19   byte 27
+byte 20   byte 28
+byte 21   byte 29
+byte 22   byte 30
+byte 23   byte 31
+byte 24   byte 32
+
+... and so on
+
+It looks like many roms store sprites this way. Of course the X and Y
+size of sprites can be fully customizable.
+
+Another neat feature of RomHack is Dump. You can have a real-time dump
+of the ROM in HEX, ASCII and 6502 DISASSEMBLY. (Fabrizio Zavagli)
+
+(B) SNES ROM HACKING TOOLS
+
+
+ 1. Ctool v1.62
+      
+    A) What it can do:
+
+* A whole NEW algorithm to verify SNES checksum!! 
+   Old versions of CTOOL only could handle 2,4,8,16 and 32 MBit cartridges. 
+   Now CTOOL V1.62 can calculate checksum of 10,12,20 and 24 Mbit carts!
+ * Verify option shows blocks left and percentage of process.
+ * Split option aborts if destination size equals original size. 
+   Old versions of CTOOL created a copy of the file. Fixed!
+ * Join option shows the name of the files being joined.
+ * When splitting SMC files, the cartridge mode byte -if present- is copied
+   to the last file. Reversely, when joining SMC files, the mode byte of the
+   last file is copied onto the new file.
+ * Transfer option sends cartridge mode byte to SWC !!!!
+   This means that we can now send High ROM games to our beloved Wild Card
+   and also avoid SRAM protections by changing the header appropiately!
+ * Transfer routine has been recoded so that SWC will not get locked when
+   the console is powered off. Old versions of CTOOL sometimes needed an
+   unlocking program like RESETPRT.COM to bring SWC back alive.
+ * Transfer option shows file name, blocks left and percentage of files 
+   being sent to the SWC.
+ * Another NEW option /m activates "Multi File mode" !!
+   Now you don't need to join your files in a full sized one. CTOOL can now
+   handle multi splitted SMC files when verifying and sending to the copier!
+   If /m flag is not set, smart detection asks you to choose it if needed.
+ * Maker ID's identification optimized to half size, as old codes were all
+   compatible with new ones. No longer needed to have 2 tables in memory!
+ * Some new Maker ID's included and some old ones fixed to real names.
+ * Japanese letter 'little tsu' now appears as (k).  (Black Hole)
+ 
+  B) How do I use it:
+    
+     It is menu driven figure it out.
+
+
+
+2. Kill Them 
+
+    A) What is it :
+
+    With this tool you are able to remove up to 95% of all present and up-
+    coming PAL, NTSC and SLOWROM Protections!
+    The best'n fastest available Fixer 4 your PC! Don't believe it? Just 
+    test and make sure.
+    
+    B) How do I use it:
+
+    Just type at the commandline: KILLEM31 <FILENAME> /<OPTION>
+
+    The options look like this: /1 : for removing PAL-Protections at once
+                                /2 : for detecting PAL-Protections and
+                                     creating an IPS file to remove 'em
+                                /3 : for removing NTSC-Protections at once
+                                /4 : for detecting NTSC-Protections and
+                                     creating an IPS file to remove 'em
+                                /5 : for removing SLOW-Protections at once
+                                /6 : for detecting SLOW-Protections and
+                                     creating an IPS file to remove 'em
+
+    Use option 1 & 2 only for NTSC-Modules and option 3 & 4 only for PAL-
+    Modules. Otherwise it can be that an NTSC game won't work on an NTSC
+    Machine and the same with PAL. But the Utility automatically detects
+    a NTSC or PAL game, so don't be shy! (Wonderboy)
+ 
+3.  SnesTool
+
+    What it is: Multipurpose tool to modify snes roms(not grafix)
+
+    How do I use it:
+
+*CONFIGURE
+This is important for adding headers, sending hi-rom games, and
+fixing headers.
+First the Printer port (1-4) is asked, if none set 1=default
+The function gets the port values from segment 40 (bios variables)
+
+Then it asks ya for 5 different style of copiers, press Y if you
+have the correct one, Double profighter works ok, Procom/Magicom also
+And the Profighter Q+ 32 mbit is ok as well, the others are NOT tested
+yet. So if Hi-rom sending does not work, try some other copiers
+instead, there are 5 different types of Hirom Sending.
+
+If you have made your choice, the fileselector gets active, then
+choose the SNESTOOL and press return, it will then patch the
+snestool.exe file to keep the values you entered. 
+You can skip the patching, but why re-enter it everytime huh ?
+Changing your settings as many times as you like is no problem 
+you can patch the Snestool.exe until you drop..
+
+*TAB
+Go to browsing mode, exit with Esc or <TAB> again.
+Use this to switch between File-Selector and Menu.
+
+*SPLIT
+Pick a snes file, then you can choose the split size for 4/8/12 mbit,
+with the arrow keys, press return to start.
+It will keep the 1st 8 letters name the extension to 1/2/3/etc..
+
+*JOIN
+Will only take *.1 files then renames the file to *.smc.
+Works on multiple files.
+
+*SLOWROMFIX
+Searches & patches the selected file for some standard fixes.
+Number of fixes will be displayed.
+Almost fixes the same ones as killem31.
+Killem is a little better however, but sometimes fixes a little
+too much...
+
+*PALFIX
+Search & patch standard protections for games which do not work on
+pal machines.
+
+*NTSCFIX
+Same but for games that do not work on NTSC machines.
+Once fixed it must work on both machines.
+
+*USE IPS
+Apply the International Patch Standard on a file.
+This type was invented by DAX and ME, we got a lot
+of success with it, because we released the programs
+on ATARI/AMIGA AND PC format at the same time.
+
+Pick an IPS file first, the the game to be patched.
+If IPS2 is detected, it will write a temporary file
+called TEMP.SMC then renames it back to the original.
+IPS2 files are ment to 'Cut' a file.
+Kill them fucking advertisement Intro's...
+
+*CREATE IPS
+Compares 2 files, then write the difference to a file called
+'2ndname.IPS'.
+
+*ADD HEADER
+Test the size, and if ok writes a TEMP.SMC, renaming it afterwoods.
+Works on multiple files.
+
+*REPAIR HEADER
+Auto detects multiple files, ask for S-ram on/off, Hirom yes/no,
+with wildcard selected, also for mode 24 (other place of S-ram).
+then patches all files accordingly.
+
+*REMOVE INTRO
+Tries to find and restore the original reset vector then cut's off
+the intro (if added to the end).
+Does NOT work on the latest Anthrox intro's, the ones who modify
+a lot of 'blanking instructions'.
+Does NOT work with the 'Hidden reset vector' stuff.
+
+*SEND & RUN
+Pick a file to send, make sure you have selected the correct
+configuration, else strange things might happen.
+It will detect multiple files and send the rest also.
+after loading 1 or 2 blocks a file info menu will pop up,
+containing some useful information about the game.
+Some company's could be wrong, because they use the incorrect company-
+value. 
+Esc cancels the sending.
+
+*SLOWFIX ON/OFF
+If ON each loaded block is scanned for fixes, if found it will
+be patched in memory only, just before sending, at the end of
+sending, the number of fixes will be displayed in the same box.
+
+*FILEINFO
+Go to browsing mode by using <TAB> press return on a snes file to get
+your information, exit with <TAB> again or esc.  
+	 
+*EXIT
+Press ESC in SELECTION mode to quit.
+
+*CHOOSE DRIVE
+press A or C to Z to choose another Harddisk or CD-Rom
+
+*DELETE
+In the file selector you can press the DELETE key to kill a file..
+
+*FILESELECTOR CONTROL KEYS
+Use the Cursor keys to Move Up and Down to select files
+and Left and Right to go in and out of Directories.
+
+*HOT-KEYS
+ The HOT Keys are obvious since there Green and in Capitals.(Sledge & MCA)
+
+4. Xchar version 2 - same description as as xchar v1 but
+                     it allows you to edit other roms.(nes/gb/smc/smd)
+5. Xchar version 2 - same as above.
+
+6. CartDisk
+
+  A)   What is it:
+
+          Display the cartridge information (ROM/SRAM size, Title, Licensee, 
+Country, Version, etc.) of the cartridge plugged into the interface.
+Browse through cartridge information contained in image files on disk(s).
+Copy the cartridge to disk (up to 32Mbits, including HiROM support).
+Load a cartridge image from disk *
+Compare a cartridge image with a cartridge in the interface.
+Copy, load and clear the Static RAM on any cartridge **
+Convert between image formats (SMC/SWC and Game Doctor)
+Split an image in half.
+Join two images together.
+
+*Pad an image which is not an even number of Mbits.
+
+*Destroy PAL/NTSC, SRAM protect and FastROM detect codes 
+Use Game Genie, Gold Finger and Action Replay codes to cheat in games 
+
+*Convert between Game Genie, Gold Finger and Action Replay codes.
+
+*Apply an IPS patch on an image.
+
+*Modify game information such as title, ROM/RAM size, Licensee, Country, etc. 
+
+
+7) RipGRFX
+
+   WHat is it:
+
+     This nifty tool allows you to rip the grafix out of snes
+games so you can do whatever u want with 'em. :)
+
+  How do i use it:
+
+
+    Ripgrfx <filename>.swc 
+*must be in swc format!!
+
+¸,.�¬=椺²°`¯ ¯`°²º¤æ=- Section III. -=椺²°`¯ ¯`°²º¤æ=¬�.,¸
+
+
+
+III. The process
+----------------
+
+
+A. The ROM
+
+        First of all, you have to choose a rom to hack. This ROM can be
+ines/pasofami/gameboy/snes/genesis format depending on the tool you use.
+Xchar version 2 allows you to edit several formats ( I'm hoping that
+they will improve the controls somewhat, but its a good tool )
+
+
+B. Changing graphics
+
+        Here's where the fun part comes in. Load up your ROM and go to
+View --> Pattern tables. A window should pop up with funny looking graphics.
+Start your game and find a certain sprite, such as Link in Zelda 2. Now, your
+sprite and the palette in the pattern table are probably different, so right
+click the left or right side of the table until the table palette and the
+sprite palette are the same. Search through the table and find a part of your
+sprite. Click on it. Another window should pop up. Under this window, you have
+an enlarged tile of that part of your sprite. Click on a color and change the
+sprite around. When your done editing your sprites, you can save your changes
+by clicking on File --> Write VROM. Be sure to make a backup copy of the
+original ROM before writing the VROM. (Blackfury)
+       
+      Using Xchar is self explanatory. you simply scroll down until you
+find the character you wish to edit and press enter. This will bring up
+a closer view of the sprite and also a color table (only 4). Then u edit as 
+you wish and press " S " to save it. 
+
+How do I use Xchar? Easy use these commands:
+
+(1) Viewing mode:
+
+ [~] Toggle SNES mode (NES mode by default)
+ [space] Change bitdepth (SNES mode only)
+ [\] Change byte offset (if tile appears disaligned, use this)
+ [-] Shrink tile array x dimension by 1
+ [+] Enlarge tile array x dimension by 1
+ [[] Shrink tile array y dimension by 1
+ []] Enlarge tile array y dimension by 1
+ [pgup]  Move up one page
+ [pgdn]  Move down one page
+ [up]    Move up one line
+ [down]  Move down one line
+ [left]  Move up one character
+ [right] Move down one character
+ [enter] Open tile array editor
+ [s] Save editted rom
+ [l] Reload rom
+ [x] cut tile array
+ [c] copy tile array
+ [v] paste tile array
+ [esc]   Exit program
+
+(2) Editing mode:
+
+ [esc]   Return to view mode
+ [+] Zoom in
+ [-] Zoom out 
+
+(3) Viewing mode:
+
+ [mouse right]   grab tile
+ [mouse left]    place tile/press button
+
+(4) Editing:
+
+ [mouse right]   grab color
+ [mouse left]    place color/press button
+
+         Another tool that comes in handy for grafix is Romhack.
+(desciption above in section II )  this is  used to find the grafix u 
+want to edit then you press a key and presto you see the bytes
+in hex or ascii, which u can then edit with a hex editor. Rather nifty.
+(HomePage at  http://www.ipsnet.it/netpages/room481)
+
+C. Changing text
+
+        Changing text is a little more complicated than changing graphics.
+First you are going to need to make a text table. To do this, go to a part of
+a game where there is text. Then, load up your pattern tables and find where
+the letters are. In ZELDA 2, for instance, the number 0 is located at D0.
+Other numbers/letters follow, so our chart will look like this:
+
+  0 1 2 3 4 5 6 7 8 9 A B C D E F
+0 
+1
+2
+3
+4
+5
+6
+7
+8
+9
+A
+B
+C
+D 0 1 2 3 4 5 6 7 8 9 A B C D E F
+E G H I J K L M N O P Q R S T U V
+F W X Y Z     -
+
+        Now, open up your hex editor and load the ROM. With given text from
+the game, search for it. For example, ZELDA in Zelda 2 would be F3DEE5DDDA in
+hex. If you do not understand any of this, then text editing is just not for
+you. Now, search through the ROM for your numbers. When you find them, just
+replace the old numbers with the new ones.
+
+NOTE: Do NOT make your word longer than the first word. Shorter is all right,
+if you replace the extra letters with spaces or something else. (Blackfury)
+
+
+
+
+¸,.�¬=椺²°`¯ ¯`°²º¤æ=- Section IV. -=椺²°`¯ ¯`°²º¤æ=¬�.,¸
+
+
+IV. The Nintendo :
+    
+(A) General Architecture :
+
+  NES is based on the 6502 CPU, and a custom video controller known as PPU
+(Picture Processing Unit). The PPU's video memory is separated from the
+main CPU memory and can be read/written via special ports. Cartridges may
+contain both ROM appearing in the main CPU address space at $8000-$FFFF,
+and VROM or VRAM appearing in the PPU address space at $0000-$1FFF and
+containing the Pattern Tables (aka Tile Tables). In smaller cartridges,
+which only have 16kB ROM, it takes place at $C000-$FFFF leaving $8000-$BFFF
+area unused. Internal NES VRAM is located at addresses $2000-$3FFF in the 
+PPU memory. Some cartridges also have RAM at $6000-$7FFF, which may or may
+not be battery-backed. 
+
+CPU Memory Map
+--------------------------------------- $10000
+ Upper Bank of Cartridge ROM
+--------------------------------------- $C000
+ Lower Bank of Cartridge ROM
+--------------------------------------- $8000
+ Cartridge RAM (may be battery-backed)
+--------------------------------------- $6000
+ Expansion Modules
+--------------------------------------- $5000
+ Input/Output
+--------------------------------------- $2000
+ 2kB Internal RAM, mirrored 4 times
+--------------------------------------- $0000
+
+
+(B) Interrupts :
+
+  NES uses non-maskable interrupts (NMIs) generated by PPU in the end of
+each frame (so-called VBlank interrupts). Maskable interrupts, or IRQs,
+can also be generated by circuitry in a cart, but most carts do not
+generate them. The VBlank interrupts can be enabled/disabled by writing
+1/0 into 7th bit of $2000. When a VBlank interrupts occur, CPU pushes
+return address and the status register on stack, and jumps to the address
+stored at location $FFFA (ROM in NES). The interrupt handler is supposed
+to finish its execution with RTI command which returns CPU to the main
+program execution. More information on the interrupt handling can be found
+in a decent book on 6502 CPU. 
+
+
+(C) I/O ports :
+
+   NES internal I/O ports are mapped into the areas of $2000-$2007 and 
+$4000-$4017. Some ports' usage is unknown or unclear, and any information
+is appreciated.
+
+I/O Ports Map
+------+-----+---------------------------------------------------------------
+$2000 | RW  | PPU Control Register 1
+      | 0-1 | Name Table to show:
+      |     |
+      |     |           +-----------+-----------+
+      |     |           | 2 ($2800) | 3 ($2C00) |
+      |     |           +-----------+-----------+
+      |     |           | 0 ($2000) | 1 ($2400) |
+      |     |           +-----------+-----------+
+      |     |
+      |     | Remember, though, that because of the mirroring, there are  
+      |     | only 2 real Name Tables, not 4.
+      |   2 | Vertical Write, 1 = PPU memory address increments by 32:
+      |     |
+      |     |    Name Table, VW=0          Name Table, VW=1
+      |     |   +----------------+        +----------------+
+      |     |   |----> write     |        | | write        |
+      |     |   |                |        | V              |
+      |     |
+      |   3 | Sprite Pattern Table address, 1 = $1000, 0 = $0000
+      |   4 | Screen Pattern Table address, 1 = $1000, 0 = $0000
+      |   5 | Sprite Size, 1 = 8x16, 0 = 8x8
+      |   6 | Hit Switch, 1 = generate interrupts on Hit (incorrect ???)
+      |   7 | VBlank Switch, 1 = generate interrupts on VBlank
+------+-----+---------------------------------------------------------------
+$2001 | RW  | PPU Control Register 2
+      |   0 | Unknown (???)
+      |   1 | Image Mask, 0 = don't show left 8 columns of the screen
+      |   2 | Sprite Mask, 0 = don't show sprites in left 8 columns 
+      |   3 | Screen Switch, 1 = show picture, 0 = blank screen
+      |   4 | Sprites Switch, 1 = show sprites, 0 = hide sprites
+      | 5-7 | Unknown (???)
+------+-----+---------------------------------------------------------------
+$2002 | R   | PPU Status Register
+      | 0-5 | Unknown (???)
+      |   6 | Hit Flag, 1 = PPU refresh has hit sprite #0
+      |     | This flag resets to 0 when VBlank starts, or CPU reads $2002
+      |     | (see "Hit/VBlank Bits").
+      |   7 | VBlank Flag, 1 = PPU is generating a Vertical Blanking Impulse
+      |     | This flag resets to 0 when VBlank ends, or CPU reads $2002
+      |     | (see "Hit/VBlank Bits").
+------+-----+---------------------------------------------------------------
+$2003 | W   | Sprite Memory Address
+      |     | Used to set the address in the 256-byte Sprite Memory to be 
+      |     | accessed via $2004. This address will increment by 1 after
+      |     | each access to $2004. The Sprite Memory contains coordinates,
+      |     | colors, and other attributes of the sprites (see "Sprites").
+------+-----+---------------------------------------------------------------
+$2004 | RW  | Sprite Memory Data
+      |     | Used to read/write the Sprite Memory. The address is set via
+      |     | $2003 and increments after each access. The Sprite Memory 
+      |     | contains coordinates, colors, and other attributes of the 
+      |     | sprites (see "Sprites").
+------+-----+---------------------------------------------------------------
+$2005 | W   | Background Scroll
+      |     | There are two scroll registers, vertical and horizontal, 
+      |     | which are both written via this port. The first value written
+      |     | will go into the Vertical Scroll Register (unless it is >239,
+      |     | then it will be ignored). The second value will appear in the
+      |     | Horizontal Scroll Register. The Name Tables are assumed to be
+      |     | arranged in the following way:
+      |     |
+      |     |           +-----------+-----------+
+      |     |           | 2 ($2800) | 3 ($2C00) |
+      |     |           +-----------+-----------+
+      |     |           | 0 ($2000) | 1 ($2400) |
+      |     |           +-----------+-----------+
+      |     |
+      |     | When scrolled, the picture may span over several Name Tables.
+      |     | Remember, though, that because of the mirroring, there are
+      |     | only 2 real Name Tables, not 4.
+------+-----+---------------------------------------------------------------
+$2006 |     | PPU Memory Address
+      |     | See "PPU Memory".
+------+-----+---------------------------------------------------------------
+$2007 |     | PPU Memory Data
+      |     | See "PPU Memory".
+------+-----+---------------------------------------------------------------
+$4000-$4013 | Sound Registers
+            | See "Sound".
+------+-----+---------------------------------------------------------------
+$4014 | W   | DMA Access to the Sprite Memory
+      |     | Writing a value N into this port, causes an area of CPU memory
+      |     | at address $100*N to be transferred into the Sprite Memory.
+------+-----+---------------------------------------------------------------
+$4015 | W   | Sound Switch
+      |   0 | Channel 1, 1 = enable sound
+      |   1 | Channel 2, 1 = enable sound
+      |   2 | Channel 3, 1 = enable sound
+      |   3 | Channel 4, 1 = enable sound
+      |   4 | Channel 5, 1 = enable sound
+      | 5-7 | Unused (???)
+------+-----+---------------------------------------------------------------
+$4016 | RW  | Joystick 1 + Strobe
+      |   0 | Joystick 1 data
+      |   1 | Joystick 1 presence, 0 = connected
+      | 2-5 | Unused, set to 0 (???)
+      | 6-7 | Unknown, set to 10 (???)
+      |     | See "Joysticks".
+------+-----+---------------------------------------------------------------
+$4017 | R   | Joystick 2
+      |   0 | Joystick 2 data
+      |   1 | Joystick 2 presence, 0 = connected
+      | 2-5 | Unused, set to 0 (???)
+      | 6-7 | Unknown, set to 10 (???)
+      |     | See "Joysticks".
+------+-----+---------------------------------------------------------------
+
+
+(D) PPU Memory :
+
+  In a real NES, reading/writing PPU memory should only be attempted
+during VBlank period. Many smaller ROMs have read-only memory (VROM) for
+the Pattern Tables. In this case, you won't be able to write into this
+memory. The $3F00 and $3F10 locations in VRAM mirror each other (i.e. it
+is the same memory cell) and define the background color of the picture. 
+
+   Writing to PPU memory:
+   a) Write upper address byte into $2006
+   b) Write lower address byte into $2006
+   c) Write data into $2007. After each write, the address will
+      increment either by 1 (bit 2 of $2000 is 0) or by 32 (bit 2 of
+      $2000 is 1).
+
+   Reading from PPU memory:
+   a) Write upper address byte into $2006
+   b) Write lower address byte into $2006
+   c) Read data from $2007. The first byte read from $2007 will be
+      invalid. Then, the address will increment by 1 after each
+      read.
+
+  Name Table contains tile numbers organized into 32 rows of 32 bytes
+each. Tiles are 8x8 pixels each. Therefore, the whole Name Table is 32x32
+tiles or 256x256 pixels. In the NTSC version of NES, upper and lower 16
+pixels are not shown, thus, the screen becomes 256x224 pixels. In the PAL
+version of NES, upper and lower 8 pixels are not show, thus, the screen
+becomes 256x240 pixels.
+
+  Pattern Table contains tile images in the following format:
+
+  Character   Colors      Contents of Pattern Table
+  ...o....    00010000    00010000 $10  +-> 00000000 $00
+  ..O.O...    00202000    00000000 $00  |   00101000 $28
+  .0...0..    03000300    01000100 $44  |   01000100 $44
+  O.....O.    20000020    00000000 $00  |   10000010 $82
+  ooooooo. -> 11111110    11111110 $FE  |   00000000 $00
+  O.....O.    20000020    00000000 $00  |   10000010 $82
+  0.....0.    30000030    10000010 $82  |   10000010 $82
+  ........    00000000    00000000 $00  |   00000000 $00
+                              +---------+
+
+  Note that only two bits for each pixel of a character are stored in the
+Pattern Table. Other two are taken from the Attribute Table. Thus, the total
+number of simultaneous colors on the NES screen is 16.
+
+  Each byte in the Attribute Table represents a 4x4 group of tiles on the 
+screen, which makes an 8x8 attribute table. Each 4x4 tile group is
+subdivided into four 2x2 squares as follows:
+
+   (0,0)  (1,0) 0|  (2,0)  (3,0) 1
+   (0,1)  (1,1)  |  (2,1)  (3,1)
+   --------------+----------------
+   (0,2)  (1,2) 2|  (2,2)  (3,2) 3
+   (0,3)  (1,3)  |  (2,3)  (3,3)
+
+  The attribute byte contains upper two bits of the color number for each
+2x2 square (the lower two bits are stored in the Pattern Table): 
+
+  Bits   Function                        Tiles
+  --------------------------------------------------------------
+  7,6    Upper color bits for square 3   (2,2),(3,2),(2,3),(3,3)    
+  5,4    Upper color bits for square 2   (0,2),(1,2),(0,3),(1,3)
+  3,2    Upper color bits for square 1   (2,0),(3,0),(2,1),(3,1)
+  1,0    Upper color bits for square 0   (0,0),(1,0),(0,1),(1,1)
+   
+  There are two 16-byte Palette Tables: the one at $3F00, used for the
+picture, and another one at $3F10, containing the sprite palette. The
+$3F00 and $3F10 locations in VRAM mirror each other (i.e. it is the same
+memory cell) and define the background color of the picture. 
+
+  There is only enough VRAM for 2 Name Tables and Attribute Tables. Two
+others are going to be mirrors of the first two, i.e. exact copies of them.
+Which pages are mirrored depends on the cartridge circuitry. With vertical
+mirroring, tables 2 and 3 are the mirrors of pages 0 and 1 appropriately.
+With horizontal mirroring, pages 1 and 3 are the mirrors of pages 0 and 2
+appropriately.
+
+PPU Memory Map
+--------------------------------------- $4000
+ Empty
+--------------------------------------- $3F20
+ Sprite Palette
+--------------------------------------- $3F10
+ Image Palette
+--------------------------------------- $3F00
+ Empty
+--------------------------------------- $3000
+ Attribute Table 3
+--------------------------------------- $2FC0
+ Name Table 3 (32x25 tiles)
+--------------------------------------- $2C00
+ Attribute Table 2
+--------------------------------------- $2BC0
+ Name Table 2 (32x25 tiles)
+--------------------------------------- $2800
+ Attribute Table 1
+--------------------------------------- $27C0
+ Name Table 1 (32x25 tiles)
+--------------------------------------- $2400
+ Attribute Table 0
+--------------------------------------- $23C0
+ Name Table 0 (32x25 tiles)
+--------------------------------------- $2000
+ Pattern Table 1 (256x2x8, may be VROM)
+--------------------------------------- $1000
+ Pattern Table 0 (256x2x8, may be VROM)
+--------------------------------------- $0000
+
+
+(E) Hit/VBlank Bits 
+
+   The VBlank flag is contained in the 7th bit of read-only location $2002. 
+It indicates whether PPU is scanning the screen, or generating a vertical
+blanking impulse. It is set in the end of each frame (scanline 232), and
+stays on until the next screen refresh starts from the scanline 8. The
+program can reset this bit prematurely by reading from $2002.
+
+   The Hit flag is contained in the 6th bit of read-only location $2002. 
+It goes to 1 when PPU starts refreshing the first scanline where sprite#0
+is located. For example, if sprite#0's Y coordinate is 34, the Hit flag
+will be set in scanline 34. The Hit flag is reset when vertical blanking
+impulse starts. The program can reset this bit prematurely by reading from
+$2002. 
+
+
+(F) Joysticks :
+
+  There are two joysticks which are accessed via locations $4016 and
+$4017. To reset joysticks, write first 1, then 0 into $4016. This way, you
+will generate a strobe in the joysticks' circuitry. Then, read either from
+$4016 (for joystick 0) or from $4017 (for joystick 1).  Each read will
+give you the status of a single button in the 0th bit (1 if pressed, 0
+otherwise): 
+
+Read # |    1      2      3      4      5      6      7      8
+-------+---------------------------------------------------------
+Button |    A      B   SELECT   START   UP    DOWN   LEFT  RIGHT
+
+  Bit 1 indicates whether joystick is connected to the port or not. It is
+set to 0 if the joystick is connected, 1 otherwise. Bits 6 and 7 of
+$4016/$4017 also seem to have some significance, which is not clear yet.
+The rest of bits is set to zeroes. Some games expect to get *exactly* $41
+from $4016/$4017, if a button is pressed, which has to be taken into
+account. 
+
+
+(G) Sprites :
+
+  There are 64 sprites, which can be either 8x8 or 8x16 pixels. Sprites
+patterns are stored in one of the Pattern Tables in the PPU Memory. Sprite
+attributes are stored in the Sprite Memory of 256 bytes, which is not a
+part of neither CPU nor PPU address space. The entire contents of Sprite
+Memory can be written via DMA transfer using location $4014 (see above).
+Sprite Memory can also be accessed byte-by-byte by putting the starting
+address into $2003 and then writing/reading $2004 (the address will be
+incremented after each access). The format of sprite attributes is as
+follows: 
+
+Sprite Attribute RAM:
+| Sprite#0 | Sprite#1 | ... | Sprite#62 | Sprite#63 |
+     |          |
+     +---- 4 bytes: 0: Y position of the left-top corner - 1
+                    1: Sprite pattern number
+                    2: Color and attributes:
+                       bits 1,0: two upper bits of color
+                       bits 2,3,4: Unknown (???)
+                       bit 5: if 1, display sprite behind background
+                       bit 6: if 1, flip sprite horizontally
+                       bit 7: if 1, flip sprite vertically
+                    3: X position of the left-top corner
+
+Sprite patterns are fetched in the exactly same way as the tile patterns
+for the background picture. The only difference occurs in the 16x8
+sprites: the top half of the sprite is taken from the Sprite Pattern Table
+set in the $2000 port, while the bottom part is taken from the same
+location of the alternative Pattern Table. Therefore, if PPU is displaying
+a 16x8 sprite, and the Sprite Pattern Table is set to $1000, the bottom
+half of this sprite will be taken out of the $0000 Pattern Table, and vice
+versa. 
+
+
+(H) Memory Mappers :
+
+  There are many diffirent memory mappers (aka MMCs) used in the NES 
+cartridges. They are used to switch ROM and VROM pages, and do some other 
+tasks. I will only describe the MMCs I'm familiar with. Any new 
+information on these and other MMCs is highly appreciated. The MMC 
+numbers are given in terms of the .NES file field "Mapper Type".
+
+
+1.  Mapper #1, Sequential
+
+  This is a sequential mapper used in many 256kB cartridges, such as
+Bomberman 2, Destiny Of The Emperor, Megaman 2, Airwolf, Operation Wolf,
+Castlevania 2, Silk Worm, Yoshi, Break Thru. It may be used to switch ROM
+and VROM. If there is no VROM, 8kB of VRAM is present at $0000. In some
+cases (mostly RPG games) such cartridges also contain battery-backed RAM
+at $6000-$7FFF. The mapper has four 5bit registers, which are accessed via
+following addresses: 
+
+Register  Address Range  Function
+---------------------------------------------------------------------------
+0         $8000-$9FFF    Mirroring and VROM Page Size select
+          The 0th bit of this register selects the mirroring type (1 for
+          horizontal, 0 for vertical). The 4th bit selects the size of
+          VROM pages. When it is 1, two 4kB VROM pages can be switched
+          independently at $0000 and $1000. Otherwise, there is a single
+          8kB VROM page at $0000.
+
+1         $A000-$BFFF    VROM page select
+          This register sets either 8kB or 4kB VROM page at $0000,
+          depending on the page size selected via register 0.
+
+2         $C000-$DFFF    Second VROM page select for 4kB pages
+          If 4kB VROM pages selected via register 0, this register sets
+          the VROM page at $1000. Otherwise, its value is ignored.
+
+3         $E000-$FFFF    ROM page select
+          This register sets 16kB ROM page at $8000. The page at $C000 is 
+          always hardwired to the last ROM page in the cartridge. The 
+          cartridge starts with page 0 at $8000.
+---------------------------------------------------------------------------
+
+  In order to write to a mapper register, write $80 into any of the
+locations first. This will reset the mapper. Then write the value bit by
+bit into an appropriate address range. For example, the following assembly
+code will write $0C into register 3: 
+
+     lda  #$80     ; Resetting mapper
+     sta  $8000    ;
+     lda  #$0C     ; This is our value
+     sta  $EFD9    ; Writing bit 0
+     lsr  a        ; Shifting
+     sta  $EFD9    ; Writing bit 1
+     lsr  a        ; Shifting
+     sta  $EFD9    ; Writing bit 2
+     lsr  a        ; Shifting
+     sta  $EFD9    ; Writing bit 3
+     lsr  a        ; Shifting
+     sta  $EFD9    ; Writing bit 4
+
+
+2. Mapper #2, Konami
+
+  This is a quite simple mapper used in most Konami (Life Force,
+Castlevania, Metal Gear) and some other cartridges. It only switches the
+ROM. All cartridges with this mapper have 8kB VRAM at $0000 (i.e. no
+VROM). The mapper has a single 8bit register which can be written via
+locations $8000-$FFFF. It contains a number of 16kB ROM page at $8000. 
+The page at $C000 is always hardwired to the last ROM page in the
+cartridge. The cartridge starts with page 0 at $8000.
+
+  There is one more thing to note about this mapper: although any address
+in the $8000-$FFFF range can be used to access the mapper, most games
+prefer to use the address with the last digit equal to the value they
+write out. Thus, $07 can be written to $9FF7, $05 to $9FF5, and so forth.
+The reason for this is unknown. 
+
+
+3. Mapper #3, VROM Switch
+
+  Mapper #3, also known as a VROM switch, is used in the Goonies series
+and many Japanese-only games. It only allows you to switch 8kB pages of
+VROM. The ROM is either 16kB or 32kB and is not paged. The mapper has a
+single 8bit register which can be written via locations $8000-$FFFF. It
+contains a number of 8kB VROM page at $0000. 
+
+  As with mapper #2, many games use locations with the last digit equal to
+the value being written. I do not know why. 
+
+
+4. Mapper #4, 5202 Chip (???)
+
+  This mapper (or should I say 'an expansion chip'?) is used in many
+recent cartridges, such as Batman Returns, Super Contra, Vindicators,
+Silver Surfer, etc. It is an extremely complicated device, which is able
+to generate its own interrupts via IRQ line, and has a set of commands to
+switch ROM and VROM. VROM pages are 1kB, ROM pages appear to be 8kB. I do
+not completely understand how this mapper works, so any information is
+appreciated. 
+
+  The chip is controlled via following locations:
+
+Address  Function
+---------------------------------------------------------------------------
+$8000    A command number (0-7) is written here. Also, write to this 
+         register appears to reset the change made by a write into $E000.
+$8001    An value for command is written here.
+$A000    The 0th bit controls mirroring (1 = horizontal mirroring).
+$A001    Same as $8001 (???)
+$C000    Unknown
+$C001    Unknown
+$E000    The 5th bit appears to swap memory at $8000-$8FFF and 
+         $A000-$AFFF, when set to 1.
+$E001    Unknown
+---------------------------------------------------------------------------
+
+  In order to use the mapper, you should first write a command number 
+into $8000, and then a value (page number) into $8001. Following commands 
+exist:
+
+Cmd  Function
+---------------------------------------------------------------------------
+ 0   Select 2 consequent 1kB VROM pages at $0000. The 0th bit of a value
+     written into $8001 does not matter, i.e. 5 will always select pages
+     4 and 5.
+ 1   Select 2 consequent 1kB VROM pages at $0800. The 0th bit of a value
+     written into $8001 does not matter, i.e. 5 will always select pages
+     4 and 5.
+ 2   Select a 1kB VROM page at $1000.
+ 3   Select a 1kB VROM page at $1400.
+ 4   Select a 1kB VROM page at $1800.
+ 5   Select a 1kB VROM page at $1C00.
+ 6   Select a 8kB ROM page at $8000. The initial value seems to be 0.
+ 7   Select a 8kB ROM page at $A000. The initial value seems to be 1.
+---------------------------------------------------------------------------
+
+  Note that the ROM pages at $C000 and $E000 are hardwired to the last 
+pages of the ROM, and can not be switched (they can be swapped via 
+$E000 though).
+
+
+5. Other mappers
+
+  There are several other mappers, some of them very sophisticated. iNES
+partially supports them, but as this support either doesn't work
+correctly, or the mappers are uncommon (such as 100-in-1 cartridge mapper,
+I don't cover them here. (Marat Fayzullin)
+
+**Note : This is provided to help rom hackers understand the nintendo.
+Provided in the above is the sprite maps, which is most useful. :)
+
+
+¸,.�¬=椺²°`¯ ¯`°²º¤æ=- Section V. -=椺²°`¯ ¯`°²º¤æ=¬�.,¸
+
+
+ V. Sample walkthrough
+
+        We're going to change Zelda 2 around a little bit. Load it up and
+start where the princess is sleeping. Go to View --> Pattern tables. In the
+tables, click on the left side of the table 3 times, or until the tiles are
+brown, tan, green, and black. Click on the upper left tile; this is Link's
+face. Click on the black color then click on where Link's eyes are. Black
+signifies that it is see through, so now you can see the background through
+Link's head. Now save it by clicking on File --> Write VROM. Now go to the
+first town. Talk to somebody. Now open your pattern tables again and locate
+the letters. In this case, 0 is D0, and so on as stated in the above table.
+Now load up a hex editor. Use the table to find a complete word (or two), with
+F4's being spaces in Zelda 2. Search for at least 7 letters in a word so you
+now you are editing the right thing. Replace those numbers with, say, F1, or
+'X'. Save the ROM. Back in NESticle, load up your new ROM. Go back to that
+same person, and talk to him/her. Does his speech seem a little different?  
+(Blackfury)
+
+¸,.�¬=椺²°`¯ ¯`°²º¤æ=- Section VI. -=椺²°`¯ ¯`°²º¤æ=¬�.,¸
+
+
+VI. The Big Thanks and Credits:
+
+     (A) Marat Fayzullin ( for letting us know how a nintendo works) ;)
+     (B) Planet X Software ( for their great tools )
+     (C) Nesticle        ( for letting us relive the old days of nes )
+     (D) Fabrizio Zavagli ( for Romhack )
+     (E) Black Hole      ( for Ctool )
+     (F) WonderBoy       ( for Kill them )
+
+<<<<<<<<<<<<<<<<< Where can u find us ? >>>>>>>>>>>>>>>>>>>>>>
+
+We have a homepage up at:
+Http://T3.great.sk/romhack/index.html
+and u can find us on IRC
+
+Who R We?
+
+SeRiAlKLR
+Corrosion
+FireWolf
+Blackfury
+XscrawlX
+Gargamel
+Gloone
+
+Thanks for using this. I hope you find it usefull..well until
+version 0.2 anyways. L8R
+
+-SK'97 (author)
+created on June 5th 1997
+<<<<<<<<<<<<<<<<<< And they all lived happily ever after >>>>>>>>>>>>>>>
+The end of "The Rom Hackers Bible v0.1"
+<<<<<<<<<<<<<<<<<<  ROMHACKERS INC. (c) 1997 >>>>>>>>>>>>>>>>>>>>>>>>>>>

+ 335 - 0
files/docs/snes/snes_cart1.txt

@@ -0,0 +1,335 @@
+------------------------------------- -  -   -    -
+SNES CART HACKING INFO #1 BY SIUDYM
+---------------------------------------- -  -   -    -     -
+
+01. Cartridge Connector LoROM Pinout
+02. Cartridge Connector HiROM Pinout
+03. Mask ROM Pinout
+04. SRAM (2KB) 6216 Pinout
+05. SRAM (8KB) 6264 Pinout
+06. Address Decoder MAD-1 Pinout (ILLUSION OF TIME 2MB HiROM)
+07. Address Decoder MAD-1 Pinout (NBA LIVE 95 1,5MB LoROM)
+08. Address Decoder 74LS00 Pinout (SOCCER SHOOTOUT 1,5MB LoROM)
+09. Address Decoder 74LS00 Pinout (JUSTICE LEAGUE TASK FORCE 3MB LoROM)
+10. Address Decoder 74LS00 Pinout (EARTHWORM JIM 2 - PIRATE 3MB HiROM)
+11. Address Decoder 74LS139 Pinout (SUPER MARIO WORLD 0,5MB LoROM)
+12. Address Decoder 74LS139 Pinout (MORTAL KOMBAT 2 - PIRATE 3MB HiROM (FIRST 2MB FOR MK2, LAST 1MB FOR KILLER INSTINCT DEMO)
+13. Address Decoder 74LS00 Spec.
+14. Address Decoder 74LS139 Spec.
+
+
+-----------------------------------------------------------------------
+01. Cartridge Connector LoROM:
+
+                         ---+---
+                    GND |05 | 36| GND
+                    A11 |06 | 37| A12
+                    A10 |07 | 38| A13
+                     A9 |08 | 39| A14
+                     A8 |09 | 40| NC
+                     A7 |10 | 41| A15
+                     A6 |11 | 42| A16
+                     A5 |12 | 43| A17
+                     A4 |13 | 44| A18
+                     A3 |14 | 45| A19
+                     A2 |15 | 46| A20 
+                     A1 |16 | 47| A21
+                     A0 |17 | 48| A22
+                   /IRQ |18 | 49| /OE
+                     D0 |19 | 50| D4
+                     D1 |20 | 51| D5
+                     D2 |21 | 52| D6
+                     D3 |22 | 53| D7
+                    /CE |23 | 54| /WE
+             Pin 1 D413 |24 | 55| Pin 2 D413
+             Pin 7 D413 |25 | 56| Pin 6 D413
+                 RAM /E |26 | 57| NC
+                    VCC |27 | 58| VCC
+                         ---+---
+
+Pin #23 -> ROM /CE and RAM /OE (connected together)
+Pin #49 -> ROM /OE
+Pin #54 -> RAM /WE
+
+
+
+-----------------------------------------------------------------------
+02. Cartridge Connector HiROM:
+
+                         ---+---
+                    GND |05 | 36| GND
+                    A11 |06 | 37| A12
+                    A10 |07 | 38| A13
+                     A9 |08 | 39| A14
+                     A8 |09 | 40| A15
+                     A7 |10 | 41| A16
+                     A6 |11 | 42| A17
+                     A5 |12 | 43| A18
+                     A4 |13 | 44| A19
+                     A3 |14 | 45| A20
+                     A2 |15 | 46| A21 
+                     A1 |16 | 47| A22
+                     A0 |17 | 48| A23
+                   /IRQ |18 | 49| /OE
+                     D0 |19 | 50| D4
+                     D1 |20 | 51| D5
+                     D2 |21 | 52| D6
+                     D3 |22 | 53| D7
+                    /CE |23 | 54| /WE
+             Pin 1 D413 |24 | 55| Pin 2 D413
+             Pin 7 D413 |25 | 56| Pin 6 D413
+                 RAM /E |26 | 57| NC
+                    VCC |27 | 58| VCC
+                         ---+---
+
+
+Pin #23 -> ROM /CE and RAM /OE (connected together)
+Pin #49 -> ROM /OE
+Pin #54 -> RAM /WE
+
+
+
+-----------------------------------------------------------------------
+03. Mask ROM Pinout:
+
+                        __  __
+                   A20 |  \/  | +5V
+                   A21 |__  __| A22
+                   A17 |01\/32| +5V
+                   A18 |02  31| /OE
+                   A15 |03  30| A19
+                   A12 |04  29| A14
+                    A7 |05  28| A13
+                    A6 |06  27| A8
+                    A5 |07  26| A9
+                    A4 |08  25| A11
+                    A3 |09  24| A16
+                    A2 |10  23| A10
+                    A1 |11  22| /CE
+                    A0 |12  21| D7
+                    D0 |13  20| D6
+                    D1 |14  19| D5
+                    D2 |15  18| D4
+                   GND |16  17| D3
+                        ------
+
+/CE connected to SNES pin #23
+/OE connected to SNES pin #49 or Address Decoder
+
+
+
+-----------------------------------------------------------------------
+04. SRAM (2KB) 6216 Pinout:
+
+                        __  __
+                    A7 |01\/24| +5V
+                    A6 |02  23| A8
+                    A5 |03  22| A9
+                    A4 |04  21| /WE
+                    A3 |05  20| /OE
+                    A2 |06  19| A10
+                    A1 |07  18| /CE
+                    A0 |08  17| D7
+                    D0 |09  16| D6
+                    D1 |10  15| D5
+                    D2 |11  14| D4
+                   GND |12  13| D3
+                        ------
+
+/CE connected to Address Decoder
+/OE connected to /CE in ROM
+/WE connected to SNES pin #54
+
+
+
+-----------------------------------------------------------------------
+05. SRAM (8KB) 6264 Pinout:
+
+                        __  __
+                   +5V |01\/28| +5V
+                   A12 |02  27| /WE
+                    A7 |03  26| NC
+                    A6 |04  25| A8
+                    A5 |05  24| A9
+                    A4 |06  23| A11
+                    A3 |07  22| /OE
+                    A2 |08  21| A10
+                    A1 |09  20| /CE
+                    A0 |10  19| D7
+                    D0 |11  18| D6
+                    D1 |12  17| D5
+                    D2 |13  16| D4
+                   GND |14  15| D3
+                        ------
+
+/CE connected to Address Decoder
+/OE connected to /CE in ROM
+/WE connected to SNES pin #54
+#26 connected to SNES pin #26 (RESET)
+
+
+
+-----------------------------------------------------------------------
+06. Address Decoder MAD-1 Pinout (ILLUSION OF TIME)
+
+                            __  __
+                        NC |01\/16| NC
+                   RAM /CE |02  15| A13
+                        NC |03  14| A14
+                   ROM /OE |04  13| A21
+                       +5V |05  12| A22
+                       +5V |06  11| SNES #49
+                       +5V |07  10| GND
+                       GND |08  09| SNES #26 and RAM #26 (only in 6264)
+                            ------
+
+
+
+-----------------------------------------------------------------------
+07. Address Decoder MAD-1 Pinout (NBA LIVE 95)
+
+                            __  __
+                  ROM2 /OE |01\/16| ROM1 /OE
+                   RAM /CE |02  15| SNES #40
+                        NC |03  14| A19
+                        NC |04  13| A20
+                       +5V |05  12| A21
+                       +5V |06  11| SNES #49
+                       +5V |07  10| GND
+                       GND |08  09| SNES #26 and RAM #26 (only in 6264)
+                            ------
+
+
+
+-----------------------------------------------------------------------
+08. Address Decoder 74LS00 Pinout (SOCCER SHOOTOUT)
+ 
+                        __  __
+                   +5V |01\/14| +5V
+              SNES #49 |02  13| A20
+                    NC |03  12| +5V
+                    NC |04  11| NC
+                   A20 |05  10| NC
+              ROM2 /OE |06  09| NC
+                   GND |07  08| ROM1 /OE
+                        ------
+
+
+Pins #03, #04, #09 connected together (NC)
+Pins #05, #13 connected together (A20)
+Pins #11, #10 connected together (NC)
+
+
+
+-----------------------------------------------------------------------
+09. Address Decoder 74LS00 Pinout (JUSTICE LEAGUE TASK FORCE)
+
+                        __  __
+                   +5V |01\/14| +5V
+              SNES #49 |02  13| A21
+                    NC |03  12| NC
+                   +5V |04  11| ROM2 /OE
+                   A21 |05  10| NC
+                    NC |06  09| NC
+                   GND |07  08| ROM1 /OE
+                        ------
+
+
+Pins #03, #12, #10 connected together (NC)
+Pins #05, #13 connected together (A21)
+Pins #06, #09 connected together (NC)
+
+
+
+-----------------------------------------------------------------------
+10. Address Decoder 74LS00 Pinout (EARTHWORM JIM 2 - PIRATE)
+
+                        __  __
+              SNES #49 |01\/14| +5V
+              SNES #49 |02  13| A21
+                    NC |03  12| NC
+                   A21 |04  11| ROM2 /OE
+                   A21 |05  10| NC
+                    NC |06  09| NC
+                   GND |07  08| ROM1 /OE
+                        ------
+
+
+Pins #03, #12, #10 connected together (NC)
+Pins #04, #05, #12 connected together (A21)
+Pins #06, #09 connected together (NC)
+Pins #01, #02 connected together (#49)
+
+
+
+-----------------------------------------------------------------------
+11. Address Decoder 74LS139 Pinout (SUPER MARIO WORLD)
+
+                            __  __
+                  SNES #49 |01\/16| +5V
+                       A21 |02  15| NC
+                       A20 |03  14| A19
+                   ROM /OE |04  13| NC
+                        NC |05  12| NC
+                        NC |06  11| NC
+                        NC |07  10| NC
+                       GND |08  09| RAM /CE
+                            ------
+
+
+Pins #07, #15 connected together (NC)
+
+
+
+-----------------------------------------------------------------------
+12. Address Decoder 74LS139 Pinout (MORTAL KOMBAT 2 - PIRATE 3MB VERSION)
+
+                            __  __
+                  SNES #23 |01\/16| +5V
+                       A21 |02  15| NC
+                       GND |03  14| NC
+           ROM1 /OE or /CE |04  13| NC
+           ROM2 /OE or /CE |05  12| NC
+                        NC |06  11| NC
+                        NC |07  10| NC
+                       GND |08  09| NC
+                            ------
+
+
+
+-----------------------------------------------------------------------
+13. Address Decoder 74LS00 Spec.
+
+                        __  __
+                    1A |01\/14| +5V
+                    1B |02  13| 4B
+                    1Y |03  12| 4A
+                    2A |04  11| 4Y
+                    2B |05  10| 3B
+                    2Y |06  09| 3A
+                   GND |07  08| 3Y
+                        ------
+
+
+
+-----------------------------------------------------------------------
+14. Address Decoder 74LS139 Spec.
+
+                            __  __
+                        1E |01\/16| +5V
+                       1A0 |02  15| 2E
+                       1A1 |03  14| 2A0
+                       1Y0 |04  13| 2A1
+                       1Y1 |05  12| 2Y0
+                       1Y2 |06  11| 2Y1
+                       1Y3 |07  10| 2Y2
+                       GND |08  09| 2Y3
+                            ------
+
+
+
+-----------------------------------------------------------------------
+      2001 siudym@pf.pl
+
+
+

+ 1385 - 0
files/docs/snes/snesmap.txt

@@ -0,0 +1,1385 @@
+I have no idea where this document came from (EPR? Who knows..), there's no credits anywhere
+or anything... weird.  Anyways, it was really hard with my eyes so I told Wordperfect to convert it
+to  initial caps' since there was no  Capitalize the first word of each line or sentence and leave
+abbreviations the way they are' option.
+     - Qwertie
+
+Address  : $2100
+Name     : Inidisp
+Contents : Initial Settings for Screen
+
+     D7   Blanking:
+               Forced Blanking, 0:non-blanking,1:blanking.
+
+        D6-d4   ---
+
+        D3-d0   Fade In/out:
+               0000-darkest,1111-brightest.
+
+
+Address  : $2101
+Name     : Obsel
+Contents : Object Size & Object Data Area Designation
+
+     D7-d5     Size Select:
+               D7 D6 D5   0   1  (Size Large/small)
+                0  0  0   8  16
+                0  0  1   8  32
+                0  1  0   8  64
+                0  1  1  16  32
+                1  0  0  16  64
+                1  0  1  32  64 (Dots.)
+
+     D4-d3     Name Select
+               The Upper 4k-word Out of the Area (8k-word)
+               Designated by "Object Base Address" is Assigned
+               As the Base Area, and the Area of the Lower 4k-
+               Word Combined with its Base Area Can Be
+               Selected. (See Appendix 1 & 2)
+
+     D2-d0     Name Base Select (Upper-3 Bit)
+               Designate the Segment (8k-word) Address Which
+               The Obj Data is Stored in Vram.    (Appendix 1 & 2)
+
+
+Address  : $2102/$2103
+Name     : Oamaddl/oamaddh
+Contents : Address for Accessing Oam
+
+     D7-d0     Oam Address (A7-a0)                2102h
+
+     D7   Oam Priority Rotation                   2103h
+     D6-d1     ---
+     D0   Oam Address Msb (A8)
+
+          This is the Initial Address to Be Set in Advance When Reading
+       Reading From the Oam Or Writing to the Oam.
+
+          By Writing "1" to D7 of Register <2103h> and Setting the Oam-
+       Address the Obj for the Address Set Has Highest Priority.
+
+          The Address Which Has Been Set Just Before Every Field
+       (Beginning of V-blank) Will Be Set Again to Registers <2102h>
+       <2103h> Automatically. But, the Address Can Not Be Set
+       Automatically During Forced Blank Period.
+
+
+Address  : $2104
+Name     : Oamdata
+Contents : Data for Oam Write
+
+     D7-d0     Oam Data (Low,high)
+
+          This is the Oam Data to Be Writting At Any Address of the Oam.
+       (See Appendix-3)
+
+          After Register <2102h> Or <2103h> is Accessed, the Data Must
+       Be Written in the Order of Lower 8-bit & Upper 8-bit of Register
+       <2104h>.
+
+          The Data Can Be Written Only During V-blank Or Forced Blank
+       Period.
+
+
+Address  : $2105
+Name     : Bgmode
+Contents : Bg Mode & Character Size Settings
+
+     D7-d4     Bg Size Designation (Bg4-bg1)
+               0:   8 X  8 Dot/character
+               1:  16 X 16 Dot/character
+
+     D3   Highest Priority Designation for Bg-3 in Mode 1
+               0: Off (See Appendix-16)
+               1: on
+
+     D2-d0     Bg Screen Mode Select (See Appendix-5)
+
+
+Address  : $2106
+Name     : Mosaic
+Contents : Size & Screen Designation for Mosaic Display
+
+     D7-d4     Mosaic Size (See Appendix-6)
+               1111 - Largest, 0000 - Smallest.
+
+     D3-d0     Mosaic Enable (Bg4-b1)
+               0: Off
+               1: on
+
+
+Address  : $2107/$2108/$2109/$210a
+Name     : Bg1sc/bg2sc/bg3sc/bg4sc
+Contents : Address for Storing Sc-data of Each Bg & Sc Size Designation
+
+     D7-d2     Sc Base Address
+               Designate the Segment Which Bg-sc in the Vram
+               Is Stored. (1k-word/segment)
+
+     D1-d0     Sc Size
+               Designate Background Screen Size (Appendix-18 & 19)
+               0 0  0 0    1 0  0 0    0 1  0 1    1 1  0 1
+                    0 0         1 1         0 1         2 3
+
+
+Address  : $210b/$210c
+Name     : Bg12nba/bg34nba
+Contents : Bg Character Data Are Designation
+
+     D7-d4     Bg2 Base Address                   210bh
+     D3-d0     Bg1 Base Address
+
+     D7-d4     Bg4 Base Address                   210ch
+     D3-d0     Bg3 Base Address
+
+          Background Name Base Address (Upper 4-bit), Segment Address
+       In the Vram Where Bg Character Data is Stored. (4k-word/segment)
+
+
+Address  : $210d/$210e/$210f/$2110/$2111/$2112/$2113/$2114
+Name     : Bg1hofs/bg1vofs/bg2hofs/bg2vofs/bg3hofs/bg3vofs/bg4hofs/bg4vofs
+Contents : H/v Scroll Value Designation for Bg
+
+     D7-d0     H-offset (Low,high)                Hofs
+
+     D7-d0     V-offset (Low,high)                Vofs
+
+          10 Bit Maximum (0-1023) Can Be Designated for H/v Scroll Value.
+       [The Size of 13-bit Maximum (-4096->4095) Can Be Designated in
+       Mode 7] (See Appendix-8 & 9)
+
+          By Writing to the Register Twice, the Data Can Be Set in Order
+       Of Low & High.
+
+
+Address  : $2115
+Name     : Vmain
+Contents : Vram Address Increment Value Designation
+
+     D7   H/l Inc (Word Or Byte Vram Access)
+
+               Designate the Increment Timing for the Address
+               0: the Address Will Be Increased After the Data Has
+                  Been Written to Register <2118h> Or the Data
+                  Has Been Read From Register <2139h>.
+                  This Will Result in Byte Vram Access, I.e. for
+                  Mode 7 Tile Map Change.
+
+               1: the Address Will Be Increased After the Data Has
+                  Been Written to Register <2119h> Or the Data
+                  Has Been Read From Register <213ah>.
+                  This Will Result in Word Vram Access, I.e. for
+                  Mode 1 Tile Map Change.
+
+     D6-d4     ---
+
+     D3-d2     Full Graphic (G1 & G0)
+
+     D1-d0     Sc Increment (I1 & I0)
+
+
+     G1 G0 I1 I0 | Increment Value
+     ----------------------------
+      0  1  0  0 | Increment by 8 for 32 Times (2-bit Formation)
+      1  0  0  0 | Increment by 8 for 64 Times (4-bit Formation)
+      1  1  0  0 | Increment by 8 for 128 Times (8-bit Formation)
+      0  0  0  0 | Address Increments 1 by 1
+      0  0  0  1 | Address Increments 32 by 32
+      0  0  1  0 | Address Increments 64 by 64
+      0  0  1  1 | Address Increments 128 by 128
+
+
+Address  : $2116/$2117
+Name     : Vmaddl/vmaddh
+Contents : Address for Vram Read
+
+     D7-d0     Vram Address (Low)                 2116h
+     D7-d0     Vram Address (High)                2117h
+
+          This is the Initial Address for Reading From the Vram Or Writing
+       To the Vram.
+
+          The Data is Read Or Written by the Address Set Initially, and
+       Every Time the Data is Read the Address Wil Be Increased
+       Automatically.
+
+          The Value to Be Increased is Determined by "Sc Increment" of
+       Register <2115h> and the Setting Value of the "Full Graphic".
+
+
+Address  : $2118/$2119
+Name     : Vmdatal/vmdatah
+Contents : Data for Vram Write
+
+     D7-d0     Vram Data (Low)                         2118h
+     D7-d0     Vram Data (High)                   2119h
+
+          This is the Screen Data and Character Data (Bg & Obj), Which
+       Can Write At Any Address of the Vram.
+
+          According to the Setting of Register <2115h> "H/l Inc.", the
+       Data Can Be Written to the Vram As Follows:
+
+     H/l Inc  |  Write to Register  |  Operation
+        --------------------------------------------------------------
+         0    |  Write to <2118h>   |  the Data is Written to Lower 8bit
+              |  Only.              |  of the Vram & the Address Will Be
+           |                     |  Increased Automatically.
+         1    |  Write to <2119h>   |  the Data is Written to Upper 8bit
+              |  Only.              |  of the Vram & the Address Will Be
+              |                     |  Increased Automatically.
+         0    |  Write in Order of  |  When the Data is Set in the Order
+              |  <2119h> & <2118h>  |  of Upper & Lower the Address Will
+              |                     |  Be Increased.
+         1    |  Write in Order of  |  When the Data is Set in the Order
+              |  <2118h> & <2119h>  |  of Lower & Upper the Address Will
+              |                     |  Be Increased.
+
+     Note:     the Data Can Only Be Written During V-blank Or Forced Blank
+     ~~~~~     Period.
+
+
+Address  : $211a
+Name     : M7sel
+Contents : Initial Setting in Screen Mode-7
+
+     D7-d6     Screen Over (O1 & O0)
+               Process Made If the Screen to Be Displayed is
+               Outside of the Screen Area. (See Below)
+
+     D5-d2     ---
+
+     D1-d0     Screen Flip (V/h)
+               0: Normal
+               1: Flipped
+
+     O1 O0  |  Process Out of Area
+        --------------------------------------------------------------
+      0  0  |  Screen Repetition If Outside of Screen Area
+      1  0  |  Character 0x00 Repetition If Outside of Screen Area
+      1  1  |  Outside of the Screen Area is the Back Drop Screen in
+            |  Single Color
+
+
+Address  : $211b/$211c/$211d/$211e/$211f/$2120
+Name     : M7a/m7b/m7c/m7d/m7x/m7y
+Contents : Rotation/enlargement/reduction in Mode-7, Center Coordinate
+        Settings & Multiplicand/multiplier Settings of Complementary
+        Multiplication.
+
+     D7-d0     Matrix Parameter A (Low[mp7-mp0],High[mp15-mp8])211bh
+     D7-d0     Matrix Parameter B (Low[mp7-mp0],High[mp15-mp8])211ch
+     D7-d0     Matrix Parameter C (Low[mp7-mp0],High[mp15-mp8])211dh
+     D7-d0     Matrix Parameter D (Low[mp7-mp0],High[mp15-mp8])211eh
+
+          The 8-bit Data Should Be Written Twice in the Order of Lower &
+       Upper. Then, the Parameter of Rotation, Enlargement and Reduction
+       Should Be Set by its 16-bit Area.
+
+          The Value Down to A Decimal Point Should Be Set to the Lower
+       8-bit. The Most Significant Bit of the Upper 8-bit is for the
+       Signed Bit. (Mp15 is the Signed Bit. There is A Decimal Point
+       Between M7 & M8)
+
+          Formula for Rotaion/enlargement/reduction (See Appendix-13)
+
+          / X2 \   / A B \ / X1-x0 \   / X0 \
+          |    | = |     | |       | + |    |
+          \ Y2 /   \ C D / \ Y1-y0 /   \ Y0 /
+
+       A=cos(gamma)*(1/alpha), B=sin(gamma)*(1/alpha)
+       C=-sin(gamma)*(1/beta), D=cos(gamma)*(1/beta)
+
+          Gamma: Rotation Angle
+          Alpha: Reduction Rates for X(h)
+          Beta : Reduction Rates for Y(v)
+          X0&y0: Center Coordinate
+          X1&y1: Display Coordinate
+          X2&y2: Coordinate Before Calculation
+
+          Set the Value of "A" to Register <211bh>. In the Same Way,
+       Set "B-d" to the Registers <211ch>-<211eh>.
+
+     * the Complementary Multiplication (16bit X 8bit) Can Be Done by
+       Using Registers <211bh> <211c>.
+       When Setting 16 Bit Data to Register <211bh> and 8bit Data to
+       Register <211ch>, the Multiplication Result Can Be Indicated
+       Rapidly by Reading Registers <2134h>-<2136h>.
+
+     D7-d0     Center Position X0 (Low[x7-x0],High[x12-x8]) 211fh
+     D7-d0     Center Position Y0 (Low[y7-x0],High[y12-x8]) 2120h
+
+          The Center Coordinate (X0,y0) for Rotation/enlargement/reduction
+       Can Be Designated by this Register.
+
+          The Coordinate Value of X0 & Y0 Can Be Designated by 13-bit
+       (Complement of 2).
+
+          The Register Requires That the Lower 8-bit is Set First and the
+       Upper 5-bit is Set. Therefore, 13-bit Data in Total Can Be Set.
+
+
+Address  : $2121
+Name     : Cgadd
+Contents : Address for Cg-ram Write
+
+     D7-d0     Cg-ram Address
+
+          This is the Initial Address for Reading From the Cg-ram Or
+       Writing to the Cg-ram
+
+          The Data is Read by the Address Set Initially, and Every Time
+       The Data is Read Or Written the Address Will Be Increased
+       Automatically.
+
+
+Address  : $2122
+Name     : Cgdata
+Contents : Data for Cg-ram Write
+
+     D7-d0     Cg-ram Data (Low[d7-d0],High[d14-d8])
+
+          This is the Color Generater Data to Be Written At Any Address
+       Of the Cg-ram.
+
+          The Mapping of Bg1-bg4 and Obj Data in Cg-ram Will Be Determined,
+       Which is Performed by Every Mode Selected by "Bg Mode" of
+       Register <2105h>. (See Appendix-14)
+
+          There Area the Color Data of 8-palettes for Each Screen of
+       Bg1-bg4. The Palette Selection is Determined by 3-bit of the
+       Sc Data "Color"
+
+          Because the Cg-ram Data is 15-bit/word, it is Necessary to Set
+       Lower 8-bit First to this Register and the the Upper 7-bit.
+       When Both Lower & Upper Are Set, the Address Will Be Increased
+       By 1 Automatically.
+
+     Note:     After the Address is Set, the Data Should Be Written From
+     ~~~~~     the Lower As Well As the Oam.
+
+     Note:     the Data Can Be Written Only During H/v Blank Or Forced-
+     ~~~~~     Blank Period.
+
+
+Address  : $2123/$2124/$2125
+Name     : W12sel/w34sel/wobjsel
+Contents : Window Mask Settins (Bg1-bg4, Obj, Color)
+
+     D7   Bg2 Window-2 Enable                2123h
+               0: Off
+               1: on
+
+     D6   Bg2 Window-2 In/out
+               The Window Mask Area Can Be Designated Whether
+               Inside Or Outside of the Frame Designated by the
+               Window Position.
+               0: in
+               1: Out
+
+     D5   Bg2 Window-1 Enable
+     D4   Bg2 Window-1 In/out
+     D3   Bg1 Window-2 Enable
+     D2   Bg1 Window-2 In/out
+     D1   Bg1 Window-1 Enable
+     D0   Bg1 Window-1 In/out
+
+     D7   Color Window-2 Enable                   2125h
+     D6   Color Window-2 In/out
+     D5   Color Window-1 Enable
+     D4   Color Window-1 In/out
+     D3   Obj Window-2 Enable
+     D2   Obj Window-2 In/out
+     D1   Obj Window-1 Enable
+     D0   Obj Window-1 In/out
+
+          The Color Window is A Window for Main & Sub Screen (It is
+       Related to Register <2130h>.
+
+
+Address  : $2126/$2127/$2128/$2129
+Name     : Wh0/wh1/wh2/wh3
+Contents : Window Position Designation (See Appendix-15)
+
+     D7-d0     Window Pposition
+
+     H0,h2     Left Position Designation
+     H1,h3     Right Position Designation
+
+     Note:     If "Left Position Setting Value > Right Position Value"
+     ~~~~~     is Assumed, There Will Be No Range of the Window.
+
+
+Address  : $212a/$212b
+Name     : Wbglog/wobjlog
+Contents : Mask Logic Settings for Window-1 & 2 on Each Screen
+
+     D7-d6     Bg4 D1/d0                     212ah
+     D5-d4     Bg3 D1/d0
+     D3-d2     Bg2 D1/d0
+     D1-d0     Bg1 D1/d0
+
+     D7-d4     ---                           212bh
+     D3-d2     Colorwindow D1/d0
+     D1-d0     Objwindow D1/d0
+
+          D1 D0  |  Logic
+             ------------------
+           0  0  |  Or
+           0  1  |  and
+           1  0  |  Xor
+           1  1  |  Xnor
+
+     Note:     "In/out" of Registers <2123h>-<2125h> Becomes the
+     ~~~~~     "Not-logic" for Each Window-1 & Window-2.
+
+
+Address  : $212c
+Name     : Tm
+Contents : Main Screen, Designation
+
+
+     D7-d5     ---
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+
+     Main Screen Designation:
+
+          Designate the Screen (Bg1-bg4, Obj) to Be Displayed
+          As the Main Screen. Designate the Screen to Be Added
+          for the Screen Addition/subtraction
+
+               0: Disable
+               1: Enable
+
+
+Address  : $212d
+Name     : Ts
+Contents : Sub Screen Designation
+
+     D7-d5     ---
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+
+     Sub Screen Designation:
+
+          Designate the Screen (Bg1-bg4, Obj) to Be Displayed
+          As Sub Screen. Designate the Addition/subtraction
+          Screen At the Point When the Screen Addition/subtraction
+          is Functioning.
+
+               0: Disable
+               1: Enable
+
+     * When the Screen Addition/subtraction is Functioning, the Sub
+       Screen is A Screen to Be Added Or Subtracted Against the Main
+       Screen.
+
+
+Address  : $212e
+Name     : Tmw
+Contents : Window Mask Designation for Main Screen
+
+
+     D7-d5     ---
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+
+     Window Mask Designation for Main Screen:
+
+          In the Window Area Designated by Register <2123h>-<2129h>,
+          the Screen to Be Displayed Can Be Designated, Which is
+          Selected Among the Main Screen Designated by Register
+          <212ch>.
+
+               0: Disable
+               1: Enable
+
+
+Address  : $212f
+Name     : Tsw
+Contents : Window Mask Designation for Sub Screen
+
+     D7-d5     ---
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+
+     Window Mask Designation for Sub Screen:
+
+          In the Window Area Designated by Register <2123h>-<2129h>,
+          the Screen to Be Displayed Can Be Designated, Which is
+          Selected Among the Sub Screen Designated by Register
+          <212ch>.
+
+               0: Disable
+               1: Enable
+
+     * When the Screen Addition/subtraction is Functioning, the Sub
+       Screen is A Screen to Be Added Or Subtracted Against the Main
+       Screen.
+
+
+Address  : $2130
+Name     : Cgwsel
+Contents : Initial Settings for Fixed Color Addition Or Screen Addition
+
+     D7-d6     Main Sw (M1/m0)
+     D5-d4     Sub Sw (S1/s0)
+     D3-d2     ---
+     D1   Cc Add Enable, Fixed Color Addition/subtraction Enable
+               Designate Whether 2 Kinds of the Data Should
+               Be Added/subtracted Each Other Or Not, Which Are
+               The Fixed Color Set by Register <2132h>, and
+               The Color Data Which is Set to Cgram.
+                    0: Addition/subtraction for Fixed Color
+                    1: Addition/subtraction for Sub Screen
+
+     D0   Direct Select (See Appendix-14)
+               The Vram Data (Color & Character Data) Become the
+               Color Data Directly. [Only When Mode-3,4 & 7]
+                    0: Disable
+                    1: Enable
+
+
+     M1(s1) M0(s0)  |  Normal Display Is:
+     --------------------------------------------------------------
+       0      0     |  All the Time
+       0      1     |  Inside Window Only
+       1      0     |  Outside Window Only
+       1      1     |  All the Time
+
+
+Address  : $2131
+Name     : Cgadsub
+Contents : Addition/subtraction & Subtraction Designation for Each Screen,
+        Obj & Background Color
+
+     D7   Color Data Addition/subtraction Select
+               Designate the Selection Either of the Addition
+               Or the Subtraction Mode.
+                    0: Addition Mode Select
+                    1: Subtraction Mode Select
+
+     D6   "1/2 of Color Data" Designation
+               When the Color Constant Addition/subtraction Or the
+               Screen Addition/subtraction is Performed, Designate
+               Whether the Rgb Result in the Addition/subtraction
+               Area Should Be "1/2" Or Not. However, in the Back
+               Color Constant Area on the Sub Screen, it Does Not
+               Become "1/2"
+                    0: Disable
+                    1: Enable
+     D5   Back
+     D4   Obj
+     D3   Bg4
+     D2   Bg3
+     D1   Bg2
+     D0   Bg1
+               Color Data Addition/subtraction Enable
+                    0: Disable
+                    1: Enable
+
+
+Address  : $2132
+Name     : Coldata
+Contents : Fixed Color Data for Fixed Color Addition/subtraction
+
+     D7   Blue
+     D6   Green
+     D5   Red
+               Bit for Selecting Desired Color
+
+     D4-d0     Color Brilliance Data
+               Set the Color Constant Data for Color Constant
+               Addition/subtraction
+
+     * R/g/b Brightness Should Be Set by the Data of Each 5-bit.
+
+          [Example] Red   : C0h, 3fh (B=00h, G=00h, R=1fh)
+                    Green : A0h, 5fh (B=00h, G=1fh, R=00h)
+                    Blue  : 60h, 9fh (B=1fh, G=00h, R=00h)
+                    White : Ffh
+                    Black : 00h
+
+
+Address  : $2133
+Name     : Setini
+Contents : Screen Initial Setting
+
+     D7   External Synchronization
+               It is Used for Super Impose and Etc. Normally,
+               "0" Should Be Written.
+
+     D6   Extbg Mode (Screen Expand)
+               Enable the Data Supplied From the External Lsi.
+               For the Sfx, Enable When the Screen with Priority
+               Is Used on Mode-7.
+
+     D5-d4     ---
+
+     D3   Horizontal Pseudo 512 Mode
+               512 Imaginary Resolution (Horizontal Can Be Made
+               By Shifting the Subscreen Half Dot to the Left.)
+                    0: Disable
+                    1: Enable
+
+     D2   Bg V-direction Display
+               Switch the Display Line of A Field to 224 Line Or
+               239 Line. (In Case of Interalace it Will Be
+               Doubled Dot.)
+                    0: 224 Line
+                    1: 239 Line
+
+     D1   Obj V-direction Display
+               In the Interlace Mode, Select Either of 1-dot Per
+               Line Or 1-dot Repeated Every 2-lines. If "1" is
+               Written, the Obj Seems Reduced Half Vertically in
+               Appearance.
+
+     D0   Scanning
+               Interlace/non-interlace Selection (It Relates to
+               <2105h>.
+                    0: Non Interlace
+                    1: Interlace
+
+
+Address  : $2134/$2135/$2136
+Name     : *Mpyl/*mpym/*mpyh
+Contents : Multiplication Result
+
+     D7-d0     Mpy (Low)                     2134h
+     D7-d0     Mpy (Mid)                     2135h
+     D7-d0     Mpy (High)                         2136h
+
+          This is A Multiplication Result (Complement of 2) Can Be Read
+       By Setting 16-bit to Register <211bh> and Setting 8 Bit to
+       Register <211ch>
+
+
+Address  : $2137
+Name     : *Slhv
+Contents : Software Latch for H/v Counter
+
+     D7-d0     Soft Latch for H/v Counter
+
+          This is A Register, Which Generate the Pulse for Latching the H/v
+       Counter Value.
+
+          The H/v Counter Value At the Point When Register <2137h> is Read
+       Can Be Latched. The Data Which Was Read is Meaningless Data.
+
+          The H/v Counter Value Latched Can Be Reffered by Registers
+       <213ch> & <213dh>.
+
+
+Address  : $2138
+Name     : Oamdataread (Name Differs From Snes Manual)
+Contents : Read Data From Oam
+
+     D7-d0     Oam Data (Low,high)
+
+          This is A Register, Which Can Read the Data At Any Address of
+       The Oam.
+
+         When the Address is Set to Register <2102h><2103h> and Register
+       <2138h> is Also Accessed the Data Can Be Read in the Order of
+       Low 8-bit/high 8-bit.
+       Afterward, the Address Will Be Increased Automatically, and the
+       Data of the Next Address Can Be Read.
+
+     Note:     the Data Can Be Read Only During H/v Blank Or Forced
+     ~~~~~     Blank Period.
+
+
+Address  : $2139/$213a
+Name     : Vmdatalread/vmdatahread (Names Differ From Snes Manual)
+Contents : Read Data From Vram
+
+     D7-d0     Vram Data (Low)                         2139h
+     D7-d0     Vram Data (High)                   213ah
+
+          This is A Register, Which Can Read the Data At Any Address of
+       The Vram.
+
+          The Initial Address Should Be Set by Registers <2116h> and
+       <2117h>. The Data Can Be Read by the Address Which Has Been Set
+       Initially.
+
+          When Reading the Data Continously, the First Data for the Address
+       Increment Should Be Read As A Dummy Data After the Address Has
+       Been Set.
+
+          Quantity to Be Increased Will Be Determined by "Sc Increment" of
+       Register <2115h> and the Setting Value of the "Full Graphic".
+
+     Note:     the Data Can Be Read Only During H/v Blank Or Forced
+     ~~~~~     Blank Period.
+
+
+Address  : $213b
+Name     : Cgdataread (Name Differs From Snes Manual)
+Contents : Read Data From Cg-ram
+
+     D7-d0     Cg Data (Low,high)
+
+          This is A Register, Which Can Read the Data At Any Address of
+       The Cg-ram.
+
+          The Initial Address Should Be Set by Register <2121h>. The Lower
+       8-bit is Read First, and the the Upper 7-bit Will Be Read by
+       Accessing this Register. The Current Address Will Be Increased
+       To the Next Address At the Same Time the Upper 7-bit is Read.
+
+     Note:     the Data Can Be Read Only During H/v Blank Or Forced
+     ~~~~~     Blank Period.
+
+
+Address  : $213c/$213d
+Name     : *Ophct/*opvct
+Contents : H/v Counter Data by External Or Software Latch
+
+     D7-d0     Output Data of H-counter [9-bit]        213ch
+     D7-d0     Output Data of V-counter [9-bit]        213dh
+
+          The H/v Counter is Latched by Reading Register <2137h>, and its
+       H/v Counter Value Can Be Read by this Register.
+
+          The H/v Counter is Also Latched by the External Latch, and its
+       Value Can Be Read by this Register.
+
+          If Register <213ch> Or <213dh> is Read After Register <213fh> Has
+       Been Read, the Lower 8-bit Data Will Be Read First, and Then the
+       Upper 1-bit Will Be Read by Reading the Register.
+
+
+Address  : $213e
+Name     : *Stat77
+Contents : Ppu Status Flag & Version Number
+
+     D7   Time Over  \
+     D6   Range Over /
+               Obj Display Status (On A Horizontal Line)
+               Range:    When Quantity of the Obj (Regardless of
+                    The Size) Becomes 33 Pcs Or More, "1"
+                    Will Be Set.
+               Time:     When Quantity of the Obj Which is Converted
+                    To "8 X 8-size" is 35 Pcs Or More, "1"
+                    Will Be Set.
+
+     D5   Master/slave Mode Select. Lsi Mode (Normally "0" is Set.)
+
+     D4   ---
+
+     D3-d0     5c77 Version Number
+
+     Note:     the Flag Will Be Reset At the End of the V-blank Period.
+     ~~~~~
+
+
+Address  : $213f
+Name     : *Stat78
+Contents : Ppu Status Flag & Version Number
+
+     D7   Field
+               This is A Status Flag, Which Indicated Whether 1st
+               Field is Scanned Or 2nd Field is Scanned in Inter-
+               Lace Mode. (The Definition is Different From the
+               Field of Ntsc.)
+                    0: 1st Field
+                    1: 2nd Field
+
+     D6   External Latch Flag
+               When the External Signal (Light Pen, Etc.) Is
+               Applied, it Enables to Latch the H/v Counter Value.
+
+     D5   ---
+
+     D4   Ntsc/pal Mode
+                    0: Ntsc
+                    1: Pal
+
+     D3-d0     5c78 Version Number
+
+     Note:     When this Register is Read, Registers <213ch><213dh> Will
+     ~~~~~     Be Initialized Individually in the Order of Low & High.
+
+
+Address  : $2140/$2141/$2142/$2143
+Name     : Apui00/apui01/apui02/apui03
+Contents : Communication Port with Apu
+
+     D7-d0     Apu I/o Port
+
+          This Port Provides More Registers for the Purpose of In/out,
+       Which Are 8 Registers in Total in the Apu. Therefore, the
+       Different Register Will Be Accessed, Whether Reading Or
+       Writing for the Same Address.
+
+          See "Apu Manual" for the Details of the Communication Method.
+
+
+Address  : $2180
+Name     : Wmdata
+Contents : Data to Consecutivley Read From and Write to Wram
+
+     D7-d0     Work Ram Data
+
+          Data to Consecutivley Read From and Write to Wram
+
+          Data is Read and Written At Address Set by Register <2181h>-<2183h>,
+       And Address Automatically Increases Each Time Data is Read Or Written.
+
+
+Address  : $2181/$2182/$2183
+Name     : Wmaddl/wmaddm/wmaddh
+Contents : Address to Consecutively Read and Write Wram
+
+     D7-d0     Wram Data (Low)                         2181h
+     D7-d0     Wram Data (Mid)                         2182h
+     D0   Wram Data (High)                   2183h
+
+          Address to Be Set Before Wram is Consecutivley Read Or Written.
+
+          A0 Trough A16 At Register <2181h>-<2183h> is Lower 17 Bit Address
+       To Show Address $7e0000-$7fffff in Memory.
+
+
+Address  : $4200
+Name     : Nmitimen
+Contents : Enable Flag for V-blank, Timer Interrupt & Joy Controller Read
+
+     D7   Nmi Enable
+               Enable Nmi At the Point When V-blank Begins
+               (When Power is Turned on Or the Reset Signal is
+               Applied, it Will Be "0".)
+                    0: Nmi Disabled
+                    1: Nmi Enabled
+
+     D6   ---
+
+     D5-d4     Timer Enable (V-en/h-en)
+
+     D3-d1     ---
+
+     D0   Joy-c Enable
+               0: Disable Automatic Reading of the Joy-controller.
+               1: Enable Automatic Reading of the Joy-controller.
+
+     V-en H-en  |  Function
+     --------------------------------------------------------
+        0    0  |  Disable Both H & V
+        0    1  |  Enable H Only, Irq Applied by H-count Timer Value Designated
+        1    0  |  Enable V Only, Irq Applied by V-count Timer Value Designated
+        1    1  |  Enable Both V & H, Irq Applied by Both H & V Count Timer Val
+                |  Designated.
+
+     * Reading the Data Can Be Started At the Beginning of V-blank
+       Period, But it Takes About for 3 Or 4 Scanning Period Until
+       Completion of Reading.
+
+
+Address  : $4201
+Name     : Wrio
+Contents : Programmable I/o Port (Out-port)
+
+     D7-d0     I/o Port
+
+          This is A Programmable I/o Port (Out-port). The Written Data
+       Will Be Output Directly From the Out-port.
+
+          When this is Used As A Inport. "1" Should Be Written to the
+       Particular Bit Which Will Be Used As in Port. The Input Can
+       Be Read by Register <4213h>.
+
+
+Address  : $4202/$4203
+Name     : Wrmpya/wrmpyb
+Contents : Multiplier & Multiplicand by Multiplication
+
+     D7-d0     Multiplicand-a                     4202h
+     D7-d0     Multiplier-b                       4203h
+
+          This is A Register, Which Can Set A Mulitplicand (A) and A
+       Multiplier (B) for Absolute Multiplication of
+       "A (8-bit) * B (8-bit)=c (16-bit)"
+
+          A Product (C) Can Be Read by Registers <4216h><4217h>
+
+          Set in the Order of (A) and (B). The Operation Will Start As
+       Soon As (B) Has Been Set, and it Will Be Completed Right After
+       8-machine Cycle Period.
+
+          Once the Data of the A-register is Set, it Will Not Be Destroyed
+       Until New Data is Set.
+
+
+Address  : $4204/$4205/$4206
+Name     : Wrdivl/wrdivh/wrdivb
+Contents : Divisor & Dividend Divide
+
+     D7-d0     Multiplier-c (Low)                 4204h
+     D7-d0     Multiplier-c (High)                4205h
+     D7-d0     Divisor-b                     4206h
+
+          This is A Register, Which Can Set A Dividend (C) and A Divisor (B)
+       For Absolute Divide of
+       "C (16-bit) / B (8-bit)=a (16-bit)"
+
+          The Divisor (A) Can Be Read by Registers <4214h><4215h>, and the
+       Remainder Can Also Be Read by Registers <4216h><4217h>.
+
+          Set in the Order of (C) and (B). The Operation Will Start As Soon
+       As (B) Has Been Set, and it Will Be Completed Right After 16-
+       Machine Cycle Period.
+
+          Once the Data of the A-register is Set, it Will Not Be Destroyed
+       Until New Data is Set.
+
+
+Address  : $4207/$4208
+Name     : Htimel/htimeh
+Contents : H-count Timer Settings
+
+     D7-d0     H Count Timer (H7-h0)                   4207h
+
+     D7-d1     ---
+     D0   H Count Timer (H8)                 4208h
+
+          This is A Register, Which Can Set the H-count Timer Value.
+
+          The Setting Value Should Be From 0 Through 339, Which is Counted
+       From the Far Left on the Screen.
+
+          Hwen the Coordinate Counter Becomes the Count Value Set, the Irq
+       Will Be Applied. And At the Same Time. "1" Will Be Written to
+       "Timer Irq" of Register <4211h>. (Read Reset)
+       Enable/disable of the Interrupt Will Be Determined by Setting
+       Register <4200h>
+
+     * this Continous Counter is Reset Every Scanning Line, Therefore
+       Once the Count Value is Set, it is Possible to Apply the Irq
+       Every Time the Scanning Line Comes to the Same Horizontal
+       Position on the Screen.
+
+
+Address  : $4209/$420ah
+Name     : Vtimel/vtimeh
+Contents : V-count Timer Settings
+
+     D7-d0     V Count Timer (V7-v0)                   4209h
+
+     D7-d1     ---
+     D0   V Count Timer (V8)                 420ah
+
+          This is A Register, Which Can Set the V-count Timer Value.
+
+          The Setting Value Should Be From 0 Through 261(262), Which is
+       Counted From the Far Top of the Screen. [The Line Number Described
+       Is Different From the Actual Line Number on the Screen.]
+
+          Hwen the Coordinate Counter Becomes the Count Value Set, the Irq
+       Will Be Applied. And At the Same Time. "1" Will Be Written to
+       "Timer Irq" of Register <4211h>. (Read Reset)
+       Enable/disable of the Interrupt Will Be Determined by Setting
+       Register <4200h>
+
+     * this is A Continous Counter Same As H-counter, and it Will Be
+       Reset Every Time 262(263) Line Are Scanned. Once the Count
+       Value is Set, it is Possible to Apply the Irq Every Time the
+       Scanning Line Comes to the Same Vertical Line on the Screen.
+
+
+Address  : $420b
+Name     : Mdmaen
+Contents : Channel Designation for General Purpose Dma & Trigger (Start)
+
+     D7-d0     General Purpose Ch7-ch0 Enable
+
+          The General Purpose Dma Consists of 8-channels in Total.
+
+          This Register is Used to Designate the Channel Out of 8-channels.
+
+          The Channel Which Should Be Used Can Be Designated by Writing "1"
+       To the Bit of this Channel. As Soon As "1" is Written to the
+       Bit (After A Few Cycles Passed), the General Purpose Dma Transfer
+       Will Be Started.
+
+          When the General Purpose Dma of the Designated Channel is
+          Completed, the Flag Will Be Cleared.
+
+     Note:     Because the Data Area (Register <4300>-) of Each Channel
+     ~~~~~     is Held in Common with the Data of Each H-dma Channel, the
+          Channel Designated by the H-dma Channel Designation
+          Register <420ch> Can Not Be Used.
+          (It is Prohibited to Write "1" to the Bit of the Channel)
+          Therefore, 8 Channels (Ch0-ch7) Should Be Assigned by the
+          H-dma and the General Purpose Dma)
+
+     Note:     If the H-blank Come During the Operation of the General
+     ~~~~~     Purpose Dma and the H-dma is Started, the General Purpose
+          Dma Will Be Discontinued in the Middle, and Re-started Right
+          After the H-dma is Complete.
+
+     Note:     If 2 Or More Channels Are Designated, the Dma Transfer Will
+     ~~~~~     Be Performed Continously According to the Priority Described
+          in Appendix-1.
+          And Also, the Cpu Stops Operation Until All the General
+          Purpose Dma Are Completed.
+
+
+Address  : $420c
+Name     : Hdmaen
+Contents : Channel Designation for H-dma
+
+     D7-d0     H-dma Ch7-dh0 Enable
+
+          The H-dma Consists of 8-channels in Total
+
+          This Register is Used to Designate the Channel Out of 8-channels
+
+          The Channel Which Should Be Used Can Be Designated by Writing
+       "1" to the Bit of this Channel. As Soon As H-blank Begins (After
+       A Few Cycles Passed), the H-dma Transfer Will Be Started.
+
+     Note:     Once this Flag is Set, it Will Not Be Destroyed (Cleared)
+     ~~~~~     Until New Data is Set. Therefore, the Initial Settings Are
+          Done Automatically Every Field, and the Same Transfer
+          Pattern Will Be Repeated.
+          And Also, the Flag is Set Out of V-blank Period, the Dma-
+          Transfer Will Be Performed Properly From Next Screen Frame.
+
+
+Address  : $420d
+Name     : Memsel
+Contents : Access Cycle Designation in Memory (2) Area
+
+     D7-d1     ---
+     D0   Access Cycle Designation in Memory (2) Area
+               0: 2.68mhz Access Cycle
+               1: 3.58mhz Access Cycle (Only When High Speed
+                               Memory is Used.)
+
+          Memory (2) Shows the Address (8000h-ffffh) of the Bank (80h-bfh)
+       And All the Address of the Bank (C0h-ffh).
+
+          When Power is Turned on Or the Reset Signal is Applied it Becomes
+       "0".
+
+          High Speed Memory Requiers 120ns Or Faster Eproms.
+
+
+Address  : $4210
+Name     : *Rdnmi
+Contents : Nmi Flag by V-blank & Version Number
+
+     D7   Nmi Flag by V-blank
+               When "1" is Written to "Nmi Enable" of Register
+               <4200h>, this Flag Will Show Nmi Status.
+                    0: Nmi Status is "Disable"
+                    1: Nmi Status is "Enable"
+
+     D6-d4     ---
+
+     D3-d0     5a22 Version Number
+
+     * "1" is Set to this Flag At Beginning of V-blank, and "0" is
+       Set At End of V-blank. Also, it Can Be Set by Reading this
+       Register.
+
+     Note:     it is Necessary to Reset by Reading this Flag During
+     ~~~~~     Nmi Processing. (See Appendix-3)
+
+
+Address  : $4211
+Name     : *Timeup
+Contents : Irq Flag by H/v Count Timer
+
+     D7   Irq Flag by H/v Count Timer
+               [In Case the Time Enable is Set by "Timer Enable"
+               Of Register <4200h>] As Soon As H/v Counter Timer
+               Becomes the Count Value Set, Irq Will Be Applied
+               And "1" Will Be Set to this Flag.
+               This Flag is "Read-reset".
+
+     D6-d0     ---
+
+     * Even If V-en="0" and H-en="0" Are Set by "Timer Enable" of
+       Register <4200h>, this Flag Will Be Reset.
+          0: Either H/v Counter is in Active Or Disable.
+          1: H/v Count Timer is Time Up.
+
+
+Address  : $4212
+Name     : Hvbjoy
+Contents : H/v Blank Flag & Joy Controller Enable Flag
+
+     D7   V-blank Period Flag
+               0: Out of V-blank Period
+               1: in V-blank Period
+
+     D6   H-blank Period Flag
+               0: Out of H-blank Period
+               1: in H-blank Period
+
+     D5-d1     ---
+
+     D0   Joy Controller Enable Flag
+               This Flag Shows the Timing to Read the Data of the
+               Joy Controller. (However, it is Limited to the Case
+               Which the "Joy-c Enable" of Register <4200h> is Set
+               To "1".
+
+
+Address  : $4213
+Name     : *Rdio
+Contents : Programmable I/o Port (In-port)
+
+     D7-d0     I/o Port
+
+          This is A Programmable I/o Port (In Port). The Data Which is Set
+       To the In-port Should Be Read Directly.
+
+          The Bit Which "1" is Written by Register <4201h> is Used As the
+       In Port.
+
+
+Address  : $4114/$4115
+Name     : *Rddivl/*rddivh
+Contents : Quotient of Divide Result
+
+     D7-d0     Quotent-a (Low)                         4114h
+     D7-d0     Quotent-a (High)                   4115h
+
+          This is A Quotent (A), Which is A Result for Absolute Divide of
+       "C (16-bit) / B (8-bit) = A (16-bit)".
+
+          Dividend (C) and Divisor (B) Are Set by Registers <4204h>-<4206h>.
+
+
+Address  : $4216/$4217
+Name     : *Rdmpyl/*rdmpyh
+Contents : Product of Multiplication Result Or Remainder of Divide Result
+
+     D7-d0     Product-c [Mul] / Remainder [Div] (Low)      4216h
+     D7-d0     Product-c [Mul] / Remainder [Div] (High)     4217h
+
+     (1) in Case of Multiplication
+          This is A Product (C) Which is A Result for Absolute
+       Multiplication of "A (8-bit) * B (8-bit) = C (16-bit)".
+
+          A Multiplicand (A) and A Multiplier (B) Are Set by Registers
+       <4202h> & <4203h>.
+
+     (2) in Case of Divide
+          This is the Remainder, Which is A Result for the Absolute
+       Divide of "C (16-bit) / B (8-bit) = A (16-bit)".
+
+          A Dividend (C) and Divisor (B) Are Set by the Registers
+       <4204h><4205h> & <4206h>.
+
+
+Address  : $4218/$4219/$421a/$421b/$421c/$421d/$421e/$421f
+Name     : Joy1l/joy1h/joy2l/joy2h/joy3l/joy3h/joy4l/joy4h
+Contents : Data for Joy Controller I, Ii, Iii & Iv
+
+     D7   X Button                      Low
+     D6   Y Button
+     D5   Tl Button
+     D4   Tr Button
+     D3-d0     ----
+
+     D7   A Button                      High
+     D6   B Button
+     D5   Select Button
+     D4   Start Button
+     D3   Up
+     D2   Down
+     D1   Left
+     D0   Right
+
+          Registers <4016h><4017h> Can Be Used the Same As the Family
+       Computer.
+
+     4016h-rd
+          D0 : Data for Controller I
+          D1 : Data for Controller Iii
+     4016h-wr
+          Out0,out1,out2
+     4017h-rd
+          D0 : Data for Controller Ii
+          D1 : Data for Controller Iv
+
+     Note:     Whether the Standard Joy Controllers Are Connected to the
+     ~~~~~     Sfx Or Not Can Be Reffered by Reading 17th Bit of <4016h>
+          and <4017h> (See Page 22).
+               0: Connected
+               1: Not Connected
+
+
+Address  : $43x0 (X: Channel Number 0-7)
+Name     : Dmapx
+Contents : Parameter for Dma Transfer
+
+     D7   Transfer Origination Designation (See Appendix-1)
+               Transfer Direction  A-bus -> B-bus
+                                   B-bus -> A-bus Designation
+                    0: A-bus -> B-bus (Cpu Memory -> Ppu)
+                    1: B-bus -> A-bus (Ppu -> Cpu Memory)
+
+     D6   Type Designation (H-dma Only)
+               Addressing Mode Designation When Accessing the
+               Data (See Appendix-2).
+                    0: Absolute Addressing
+                    1: Indirect Addressing
+
+     D5   ---
+
+     D4-d3     Fixed Address for A-bus & Automatic Inc./dec. Select.
+               D3   0: Automatic Address Increment/decrement
+                    1: Fixed Address <To Be Used When Clearing
+                       Vram Etc.>
+               D4   0: Automatic Increment
+                    1: Automatic Decrement (In Case "0" is
+                       Written to D3)
+
+     D2-d0     Dma Transfer Word Select
+               General Purpose Dma: B-address Change Method
+
+                    D2 D1 D0  | Address to Be Written
+                    ---------------------------------
+                     0  0  0  | 1-address
+                     0  0  1  | 2-address (Vram Etc.)   L,h
+                     0  1  0  | 1-address
+                     0  1  1  | 2-address (Write Twice) L,l,h,h
+                     1  0  0  | 4-address               L,h,l,h
+
+               H-dma: the Number of Byte to Be Transfered Per Line
+               And Write Method Designation
+
+                    D2 D1 D0  | Address to Be Written
+                    ---------------------------------
+                     0  0  0  | 1-address                     (1)
+                     0  0  1  | 2-address (Vram Etc.)  L,h    (2)
+                     0  1  0  | Write Twice            L,l    (1)
+                     0  1  1  | 2-address/write Twice  L,l,h,h(2)
+                     1  0  0  | 4-address              L,h,l,h(4)
+
+
+Address  : $43x1 (X: Channel Number 0-7)
+Name     : Bbadx
+Contents : B-bus Address for Dma
+
+     D7-d0     B-address
+
+          This is A Register, Which Can Set the Address of B-bus.
+
+          Whether this is the Address of the "Transfer Destination" Or
+       The Address of the "Transfer Origination" Can Be Determined by
+       D7 (Transfer Origination) of Register <4300h>.
+
+     * When the H-dma is Performed, it Will Be Address of "Transfer
+       Destination".
+
+
+Address  : $43x2/$43x3/$43x4 (X: Channel Number 0-7)
+Name     : A1txl/a1txh/a1bx
+Contents : Table Address of A-bus for Dma <A1 Table Address>
+
+     D7-d0     A1 Table Address (Low)                  43x2h
+     D7-d0     A1 Table Address (High)                 43x3h
+     D7-d0     A1 Table Bank                      43x4h
+
+          This is A Register, Which Can Set the Address of A-bus
+
+          Whether this is the Address of the "Transfer Destination" Or
+       The Address of the "Transfer Origination" Can Be Determined by
+       D7 (Transfer Origination) of Register <4300h>.
+       "0" Should Be Written to D7 Except A Special Case.
+
+          In the H-dma Mode, the Address of the Transfer Origination is
+       Designated by this Address, the Data (Appendix-2) Must Be
+       Set by the Absolute Addressing Mode Or the Indirect Addressing
+       Mode.
+
+          This Address Becomes the Basic Address on the A-bus During Dma
+       Transfer Period, and the Address Will Be Increased Or Decreased
+       Based on this Address. (When the General Purpose Dma is Performed
+       It Will Be Decreased.)
+
+
+Address  : $43x5/$43x6/$43x7 (X: Channel Number 0-7)
+Name     : Dasxl/dasxh/dasbx
+Contents : Data Address Store by H-dma & Number of Byte to Be Transfered
+        Settings by General Purpose Dma
+
+     D7-d0     Data Address (Low)             H-dma    43x5h
+          Number of Bytes to Be Transfered (Low)  Gp-dma
+
+     D7-d0     Data Address (High)            H-dma    43x6h
+          Number of Bytes to Be Transfered (High) Gp-dma
+
+     D7-d0     Data Bank                     43x7h
+
+          In Case of H-dma
+          this is A Register Which the Indirect Address Will Be
+          Stored Automatically in the Indirect Addressing Mode.
+          The Indirect Address Means the Data Address Described
+          on Appendix-2. It is Not Necessary to Read Or Write
+          Directly by the Cpu Except in Special Cases.
+
+          In Case of General Purpose Dma
+          this is the Register, Which Can Set the Number of Byte
+          to Transfer Or to Be Transfered. However, the Number of
+          Byte "0000h" Means "10000h".
+
+
+Address  : $43x8/$43x9 (X: Channel Number 0-7)
+Name     : A2axl/a2axh
+Contents : Table Address of A-bus by Dma < A2 Table Address
+
+     D7-d0     A2 Table Address (Low)                  43x8h
+     D7-d0     A2 Table Address (High)                 43x9h
+
+          These Are the Addresses, Which Are Used to Access the Cpu & Ram,
+       And it Will Be Increased Automatically. (See Appendix-2)
+
+          The Data of These Registers Are Used As the Basic Address Which
+       Is the Addresss Set by the "A1 Table Address". Afterwards,
+       Because it Will Be Increased Or Decreased Automatically, it is
+       Necessary to Set the Address Into this Register by the Cpu
+       Directly.
+
+     Following Apply to H-dma Only:
+          However, If the Data Which is Transfered Need to Be Changed
+          by Force, it Can Be Done by Setting the Cpu Memory Address
+          to this Register. And Also, the Address of the Cpu Which is
+          Accessed Currently Will Be Changed by Reading this Register.
+
+
+Address  : $43xa (X: Channel Number 0-7)
+Name     : Ntrlx
+Contents : the Number of Lines to Be Transfered by H-dma›0;31;40m
+
+     D7   Continue
+     D6-d0     Number of Lines to Be Transfered
+
+          This is A Register Which Shows Number of Lines for H-dma Transfer
+       (See Appendix-2)
+
+          The Number of Lines Written to the Cpu Memory Will Be the Basic
+       Number of Line, it is Not Necessary to Set the Address Into
+          This Register Directly.
+
+

+ 850 - 0
files/docs/snes/snestech.txt

@@ -0,0 +1,850 @@
+
+ SNES hardware notes
+ by Charles MacDonald
+ WWW: http://cgfm2.emuviews.com
+
+ Unpublished work Copyright 2003  Charles MacDonald
+
+ This document is in a very preliminary state and is subject to change.
+ Most everything within has been tested and verified on a SNES but
+ please be aware that my testing methods or interpretations of results
+ could be flawed. I can't guarantee that everything is 100% accurate.
+
+ Last updated 09/17/03
+
+ [09/17/03]
+ - Added the cartridge information section.
+ - Added some details on the screen layout.
+
+ [08/27/03]
+ - Fixed some typos
+ - Added CGRAM information
+ - Added notes about valid times to access OAM
+
+ [08/25/03]
+ - Added some sprite information
+
+ [08/22/03]
+ - Added mouse information
+ - Added multitap information
+ - Changed joypad section
+
+ [08/20/03]
+ - Initial release
+
+ Table of contents
+
+ 1. Various notes
+ 2. CGRAM
+ 3. Sprites
+ 3. Hardware version registers
+ 4. I/O hardware
+ 5. Register reference
+ 6. Cartridge information
+ 7. Assistance needed
+ 8. Credits and acknowledgements
+ 9. Disclaimer
+
+ ----------------------------------------------------------------------------
+ Various notes
+ ----------------------------------------------------------------------------
+
+ V-Blank occurance flag
+
+ - Bit 7 of $4212 is set at line $00E1 and cleared at line $0000 in 224-line
+   mode.
+
+ - Bit 7 of $4212 is set at line $00F0 and cleared at line $0000 in 239-line
+   mode.
+
+ Joypad automatic scanning flag
+
+ - Bit 0 of $4212 is set at line $00E1 and cleared at line $00E4 in 224-line
+   mode.
+
+ - Bit 0 of $4212 is set at line $00F0 and cleared at line $00F3 in 239-line
+   mode.
+
+ Non-maskable interrupts
+
+ According to the 65816 manual, the NMI signal is an edge-sensitive input,
+ so that only a high to low transition on the NMI pin will cause an interrupt
+ to occur. Leaving it high, low, or having a low to high transition has no
+ effect. I'm going to assume the PPU normally holds NMI high and brings it
+ low to trigger an interrupt.
+
+ The PPU will pull NMI low at line $00E8 in 224-line mode or line $00F7 in
+ 239-line mode. It will remain low until either $4210 is read, or a new
+ frame starts, at which point the PPU will bring NMI high again.
+
+ The inverted state of the NMI signal from the PPU can be read through bit 7
+ of $4210, where 0= no NMI has been requested, 1= an NMI is pending. After
+ reading this register, the PPU resets the NMI signal by pulling it high.
+
+ Bit 7 of $4200 doesn't affect how the PPU manages NMIs at all, it is just
+ a gate between the NMI output of the PPU and the NMI input of the CPU.
+ When set, NMIs can be generated. When cleared, the CPU ignores the state of
+ the NMI pin.
+
+ Here are some details of specific situations:
+
+ When there is a pending NMI, toggling bit 7 of $4200 does not create any
+ additional interrupts.
+
+ Bit 7 of $4210 will be set in the NMI routine when it executes.
+
+ After the NMI routine finishes, bit 7 will remain set (assuming $4210 wasn't
+ read) until the start of the next frame. This will not cause more NMIs to
+ occur as they are only triggered by high-to-low transitions, having the NMI
+ pin remain low does not do anything.
+
+ Bit 7 of $4210 reflects the NMI status independantly of bit 7 of $4200.
+
+ Interlaced display
+
+ When bit 0 of $2133 is set, the screen becomes interlaced regardless of
+ the BG mode setting. When the screen is interlaced, the following applies:
+
+ - For BG modes 0,1,2,3,4,7 each line of the background is repeated in the
+   even and odd frames for single-density interlace. (224 or 239 lines shown)
+
+ - For BG modes 5,6 each line of the background is unique for the even and
+   odd frames for double-density interlace. (448 or 478 lines shown)
+
+ Screen layout
+
+ For an NTSC non-interlaced display, each frame consists of 262 lines.
+ Depending on the screen height, these lines are divided into the following
+ groups:
+
+ Section            224-line mode   239-line mode
+
+ Active display         224          239
+ Bottom blanking         12           15
+ Vertical sync            3            3
+ Top blanking            23            5
+ Total                  262          262
+
+ Active display is the portion of the screen where graphics are displayed.
+
+ Bottom blanking is the bottom border after the active display shown at the
+ very bottom of the display. Lines are filled with black.
+
+ Vertical sync is the period between the bottom and top borders which is
+ off-screen. Lines are filled with a darker black color than in the blanking
+ areas.
+
+ Top blanking is the border after the vertical sync period shown at the very
+ top of the display. Lines are filled with black.
+
+ ----------------------------------------------------------------------------
+ CGRAM
+ ----------------------------------------------------------------------------
+
+ Overview
+
+ The PPU has 512 bytes of on-chip RAM called CGRAM which holds palette data.
+ CGRAM is divided into 256 2-byte entries that define a single color.
+
+ Each entry has the following format:
+
+ MSB          LSB
+ -bbbbbgggggrrrrr
+
+ b = Blue component (0=black, 31=bright)
+ g = Green component (0=black, 31=bright)
+ r = Red component (0=black, 31=bright)
+ - = Unused bit.
+
+ The background can use the first 128 colors in BG modes 0,1,2,5,6, and all
+ 256 colors in BG modes 3,4,7 when not in direct color mode. Sprites always
+ use the latter 128 colors. Specific details about palette use and selection
+ for each mode will be described later.
+
+ The PPU provides several registers for using CGRAM:
+
+ $2121 - CGRAM address
+ $2122 - CGRAM data port (write)
+ $213B - CGRAM data port (read)
+
+ CGRAM access
+
+ The PPU has a 9-bit address register which gives a byte offset into CGRAM.
+ Writing to $2121 loads the CPU data into bits 8-1 of the address register
+ and clears bit 0, forcing an even address to be set.
+
+ Each time $213B is read, the byte at the current offset pointed to by the
+ address register is returned to the CPU, and the address register is
+ incremented by one.
+
+ Each time $2122 is written to the address register is incremented by one.
+ If the address register is even during a write, the CPU data is stored in
+ a latch. If the address register is odd, the latched data becomes the LSB
+ and the new data written becomes the MSB of a 16-bit word. This word is
+ written to the current address, with bit 0 of the address register ignored.
+
+ The address register will wrap from $01FF to $0000 due to reading $213B or
+ writing to $2122. You can mix reads and writes freely.
+
+ Valid access times
+
+ When the screen is forcibly blanked or in the V-Blank period, CGRAM can be
+ read and written. I haven't tested access during H-Blank yet.
+
+ Here are my observations about CGRAM access during the active display
+ period:
+
+ - Writing to CGRAM always results in the last word written to the data port
+   being written to address 0,1 regardless of the address register setting.
+   You could think of address bits 8-1 as always being fixed to zero during
+   this time.
+
+ - Reading from CGRAM returns a random mix of bytes from CGRAM and data that
+   wasn't stored in CGRAM. The address register has no effect on where the
+   data comes from.
+
+ - When the screen is turned on, the previously set value in the address
+   register not changed. Following reads or writes with the screen off
+   affect the address originally selected.
+
+ CGRAM access examples
+
+ Here are some examples of unexpected behavior. Assume CGRAM contains the
+ bytes $AA, $BB, $CC, $DD at address $0000 for each test:
+
+ - Set address to $0000
+ - Write $45
+
+ CGRAM is not updated, and the LSB latch contains $45
+
+ - Set address to $0000
+ - Read $2138
+ - Write #$45
+
+ The bytes $CC, $45 are written to address $0000. $CC was the last value
+ in the LSB latch, and a single byte write triggers a write to CGRAM as the
+ previous read made the address register odd.
+
+ ----------------------------------------------------------------------------
+ Sprites
+ ----------------------------------------------------------------------------
+
+ The PPU can manage up to 128 sprites. Sprites use 16-color 8x8 tiles, the
+ same as used by the backgrounds. The sprite size can range from 1x1 tiles
+ up to 8x8 tiles, with several variations in between.
+
+ The attributes for each sprite are stored in 544 bytes of on-chip RAM called
+ OAM or "Object Attribute Memory". The OAM can be thought of having two
+ sections, a 512-byte table that has 128 x 4-byte entries, and a 32-byte
+ table used as 128 x 2-bit entries.
+
+ The PPU provides several registers for sprite control:
+
+ $2101 - OAM control
+ $2102 - OAM address LSB
+ $2103 - OAM address MSB
+ $2104 - OAM data port (write)
+ $2138 - OAM data port (read)
+
+ The OAM control register defines various aspects about the sprites:
+
+ D7 : Sprite size, bit 2
+ D6 : Sprite size, bit 1
+ D5 : Sprite size, bit 0
+ D4 : Sprite name offset, bit 1
+ D3 : Sprite name offset, bit 0
+ D2 : Sprite pattern table base, bit 2
+ D1 : Sprite pattern table base, bit 1
+ D0 : Sprite pattern table base, bit 0
+
+ The sprite pattern table is where the tile data for sprites is fetched from.
+ The table is 16K in size and can be positioned on 16K boundaries. Bits 2-0
+ of this register correspond to bits 16-14 of the VRAM address.
+
+ As there is only 64K of VRAM, bit 2 has no effect. Pattern data read from
+ $10000-$1FFFF is instead read from $00000-$0FFFF due to mirroring.
+
+ When a sprite has bit 8 of it's name field set so that it reads patterns
+ out of the upper 8K of the 16K table (tiles 256-511), bits 4, 3 of this
+ register are added to bits 14 and 13 of the VRAM address.
+
+ If the resulting address is bigger than $10000 then data is read from
+ $00000 onwards due to mirroring. The same holds true if the address is
+ bigger than $20000, due to wrapping.
+
+ The sprite sizes are as follows:
+
+ D7 D6 D5       Small           Large
+
+  0  0  0       8x8             16x16
+  0  0  1       8x8             32x32 
+  0  1  0       8x8             64x64
+  0  1  1       16x16           32x32
+  1  0  0       16x16           64x64
+  1  0  1       32x32           64x64
+  1  1  0       16x32           32x64
+  1  1  1       16x32           32x32
+
+ The last two settings are undocumented but appear to function normally.
+
+ Overview
+
+ The CPU interface to the OAM appears as a 1024-byte array. Here's a memory
+ map:
+
+ $0000-$01FF : 512 bytes, used as 128 x 4-byte entries
+ $0200-$03FF : 32 bytes, mirrored every 32 bytes (so mirrored 16 times)
+
+ Reading and writing from the mirrored areas are valid.
+
+ OAM access
+
+ The PPU has a 10-bit address register which gives a byte offset into OAM.
+ Writing to $2102 will load the CPU data into bits 8-1 of the address
+ register. Writing to $2103 will load bit 0 of the CPU data into bit 9 of
+ the address register. Writing to $2102 or $2103 will clear bit 0 of the
+ address register so an even address is always selected. You can write to
+ $2102 and $2103 in any order, or write to just one or the other to update
+ part or all of the address.
+
+ Each time $2138 is read, the byte at the current offset pointed to by the
+ address register is returned to the CPU, and the address register is
+ incremented by one.
+
+ Each time $2104 is written to the address register is incremented by one.
+ If the address register is even during a write, the CPU data is stored in
+ a latch. If the address register is odd, the latched data becomes the LSB
+ and the new data written becomes the MSB of a 16-bit word. This word is
+ written to the current address, with bit 0 of the address register ignored.
+
+ This only affects writing to offsets $0000-$01FF. The 32 byte table at
+ $0200-$03FF will be updated for a write to even or odd addresses. Writes
+ to even addresses still update the LSB latch, however.
+
+ The address register will wrap from $03FF to $0000 due to reading $2138 or
+ writing to $2104. You can mix reads and writes freely.
+
+ Valid access times
+
+ When the screen is forcibly blanked or in the V-Blank period, OAM can be
+ read and written. I haven't tested access during H-Blank yet.
+
+ It would seem that the address register is used for some internal operation
+ during the active display period, which involves incrementing it. Here are
+ my observations:
+
+ - Writing to OAM during this time results in the data being written to
+   consecutively larger addresses, starting at a random offset and with
+   a random amount of skipped bytes between the data. The address register
+   has no effect on where the data goes.
+
+ - Reading from OAM returns data from consecutively larger addresses,
+   starting at a random offset and with a random amount of skipped bytes
+   between the data. The address register has no effect on where the data
+   goes.
+
+ - Setting the address register to a known value and waiting a few scanlines
+   with the screen turned on results in data being read or written to a
+   larger address than the one originally set.
+
+ - Writing to the address register on the same scanline where a sprite is
+   being displayed has no effect on the sprite. I would assume during the
+   active display period, the address register can't be updated by the CPU
+   as it is being used by the PPU exclusively.
+
+ OAM access examples
+
+ Here are some examples of unexpected behavior. Assume OAM contains the
+ bytes $AA, $BB, $CC, $DD at address $0000 for each test:
+
+ - Set address to $0000
+ - Write $45
+
+ OAM is not updated, and the LSB latch contains $45
+
+ - Set address to $0000
+ - Read $2138
+ - Write #$45
+
+ The bytes $CC, $45 are written to address $0000. $CC was the last value
+ in the LSB latch, and a single byte write triggers a write to OAM as the
+ previous read made the address register odd.
+
+ - Set address to $0000
+ - Write #$12
+ - Write #$00 to $2103
+ - Write #$34
+
+ OAM is not updated. The second write only loads the LSB latch as the
+ write to $2103 cleared bit 0 of the address register.
+
+ ----------------------------------------------------------------------------
+ Hardware version registers
+ ----------------------------------------------------------------------------
+
+ Here are the version register return values and chip markings for my
+ original model NTSC SNES:
+
+ Register       Value           Chip
+
+ $4210          $01             Nintendo S-CPU  5A22-01
+ $213E          $01             Nintendo S-PPU1 5C77-01
+ $213F          $01             Nintendo S-PPU2 5C78-01
+
+ ----------------------------------------------------------------------------
+ I/O hardware
+ ----------------------------------------------------------------------------
+
+ The SNES has two 7-pin joypad ports. Here's a diagram of the faceplate of
+ the SNES to show the pin configuration:
+
+                 1P port                2P port
+ (Power light)   ( o o o | o o o o ]    [ o o o o | o o o )
+                   7 6 5   4 3 2 1        1 2 3 4   5 6 7
+
+ Pin #  Description     S-CPU pin (1P)    S-CPU pin (2P)
+
+ Pin 1  +5V             n/a               n/a
+ Pin 2  Output strobe   35                36
+ Pin 3  Output          37                37 (common between both ports)
+ Pin 4  Serial input 1  32                28
+ Pin 5  Serial input 2  33                27
+ Pin 6  Bidirectional   25                26
+ Pin 7  Ground          n/a               n/a
+
+ Each pin is accessible through the various hardware registers as follows:
+
+ 1P port
+
+ - Read $4016 to pulse pin 2.
+ - Writing to bit 0 of $4016 controls pin 3.
+ - Reading bit 0 of $4016 returns data from pin 4.
+ - Reading bit 1 of $4016 returns data from pin 5.
+ - Pin 6 is connected to bit 6 of $4201 (WRIO) and $4213 (RDIO).
+
+ 2P port
+
+ - Read $4017 to pulse pin 2.
+ - Writing to bit 0 of $4016 controls pin 3.
+ - Reading bit 0 of $4017 returns data from pin 4.
+ - Reading bit 1 of $4017 returns data from pin 5.
+ - Pin 6 is connected to bit 7 of $4201 (WRIO) and $4213 (RDIO).
+
+ 2P pin 6 is also connected to S-PPU2 pin 29. This is most likely the
+ external input signal that can be used to latch the H/V counter. A lightgun
+ such as the Super Scope or Konami Justifier would use pulse pin 6 of the 2P
+ port to make the PPU2 latch the H/V counter when it detects the raster beam.
+
+ The second serial input from pin 5 and bidirectional pin 6 are unused by
+ the joypad and mouse. The Hudson Super Multitap may be the only peripheral
+ to use them, see the multitap section for more details.
+
+ The standard way most peripherals work is to write 1 then 0 to bit 0 of
+ $4016 to reset the devices in the 1P and 2P ports. You can then read bit 0
+ of $4016 and $4017 multiple times to return data serially, starting with
+ the MSB down to the LSB.
+
+ I/O port
+
+ The SNES is described as having an 8-bit bidirectional I/O port. I don't
+ know if this physically corresponds to the expansion port on the bottom of
+ the control deck, or if the CPU just has an I/O port built in and some or
+ all of the port pins are used.
+
+ Writing to $4201 (WRIO) sets the data to be output through the I/O port.
+ Any bit that is also set to 1 will allow the corresponding pin to act
+ as an input, and data from that pin can be read through $4213 (RDIO).
+
+ The only uses I know of for the I/O port are as follows:
+
+ - Any value written to $4201 can be read back through $4213.
+
+ - As bit 7 of $4201 controls pin 6 of the 2P port, which is also shared with
+   the external signal input of the PPU to latch the H/V counter, writing 1
+   then 0 to bit 7 of $4201 will latch the H/V counter.
+
+   While bit 7 is set to 0, the latch will always hold the same value and
+   reading $2137 will not change the latched value. If you want to poll
+   the H/V counter using $2137, set bit 7 back to 1 for it to work properly.
+
+ - Pin 6 of the 1P or 2P port is used as an output to control the Hudson
+   Super Multitap. See the multitap section for more details.
+
+ ----------------------------------------------------------------------------
+ Automatic reading
+ ----------------------------------------------------------------------------
+
+ The SNES has a feature to automatically read the four serial input pins
+ and store them into a set of registers during V-Blank. This can be done
+ without the CPU having to manually write and read $4016 / $4017, saving
+ time for other tasks.
+
+ When bit 0 of $4200 is set, at the start of V-Blank (depending on the screen
+ height) the SNES will automatically do the following steps:
+
+ - Write 1 then 0 to bit 0 of $4016.
+
+ - Read $4016 and $4017 sixteen times, storing the return values from bits
+   0 and 1 into eight registers like so:
+
+ - 16 bits from bit 0 of $4016 are stored in $4218 (LSB) and $4219 (MSB)
+ - 16 bits from bit 1 of $4016 are stored in $421C (LSB) and $421D (MSB)
+ - 16 bits from bit 0 of $4017 are stored in $421A (LSB) and $421B (MSB)
+ - 16 bits from bit 1 of $4017 are stored in $421E (LSB) and $421F (MSB)
+
+ This process takes three scanlines to complete. Bit 0 of $4212 shows the
+ scanning status, where 1= the SNES is still reading data, 0= the SNES has
+ finished or automatic scanning was not enabled.
+
+ The use I've seen in games and demos is to wait for this bit to be set, and
+ then cleared in the NMI handler.
+
+ ----------------------------------------------------------------------------
+ Hudson Super Multitap
+ ----------------------------------------------------------------------------
+
+ The multitap plugs into the 1P or 2P port. It has four connectors to plug
+ additional joypads into, and has a switch for selecting a multiplayer or
+ compatability mode.
+
+ In compatability mode (switch = 2P) the joypad plugged in to connector #1
+ works like a standard pad. All remaining connectors are ignored, pin 6
+ is ignored in terms of selecting which set of joypad data to return, and
+ no extra data is returned in the second serial input.
+
+ In multiplayer mode (switch = 3P-5P) the first serial input returns data
+ from the joypad in connector #1 or #3, and the second serial input returns
+ data from the joypad in connector #2 or #4. Pin 6 of the 1P or 2P port
+ is used to select connectors #1 and #3 when set to 1, or #2 and #4 when
+ set to 0.
+
+ ----------------------------------------------------------------------------
+ SNES joypad
+ ----------------------------------------------------------------------------
+
+ The SNES joypad uses two 4021 ICs, which are 8-stage static shift registers.
+ They are cascaded together to form a 16-bit shift register that stores the
+ state of the directional pad and buttons, allowing the SNES to read out
+ the state of the joypad serially.
+
+ The button states will be loaded into the shift register when bit 0 of
+ $4016 is set to 1 and then 0. This happens to both control pads as they
+ share a common pin. Each time $4016 or $4017 is read, the shift register
+ for the 1P or 2P pad advances by one, outputting a bit which can be read
+ in bit 0 of $4016 or $4017 respectively.
+
+ The tail end of the shift register is filled with a one on each shift. After
+ the sixteenth time $4016 or $4017 has been read, all consecutive reads will
+ return one due to the shift register being completely filled with ones.
+ This will go on forever until the shift register is loaded again by writing
+ 1 then 0 to $4016.
+
+ If at any time $4016 is left at 1, reading either joypad will always return
+ the state of the first input, which is the 'B' button. This won't stop until
+ $4016 is set to zero again.
+
+ Here is the order of button states read out through $4016 or $4017:
+
+ Read  1 - Button B             Read  9 - Button A
+ Read  2 - Button Y             Read 10 - Button X
+ Read  3 - Button Select        Read 11 - Button L
+ Read  4 - Button Start         Read 12 - Button R
+ Read  5 - Up                   Read 13 - '0'
+ Read  6 - Down                 Read 14 - '0'
+ Read  7 - Left                 Read 15 - '0'
+ Read  8 - Right                Read 16 - '0'
+
+ All reads after read 16 will return 1.
+
+ All buttons are 1= pressed, 0= released.
+
+ If no joypad is plugged in, then zero is always read from $4016 or $4017.
+ A game can check if a joypad is connected by seeing if any reads beyond
+ the 16th one return '1', otherwise there is no joypad.
+
+ As far as I can tell, the joypad does not return any data through pin 5
+ (which always returns zero) and any setting of pin 6 will not affect the
+ joypad operation.
+
+ ----------------------------------------------------------------------------
+ SNES mouse
+ ----------------------------------------------------------------------------
+
+ The SNES mouse works in a similar fashion to the joypad. It has a custom
+ 18-pin chip called the "SFM1" which returns data about the mouse status
+ serially to the SNES.
+
+ Writing 1, then 0 to bit 0 of $4016 will reset the SFM1 and subsequent reads
+ from $4016 or $4017 (depending on which port the mouse is plugged into) will
+ return the mouse state data. Leaving bit 0 of $4016 set to 1 will result
+ in zero always being read back.
+
+ The mouse data is as follows:
+
+ Read  1 - '0'                  Read 17 - Y sign
+ Read  2 - '0'                  Read 18 - Y movement bit 6 (?)
+ Read  3 - '0'                  Read 19 - Y movement bit 5
+ Read  4 - '0'                  Read 20 - Y movement bit 4
+ Read  5 - '0'                  Read 21 - Y movement bit 3
+ Read  6 - '0'                  Read 22 - Y movement bit 2
+ Read  7 - '0'                  Read 23 - Y movement bit 1
+ Read  8 - '0'                  Read 24 - Y movement bit 0
+ Read  9 - Right button         Read 25 - X sign
+ Read 10 - Left button          Read 26 - X movement bit 6 (?)
+ Read 11 - '0'                  Read 27 - X movement bit 5
+ Read 12 - '0'                  Read 28 - X movement bit 4
+ Read 13 - '0'                  Read 29 - X movement bit 3
+ Read 14 - '0'                  Read 30 - X movement bit 2
+ Read 15 - '0'                  Read 31 - X movement bit 1
+ Read 16 - '1'                  Read 32 - X movement bit 0
+
+ All reads after read 32 will return 1.
+
+ The left/right buttons are 1= pressed, 0= released.
+
+ The Y and X sign are 1= up/left movement, 0= down/right movement. The sign
+ bits do not change until the mouse is moved in a opposite direction. So
+ moving the mouse up, and leaving it stationary would keep the Y sign bit
+ set to 1.
+
+ The Y and X movement fields indicate how rapidly the mouse was moved in a
+ particular direction. This is usually $00-$1F, but extremely rapid movements
+ can yield higher values. I haven't been able to get values large enough
+ to indicate there is a seventh movement bit, but there may likely be one.
+ Both fields are zero when there is no movement.
+
+ As far as I can tell, the mouse does not return any data through pin 5
+ (which always returns zero) and any setting of pin 6 will not affect the
+ mouse operation.
+
+ ----------------------------------------------------------------------------
+ Register reference
+ ----------------------------------------------------------------------------
+
+ $2180 - WRAM data port
+ $2181 - WRAM offset (bits 7-0 are offset bits 7-0)
+ $2182 - WRAM offset (bits 7-0 are bits 15-8)
+ $2183 - WRAM offset (bit 0 is offset bit 16, bits 7-1 are unused)
+
+ Registers $2181-$2183 define a 17-bit offset in WRAM. Reading or writing
+ $2180 will return a byte from or write a byte to WRAM, and automatically
+ increment the WRAM offset by one. The offset wraps from $01FFFF to $000000.
+
+ Reading $2180, $2181, or $2183 returns the last value on the data bus,
+ which is usually the last byte of the opcode fetched. For example, this
+ value would be $21 for 'lda $2181', or $00 for 'lda [$00]' when the pointer
+ at $00 is $2181.
+
+ ----------------------------------------------------------------------------
+ Cartridge information
+ ----------------------------------------------------------------------------
+
+ Cartridge pinout
+
+      Solder side   Component side
+
+     MCK     - 01   32 - /RAMSEL
+     EXPAND  - 02   33 - REFRESH
+     PA6     - 03   34 - PA7
+     /PARD   - 04   35 - /PAWR
+                <key>
+     GND     - 05   36 - GND
+     A11     - 06   37 - A12
+     A10     - 07   38 - A13
+     A9      - 08   39 - A14
+     A8      - 09   40 - A15
+     A7      - 10   41 - A16
+     A6      - 11   42 - A17
+     A5      - 12   43 - A18
+     A4      - 13   44 - A19
+     A3      - 14   45 - A20
+     A2      - 15   46 - A21
+     A1      - 16   47 - A22
+     A0      - 17   48 - A23
+     /IRQ    - 18   49 - /ROMSEL
+     D0      - 19   50 - D4
+     D1      - 20   51 - D5
+     D2      - 21   52 - D6
+     D3      - 22   53 - D7
+     /RD     - 23   54 - /WR
+     CIC0    - 24   55 - CIC1
+     CIC2    - 25   56 - CIC3
+     /RESET  - 26   57 - SYSCK
+     +5V     - 27   58 - +5V
+                <key>
+     PA0     - 28   59 - PA1
+     PA2     - 29   60 - PA3
+     PA4     - 30   61 - PA5
+     SOUND-L - 31   62 - SOUND-R
+
+ Pin assignments
+
+ A23-0   - CPU address bus
+ D7-0    - CPU data bus
+ /WR     - CPU write strobe
+ /RD     - CPU read strobe
+ /IRQ    - CPU IRQ input. Allows on-cart hardware to interrupt the CPU.
+ /RESET  - When the system is reset (power-up or hard reset) this goes low.
+           Could be used to reset additional on-cart hardware.
+ /RAMSEL - Goes low on accesses to WRAM at the following addresses:
+           00-3F:0000-1FFF
+           80-BF:0000-1FFF
+           7E-7F:0000-FFFF
+ /ROMSEL - Goes low on access to cartridge ROM at the following addresses:
+           00-3F:8000-FFFF
+           40-7D:0000-FFFF
+           80-BF:8000-FFFF
+           C0-FF:0000-FFFF
+ PA7-0   - Address bus for $2100-$21FF range in banks $00-$3F/$80-$BF (B-Bus)
+ /PAWR   - Write strobe for B-Bus
+ /PARD   - Read strobe for B-Bus
+ MCK     - 21.47727 MHz master clock
+ SYSCK   - Unknown, is an output from the CPU.
+ SOUND-L - Audio input to be mixed with left channel output
+ SOUND-R - Audio input to be mixed with right channel output
+ THROUGH - Connected to pin 24 of the expansion port.
+ REFRESH - Unknown, is an output from the CPU also connected to WRAM.
+           This is most likely to manage DRAM refresh.
+ CIC3-0  - To CIC chip on cartridge
+
+ Details
+
+ For more information about the CIC chip, please see the following:
+
+ - U.S. Patent no. 4,799,635 (NES specific)
+ - http://home.freeuk.com/markk/Consoles/SNES_Lockout.txt
+
+ The only hardware I know of which uses the two sound input pins is the
+ Super Gameboy and Super Gameboy 2.
+
+ The SNES has two address busses, the A-Bus which is used by the CPU, ROM,
+ WRAM, etc. and the B-Bus which is used by the PPU1, PPU2, APU I/O ports,
+ and WRAM. When the SNES does DMA, it can transfer data from the A-Bus to
+ the B-Bus or vice-versa, but not to the same bus. This holds true even
+ for WRAM, which is connected to both the A-Bus and B-Bus.
+
+ I would guess the B-Bus signals are brought out to the cartridge connector
+ so any on-cart hardware could map it's own registers within that region,
+ allowing for DMA from the A-Bus to it. Exactly what range of B-Bus addresses
+ are open for expansion purposes is unknown.
+
+ Cartridge information
+
+ Here's some information about several cartridges I've examined:
+
+ Name:  Lagoon
+ Board: SHVC-1A3B-12
+ Type:  LoROM / 16 megabits / 8K SRAM
+
+ This cartridge has a 74LS139 for address decoding and a 8K SRAM chip.
+
+ 00-1F:8000-FFFF : Program ROM
+ 20-3F:8000-FFFF : Unmapped
+ 40-6F:0000-FFFF : Unmapped
+ 70-7D:0000-FFFF : SRAM
+ 7E-7F:0000-FFFF : Work RAM
+ 80-9F:8000-FFFF : Program ROM
+ A0-BF:8000-FFFF : Unmapped
+ C0-EF:0000-FFFF : Unmapped
+ F0-FF:0000-FFFF : SRAM
+
+ - A23 and A15 are ignored, so banks $80-FF are a mirror of $00-7F.
+ - SRAM is mirrored repeatedly in the areas it's assigned to.
+ - When accessing an unmapped region, neither the ROM or SRAM are enabled.
+
+ Name:  Pilotwings
+ Board: SHVC-1BON-02
+ Type:  LoROM / 8 megabits / DSP-1
+
+ This cartridge has a 74LS139 for address decoding and a NEC uPD77C25 DSP
+ which Nintendo labels as the "DSP-1" custom chip. It also has a oscillator
+ and 74HCU04 to provide a clock signal, but I don't know what speed the DSP
+ actually runs at.
+
+ 00-1F:8000-FFFF : Program ROM
+ 20-2F:8000-FFFF : Unmapped
+ 30-3F:8000-BFFF : DSP data register (r/w)
+ 30-3F:C000-FFFF : DSP status register (r/o)
+ 40-7D:0000-FFFF : Unmapped
+ 7E-7F:0000-FFFF : Work RAM
+ 80-9F:8000-FFFF : Program ROM
+ A0-AF:8000-FFFF : Unmapped
+ 80-BF:8000-BFFF : DSP data register (r/w)
+ 80-BF:C000-FFFF : DSP status register (r/o)
+ C0-FF:0000-FFFF : Unmapped
+
+ - A23 and A15 are ignored, so banks $80-FF are a mirror of $00-7F.
+ - DSP pins INT, SCK, /SIEN, /SOEN are all tied to +5V and are unused.
+ - When accessing an unmapped region, neither the ROM or DSP are enabled.
+
+ Name:  Killer Instinct
+ Board: SHVC-1JON-20
+ Type:  HiROM / 32 megabits
+
+ The mask ROM socket on the PCB has the following pin assignments:
+
+         +---\/---+
+    A20 -|01    36|- +5V
+    A21 -|02    35|- A23
+    A17 -|03    34|- +5V
+    A18 -|04    33|- /ROMSEL (ROM /CS)
+    A15 -|05    32|- A19
+    A12 -|06    31|- A14
+     A7 -|07    30|- A13
+     A6 -|08    29|- A8 
+     A5 -|09    28|- A9 
+     A4 -|10    27|- A11
+     A3 -|11    26|- A16
+     A2 -|12    25|- A10
+     A1 -|13    24|- /RD (ROM /OE)
+     A0 -|14    23|- D7 
+     D0 -|15    22|- D6 
+     D1 -|16    21|- D5 
+     D2 -|17    20|- D4 
+    GND -|18    19|- D3 
+         +--------+
+
+ - A22 is unconnected.
+ - This game uses a MX23C3201 4096Kx8 mask ROM. I can't find a datasheet for
+   this chip, so I'm not sure what pin 35 (A23) is used for. It could be
+   an inverted chip select so the ROM is only mapped to banks $40-$7E and
+   $C0-$FF, but that's just a guess.
+
+ ----------------------------------------------------------------------------
+ Assistance needed
+ ----------------------------------------------------------------------------
+
+ If any games have a legitimate use of writing to OAM or reading OAM or CGRAM
+ during the active display period, I'd like to hear about the details of how
+ the data is used. So far it's been confirmed that Uniracers writes to OAM
+ this way, maybe there are others.
+
+ ----------------------------------------------------------------------------
+ Credits and acknowlegements
+ ----------------------------------------------------------------------------
+
+ - ToToTek Multimedia for the Game Doctor SF7. (www.tototek.com)
+ - neviksti for the SNES starter kit. (available at nesdev.parodius.com)
+ - John Weidman, CaitSith2, neviksti, for the SNES schematic scans.
+ - Gilligan for the SNES documentation.
+ - Qwertie for the SNES documentation.
+ - anomie for the post about SNES peripherals at the SNES9X development forum,
+   pointing out errors, and suggesting tests.
+ - Overload for clarifying some details about the mouse.
+ - Chris MacDonald for testing and support.
+
+ ----------------------------------------------------------------------------
+ Disclaimer
+ ----------------------------------------------------------------------------
+
+ If you use any information from this document, please credit me
+ (Charles MacDonald) and optionally provide a link to my webpage
+ (http://cgfm2.emuviews.com/) so interested parties can access it.
+
+ The credit text should be present in the accompanying documentation of
+ whatever project which used the information, or even in the program
+ itself (e.g. an about box).
+
+ Regarding distribution, you cannot put this document on another
+ website, nor link directly to it.
+

+ 175 - 0
files/docs/snes/tile_format.txt

@@ -0,0 +1,175 @@
+                ----------------------------
+                     By DAX on 28/2/93
+
+This is a short text file on how the data for the gfx on the SNES are
+set up..
+Everything is based around an 8x8 pixel 'Tile' and thinking in terms of
+tiles makes the whole thing a lot easier.
+ 
+4 Colour mode - 2 Bitplanes
+---------------------------
+If you split the screen into 8x8 pixel tiles, the order of the graphics data
+is tile 0,1,2,3,4 etc.(with tile 0 being the first, and 1 being the one on
+the right of it.)
+ 
+Then for each tile, the data is stored as shown below.
+        00 01 02 03 04 05 06 07
+        10 11 12 13 14 15 16 17    Each number representing one pixel in
+        20 21 22 23 24 25 26 27    the 8x8 tile.
+        30 31 32 33 34 35 36 37
+        40 41 42 43 44 45 46 47
+        50 51 52 53 54 55 56 57
+        60 61 62 63 64 65 66 67
+        70 71 72 73 74 75 76 77
+         
+The data is stored in the SNES binary in the following format.
+        Bitplane 0 ..   Line 00-07 (One Byte)
+                        Line 10-17
+                        Line 20-27
+                        Line 30-37
+                        Line 40-47
+                        Line 50-57
+                        Line 60-67
+                        Line 70-77
+then    Bitplane 1 ..   Line 00-07
+                        Line 10-17
+                        Line 20-27
+                        Line 30-37
+                        Line 40-47
+                        Line 50-57
+                        Line 60-67
+                        Line 70-77
+then comes the data for the next tile (the one on the right).etc.
+ 
+16 Colour - 4 Bitplanes
+-----------------------
+The data for this mode is stored in the same format, with one main change.
+The data is stored in the format
+        Bitplane 0 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+        Bitplane 1 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+        Bitplane 2 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+        Bitplane 3 ..   Line 00-07
+                               |
+                        Line 70-77
+                         
+then the data for the next tile.
+ 
+256 Colour - 8 Bitplanes
+------------------------
+This is simply an expansion of the 4 and 16 colour modes.
+        Bitplane 0 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+        Bitplane 1 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+        Bitplane 2 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+        Bitplane 3 ..   Line 00-07
+                               |
+                        Line 70-77
+         
+        Bitplane 4 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+        Bitplane 5 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+        Bitplane 6 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+        Bitplane 7 ..   Line 00-07
+                               |
+                        Line 70-77
+ 
+then the data for the next tile.
+
+256 Colours - Mode 7 format
+---------------------------
+This has some very major differences to the other graphics data formats
+ 
+there are two mode7 modes, normal and EXTBG, the data is stored in the
+same way in both, apart from in EXTBG the Bitplane 7 value will be a 
+priority bit for the pixel, which cuts the colours down to 128.
+ 
+Each byte of 'graphics data' is actually the colour value for that pixel
+on the screen, so if the value is 64, then the colour of that pixel will
+be the contents of colour register 64.
+ 
+The data is stored in VRAM differently to the other modes, with the tile
+numbers, and the graphics data 'interleaved', starting at $0000 in VRAM,
+with alternate bytes containing one byte of tile, one byte of gfx - this
+is shown below.
+ 
+        Word of VRAM.        HI                         LO
+        Bit  15  14  13  12  11  10  09  08  07  06  05  04  03  02  01  00
+content     |------------------------------||------------------------------|
+               Graphics data(CHAR DATA)             Tile number(NAME)
+ 
+Because of the storing of 16 bit data in reverse format (LO-HI) this means
+that if you set the VRAM addr to $0.the first byte written should be the
+tile name for that position on screen and the second byte should be the first
+byte of the Mode7 graphics data.if the VRAM addr is set to $1 the first byte
+written will be the tile name for that position on scr, and the second byte
+should be the second byte of the mode7 graphics data.
+  ETC
+   
+In mode7 you can only have a maximum of 256 tiles, because of the fact that
+the mode7 data only takes up the first half of VRAM(32k) you can only have 16k
+of graphics data which is 256 tiles of 8x8 with 256 colours.
+This is quite a limitation, but can be used quite effectively.
+                  
+The tile numbers are stored in a format according to a 128x128 tile screen
+so tile 128($80) would be the tile below 0($0) on the screen, and so on.
+so VRAM addr $0 is the top left tile, and $1 is the one on the right of it
+$80 is the one on the left side, one row down.
+ 
+the graphics data is stored based on an 8x8 tile again.
+but slightly different.
+Each byte(pixel) is stored so... 
+                        Bit number    Contents
+                                0          Bitplane 0 pixel value
+                                1          Bitplane 1 pixel value    
+                                2          Bitplane 2 pixel value
+                                3          Bitplane 3 pixel value
+                                4          Bitplane 4 pixel value
+                                5          Bitplane 5 pixel value
+                                6          Bitplane 6 pixel value
+                                7          Bitplane 7 pixel value /
+                                           (EXTBG mode - Priority value)
+                                            
+The data is then stored in the sequence
+                00,01,02,03,04,05,06,07
+                10,11,12,13,14,15,16,16  (Look at diagram at start of file
+                    |      |      |       for explanation)
+                70,71,72,73,74,75,76,77
+                                         
+with one byte for each position(pixel), according to the 8x8 tile format,  
+with one tile after another.
+ 
+---------------------------------------------------------------------------
+I hope this text file helps those of you having trouble converting graphics
+for use on the SNES, I have been asked a few times recently for this info
+so I decided to type up this short text file on it.
+Hopefully it should explain it!
+ 
+If you have any further questions contact :-
+                Dax      or    Corsair
+
+

+ 188 - 0
files/docs/snes/tiles.txt

@@ -0,0 +1,188 @@
+[Image]
+
+                             SNES Screen Format
+
+[Image]
+
+
+                SNES GRAPHICS INFO FILE V1.0
+                ----------------------------
+                     By DAX on 28/2/93
+
+This is a short text file on how the data for the gfx on the SNES are
+set up..
+Everything is based around an 8x8 pixel 'Tile' and thinking in terms of
+tiles makes the whole thing a lot easier.
+
+4 Colour mode - 2 Bitplanes
+---------------------------
+If you split the screen into 8x8 pixel tiles, the order of the graphics data
+is tile 0,1,2,3,4 etc.(with tile 0 being the first, and 1 being the one on
+the right of it.)
+
+Then for each tile, the data is stored as shown below.
+        00 01 02 03 04 05 06 07
+        10 11 12 13 14 15 16 17    Each number representing one pixel in
+        20 21 22 23 24 25 26 27    the 8x8 tile.
+        30 31 32 33 34 35 36 37
+        40 41 42 43 44 45 46 47
+        50 51 52 53 54 55 56 57
+        60 61 62 63 64 65 66 67
+        70 71 72 73 74 75 76 77
+
+The data is stored in the SNES binary in the following format.
+        Bitplane 0 ..   Line 00-07 (One Byte)
+                        Line 10-17
+                        Line 20-27
+                        Line 30-37
+                        Line 40-47
+                        Line 50-57
+                        Line 60-67
+                        Line 70-77
+then    Bitplane 1 ..   Line 00-07
+                        Line 10-17
+                        Line 20-27
+                        Line 30-37
+                        Line 40-47
+                        Line 50-57
+                        Line 60-67
+                        Line 70-77
+then comes the data for the next tile (the one on the right).etc.
+
+16 Colour - 4 Bitplanes
+-----------------------
+The data for this mode is stored in the same format, with one main change.
+The data is stored in the format
+        Bitplane 0 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 1 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 2 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 3 ..   Line 00-07
+                               |
+                        Line 70-77
+
+then the data for the next tile.
+
+256 Colour - 8 Bitplanes
+------------------------
+This is simply an expansion of the 4 and 16 colour modes.
+        Bitplane 0 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 1 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 2 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 3 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 4 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 5 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 6 ..   Line 00-07
+                               |
+                        Line 70-77
+
+        Bitplane 7 ..   Line 00-07
+                               |
+                        Line 70-77
+
+then the data for the next tile.
+
+256 Colours - Mode 7 format
+---------------------------
+This has some very major differences to the other graphics data formats
+
+there are two mode7 modes, normal and EXTBG, the data is stored in the
+same way in both, apart from in EXTBG the Bitplane 7 value will be a
+priority bit for the pixel, which cuts the colours down to 128.
+
+Each byte of 'graphics data' is actually the colour value for that pixel
+on the screen, so if the value is 64, then the colour of that pixel will
+be the contents of colour register 64.
+
+The data is stored in VRAM differently to the other modes, with the tile
+numbers, and the graphics data 'interleaved', starting at $0000 in VRAM,
+with alternate bytes containing one byte of tile, one byte of gfx - this
+is shown below.
+
+        Word of VRAM.        HI                         LO
+        Bit  15  14  13  12  11  10  09  08  07  06  05  04  03  02  01  00
+content     |------------------------------||------------------------------|
+               Graphics data(CHAR DATA)             Tile number(NAME)
+
+Because of the storing of 16 bit data in reverse format (LO-HI) this means
+that if you set the VRAM addr to $0.the first byte written should be the
+tile name for that position on screen and the second byte should be the first
+byte of the Mode7 graphics data.if the VRAM addr is set to $1 the first byte
+written will be the tile name for that position on scr, and the second byte
+should be the second byte of the mode7 graphics data.
+  ETC
+
+In mode7 you can only have a maximum of 256 tiles, because of the fact that
+the mode7 data only takes up the first half of VRAM(32k) you can only have 16k
+of graphics data which is 256 tiles of 8x8 with 256 colours.
+This is quite a limitation, but can be used quite effectively.
+
+The tile numbers are stored in a format according to a 128x128 tile screen
+so tile 128($80) would be the tile below 0($0) on the screen, and so on.
+so VRAM addr $0 is the top left tile, and $1 is the one on the right of it
+$80 is the one on the left side, one row down.
+
+the graphics data is stored based on an 8x8 tile again.
+but slightly different.
+Each byte(pixel) is stored so...
+                        Bit number    Contents
+                                0          Bitplane 0 pixel value
+                                1          Bitplane 1 pixel value
+                                2          Bitplane 2 pixel value
+                                3          Bitplane 3 pixel value
+                                4          Bitplane 4 pixel value
+                                5          Bitplane 5 pixel value
+                                6          Bitplane 6 pixel value
+                                7          Bitplane 7 pixel value /
+                                           (EXTBG mode - Priority value)
+
+The data is then stored in the sequence
+                00,01,02,03,04,05,06,07
+                10,11,12,13,14,15,16,16  (Look at diagram at start of file
+                    |      |      |       for explanation)
+                70,71,72,73,74,75,76,77
+
+with one byte for each position(pixel), according to the 8x8 tile format,
+with one tile after another.
+
+---------------------------------------------------------------------------
+I hope this text file helps those of you having trouble converting graphics
+for use on the SNES, I have been asked a few times recently for this info
+so I decided to type up this short text file on it.
+Hopefully it should explain it!
+
+
+
+                                  [Image]
+
+                         © 1996 Damaged Cybernetics
+
+
+
+                                  [Image]

+ 74 - 0
files/docs/snes/vram.txt

@@ -0,0 +1,74 @@
+From:     vic@physci.psu.edu (Vic Ricker)
+To:       "Super Famicom Development Group" <famidev@busop.cit.wayne.edu>
+Subject:  Re:  some programming questions
+Date:     Tue, 9 Nov 93 20:20:35 EST
+
+>Hi Folks.
+
+>I need help with a few SNES programming questions... 
+
+>(1) Can anyone tell me how to make noises come out of my SNES?
+
+Insert your favorite cart, power up the TV, switch the snes power to
+ON.. :-)
+
+>(3) Is the sprite position table held in RAM or VRAM? And how
+>    do the 5 address bits in $2101 relate to this location?
+
+The sprite images are stored in VRAM.  The palettes for the sprites
+are stored in CGRAM.  The coordinates and char attributes are stored
+in OAM.
+
+The format of each OBJ is:
+
+OBJ H position: 8 bits
+OBJ V position: 8 bits
+V flip: 1 bit
+H flip: 1 bit
+OBJ priority: 2 bits
+color palette: 3 bits
+character name: 9 bits
+
+there are 128 of these in sequence making 512 bytes then 32 bytes
+follow in the format:
+size: 1 bit
+x msb: 1 bit
+
+there are 128 of these (one for every OBJ) making 32 more bytes.
+
+$2101 is OBJSEL
+
+it chooses the size of sprites to use and also sets the address of the
+images in VRAM.  the top 3 bits chose the size:
+
+000 means 8x8 and 16x16 sprites
+001 8x8 and 32x32
+010 8x8 and 64x64
+011 16x16 and 32x32
+100 16x16 and 64x64
+101 32x32 and 64x64
+
+the other bits are the address in vram of the sprite images.
+
+
+$2102-$2103 is OAMADDL/H
+the lower 9 bits are the address for accessing the OAM. (like $2116
+for VRAM)
+the high bit (15) enables priority rotation (causes OBJ's to change
+priority as to keep them from disappearing totally when time out and range
+over occur.)
+
+$2104 is OAMDATA
+
+it is the write register for the OAM. (like $2118-$2119 for VRAM)
+
+
+$2138 is *OAMDATA
+
+it is the read register for the OAM.
+
+
+Hope this gives you enough to play with.  Most is from memory, I hope
+its all correct. :-)
+
+Lemme know if you have questions.

BIN
files/docs/snes/w65c816s.pdf


+ 3354 - 0
files/docs/snes/wla_doc.txt

@@ -0,0 +1,3354 @@
+
+--------------------------------------------------------------------------------
+ WLA DX GB-Z80/Z80/6502/65C02/6510/65816/HUC6280/SPC-700 Macro Assembler Package
+                      Written by 1998-2002 Ville Helin
+--------------------------------------------------------------------------------
+
+
+1..... Introduction
+2..... WLA GB-Z80/Z80/6502/65C02/6510/65816/HUC6280/SPC-700 History
+3..... WLAB History
+4..... WLAD History
+5..... WLALINK History
+6..... Assembler Directives
+7..... Assembler Syntax
+ 7.1.. Case Sensitivity
+ 7.2.. Comments
+ 7.3.. Labels
+ 7.4.. Number Types
+ 7.5.. Strings
+ 7.6.. Supported Mnemonics
+ 7.7.. Brackets?
+8..... Error Messages
+9..... Supported ROM/RAM/Cartridge Types (WLA-GB)
+ 9.1.. ROM Size
+ 9.2.. RAM Size
+ 9.3.. Cartridge Type
+10.... Bugs
+11.... Files
+ 11.1. 'examples'
+ 11.2. 'examples/gb-z80/lib'
+12.... Temporary Files
+13.... Compiling
+ 13.1. Compiling Object Files
+ 13.2. Compiling Library Files
+14.... Linking
+15.... Arithmetics
+16.... Disassembling
+17.... Binary to DB Conversion
+18.... Things you should know about coding for...
+ 18.1. Z80
+ 18.2. 6502
+ 18.3. 65C02
+ 18.4. 6510
+ 18.5. 65816
+ 18.6. HUC6280
+ 18.7. SPC-700
+ 18.8. Pocket Voice (GB-Z80)
+19.... WLA Flags
+20.... Extra compile time definitions
+21.... Good things to know about WLA
+22.... Author
+23.... Thanks
+24.... Future
+25.... Support
+26.... Legal Note
+
+
+
+------------------------------------------------------------------------------
+1... Introduction
+------------------------------------------------------------------------------
+
+
+I wrote this because I had never written an assembler before and I really
+needed a macro assembler which could compile the GB-Z80 code I wrote. ;)
+Gaelan Griffin needed real Z80 support for his SMS projects so I thought
+I could write WLA to be a little more open and nowadays it supports all
+the Z80 systems you can think of. You'll just have to define the memorymap
+of the destination machine for your project. After fixing some bugs I thought
+I could add support for 6502 systems so all NES-people would get their
+share of WLA as well. After finishing that few people said they'd like 65816
+support (they had SNES developing in mind) so I added support for that. And
+then I thought I should write a 6510 version of WLA as well...
+
+Almost all rules that apply to Z80 compiling apply also to 6502, 65C02, 6510,
+65816, HUC6280 and SPC-700.
+
+This is my ideal GB-Z80 macro assembler (not in final form, not yet). ;)
+Tastes differ. Thus WLA! Notice that WLA was initially made for Game Boy
+developers so the GB-Z80 version and the rest differ a little.
+
+Currently WLA can also be used as a patch tool. Just include the original
+ROM image into the project with .BACKGROUND and insert OVERWRITE .SECTIONs
+to patch the desired areas. Output the data into a new ROM image and there
+you have it. 100% readable (asm coded) patches are reality!
+
+Note that you can directly compile only object and library files. You must
+use WLALINK to link these (or only one, if you must) into a ROM/program file.
+
+About the names... WLA DX means all the tools covered in this documentation.
+So WLA DX includes WLA GB-Z80/Z80/6502/65C02/6510/65816/HUC6280/SPC-700
+macro assembler (what a horribly long name), WLAB, WLAD and WLALINK
+GB-Z80/Z80/6502/65C02/6510/65816/HUC6280/SPC-700 linker. I use plain WLA to refer
+to the macro assembler.
+
+WLA DX's homepage: http://www.hut.fi/~vhelin/wla.html
+
+And if you happen to write something cool using WLA DX, please let me know,
+I want to see it!
+
+
+
+------------------------------------------------------------------------------
+2... WLA GB-Z80/Z80/6502/65C02/6510/65816/HUC6280/SPC-700 History
+------------------------------------------------------------------------------
+
+
+v8.7 (07-Sep-2002) [ALL] Added DSB and DSW, and EXPORT to .ENUM.
+                   [ALL] Added DSB and DSW to .RAMSECTION.
+                   [ALL] "dec" and "hex" work now in .PRINTV (only the
+                     uppercase "DEC" and "HEX" used to work).
+                   [ALL] Value parsers accept now big (32bit) values.
+                     Previously only 16bit (and 24bit for 65816) values
+                     were accepted.
+	           [ALL] ".ende" works now also (only ".ENDE" used to work).
+                   [ALL] Added .STRUCT.
+                   [65x] Fixed a case when operand hinting was ignored.
+
+v8.6 (02-May-2002) [65x] Forgot to add .b/.w operand hint support to
+                     pure hexadecimal and binary operands.
+                   [65x] Fixed a lot of 8bit relative operands to be absolute.
+                   [65x] Added support for 65C02 systems (wla-65c02).
+                   [HuC] Added support for HuC6280 systems (wla-huc6280).
+                   [Z80] WLALINK would discard (with flag d) all SDSCTAG-
+                     sections generated with .SDSCTAG.
+                   [Z80] Added few missing Z80 opcodes (eg. "JP (IY)").
+                   [Z80] Fixed a silly bug in .SDSCTAG.
+                   [SPC] Renamed "wla-spc" to "wla-spc700".
+
+v8.5 (19-Apr-2002) [ALL] All unidentified free strings were treated as labels.
+                     Fixed so that labels can only start at the beginning of
+                     a new line.
+                   [ALL] Added support for yet another un-named label (__).
+                   [ALL] ".endm" works now also (only ".ENDM" used to work).
+                   [ALL] Fixed the preprocessor to work better.
+                   [ALL] Fixed .DxSIN & .DxCOS to finally work properly.
+                   [ALL] 'x' switch generates now also WLA_VERSION.
+                   [ALL] Fixed the preprocessor to handle few special cases
+                      related to the use of '+'.
+                   [65x] WLA can now be also hinted about the operand size
+                     with .b and .w in the operand (eg. "and 10.w").
+
+v8.4 (24-Dec-2001) [ALL] Token parser could fail while skipping comma
+                     separated tokens inside .IF.
+                   [ALL] Updated the documentation (few crucial things were
+                     missing).
+                   [ALL] Fixed .RAMSECTION to work (was missing since its
+                     introduction).
+                   [ALL] Internal pass 1 failed to see duplicate labels.
+                   [ALL] Address labels don't need to end to ':' any more.
+                   [ALL] Added support for un-named labels
+                     (-, --, +, ++, ...).
+                   [ALL] Stack calculator can now return strings (and will
+                     if the result consist of only one string).
+
+v8.3 (21-Oct-2001) [ALL] Added .INPUT.
+                   [ALL] It's now possible to set the bank/slot size to
+                     full 65536 bytes.
+                   [ALL] Removed switch u.
+                   [ALL] Redefining a value definition to be a string
+                     definition would crash WLA.
+                   [SPC] Added support for SPC-700 systems (wla-spc).
+                   [658] Class 4 mnemonic ("ADC #x", "LDA #x", etc) decoder
+                     handles now labels correctly in 8bit operand mode.
+                   [Z80] "SUB (IX+n)" was mistyped as "SUB A, (IX+n)".
+                   [Z80] Updated .SDSCTAG to support the version 1.01
+                     of SDSC ROM Tag Specification.
+
+v8.2 (19-Jul-2001) [ALL] Added .OUTNAME.
+                   [ALL] Added .ORGA.
+                   [ALL] Added .RAMSECTION for variables.
+                   [ALL] It's now possible to create string and value
+                     definitions on the command line (-Ddefinition[=value]).
+                   [ALL] Code cleanups.
+                   [ALL] Optimized internal data format.
+                   [ALL] Optimized stack calculator routines.
+                   [ALL] Definition labels inside .ENUM can now end to ':'.
+                   [ALL] Fixed parser holes in .ENUM.
+                   [ALL] Added XOR-operator (~) support to computations.
+                   [658] Fixed "BRL" to work (the fix was partially missing in 
+                     v8.1 due to a uncareful source tree merge).
+                   [658] Fixed "PER" to work.
+
+v8.1 (03-Jul-2001) [ALL] EXPORT'ing more than once the same definition
+                     gives an warning instead of an error.
+                   [ALL] It's now possible to export more than one
+                     definition with .EXPORT.
+                   [ALL] It's now possible to undefine more than one
+                     definition with .UNDEF.
+                   [ALL] Some directive arguments could only be accepted
+                     if they were in uppercase (eg. FORCE, FREE, SWAP, ...).
+                   [ALL] Unix users can now define the WLA DX compiling
+                     flags by defining CFLAGS before executing make.
+                   [ALL] Parse code cleanups.
+                   [ALL] Macro argument place holders (eg. \1 and \@) can
+                     now be used inside labels and strings.
+                   [ALL] WLA doesn't even try to solve any of the label
+                     references (even trivial), all that is now left
+                     for WLALINK.
+                   [65x] Now there are .B, .W and .L versions of all
+                     the mnemonics that take immediate values.
+                   [65x] BRK & COP -mnemonics now have a default signature
+                     byte $00.
+                   [65x] Added "BRK x" (and "COP x" to WLA-65816).
+                   [658] Fixed BRL to work.
+                   [658] Fixed .NAME to write the name data to $FFC0-> in
+                     HiROM- and to $7FC0-> in LoROM-mode.
+                   [658] All the SNES ROM information bytes WLA supports
+                     obey now .HIROM and .LOROM.
+                   [658] Fixed SNES directives.
+                   [650] Fixed "STY x,Y" to "STY x,X".
+                   [Z80] Fixed few cases where IX&IY were interpreted
+                     as labels.
+
+v8.0 (19-May-2001) [ALL] Simplified WLA engine a lot by leaving away ROM and
+                     program file compiling, and the old, crippled error
+                     reporting engine.
+                   [ALL] Removed .FOOTER and .HEADER (no longer required).
+                   [ALL] WLA compiles now "WLAQ" library files and "WLAD"
+                     object files (merged old object file formats).
+                   [ALL] Removed few redundant error messages.
+                   [ALL] Removed label name compactor.
+                   [ALL] Optimized internal pass 1.
+                   [ALL] Optimized object and library file writing.
+                   [ALL] Optimized Z80, 6502, 6510 and 65816 opcode tables
+                     (smaller WLA executables).
+                   [ALL] Empty sections get discarded (and labels inside
+                     them as well).
+                   [ALL] ".IF A==B" works now as well (only ".IF A == B"
+                     used to work).
+                   [ALL] WLA doesn't strip the size from the section name
+                     if the size is explicitly defined.
+
+v7.8 (13-May-2001) [ALL] Optimized preprocessor a little, output is now
+                     even more compact than before.
+                   [Z80] Reordered LD-mnemonics in the mnemonics table a
+                     little so all common mnemonics get decoded faster.
+                   [Z80] Added "RST $00" (plain "RST" is still there, too).
+
+v7.7 (12-May-2001) [Z80] Fixed "LD ?,IX" and "LD ?,IY" to "LD (?),IX" and
+                     "LD (?),IY".
+
+v7.6 (10-May-2001) [ALL] Not all mnemonics were case insensitive, a bug
+                     introduced in the previous release.
+
+v7.5 (07-May-2001) [ALL] Optimized mnemonic decoders a little.
+                   [651] Fixed all NOP -mnemonics to work.
+
+v7.4 (02-May-2001) [ALL] Added many new error messages.
+                   [ALL] Result placing in stack calculator could fail if the
+                     result's position wasn't inside a section.
+                   [ALL] Modulo/division by zero doesn't crash WLA anymore.
+                   [ALL] Now also in ROM compiling mode it's possible to refer
+                     to future value definitions with .DB and .DW.
+                   [ALL] Win32 port uses now PID in the temp file name.
+                   [ALL] Fixed few places which could generate incorrect
+                     destination memory overwrite warnings.
+                   [ALL] Program file compiler dislayed a wrong binary size
+                     in verbose mode.
+                   [ALL] Enhanced .INCBIN.
+                   [Z80] Loose strings given to .SDSCTAG don't cause
+                     overwrite warnings anymore.
+                   [658] Fixed "STZ ?, X" to work (misclassified earlier).
+                   [65x] Added new fixed value size mnemonics to the mnemonics
+                     tables to speed up the coding and parsing (eg.
+                     "CMP.W ?"). Only those mnemonics with multiple argument
+                     size choices are affected.
+                   [650] Fixed "DEC ?,X" and "DEC ?" to work (misclassified
+                     earlier).
+                   [658] Added .LOROM, .HIROM and .BASE to help generating
+                     SNES 24bit addresses.
+                   [658] Added .SLOWROM and .FASTROM for ROM memory speed
+                     identification.
+                   [658] .NAME works also in WLA-65816 (SNES ROM name string
+                     starting at $FFC0).
+
+v7.3 (12-Apr-2001) [ALL] Fixed possible problems with bank overflows
+                     (bank size wasn't always up to date).
+                   [ALL] Preprocessor modifications introduced a bug
+                     which trashed included source files.
+                   [ALL] Optimized preprocessor even more.
+                   [ALL] .DEFINE and .REDEFINE missed linecounter
+                     checks due to the new multibyte definitions.
+                   [Z80] Added .SDSCTAG (SDSC ROM tag).
+                   [Z80] Added .SMSTAG (SMS/GG ROM tag).
+
+v7.2 (08-Apr-2001) [ALL] Rewrote the preprocessor code, now it produces
+                     much more compact output and is generally faster.
+                   [ALL] Files can now begin with "/*".
+                   [ALL] Now there can be comments after one word
+                     mnemonics (broken before).
+                   [ALL] .REPT takes now also zero as argument.
+                   [ALL] Multibyte definitions are now possible.
+                   [ALL] WLA_TIME ended to a linefeed, thanks to
+                     ctime(), but not anymore.
+                   [Z80] Fixed "LD BC,(?)" and "LD BC,?" recognition to
+                     work better.
+
+v7.1 (13-Mar-2001) [ALL] Added 'x' switch to generate extra compile time
+                     definitions (WLA_TIME, WLA_FILENAME).
+                   [ALL] Characters can now be used in computations (eg.
+                     LD A, 'F'-10).
+                   [ALL] WLA could not get the correct section size
+                     from a section name if more than one underline
+                     was used.
+                   [ALL] .INCLUDE and .INCBIN used wrong name in error
+                     messages if the file was found on the current working
+                     directory and not in the .INCDIR directory.
+                   [ALL] Unix makefiles default now to gcc (if no CC/LD is
+                     defined).
+                   [ALL] .REPT can now be used inside macros.
+                   [ALL] .REPTs can be used inside .REPTs.
+                   [ALL] Macro arguments in computations work now better.
+                   [ALL] Error engine's line counting works now inside
+                     macros.
+                   [ALL] File doesn't need to end to a line feed anymore.
+                   [ALL] Added '>=' and '<=' to .IF.
+                   [ALL] Added .IFGREQ and .IFLEEQ.
+                   [ALL] .IF -directives should now work with computations.
+                   [Z80] WLA gives only a warning if .COMPUTESMSCHECKSUM
+                     is used on a ROM file smaller than 32KB.
+                   [650] Fixed "INC ?" to work (wrong type previously).
+
+v7.0 (03-Mar-2001) [ALL] WLA couldn't handle files starting with ";".
+                   [ALL] Enhanced error messages.
+                   [ALL] Compiling WLA DX under Unix is now done with egcs
+                     (if no CC is defined).
+                   [ALL] Added error messages to .ENUM and made it to accept
+                     lowercase symbols. Also added fake symbols.
+                   [ALL] Fixed a serious bug with 8bit pending calculations.
+                   [ALL] Enhanced makefiles (behave now better under Unix).
+                   [ALL] The code works now regardless of the endian type.
+                   [ALL] .INCLUDE and .INCBIN try to find the file in the
+                     current working directory if it's not in the .INCDIR
+                     directory.
+                   [ALL] Definitions take also strings as values.
+                   [ALL] Code cleanups.
+                   [ALL] Exporting an undefined definition doesn't break
+                     the compiling loop (only a warning is issued).
+                   [ALL] Quotation marks are accepted inside strings.
+                   [ALL] Temporary files are placed into the current working
+                     directory and under Unix the names incorporate PID.
+                   [ALL] .DBSIN and the rest were broken due to a typo.
+                   [ALL] Optimized string parsers.
+                   [ALL] Added .IFEXISTS.
+                   [ALL] Macro argument place holders (eg. "\1") and \@ can
+                     now be used in computations (eg. "LD A, \1+\2+\@").
+                   [ALL] Macros can be used inside macros (but macro arguments
+                     cannot be directly forwarded to the next level).
+                   [ALL] "/*/" isn't interpreted as an empty comment anymore.
+                   [ALL] Section size can be defined insize the section name
+                     string.
+                   [Z80] Added TI-86 system include file to the archive.
+                   [Z80] Added .COMPUTESMSCHECKSUM for computing the
+                     Sega Master System ROM checksum.
+                   [Z80] Fixed "LD (IX+x), x" to work.
+                   [!GB] Few mnemonics caused stack calculator to create
+                     garbage.
+                   [GB ] Complement check computing could fail with some
+                     really bad luck.
+
+v6.9 (23-Oct-2000) [ALL] Enhanced .MACRO error messages.
+                   [ALL] Enhanced .DW error recognition.
+                   [ALL] .SECTION handling might broke with some bad luck.
+                   [ALL] \@ can now be used inside strings inside a .MACRO.
+                   [65x] Added support for "ASL", "LSR", "ROL" and "ROR".
+                   [650] Fixed "STA ?" to $8D (was $80).
+                   [650] Fixed "EOR ?" to $4D (was $40).
+                   [650] Fixed "RTI" to $40 (was $4D).
+                   [650] Fixed "STA ?,X" to $9D (was $90).
+                   [650] Fixed "ORA ?,X" to $1D (was $10).
+                   [650] Fixed "EOR ?,X" to $5D (was $50).
+                   [650] Fixed "ADC ?" to $6D (was $60).
+                   [650] Fixed "ADC ?,X" to $7D (was $70).
+
+v6.8 (09-Oct-2000) [Z80] Fixed "LD C, RL*" -mnemonics.
+                   [651] Added support for 6510 systems (wla-6510).
+                   [ALL] Enhanced documentation.
+                   [ALL] Library file compiling was broken in the previous
+                     release.
+
+v6.7 (07-Oct-2000) [ALL] Added NARGS to .MACRO.
+                   [ALL] Enhanced documentation.
+                   [ALL] Enhanced error messages.
+                   [ALL] Optimized the first internal pass.
+                   [ALL] Macros couldn't have .PRINTT directives with
+                     linefeeds.
+                   [65x] Added .8BIT and .16BIT.
+                   [658] Added support for 65816 systems (wla-65816).
+                   [658] Added .24BIT.
+                   [Z80] Fixed RST-mnemonics.
+                   [GB ] Moved lib to examples/gb.
+
+v6.6 (25-Sep-2000) [ALL] .EMPTYFILL didn't function properly when .ROMBANKMAP
+                     was used instead of .ROMBANKS.
+                   [ALL] Fixed few byte size checks.
+                   [650] Added support for 6502 systems (wla-6502).
+                   [!GB] Header and footer sizes are now shown in the
+                     verbose mode's result information.
+
+v6.5 (20-Sep-2000) [ALL] Optimized number decoding.
+                   [ALL] Enhanced documentation.
+                   [ALL] Binary file compiling is now called program file
+                     compiling (still doesn't suit it 100%).
+                   [ALL] Macros couldn't be used before setting an ORG.
+                   [Z80] Program file compiling accepts now BANKHEADER
+                     section for bank 0.
+                   [Z80] The default program file suffix is now '.prg'.
+                   [Z80] NO$GMB symbol files can also be written.
+
+v6.4 (12-Sep-2000) [ALL] Returned '*' commenting (from the beginning of a
+                     line).
+                   [ALL] 'LABEL:XYZ' is now correctly decoded.
+                   [ALL] BIT/RES/RST/SET opcodes understand now defines
+                     and calculations.
+                   [ALL] References to local labels outside sections were
+                     possible.
+                   [ALL] Added a much faster and enhanced MACRO language.
+                   [ALL] IF directives can now be nested.
+                   [ALL] .INCBIN works in library files.
+                   [ALL] Added .REDEFINE.
+                   [ALL] Added .PRINTT and .PRINTV.
+                   [ALL] Added .DBSIN, .DBCOS, .DWSIN and DWCOS.
+                   [ALL] Added .IFEQ, .IFNEQ, .IFGR and .IFLE.
+                   [ALL] Added .IF with the following operators: '>', '<',
+                     '!=' and '=='.
+                   [ALL] Added .IFNDEFM and .IFDEFM.
+                   [ALL] Added .UNDEF.
+                   [ALL] Added .FAIL.
+                   [ALL] Added SEMIFREE sections.
+                   [ALL] Fixed a bug in opcode case sensitivity checks.
+                   [ALL] Opcode case sensitivity mode can be changed so
+                     WLA understands only uppercase letters (flag u).
+                   [ALL] Added support for modulo ('#') in calculations.
+                   [ALL] Enhanced error messages.
+                   [ALL] ROM banks can be inserted into different sized
+                     slots as long as the bank fits fully inside the slot.
+                   [ALL] Computations are now computed internally with higher
+                     precision when possible and the result is converted to
+                     an integer.
+
+v6.3 (04-Sep-2000) [ALL] Enhanced error messages.
+                   [ALL] Optimized section handling.
+                   [ALL] Optimized label handling.
+                   [ALL] Removed support for '*' commenting.
+                   [ALL] Added support for special ROM bank header sections.
+                   [ALL] Added support for powers ('^') and shifts ('<<'
+                     and '>>') in calculations.
+                   [ALL] Fixed calculator engine to work better.
+                   [ALL] Enhanced calculation detection.
+                   [ALL] .DB and .DW take now comma separated data. Make
+                     sure to use commas when placing arithmetic calculations
+                     inside .DB and .DW data fields.
+                   [ALL] .DSW, .DSB, .DW and .DB take labels and pending
+                     computations as data.
+                   [ALL] The following directives can be redefined as long
+                     as the values equal: .ROMBANKS, .EMPTYFILL and
+                     .ROMBANKSIZE.
+                   [ALL] .ROMBANKMAPs and .ROMBANKS can be redefined as long
+                     as they match (as much as possible). WLA will then use
+                     the biggest defined ROM bank map.
+                   [GB ] The following directives can be redefined as long
+                     as the values equal: .NAME, .RAMSIZE,
+                     .CARTRIDGETYPE, .LICENSEECODENEW, .LICENSEECODEOLD,
+                     .COMPUTECHECKSUM, .COMPUTECOMPLEMENTCHECK, .ROMDMG,
+                     .ROMGBC and .ROMSGB.
+
+v6.2 (31-Aug-2000) [ALL] Enhanced error messages.
+                   [ALL] Enhanced number size checks in the opcode decoding
+                     loop.
+                   [ALL] Braces are not needed anymore in arithmetics.
+                   [ALL] Added a fully functional stack calculator engine.
+                   [ALL] Unused local labels don't get smoked anymore.
+                   [ALL] WLA could crash when including a file while
+                     using the old error message engine.
+                   [ALL] Negative values in the 16bit range are now
+                     handled with better care.
+                   [ALL] When compiling a ROM image and using a section
+                     inside direct mapped code WLA would screw up the data.
+
+v6.1 (26-Aug-2000) [ALL] Directives accept now definitions as arguments.
+                   [ALL] Added more security checks to .MEMORYMAP.
+                   [ALL] Optimized .MEMORYMAP building.
+                   [ALL] Optimized SLOT usage.
+                   [ALL] Added .ROMBANKMAP and .ENDRO.
+                   [ALL] .BANKSIZE is now .ROMBANKSIZE.
+                   [ALL] 4G worth of ROM banks are supported.
+                   [ALL] SLOT numbers start from 0.
+
+v6.0 (23-Aug-2000) [ALL] Rewrote and optimized opcode decoding.
+                   [ALL] Preprocessing subroutine removed comments from inside
+                     data strings.
+                   [ALL] Support for old syntax directives is dropped.
+                   [ALL] Enhanced the documentation.
+                   [ALL] Enhanced the error messages.
+                   [ALL] .INCBIN could break the line numbering in the
+                     error messaging engine.
+                   [ALL] Fixed a bug in .FORCE section handling.
+                   [ALL] Added .BANKSIZE.
+                   [ALL] Added .MEMORYMAP and .ENDME.
+                   [ALL] Added .ENDASM and .ASM.
+                   [ALL] '*' can also be used to comment away lines.
+                   [ALL] WLA can now test compile (flag t).
+                   [ALL] .ROMSIZE is replaced with .ROMBANKS.
+                   [ALL] Changed FREE section positioning a little.
+                   [Z80] Binary files can be compiled with the flag 'b'.
+                   [Z80] Added .HEADER.
+                   [Z80] Added .FOOTER.
+
+v5.0 (09-Jul-2000) Enhanced brackets detection.
+                   Enhanced the documentation.
+                   Enhanced error messages.
+                   WLA outputs now a NO$GMB symbolic information file along
+                     with a ROM image (s flag).
+                   .SECTION without a specifier is treated as a FREE section.
+                   Optimized directive decoding.
+                   Optimized parser loop.
+                   If .RAMSIZE is not defined a warning is issued instead
+                     of an error.
+                   Added SWAP to .INCBIN.
+                   Verbose mode shows data usage percentages (per bank
+                     as well).
+                   WLAD (WLA Disassembler) is now included with the WLA
+                     archive.
+
+v4.6 (21-Jun-2000) Enhanced the documentation.
+                   Optimized directive decoding.
+                   "JP (HL)" is now known as "JP HL".
+                   GB-Z80 syntax parser supports now brackets as well.
+                   WLA doesn't crash if the project's main file is missing.
+
+v4.5 (15-Jun-2000) Enhanced the documentation.
+                   Fixed the reintroduced '.INCDIR ""'-bug.
+                   Target file name can now be left away as WLA has now
+                     built in default suffices (.gb, .o and .lib).
+                   Added lib-directory to the archive.
+                   Trying to compile a compact ROM file will give a warning.
+
+v4.4 (09-Jun-2000) Enhanced the documentation.
+                   Fixed "RR A"->"RRCA" and "RL A"->"RLCA" transformations.
+                   "EI" and "RST $x" were followed by a "NOP"!
+                   Hexadecimal and binary values are supported in
+                     arithmetics.
+                   Optimized number decoding.
+
+v4.3 (03-Jun-2000) Enhanced error messages.
+                   Number decoding routines are now compatible with the
+                     new error messaging system.
+                   Optimized define and macro handling.
+                   Optimized GB-Z80 opcode decoding.
+                   Optimized source file parsing.
+                   Very long (typos?) tokens don't crash WLA anymore.
+                   .INCDIR accepts directory paths which are not terminated
+                     with '/' (or '\' under MSDOS).
+                   Added support for very simple arithmetics.
+                   Fixed "LD HL, SP+x".
+                   Removed "EX HL, (SP)".
+                   Added OVERWRITE to .SECTION (patch tool function).
+                   Added .BACKGROUND (patch tool function).
+                   WLA would crash if the whole project was inside one
+                     file, and if the file was not found.
+                   "=" can be optionally left away from many directives.
+                   Added "JP (HL)".
+
+v4.2 (11-Apr-2000) Enhanced documentation.
+                   Enhanced error messages.
+                   WLA could crash if .REPT wasn't ended with .ENDR.
+                   .MACRO and .REPT are now compatible with the new
+                     error messaging system.
+                   .REPT size is now 2k.
+
+v4.1 (29-Mar-2000) Enhanced documentation.
+                   Enhanced error messages.
+                   Optimized number conversion.
+                   Added ANSI-C -like commenting ("/* ... */").
+
+v4.0 (19-Mar-2000) Optimized data parsing.
+                   Added a much better error messaging system as default.
+                   Added "-f" -option for fast compiling (uses old error
+                     messaging system with few enhancements).
+                   "LDH (x), A" and "LDH A, (x)" support was broken due to a
+                     typo.
+                   WLA accepts now negative values as well.
+                   WLA's flags and usage changed totally! Read about the
+                     changes in the documentation.
+                   Input and output files cannot be the same.
+                   Enhanced the documentation.
+
+v3.0 (20-Feb-2000) Added support for "LDH (x), A", "LDH A, (x)",
+                     "LD (HLI), A", "LD (HL+), A", "LD A, (HLI)",
+                     "LD A, (HL+)", "LD (HLD), A", LD (HL-), A",
+                     "LD A, (HLD)" and "LD A, (HL-)".
+                   WLA filters away unreferenced local lables in
+                     object/library output mode.
+                   MSDOS temporary file directory is now the current
+                     working directory.
+                   Added "-co" -option for compact object file producing.
+                   Added "-cl" -option for compact library file producing.
+                   Enhanced .SECTION logic (syntax changed!).
+                   Added new error messages.
+                   Optimized temporary file usage.
+                   Optimized directive decoding.
+                   Optimized internal pass 2.
+                   Optimized .SECTION handling.
+                   Optimized .DSB and .DSW.
+                   Optimized pass 1.
+                   Optimized .INCLUDE.
+
+v2.9 (16-Feb-2000) Section names with spaces crashed WLA.
+                   Fixed address bound checking in .BANK.
+                   Added more error messages.
+
+v2.8 (15-Feb-2000) Added .EXPORT.
+                   All strings starting with "." are treated as directives.
+                   Directives are not case sensitive any more.
+                   Fixed a broken 0x0D filter (in MSDOS text files).
+                   Source file ending into a comment could crash WLA.
+                   Optimized .INCLUDE.
+                   Libraries can now have references outside.
+                   Amiga object/library files were not compatible with
+                     PC files.
+                   Fixed a bug in object file generator that could crash WLA.
+
+v2.7 (07-Feb-2000) WLA returns 0 when help information is displayed.
+                   WLA returns 1 when execution ended in error. -1 produced
+                     ugly error messages on Amiga computers.
+                   WLA gives now an error when the user tries to produce
+                     a library file which has references to outside.
+                   Amiga version has version string.
+                   Enhanced some error messages.
+                   Enhanced documents.
+
+v2.6 (03-Feb-2000) PC relative reference distances inside sections could be
+                     more than 127 bytes.
+
+v2.5 (29-Jan-2000) Enhanced documents.
+                   Fixed GBC indicator from $C0 to $80.
+
+v2.4 (26-Jan-2000) Fixed a typo "NET NC" to "RET NC".
+                   Enhanced some error messages.
+                   Added .ROMGBC, .ROMDMG and .ROMSGB.
+                   Rewriting memory with equal data doesn't give an error.
+
+v2.3 (23-Jan-2000) Added .SECTION, .ENDS.
+                   Added "-l" -option for library file producing.
+                   Fixed address calculations a little more.
+                   WLA returns -1 when execution ended in error.
+                   Local labels are now local to sections or object file.
+                   Enhanced the documents.
+
+v2.2 (16-Jan-2000) Added .DSW, .DW, .ENUM and .ENDE.
+
+v2.1 (14-Jan-2000) Added $BE (Pocket Voice) to supported cartridge types.
+                   Added "-v" -option for verbose information displaying.
+                   Optimized pass 1.
+                   Fixed possible errors in address calculations.
+
+v2.0 (12-Jan-2000) Enhanced the documents.
+                   Optimized internal pass 2 and directive including.
+                   Fixed overflow check (in .ORG).
+                   Added "-o" -option for object file producing.
+                   Added linker executable "wlalink".
+                   Added .INCDIR.
+
+v1.9 (06-Jan-2000) Optimized .INCBIN, .INCLUDE and internal passes
+                    1 and 2.
+
+v1.8 (23-Dec-1999) Enhanced the documents.
+                   Fixed overflow checker once again. Every bank gained one
+                    byte more (total 16384).
+
+v1.7 (04-Dec-1999) Enhanced the documents.
+                   Added gb_hardware.i.
+                   .INCBIN didn't free buffer memory.
+                   Optimized .INCBIN.
+                   .INCBIN now caches all the files.
+                   Optimized internal passes 1 and 2.
+                   Linux version is optimized for 486.
+
+v1.6 (14-Nov-1999) Enhanced the documents.
+                   Fixed nintendo_logo.i so it works on a real Game Boy.
+                   Fixed complement check calculation to work.
+                   Overflow checker thought GB ROM banks were 8KB each!
+                    Fixed to 16KB. Ville no baka!
+                   Added .REPT.
+                   Added .ENDR.
+
+v1.5 (10-Jun-1999) Enhanced the documents.
+                   WLA does now one pass to the input data and
+                    two passes to the internal data.
+
+v1.4 (25-May-1999) Renamed nintendo_logo.s to nintendo_logo.i.
+                   Fixed nintendo_logo.i Wzonka-Lad-compatible.
+                   Fixed pass-texts, as WLA does actually one pass,
+                    three of the old ones were made to the WLA's internal data.
+                   Added one funky new optcode, "DEBUG", which will
+                    translate to $ED (unused in GB-Z80). This one will
+                    flash the power light when executed on Wzonka-Lad,
+                    my Game Boy emulator. Use it only for debugging!
+
+v1.3 (01-Jan-1999) Enhanced the documents.
+                   WLA now shows the unused areas of the ROM file after
+                    a successful compile in hexadecimal format.
+                   Many WLA directives accepted non-pure values, not anymore.
+                   Added .DSB.
+                   .DB handles now strings as well.
+
+v1.2 (21-Dec-1998) Enhanced the documents.
+                   Added a list ("gb-z80.txt") of the supported GB-Z80 commands
+                    to the archive.
+                   Free strings don't break the compile loop anymore.
+                   Added .INCBIN.
+
+v1.1 (13-Dec-1998) Enhanced the documents.
+                   Removed an unused function.
+                   Number input now detects and discards numbers from
+                    outside the word boundaries.
+                   WLA now shows the unused areas of the ROM file after
+                    a successful compile.
+                   Added .IFNDEF.
+                   Added .IFDEF.
+                   Added .ELSE.
+                   Added .ENDIF.
+                   Added @@@ to .MACRO.
+                   .DB accepted values from outside the byte boundaries.
+
+v1.0 (12-Dec-1998) The first public release.
+
+
+
+------------------------------------------------------------------------------
+3... WLAB History
+------------------------------------------------------------------------------
+
+
+v1.1 (04-Sep-2000) Uses now WLA v6.3+ syntax (introduced commas).
+                   Accepts now files bigger than 64KB.
+
+v1.0 (23-Aug-2000) The first public release.
+
+
+
+------------------------------------------------------------------------------
+4... WLAD History
+------------------------------------------------------------------------------
+
+
+v1.3 (21-Oct-2000) String detection works better.
+
+v1.2 (01-Sep-2000) SLOT numbers are handled correctly.
+                   Uses ROMBANKS instead of ROMSIZE.
+                   String detection works better.
+
+v1.1 (23-Aug-2000) Added flag 'a' to disable address output.
+
+v1.0 (10-Jul-2000) The first public release.
+
+
+
+------------------------------------------------------------------------------
+5... WLALINK History
+------------------------------------------------------------------------------
+
+
+v4.9 (28-Apr-2002) When computing SMS ROM checksum WLALINK now writes
+                     $4C to $7FFF (32KB checksum, and SMS export).
+                   8bit label references are now allowed (zero page labels).
+
+v4.8 (22-Jan-2002) Added support for yet another un-named label (__).
+
+v4.7 (22-Dec-2001) Added support for un-named labels (-, --, +, ++, ...).
+
+v4.6 (31-Aug-2001) It's possible to make value definitions inside the
+                     linkfile.
+
+v4.5 (16-Jul-2001) WLALINK wrote SNES ROM info byte into $FFD5 regardless
+                     of the ROM mode.
+                   Added XOR-operator (~) support to computations.
+                   Added support for RAM sections.
+
+v4.4 (30-Jun-2001) For example a reference to ":label_01" will give the
+                     label_01's bank number instead of its address.
+                   Linkfile's library loader supports now BASE (works
+                     like WLA's .BASE).
+                   Linkfile parser supports now hexadecimal values.
+                   Added support for 16bit relative references.
+
+v4.3 (19-May-2001) Optimized FREE and SEMIFREE section placing.
+                   Optimized section data inserting.
+                   Supported object file format is now "WLAD" and library
+                     file format is "WLAQ".
+                   Thanks to WLA simplifications, WLALINK code also
+                     experienced small simplifications.
+                   OVERWRITE and FORCE sections which overflow from the ROM
+                     file don't crash WLALINK any more.
+                   Added flag 'd' for unreferenced section discarding.
+
+v4.2 (10-May-2001) Memory overwrite error messages could crash WLALINK
+                     (supplied a bad object pointer to message routine).
+
+v4.1 (05-May-2001) A bug was introduced in memory overwrite check
+                     optimizations, FREE sections could be written on top
+                     of each other.
+
+v4.0 (22-Apr-2001) WLALINK doesn't crash anymore when a modulo/division
+                     by zero happens in the stack calculator routines.
+                   Added support for 24bit references.
+                   Enhanced error messages.
+
+v3.9 (12-Apr-2001) Updated few structures to satisfy the internal changes in
+                     the latest WLA.
+                   If a FORCE section matches the underlying, written data
+                     (other FORCE sections) completely, no error is issued.
+                   Added support for unique SECTIONs.
+
+v3.8 (02-Feb-2001) Supported object file format is now "WLAB" for non
+                     GB-Z80 systems (adds checksum computing).
+                   Due to a typo the bank number of the pending calculation
+                     could get corrupted in object file parsing.
+
+v3.7 (08-Oct-2000) Added support for 6510.
+
+v3.6 (07-Oct-2000) Added support for 65816 (24bit values).
+
+v3.5 (24-Sep-2000) Added support for program file output (!GB, flag b).
+                   NO$GMB symbol files can also be written (!GB).
+                   Fxied few byte size checks.
+                   Header and footer sizes are now shown in the verbose
+                     mode's result information.                   
+
+v3.4 (09-Sep-2000) Label duplicate checker didn't handle local labels
+                     correctly.
+                   Added support for modulo in calculations.
+                   Added support for SEMIFREE sections.
+                   Computations are now computed internally with higher
+                     precision when possible and the result is converted to
+                     an integer.
+
+v3.3 (04-Sep-2000) Enhanced error messages.
+                   Added support for powers and shifts in calculations.
+                   Added support for special ROM bank header sections.
+                   Labels' slot and bank numbers inside library files could
+                     get corrupted.
+                   Optimized label handling.
+
+v3.2 (31-Aug-2000) The supported file formats are only "WLAP", "WLA9" (GB-Z80)
+                     and "WLAA" (Z80).
+                   Added a fully functional stack calculator engine.
+                   Objects with different ROM sizes can be combined, and the
+                     result will use the biggest ROM size found as long as
+                     the sizes of the ROM banks match.
+                   Optimized file parsers.
+                   Enhanced error messages.
+
+v3.1 (26-Aug-2000) The supported file formats are only "WLAO", "WLA7" (GB-Z80)
+                     and "WLA8" (Z80).
+                   Exported definitions were handled incorrectly.
+                   Memory overwrite warnings were displayed when fixing
+                     relative addresses.
+
+v3.0 (23-Aug-2000) The supported file formats are only "WLAO", "WLA5" (GB-Z80)
+                     and "WLA6" (Z80).
+                   Rewrote 30% of the code.
+                   WLALINK arguments changed!
+                   WLALINK needs now a linkfile.
+
+v2.0 (09-Jul-2000) WLALINK outputs now NO$GMB symbolic information 
+                     files along with a ROM image (flag s).
+                   Verbose mode shows data usage percentages (per bank
+                     as well).
+
+v1.9 (25-May-2000) Added support for WLA v4.3's .SECTION OVERWRITE.
+
+v1.8 (20-Feb-2000) The supported file formats are only "WLAN" and "WLA4".
+                   WLALINK uses now less memory.
+                   Enhanced some error messages.
+
+v1.7 (15-Feb-2000) Added support for WLA's .EXPORT.
+                   Enhanced some error messages.
+                   Optimized ROM file generation.
+                   The supported file formats are only "WLAM" and "WLA3".
+                   Amiga object/library files were not compatible with
+                     PC files.
+
+v1.6 (07-Feb-2000) WLALINK returns 0 when help information is displayed.
+                   Amiga version has version string.
+
+v1.5 (03-Feb-2000) PC relative reference distances inside sections could be
+                     more than 127 bytes.
+                   Enhanced some error messages.
+
+v1.4 (31-Jan-2000) Duplicate labels positioned in different places in Game
+                     Boy memory map break the linking loop.
+                   Fixed object identifier, verbose mode screwed up the names.
+                   Enhanced some error messages.
+                   Referencing to a label inside a section more than once
+                     screwed up the label's address.
+
+v1.3 (26-Jan-2000) Rewriting memory with equal data doesn't give an error.
+                   Enhanced some error messages.
+
+v1.2 (23-Jan-2000) Added support for library files.
+
+v1.1 (14-Jan-2000) Added support for Pocket Voice.
+                   Added "-v" -option for verbose information displaying.
+                   WLALINK now checks the object file formats.
+
+v1.0 (12-Jan-2000) The first public release.
+
+
+
+------------------------------------------------------------------------------
+6... Assembler Directives
+------------------------------------------------------------------------------
+
+
+Here's the order in which the data is placed into the output:
+
+1. Data and group 3 directives outside sections.
+2. Group 2 directives.
+3. Data and group 3 directives inside sections.
+4. Group 1 directives.
+
+
+Here are the supported directives (with examples) in WLA:
+
+[ALL] - All, GB-Z80, Z80, 6502, 65C02, 6510, 65816, HUC6280 and SPC-700
+        versions apply.
+[GB ] - Only the GB-Z80 version applies.
+[GB8] - Only the GB-Z80 and 65816 versions apply.
+[Z80] - Only the Z80 version applies.
+[658] - Only the 65816 version applies.
+[SPC] - Only the SPC-700 version applies.
+[65x] - Only the 6502, 65C02, 6510, 65816 and HUC6280 versions apply.
+[!GB] - Only the Z80, 6502, 65C02, 6510, 65816, HUC6280 and SPC-700
+        versions apply.
+
+
+Group 1:
+
+[GB ] .COMPUTECHECKSUM
+[Z80] .COMPUTESMSCHECKSUM
+[Z80] .SDSCTAG 1.0, "DUNGEON MAN", "A wild dungeon exploration game", "Ville Helin"
+[Z80] .SMSTAG
+
+Group 2:
+
+[GB ] .CARTRIDGETYPE 1
+[GB ] .COMPUTECOMPLEMENTCHECK
+[ALL] .EMPTYFILL $C9
+[ALL] .EXPORT work_x
+[658] .FASTROM
+[658] .HIROM
+[GB ] .LICENSEECODENEW "1A"
+[GB ] .LICENSEECODEOLD $1A
+[658] .LOROM
+[GB8] .NAME "NAME OF THE ROM"
+[ALL] .OUTNAME "other.o"
+[GB ] .RAMSIZE 0
+[GB ] .ROMDMG
+[GB ] .ROMGBC
+[GB ] .ROMSGB
+[658] .SLOWROM
+
+Group 3:
+
+[65x] .16BIT
+[658] .24BIT
+[65x] .8BIT
+[ALL] .ASM
+[ALL] .BACKGROUND "parallax.gb"
+[ALL] .BANK 0 SLOT 1
+[658] .BASE $80
+[ALL] .ROMBANKSIZE $4000
+[ALL] .DB 100, $30, %1000, "HELLO WORLD!"
+[ALL] .DBCOS 0.2, 10, 3.2, 120, 1.3
+[ALL] .DBSIN 0.2, 10, 3.2, 120, 1.3
+[ALL] .DEFINE IF $FF0F
+[ALL] .DSB 256 $10
+[ALL] .DSW 128 20
+[ALL] .DW 16000, 10, 255
+[ALL] .DWCOS 0.2, 10, 3.2, 1024, 1.3
+[ALL] .DWSIN 0.2, 10, 3.2, 1024, 1.3
+[ALL] .ELSE
+[ALL] .ENDASM
+[ALL] .ENDE
+[ALL] .ENDIF
+[ALL] .ENDM 
+[ALL] .ENDME
+[ALL] .ENDR
+[ALL] .ENDRO
+[ALL] .ENDS
+[ALL] .ENDST
+[ALL] .ENUM $C000 
+[ALL] .FAIL
+[ALL] .IF DEBUG == 2
+[ALL] .IFDEF IF
+[ALL] .IFDEFM \2
+[ALL] .IFEQ DEBUG 2
+[ALL] .IFEXISTS "main.s"
+[ALL] .IFGR DEBUG 2
+[ALL] .IFGREQ DEBUG 1
+[ALL] .IFLE DEBUG 2
+[ALL] .IFLEEQ DEBUG 1
+[ALL] .IFNDEF IF
+[ALL] .IFNDEFM \2
+[ALL] .IFNEQ DEBUG 2
+[ALL] .INCBIN "sorority.bin"
+[ALL] .INCDIR "/usr/programming/gb/include/"
+[ALL] .INCLUDE "cgb_hardware.i"
+[ALL] .INPUT NAME
+[ALL] .MACRO TEST
+[ALL] .MEMORYMAP
+[ALL] .ORG $150
+[ALL] .ORGA $150
+[ALL] .PRINTT "Here we are...\n"
+[ALL] .PRINTV DEC DEBUG+1
+[ALL] .RAMSECTION "Vars" BANK 0 SLOT 1
+[ALL] .REDEFINE IF $F
+[ALL] .REPT 6
+[ALL] .ROMBANKMAP
+[ALL] .ROMBANKS 2
+[ALL] .SECTION "Init" FORCE
+[ALL] .STRUCT enemy_object
+[ALL] .UNDEF DEBUG
+
+
+Descriptions:
+
+-----
+.8BIT
+-----
+
+There are a few mnemonics that look identical, but take different sized
+arguments. Here's a list of such 6502 mnemonics:
+
+ADC, AND, ASL, BIT, CMP, CPX, CPY, DEC, EOR, INC, LDA, LDX, LDY, ORA, ROL,
+SBC, STA, STX and STY.
+
+For example:
+
+LSR 11       ; $46 $0B
+LSR $A000    ; $4E $00 $A0
+
+The first one could also be
+
+LSR 11       ; $4E $0B $00
+
+.8BIT is here to help WLA to decide to choose which one of the opcodes it
+selects. When you give .8BIT (default) no 8bit address/value is expanded
+to 16bits.
+
+By default WLA uses the smallest possible size. This is true also when WLA
+finds a computation it can't solve right away. WLA assumes the result will
+be inside the smallest possible bounds, which depends on the type of the
+mnemonic.
+
+You can also use the fixed argument size versions of such mnemonics by
+supplying the size with the mnemonic itself or giving it with the
+operand. Here are few examples:
+
+LSR.B 11     ; $46 $0B
+LSR.W 11     ; $46 $0B $00
+LSR   11.B   ; $46 $0B
+LSR   11.W   ; $46 $0B $00
+
+It is recommended to give the operand size hint with the operand itself
+(eg. LSR 11.B) instead of descriptive mnemonics (eg. LSR.B and LSR.W)
+or these three size defining directives (.8BIT, .16BIT and .24BIT).
+
+This is not a compulsory directive.
+
+------
+.16BIT
+------
+
+Analogous to .8BIT. .16BIT forces all addresses and values to be expanded
+into 16bit range, when possible, that is.
+
+LSR 11       ; $46 $0B
+
+that would be the case, normally, but after .16BIT it becomes
+
+LSR 11       ; $4E $0B $00
+
+This is not a compulsory directive.
+
+------
+.24BIT
+------
+
+Analogous to .8BIT and .16BIT. .24BIT forces all addresses to
+be expanded into 24bit range, when possible, that is.
+
+AND $11       ; $25 $11
+
+that would be the case, normally, but after .24BIT it becomes
+
+AND $11       ; $2F $11 $00 $00
+
+If it is not possible to expand the address into .24BIT range,
+then WLA tries to expand it into 16bit range.
+
+This is not a compulsory directive.
+
+----
+.ASM
+----
+
+Tells WLA to start assembling. Use .ASM to continue the work which has been
+disabled with .ENDASM. .ASM and .ENDASM can be used to mask away big blocks
+of code. This is analogous to the ANSI C -comments (/*...*/), but .ASM and
+.ENDASM can be nested, unlike the ANSI C -counterpart.
+
+This is not a compulsory directive.
+
+-------
+.ENDASM
+-------
+
+Tells WLA to stop assembling. Use .ASM to continue the work.
+
+This is not a compulsory directive.
+
+-----------------------------
+.DBCOS 0.2, 10, 3.2, 120, 1.3
+-----------------------------
+
+Defines bytes just like .DSB does, only this time they are filled with
+cosine data. .DBCOS takes five arguments.
+
+The first argument is the starting angle. Angle value ranges from 0 to
+359.999..., but you can supply WLA with values that are out of the range -
+WLA fixes them ok. The value can be integer or float.
+
+The second one descibes the amount of additional angles. The example
+will define 11 angles.
+
+The third one is the adder value which is added to the angle value when
+next angle is calculated. The value can be integer or float.
+
+The fourth and fifth ones can be seen from the pseudo code below, which
+also describes how .DBCOS works. The values can be integer or float.
+
+Remember that cos (and sin) here returns values ranging from -1 to 1.
+
+.DBCOS A, B, C, D, E
+
+for (B++, B > 0; B--) {
+  output_data((D * cos(A)) + E)
+  A = keep_in_range(A + C)
+}
+
+This is not a compulsory directive.
+
+-----------------------------
+.DBSIN 0.2, 10, 3.2, 120, 1.3
+-----------------------------
+
+Analogous to .DBCOS, but does sin() instead of cos().
+
+This is not a compulsory directive.
+
+------------------------------
+.DWCOS 0.2, 10, 3.2, 1024, 1.3
+------------------------------
+
+Analogous to .DBCOS (but defines words).
+
+This is not a compulsory directive.
+
+------------------------------
+.DWSIN 0.2, 10, 3.2, 1024, 1.3
+------------------------------
+
+Analogous to .DBCOS (but defines words and does sin() instead of cos()).
+
+This is not a compulsory directive.
+
+-----------------------
+.NAME "NAME OF THE ROM"
+-----------------------
+
+If .NAME is used with WLA-GB then the 16 bytes ranging from $0134
+to $0143 are filled with the provided string. WLA-65816 fills
+the 21 bytes from $FFC0 to $FFD4 in HiROM- and from $7FC0 to $7FD4
+in LoROM-mode with the name string (SNES ROM title).
+
+If the string is shorter than 16/21 bytes the remaining space is
+filled with $00.
+
+This is not a compulsory directive.
+
+-----------
+.ROMBANKS 2
+-----------
+
+Indicates the size of the ROM in rombanks. This value is converted to a
+standard GB ROM size indicator value found at $148 in a GB ROM, and there
+this one is put into.
+
+This is a compulsory directive unless .ROMBANKMAP is defined.
+
+You can redefine .ROMBANKS as many times as you wish as long as
+the old and the new ROM bank maps match as much as possible. This
+way you can enlarge the size of the project on the fly.
+
+----------
+.RAMSIZE 0
+----------
+
+Indicates the size of the RAM. This is a standard GB RAM size indicator value
+found at $149 in a GB ROM, and there this one is put to also.
+
+This is not a compulsory directive.
+
+--------------
+.EMPTYFILL $C9
+--------------
+
+This byte is used in filling the unused areas of the ROM file. EMPTYFILL
+defaults to $00.
+
+This is not a compulsory directive.
+
+----------------
+.CARTRIDGETYPE 1
+----------------
+
+Indicates the type of the cartridge (mapper and so on). This is a standard
+GB cartridge type indicator value found at $147 in a GB ROM, and there this
+one is put to also.
+
+This is not a compulsory directive.
+
+--------------------
+.LICENSEECODEOLD $1A
+--------------------
+
+This is a standard old licensee code found at $14B in a GB ROM, and there this
+one is put to also. .LICENSEECODEOLD cannot be defined with .LICENSEECODENEW.
+
+This is not a compulsory directive.
+
+---------------------
+.LICENSEECODENEW "1A"
+---------------------
+
+This is a standard new licensee code found at $144 and $145 in a GB ROM, and
+there this one is put to also. .LICENSEECODENEW cannot be defined with
+.LICENSEECODEOLD. $33 is inserted into $14B, as well.
+
+This is not a compulsory directive.
+
+----------------
+.COMPUTECHECKSUM
+----------------
+
+When this directive is used WLA computes the ROM checksum found at $14E and
+$14F in a GB ROM. Note that this directive can only be used with wla-gb.
+
+This is not a compulsory directive.
+
+-------------------
+.COMPUTESMSCHECKSUM
+-------------------
+
+When this directive is used WLA computes the ROM checksum found at $7FFA and
+$7FFB in a SMS/GG ROM. Note that this directive can only be used with wla-z80.
+Also note that the ROM size must be at least 32KB. Data beyond 256KB limit
+is not taken into account when calculating the SMS checksum, which should
+be the right way to do it.
+
+This is not a compulsory directive.
+
+-------
+.SMSTAG
+-------
+
+.SMSTAG forces WLA to write an ordinary SMS/GG ROM tag to the ROM file.
+Currently only the string "TMR SEGA" and ROM checksum are written
+(meaning that .SMSTAG also defines .COMPUTESMSCHECKSUM).
+
+This is not a compulsory directive.
+
+-----------------------------------------------------------------------------
+.SDSCTAG 1.0, "DUNGEON MAN", "A wild dungeon exploration game", "Ville Helin"
+-----------------------------------------------------------------------------
+
+.SDSCTAG adds SDSC tag to your SMS/GG ROM file. The ROM size must be at least
+32KB just like with .COMPUTESMSCHECKSUM and .SMSTAG, as the data goes into
+$7FE0-$7FEF of the ROM. For more information about this header take a look
+at http://www.smspower.org/dev/sdsc/. Here's an explanation of the arguments:
+
+.SDSCTAG {version number}, {program name}, {program release notes}, {program author}
+
+Note that program name, release notes and program author can also be pointers
+to strings instead of being only strings (which WLA terminates with zero, and
+places them into suitable locations inside the ROM file). So
+
+.SDSCTAG 0.8, PRGNAME, PRGNOTES, PRGAUTHOR
+...
+PRGNAME:  .DB "DUNGEON MAN", 0
+PRGNOTES: .DB "A wild and totally crazy dungeon exploration game", 0
+PRGAUTHOR:.DB "Ville Helin", 0
+
+works also. All strings supplied explicitly to .SDSCTAG are placed somewhere
+in .BANK 0 SLOT 0.
+
+.SDSCTAG 1.0, "", "", ""
+.SDSCTAG 1.0, 0, 0, 0
+
+are also valid, here 0 and "" mean the user doesn't want to use any descriptive
+strings. Version number can also be given as an integer, but then the minor
+version number defaults to zero.
+
+.SDSCTAG also defines .SMSTAG (as it's part of the SDSC ROM tag specification).
+
+This is not a compulsory directive.
+
+-----------------------
+.COMPUTECOMPLEMENTCHECK
+-----------------------
+
+When this directive is used WLA computes the ROM complement check found at
+$14D in a GB ROM.
+
+This is not a compulsory directive, but very recommended. ;)
+
+--------------------------------------
+.INCDIR "/usr/programming/gb/include/"    
+--------------------------------------
+
+Changes the current include root directory. Use this to specify main
+directory for the following .INCLUDE and .INCBIN directives.
+If you want to change to the current working directory (WLA also defaults
+to this), use
+
+.INCDIR ""
+
+This is not a compulsory directive.
+
+-------------------------
+.INCLUDE "cgb_hardware.i"
+-------------------------
+
+Includes the specified file to the source file. If the file's not found
+in the .INCDIR directory, WLA tries to find it in the current working
+directory.
+
+This is not a compulsory directive.
+
+----------------------
+.INCBIN "sorority.bin"
+----------------------
+
+Includes the specified data file into the source file. .INCBIN caches
+all files into memory, so you can .INCBIN any data file millions of
+times, but it is loaded from hard drive only once.
+
+You can optionally use SWAP after the file name, e.g.
+
+.INCBIN "kitten.bin" SWAP
+
+.INCBIN data is divided into blocks of two bytes, and inside every block
+the bytes are exchanged (like "SWAP r" does to nibbles). This requires that
+the size of the file is even.
+
+You can also force WLA to skip n bytes from the beginning of the file
+by writing for example:
+
+.INCBIN "kitten.bin" SKIP 4
+
+Four bytes are skipped from the beginning of kitten.bin and the rest
+is incbinned.
+
+It is also possible to incbin only n bytes from a file:
+
+.INCBIN "kitten.bin" READ 10
+
+Will read ten bytes from kitten.bin's beginning.
+
+You can also combine all these three commands:
+
+.INCBIN "kitten.bin" SKIP 10 READ 8 SWAP
+
+This example shows how to incbin eight bytes (swapped) after skipping
+10 bytes from the beginning of file "kitten.bin". Note that the
+order of the extra commands is important.
+
+If the file's not found in the .INCDIR directory, WLA tries to find it
+in the current working directory.
+
+This is not a compulsory directive.
+
+-----------
+.INPUT NAME
+-----------
+
+.INPUT is much like any Basic-language input: .INPUT asks the user
+for a value or string. After .INPUT is the variable name used to store
+the data.
+
+.INPUT works like .REDEFINE, but the user gets to type in the data.
+
+Here are few examples how to use input:
+
+.PRINTT "The name of the ROM? "
+.INPUT NAME
+.NAME NAME
+
+...
+
+.PRINTT "Give the .DB amount.\n"
+.INPUT S
+.PRINTT "Give .DB data one at a time.\n"
+.REPT S
+  .INPUT B
+  .DB B
+.ENDR
+
+...
+
+This is not a compulsory directive.
+
+-------------------------
+.BACKGROUND "parallax.gb"
+-------------------------
+
+This chooses an existing ROM image (parallax.gb in this case) as a
+background data for project. You can overwrite the data with OVERWRITE
+sections only. With .BACKGROUND defined you can leave away .ROMSIZE,
+.ROMTYPE and .RAMTYPE. .BACKGROUND can be used only when compiling
+a ROM image, not library or object file.
+
+.BACKGROUND is useful if you wish to patch an existing ROM image with
+new code or data.
+
+This is not a compulsory directive.
+
+-----
+.FAIL
+-----
+
+Terminates the compiling process.
+
+This is not a compulsory directive.
+
+-----------
+.MACRO TEST
+-----------
+
+Begins a macro called 'TEST'.
+
+You can use '\@' inside a macro to eg. separate a label from the other
+macro 'TEST' occurrences. '\@' is replaced with an integer number
+indicating the amount of times the macro has been called previously so
+it is unique to every macro call. '\@' can also be used inside strings
+inside a macro or just as a plain value. Look at the following examples
+for more information.
+
+Also, if you want to use macro arguments in eg. calculation, you can
+type '\X' where X is the number of the argument. X ranges from 1 to
+256 as you can give maximum of 256 parameters to a macro.
+
+Remember to use .ENDM to finish the macro definition. Note that you
+cannot use .INCLUDE inside a macro.
+
+You can call macros from inside a macro. Note that the preprocessor
+does not expand the macros. WLA traverses through the code according to
+the macro calls, so macros really define a very simple programming
+language. Also note that you cannot pass macro arguments (eg '\1')
+directly to another macro call, you must use a temporary definition
+to pass on the value.
+
+
+Here are some examples:
+
+.MACRO NOPMONSTER
+       .REPT 32         ; evil...
+       NOP
+       .ENDR
+.ENDM
+
+.MACRO LOAD_ABCD
+       LD A, \1
+       LD B, \2
+       LD C, \3
+       LD D, \4
+       NOPMONSTER
+       LD HL, 1<<\1
+.INCBIN \5
+.ENDM
+
+.MACRO QUEEN
+
+QUEEN\@:
+	LD   A, \1
+	LD   B, \1
+	CALL QUEEN\@
+
+	.DB  "\@", 0     ; will translate into a zero terminated string
+                         ; holding the amount of macro QUEEN calls.
+        .DB  "\\@", 0    ; will translate into a string containing
+                         ; \@.
+        .DB  \@          ; will translate into a number indicating
+                         ; the amount of macro QUEEN calls.
+
+.ENDM
+
+And here's how they can be used:
+
+NOPMONSTER
+LOAD_ABCD $10, $20, $30, XYZ, "merman.bin"
+QUEEN 123
+
+Note that you must separate the arguments with commas.
+
+Every time a macro is called a definition NARGS is created. It shows
+only inside the macro and holds the amount of arguments the macro
+was called with. So don't have your own definition called NARGS.
+Here's an example:
+
+.MACRO LUPIN
+  .IF NARGS != 1
+    .FAIL
+  .ENDIF
+
+  .PRINTT "Totsan! Ogenki ka?\n"
+.ENDM
+
+This is not a compulsory directive.
+
+-----
+.ENDM
+-----
+
+Ends the macro.
+
+This is not a compulsory directive, but when .MACRO is used this one is
+required to terminate it.
+
+--------
+.FASTROM
+--------
+
+Sets the ROM memory speed bit in $FFD5 to indicate that the SNES ROM
+chips are 120ns chips.
+
+This is not a compulsory directive.
+
+--------
+.SLOWROM
+--------
+
+Clears the ROM memory speed bit in $FFD5 to indicate that the SNES ROM
+chips are 200ns chips.
+
+This is not a compulsory directive.
+
+------
+.HIROM
+------
+
+With this directive you can define the SNES ROM mode to be HiROM.
+
+.HIROM also sets the ROM mode bit in $FFD5.
+
+This is not a compulsory directive.
+
+------
+.LOROM
+------
+
+With this directive you can define the SNES ROM mode to be LoROM.
+
+WLA defaults to .LOROM.
+
+This is not a compulsory directive.
+
+---------
+.BASE $80
+---------
+
+Defines the base value for the 65816 CPU bank number (used only in 24bit
+addresses). Here are few examples of how to use .BASE (both examples assume
+the label resides in the first ROM bank):
+
+.BASE $00
+  JSL label    ; if label address is $1234, this will assemble into
+               ; JSL $001234
+.BASE $80
+  JSL label    ; again, label is $1234, but this time the result will be
+               ; JSL $801234
+
+.BASE defaults to $00.
+
+Use .LOROM or .HIROM to define the ROM mode. Note that the address
+of the label will also contribute to the 65816 CPU bank number (CPU
+bank number == .BASE + CPU ROM bank of the label).
+
+This is not a compulsory directive.
+
+--------------
+.BANK 0 SLOT 1
+--------------
+
+Defines the ROM bank and the slot it is inserted into in the memory. You
+can also type the following:
+
+.BANK 0
+
+This tells WLA to move into BANK 0 which will be put into the DEFAULTSLOT
+of .MEMORYMAP.
+
+This is a compulsory directive.
+
+------------------
+.ROMBANKSIZE $4000
+------------------
+
+Defines the ROM bank size. Old syntax is ".BANKSIZE x".
+
+This is a compulsory directive unless .ROMBANKMAP is defined.
+
+---------
+.ORG $150
+---------
+
+Defines the starting address. The value supplied here is relative to the
+ROM bank given with .BANK.
+
+This is a compulsory directive.
+
+----------
+.ORGA $150
+----------
+
+Defines the starting address. The value supplied here is absolute and used
+directly in address computations. WLA computes the right position in
+ROM file. By using .ORGA you can instantly see from the source file where the
+following code is located in the 16bit memory.
+
+Here's an example:
+
+.MEMORYMAP
+SLOTSIZE $4000
+DEFAULTSLOT 0
+SLOT 0 $0000
+SLOT 1 $4000
+.ENDME
+
+.ROMBANKMAP
+BANKSTOTAL 2
+BANKSIZE $4000
+BANKS 2
+.ENDRO
+
+.BANK 0 SLOT 1
+.ORGA $4000
+
+MAIN:	JP	MAIN
+
+Here "MAIN" is at $0000 in the ROM file, but the address for "MAIN"
+is $4000.
+
+This is a compulsory directive.
+
+------------
+.DSB 256 $10
+------------
+
+Defines 256 bytes of $10.
+
+This is not a compulsory directive.
+
+-----------
+.DSW 128 20
+-----------
+
+Defines 128 words (two bytes) of 20.
+
+This is not a compulsory directive.
+
+-----------------------------------
+.DB 100, $30, %1000, "HELLO WORLD!"
+-----------------------------------
+
+Defines bytes.
+
+This is not a compulsory directive.
+
+------------------
+.DW 16000, 10, 255
+------------------
+
+Defines words (two bytes each). .DW takes only numbers and
+characters as input, not strings.
+
+This is not a compulsory directive.
+
+----------------
+.DEFINE IF $FF0F
+----------------
+
+Assigns a number or a string to a definition label.
+
+By default all defines are local to the file where they are
+presented. If you want to make the definition visible to all the
+files in the project, use .EXPORT.
+
+Here are some examples:
+
+.DEFINE X 1000
+.DEFINE FILE "level01.bin"
+.DEFINE TXT1 "hello and welcome", 1, "to a new world...", 0
+.DEFINE BYTES 1, 2, 3, 4, 5
+
+All definitions with multiple values are marked as data strings,
+and .DB is about the only place where you can later on use them.
+
+.DEFINE BYTES 1, 2, 3, 4, 5
+.DB 0, BYTES, 6
+
+is the same as
+
+.DB 0, 1, 2, 3, 4, 5, 6
+
+Note that you must do your definition before you use it, otherwise
+WLA uses final value of the definition. Here's an example of this:
+
+.DEFINE AAA 10
+.DB AAA            ; will be 10.
+.REDEFINE AAA 11
+
+but
+
+.DB AAA            ; will be 11.
+.DEFINE AAA 10
+.REDEFINE AAA 11
+
+You can also create definitions on the command line. Here's an
+example of this:
+
+wla-gb -vl -DMOON -DNAME=john -DPRICE=100 -DADDRESS=$100 math.s
+
+MOON's value will be 0, NAME is a string definition with value "john",
+PRICE's value will be 100, and ADDRESS's value will be $100.
+
+This is not a compulsory directive.
+
+----------------
+.REDEFINE IF $0F
+----------------
+
+Assigns a new value or a string to an old definition. If the
+definition doesn't exist, REDEFINE performs DEFINE's work.
+
+When used with .REPT REDEFINE helps creating tables:
+
+.DEFINE CNT 0
+
+.REPT 256
+.DB CNT
+.REDEFINE CNT CNT+1
+.ENDR
+
+This is not a compulsory directive.
+
+--------------
+.IF DEBUG == 2
+--------------
+
+If the condition is fulfilled the following piece of code is
+acknowledged until .ENDIF/.ELSE occurs in the text, otherwise
+it is skipped. Operands must be immediate values.
+
+The following operators are supported:
+<  - smaller than
+<= - smaller or equal to
+>  - greater than
+>= - greater or equal to
+== - equals to
+!= - doesn't equal to
+
+All IF (yes, including .IFDEF, .IFNDEF, etc) directives can be
+nested.
+
+This is not a compulsory directive.
+
+---------
+.IFDEF IF
+---------
+
+If "IF" is defined, then the following piece of code is acknowledged
+until .ENDIF/.ELSE occurs in the text, otherwise it is skipped.
+
+This is not a compulsory directive.
+
+------------------
+.IFEXISTS "main.s"
+------------------
+
+If "main.s" file can be found, then the following piece of code is
+acknowledged until .ENDIF/.LESE occurs in the text, otherwise it is
+skipped.
+
+By writing the following few lines you can include a file if it exists
+without breaking the compiling loop if it doesn't exist.
+
+.IFEXISTS FILE
+.INCLUDE FILE
+.ENDIF
+
+This is not a compulsory directive.
+
+------------
+.UNDEF DEBUG
+------------
+
+Removes the supplied definition label from system. If there is no
+such label as given no error is displayed as the result would be the
+same.
+
+You can undefine as many definitions as you wish with one .UNDEF:
+
+.UNDEF NUMBER, NAME, ADDRESS, COUNTRY
+.UNDEF NAME, AGE
+
+This is not a compulsory directive.
+
+----------
+.IFNDEF IF
+----------
+
+If "IF" is not defined, then the following piece of code is acknowledged
+until .ENDIF/.ELSE occurs in the text, otherwise it is skipped.
+
+This is not a compulsory directive.
+
+----------
+.IFDEFM \2
+----------
+
+If the specified argument is defined (argument number two, in the example),
+then the following piece of code is acknowledged until .ENDIF/.ELSE occurs
+in the macro, otherwise it is skipped.
+
+This is not a compulsory directive. .IFDEFM works only inside a macro.
+
+-----------
+.IFNDEFM \2
+-----------
+
+If the specified argument is not defined, then the following piece of
+code is acknowledged until .ENDIF/.ELSE occurs in the macro, otherwise
+it is skipped.
+
+This is not a compulsory directive. .IFNDEFM works only inside a macro.
+
+-------------
+.IFEQ DEBUG 2
+-------------
+
+If the value of DEBUG equals to 2, then the following piece of code is
+acknowledged until .ENDIF/.ELSE occurs in the text, otherwise it is skipped.
+Both arguments can be computations, defines or immediate values.
+
+This is not a compulsory directive.
+
+--------------
+.IFNEQ DEBUG 2
+--------------
+
+If the value of DEBUG doesn't equal to 2, then the following piece of
+code is acknowledged until .ENDIF/.ELSE occurs in the text, otherwise it is
+skipped. Both arguments can be computations, defines or immediate
+values.
+
+This is not a compulsory directive.
+
+-------------
+.IFLE DEBUG 2
+-------------
+
+If the value of DEBUG is less than 2, then the following piece of code is
+acknowledged until .ENDIF/.ELSE occurs in the text, otherwise it is skipped.
+Both arguments can be computations, defines or immediate values.
+
+This is not a compulsory directive.
+
+---------------
+.IFLEEQ DEBUG 2
+---------------
+
+If the value of DEBUG is less or equal to 2, then the following piece of code is
+acknowledged until .ENDIF/.ELSE occurs in the text, otherwise it is skipped.
+Both arguments can be computations, defines or immediate values.
+
+This is not a compulsory directive.
+
+-------------
+.IFGR DEBUG 2
+-------------
+
+If the value of DEBUG is greater than 2, then the following piece of code is
+acknowledged until .ENDIF/.ELSE occurs in the text, otherwise it is skipped.
+Both arguments can be computations, defines or immediate values.
+
+This is not a compulsory directive.
+
+---------------
+.IFGREQ DEBUG 2
+---------------
+
+If the value of DEBUG is greater or equal to 2, then the following piece of code is
+acknowledged until .ENDIF/.ELSE occurs in the text, otherwise it is skipped.
+Both arguments can be computations, defines or immediate values.
+
+This is not a compulsory directive.
+
+-----
+.ELSE
+-----
+
+If the previous .IFxxx failed then the following text until
+.ENDIF is acknowledged.
+
+This is not a compulsory directive.
+
+------
+.ENDIF
+------
+
+This terminates any .IFxxx directive.
+
+This is not a compulsory directive, but if you use any .IFxxx then
+you need also to apply this.
+
+-------
+.REPT 6
+-------
+
+Repeats the text enclosed between ".REPT x" and ".ENDR" x times (6 in
+this example). You can use .REPTs inside .REPTs. 'x' must be >= 0.
+
+This is not a compulsory directive.
+
+-----
+.ENDR
+-----
+
+Ends the repetition.
+
+This is not a compulsory directive, but when .REPT is used this one is
+required to terminate it.
+
+-----------
+.ENUM $C000
+-----------
+
+Starts enumeration from $C000. Very useful for defining variables.
+You can also add "EXPORT" after the enumeration starting value
+if you want to export all the generated definitions automatically.
+Here's an example of .ENUM:
+
+...
+.STRUCT mon                ; check out the documentation on
+name ds 2                  ; .STRUCT
+age  db
+.ENDST
+
+.ENUM $A000
+_scroll_x DB               ; db  - define byte
+_scroll_y DB
+player_x: DW               ; dw  - define word
+player_y: DW
+map_01:   DS  16           ; ds  - define size (bytes)
+map_02    DSB 16           ; dsb - define size (bytes)
+map_03    DSW  8           ; dsw - define size (words)
+monster   INSTANCEOF mon 3 ; three instances of structure mon
+dragon    INSTANCEOF mon   ; one mon
+.ENDE
+...
+
+Previous example transforms into following definitions:
+
+.DEFINE _scroll_x      $A000
+.DEFINE _scroll_y      $A001
+.DEFINE player_x       $A002
+.DEFINE player_y       $A004
+.DEFINE map_01         $A006
+.DEFINE map_02         $A016
+.DEFINE map_03         $A026
+.DEFINE monster        $A036
+.DEFINE monster.name   $A036
+.DEFINE monster.age    $A038
+.DEFINE monster.1      $A036
+.DEFINE monster.1.name $A036
+.DEFINE monster.1.age  $A038
+.DEFINE monster.2      $A039
+.DEFINE monster.2.name $A039
+.DEFINE monster.2.age  $A03B
+.DEFINE monster.3      $A03C
+.DEFINE monster.3.name $A03C
+.DEFINE monster.3.age  $A03E
+.DEFINE dragon         $A03F
+.DEFINE dragon.name    $A03F
+.DEFINE dragon.age     $A041
+
+DB, DW, DS, DSB, DSW and INSTANCEOF can also be in lowercase. You
+can also use a dot version of the symbols, but it doesn't advance
+the memory address. Here's an exmple:
+
+.ENUM $C000 EXPORT
+bigapple:  .dw
+bigapple_l db
+bigapple_h db
+.ENDE
+
+And this is what is generated:
+
+.DEFINE bigapple   $C000
+.DEFINE bigapple_l $C000
+.DEFINE bigapple_h $C001
+.EXPORT bigapple, bigapple_l, bigapple_h
+
+This way you can generate a 16bit variable address along with pointers
+to its parts.
+
+If you want more flexible variable positioning, take a look at
+.RAMSECTIONs.
+
+This is not a compulsory directive.
+
+-----
+.ENDE
+-----
+
+Ends the enumeration.
+
+This is not a compulsory directive, but when .ENUM is used this one is
+required to terminate it.
+
+--------------------
+.STRUCT enemy_object
+--------------------
+
+Begins the definition of a structure. These structures can be placed
+inside RAMSECTIONs and ENUMs. Here's an example:
+
+.STRUCT enemy_object
+id    dw               ; the insides of a .STRUCT are 1:1 like in .ENUM
+x     db               ; except that no structs inside structs.
+y     db
+data  ds  10
+info  dsb 16
+stats dsw  4
+.ENDST
+
+This also creates a definition "_sizeof_[struct name]", in our example
+this would be "_sizeof_enemy_object", and the value of this definition
+is the size of the object, in bytes (2+1+1+10+16+4*2 = 38 in the example).
+
+After defining a .STRUCT you can create an instance of it in a .RAMSECTION /
+.ENUM by typing
+
+<instance name> INSTANCEOF <struct name> [optional, amount of structures]
+
+Here's an example:
+
+.RAMSECTION "enemies" BANK 4 SLOT 4
+enemies   INSTANCEOF enemy_object 4
+enemyman  INSTANCEOF enemy_object
+enemyboss INSTANCEOF enemy_object
+.ENDS
+
+This will create labels like "enemies", "enemies.id", "enemies.x", "enemies.y"
+and so on. Label "enemies" is followed by four "enemy_object" structures,
+and only the first one is labeled. After there four come "enemyman" and
+"enemyboss" instances.
+
+Take a look at the documentation on .RAMSECTION & .ENUM, they have more
+examples of how you can use .STRUCTs.
+
+A WORD OF WARNING: Don't use labels b, B, w and W inside a struct as eg.
+WLA sees enemy.b as a byte sized reference to enemy. All other labels should
+be safe.
+
+lda enemy1.b  ; load a byte from zeropage address enemy1 or from the address
+              ; of enemy1.b??? i can't tell you, WLA can't tell you...
+
+This is not a compulsory directive.
+
+------
+.ENDST
+------
+
+Ends the structure definition.
+
+This is not a compulsory directive, but when .STRUCT is used this one is
+required to terminate it.
+
+----------
+.MEMORYMAP
+----------
+
+Begins the memory map definition. Using .MEMORYMAP you must first
+describe the target system's memory architecture to WLA before it
+can start to compile the code. .MEMORYMAP gives you the freedom to
+use WLA Z80/6502/65C02/6510/65816/HUC6280/SPC-700 to compile data
+for numerous different real Z80/6502/65C02/6510/65816/HUC6280/SPC-700
+based systems.
+
+Examples:
+
+.MEMORYMAP
+SLOTSIZE $4000
+DEFAULTSLOT 2
+SLOT 0 $0000
+SLOT 1 $4000
+.ENDME
+
+.MEMORYMAP
+DEFAULTSLOT 1
+SLOTSIZE $6000
+SLOT 0 $0000
+SLOTSIZE $2000
+SLOT 1 $6000
+SLOT 2 $8000
+.ENDME
+
+Here's a real life example from Adam Klotblixt. It should be interesting
+for all the ZX81 coders:
+
+...
+
+.MEMORYMAP
+DEFAULTSLOT 1
+SLOTSIZE $2000
+SLOT 0 $0000
+SLOTSIZE $6000
+SLOT 1 $2000
+.ENDME
+
+.ROMBANKMAP
+BANKSTOTAL 2
+BANKSIZE $2000
+BANKS 1
+BANKSIZE $6000
+BANKS 1
+.ENDRO
+
+.BANK 1 SLOT 1
+.ORGA $2000
+
+...
+
+SLOTSIZE defines the size of the following slots. You can redefine it
+as many times as you wish, like in the second example.
+
+DEFAULTSLOT describes the default slot for banks which aren't explicitly
+inserted anywhere. Check .BANK definition for more information.
+
+SLOT defines a slot and its starting address. SLOT numbering starts at
+0 and ends to 255 so you have 256 slots at your disposal.
+
+This is a compulsory directive, and make sure all the object files share
+the same .MEMORYMAP or you can't link them together.
+
+------
+.ENDME
+------
+
+Ends the memorymap.
+
+This is not a compulsory directive, but when .MEMORYMAP is used this one
+is required to terminate it.
+
+-----------
+.ROMBANKMAP
+-----------
+
+Begins the ROM bank map definition. You can use this directive to
+describe the project's ROM banks. Use .ROMBANKMAP when not all the
+ROM banks are of equal size. Note that you can use .ROMBANKSIZE and
+.ROMBANKS instead of .ROMBANKMAP, but that's only when the ROM banks
+are equal in size. Some systems based on a real Z80 chip,
+6502/65C02/6510/65816/HUC6280/SPC-700 CPUs and Pocket Voice cartridges
+for Game Boy require the usage of this directive.
+
+Examples:
+
+.ROMBANKMAP
+BANKSTOTAL 16
+BANKSIZE $4000
+BANKS 16
+.ENDRO
+
+.ROMBANKMAP
+BANKSTOTAL 510
+BANKSIZE $6000
+BANKS 1
+BANKSIZE $2000
+BANKS 509
+.ENDRO
+
+The first one describes an ordinary ROM image of 16 equal sized
+banks. The second one defines a 4MB Pocket Voice ROM image.
+In the PV ROM image the first bank is $6000 bytes and the remaining
+509 banks are smaller ones, $2000 bytes each.
+
+BANKSTOTAL tells the total amount of ROM banks. It must be
+defined prior to anything else.
+
+BANKSIZE tells the size of the following ROM banks. You can
+supply WLA with BANKSIZE as many times as you wish.
+
+BANKS tells the amount of banks that follow and that are of
+the size BANKSIZE which has been previously defined.
+
+This is not a compulsory directive when .ROMBANKSIZE and
+.ROMBANKS are defined.
+
+You can redefine .ROMBANKMAP as many times as you wish as long as
+the old and the new ROM bank maps match as much as possible. This
+way you can enlarge the size of the project on the fly.
+
+------
+.ENDRO
+------
+
+Ends the rom bank map.
+
+This is not a compulsory directive, but when .ROMBANKMAP is used this
+one is required to terminate it.
+
+---------------------
+.SECTION "Init" FORCE
+---------------------
+
+Section is a continuous area of data which is placed into the output
+file according to the section type and .BANK and .ORG directive
+values.
+
+The example begins a section called "Init". Before a section can be
+declared, .BANK and .ORG must be used unless WLA is in library file
+output mode. Library file's sections must all be FREE ones. .BANK tells
+the bank number where this section will be later relocated into. .ORG
+tells the offset for the relocation from the beginning of .BANK.
+
+You can supply the preferred section size (bytes) inside the section
+name string. Here's an example:
+
+.SECTION "Init_100"
+
+will create a section ("Init") with size of 100 bytes, unless the actual
+data overflows from the section, in which case the section size is
+enlarged to contain all the data. Note that the syntax for explicit
+section size defining is: "NAME_X", where "NAME" is the name of the
+section and "X" is the size (decimal or hexadecimal value). 
+
+Note also that if your section name begins with double underlines (eg.
+"__UNIQUE_SECTION!!!") the section will be unique in the sense that
+when WLALINK recieves files containing sections which share the same
+name, WLALINK will save only the first of them for further processing,
+all others are deleted from memory with corresponding labels, references
+and calculations. This can be very useful...
+
+If a section name begins with an exclamation mark ('!') it tells
+WLALINK to not to drop it, even if you use WLALINK's ability to discard
+all unreferenced sections and there are no references to the section.
+
+FORCE after the name of the section tells WLA that the section _must_ be
+inserted so it starts at .ORG. FORCE can be replaced with FREE which
+means that the section can be inserted somewhere in the defined bank,
+where there is room. You can also use OVERWRITE to insert the section
+into the memory regardless of data collisions. Using OVERWRITE you can
+easily patch an existing ROM image just by .BACKGROUND'ing the data
+and inserting an OVERWRITE section into it. SEMIFREE sections are also
+possible and they behave much like FREE sections. The only difference
+is that they are positioned somewhere in the bank starting from .ORG.
+You can also leave away the type specifier as the default type for the
+section is FREE.
+
+You can name the sections as you wish, but there is one special name.
+A section called "BANKHEADER" is placed in the front of the bank
+where it is defined. These sections contain data that is not in the
+memory map of the machine, so you can't refer to the data of a
+BANKHEADER section, but you can write references to outside. So no
+labels inside BANKHEADER sections. These special sections are useful
+when writing eg. MSX programs. Note that library files don't take
+BANKHEADER sections.
+
+Here's an example of a "BANKHEADER" section:
+
+.BANK 0
+.ORG 0
+.SECTION "BANKHEADER"
+	.DW MAIN
+	.DW VBI
+.ENDS
+
+.SECTION "Program"
+MAIN:	 CALL	monty_on_the_run
+VBI:	 PUSH	HL
+	 ...
+	 POP	HL
+	 RETI
+.ENDS
+
+
+Here's an example of an ordinary section:
+
+.BANK 0
+.ORG $150
+.SECTION "Init" FREE
+        DI
+        LD      SP, $FFFE
+        SUB     A
+        LD      ($FF00+R_IE), A
+.ENDS
+
+This tells WLA that a FREE section called "Init" must be located somewhere
+in bank 0. If you replace FREE with SEMIFREE the section will be inserted
+somewhere in the bank 0, but not in the $0-$14F area.
+
+Here's the order in which WLA writes the sections:
+1. FORCE
+2. SEMIFREE & FREE
+3. OVERWRITE
+
+You can also create a RAM section. For more information about them, please
+read .RAMSECTION directive explanation.
+
+This is not a compulsory directive.
+
+--------------------------------
+.RAMSECTION "Vars" BANK 0 SLOT 1
+--------------------------------
+
+RAMSECTIONs accept only variable labels and variable sizes, and the
+syntax to define these is identical to .ENUM (all the syntax rules that
+apply to .ENUM apply also to .RAMSECTION). Additionally you can embed
+structures (.STRUCT) to a RAMSECTION. Here's an example:
+
+.RAMSECTION "Some of my variables" BANK 0 SLOT 1
+vbi_counter:   db
+player_lives:  db
+.ENDS
+
+RAMSECTIONs behave like FREE sections, but instead of filling any banks
+RAM sections will occupy area inside slots. You can fill different slots
+with different variable labels. It's recommend that you create separate
+slots for holding variables (as ROM and RAM don't usually overlap).
+Here's another example:
+
+.MEMORYMAP
+SLOTSIZE $4000
+DEFAULTSLOT 0
+SLOT 0 $0000   ; ROM slot 0.
+SLOT 1 $4000   ; ROM slot 1.
+SLOT 2 $A000   ; variable RAM is here!
+.ENDME
+
+.STRUCT game_object
+x DB
+y DB
+.ENDST
+
+.RAMSECTION "vars 1" BANK 1 SLOT 2
+moomin    DW
+phantom   DB
+nyanko    DB
+enemy     INSTANCEOF game_object
+.ENDS
+
+If no other RAM section is used, then this is what you will get:
+
+.DEFINE moomin  $A000
+.DEFINE phantom $A002
+.DEFINE nyanko  $A003
+.DEFINE enemy   $A004
+.DEFINE enemy.x $A004
+.DEFINE enemy.y $A005
+
+Note that the BANK value is only used when referring labels using
+notation ":label". BANK in .RAMSECTION is optional so you can
+leave it away if you think you don't need to know the bank number
+for a label inside a RAM section.
+
+This is not a compulsory directive.
+
+-----
+.ENDS
+-----
+
+Ends the section.
+
+This is not a compulsory directive, but when .SECTION is used this one is
+required to terminate it.
+
+-------
+.ROMGBC
+-------
+
+Inserts data into the specific ROM location to mark the ROM as a GBC ROM
+($C0 -> $0143, so ROM name is max. 15 characters long).
+
+This is not a compulsory directive.
+
+-------
+.ROMDMG
+-------
+
+Inserts data into the specific ROM location to mark the ROM as a DMG ROM
+($00 -> $0146).
+
+This is not a compulsory directive. .ROMDMG cannot be used with .ROMSGB.
+
+-------
+.ROMSGB
+-------
+
+Inserts data into the specific ROM location to mark the ROM as a SGB enhanced
+ROM ($03 -> $0146).
+
+This is not a compulsory directive. .ROMSGB cannot be used with .ROMDMG.
+
+--------------
+.EXPORT work_x
+--------------
+
+Exports the definition "work_x" to outside world. .EXPORT can only be used
+inside object and library files. Exported definitions are visible to all
+object files and libraries in the linking procedure. Note that you can only
+export value definitions, not string definitions.
+
+You can export as many definitions as you wish with one .EXPORT:
+
+.EXPORT NUMBER, NAME, ADDRESS, COUNTRY
+.EXPORT NAME, AGE
+
+This is not a compulsory directive.
+
+--------------------------
+.PRINTT "Here we are...\n"
+--------------------------
+
+Prints the given text into stdout. Good for debugging stuff. PRINTT takes
+only a string as argument, and the only supported formatting symbol is '\n'
+(line feed).
+
+This is not a compulsory directive.
+
+-------------------
+.PRINTV DEC DEBUG+1
+-------------------
+
+Prints the value of the supplied definition or computation into stdout.
+Computation must be solvable at the time of printing (just like definitions
+values). PRINTV takes two parameters. The first describes the type of the
+print output. "DEC" means decimal, "HEX" means hexadecimal.
+
+Use PRINTV with PRINTT as PRINTV doesn't print linefeeds, only the result.
+Here's an example:
+
+.PRINTT "Value of \"DEBUG\" = $"
+.PRINTV HEX DEBUG
+.PRINTT "\n"
+
+This is not a compulsory directive.
+
+------------------
+.OUTNAME "other.o"
+------------------
+
+Changes the name of the output file. Here's and example:
+
+wla-gb -o test.s
+
+would normally output "test.o", but if you had written
+
+.OUTNAME "new.o"
+
+somewhere in the code WLA would write the output to new.o instead.
+
+This is not a compulsory directive.
+
+
+
+------------------------------------------------------------------------------
+7... Assembler Syntax
+------------------------------------------------------------------------------
+
+
+7.1. Case Sensitivity
+
+WLA is case sensitive, so be careful.
+
+
+7.2. Comments
+
+Comments begin with ';' or '*' and end along with the line. ';' can be
+used anywhere, but '*' can be placed only at the beginning of a new line.
+
+Version 4.1 of WLA introduced ANSI-C -like commenting. This means you can
+start a multiline comment with "/*" and end it with "*/".
+
+Version 6.0 of WLA introduced .ASM and .ENDASM directives. These function
+much like ANSI-C comments, but unlike the ANSI-C comments these can be
+nested.
+
+
+7.3. Labels
+
+Labels are ordinary strings (that can also end to ':'). Labels starting
+with "_" are considered as local labels and do not show outside sections
+where they were defined, or outside object files, if they were not defined
+inside a section.
+
+Here are few examples of different labels:
+
+VBI_IRQ:
+VBI_IRQ2
+_VBI_LOOP:
+main:
+
+Note that when you place ':' in front of the label string when referring to
+it, you'll get the bank number of the label, instead of the label's address.
+Here's an example:
+
+LD A, :LOOP
+.BANK 2 SLOT 0
+LOOP:
+
+Here "LD A, :LOOP" will be replaced with "LD A, 2" regardless of the label's
+address.
+
+When you are referring to a label and you are adding something to its address
+(or subtracting, any arithmetics apply) the result will always be bytes.
+
+.org 20
+DATA:  .dw 100, 200, 300
+       ld  a, DATA+1
+              ^^^^^^ = r
+
+So here the result r will be the address of DATA plus one, here 21. Some x86
+assemblers would give here 22 as the result r as DATA points to an array
+or machine words, but WLA isn't that smart (and some people including me
+think this is the better solution).
+
+You can also use -, --, ---, +, ++, +++, ... as un-named labels.
+Labels consisting of '-' are meant for reverse jumps and labels consisting
+of '+' are meant for forward jumps. You can reuse un-named labels as much
+as you wish inside your source code. Here's an example of this:
+
+    dec e
+    beq ++      ; jump -> ?
+    dec e
+    beq +       ; jump -> %
+    ld d, 14
+--- ld a, 10    ; !
+--  ld b, c     ; #
+-   dec b       ; *
+    jp nz, -    ; jump -> *
+    dec c
+    jp nz, --   ; jump -> #
+    dec d
+    jp nz, ---  ; jump -> !
+    ld a, 20
+-   dec a       ; $
+    jp nz, -    ; jump -> $
++   halt        ; %
+++  nop         ; ?
+
+Note that "__" (that's two underline characters) serves also as a un-named
+label. You can refer to this label from both directions. Use "_b" when
+you are jumping backwards and "_f" when you are jumping forwards label "__".
+
+Example:
+
+   dec e
+   jp z, _f     ; jump -> *
+   dec e
+__ ldi a, (hl)  ; *
+   dec e
+   jp nz, _b    ; jump -> *
+
+CAVEAT! CAVEAT! CAVEAT!
+
+The following code doesn't work as it would if WLA would determine the
+distance lexically (but in practice it's WLALINK that does all the
+calculations and sees only the preprocessed output of WLA):
+
+.macro dummy
+-  dec a        ; #
+   jp nz, -     ; jump -> #
+.endm
+
+   ...
+-  nop          ; *
+   dummy
+   dec e
+   jp nz, -     ; i'd like to jump to *, but i'll end up jumping
+                ; to # as it's closest to me in the output WLA produces
+                ; for WLALINK (so it's better to use \@ with labels inside
+                ; a macro).
+
+
+7.4. Number Types
+
+1000 - decimal.
+$100 - hexadecimal.
+%100 - binary.
+'x'  - character.
+
+All numbers must be integers. *SIN/*COS -families are exceptions as
+they take real numbers as some of their arguments.
+
+
+7.5. Strings
+
+Strings begin with and end to '"'. Note that no 0 is inserted to indicate
+the termination of the string like in eg. ANSI C. You'll have to do it
+yourself. You can place quotation marks inside strings the way C
+preprocessors accept them.
+
+Here are some examples of strings:
+
+"Hello world!"
+"He said: \"Please, kiss me honey.\""
+
+
+7.6. Supported Mnemonics
+
+Note that WLA 6502/65C02/6510/HUC6280/65816 support .B, .W (and .L) versions
+of mnemonics that take immediate values. WLA Z80/GB/SPC-700 don't have this
+functionality as Z80/GB-Z80/SPC-700 don't have mnemonics which could collide.
+Here are few examples using 6502 syntax:
+
+and.b #20
+and.w #20
+bit.b loop
+bit.w loop
+
+You can also give the operand size with the operand itself (and this is
+highly recommended):
+
+and #20.b
+and #20.w
+bit loop.b
+bit loop.w
+
+Additionally there is an extra mnemonic in the GB-Z80 version of WLA
+called "DEBUG" which will translate to $ED. This one is not used in
+real GB-Z80, but my Game Boy emulator, Wzonka-Lad, will invert the
+Amiga's power light mode when $ED is executed.
+
+Don't use DEBUG if you are going to use your code elsewhere!
+
+
+7.7. Brackets?
+
+Brackets are also supported in the GB-Z80/Z80/6502/65C02/HUC6280/6510 syntax.
+So you can write
+
+LDI (HL), A
+or
+LDI [HL], A
+
+Yes, you could write
+LDI [HL), A
+but I don't recommend that. ;)
+
+Note that brackets have special meaning when dealing with a 65816/SPC-700
+system so you can't use
+
+AND [$65]
+instead of
+AND ($65)
+
+as they mean different things.
+
+
+
+------------------------------------------------------------------------------
+8... Error Messages
+------------------------------------------------------------------------------
+
+
+There are quite a few of them in WLA, but most of them are not as informative
+as I would like them to be. This will be fixed in the future. Mean while, be
+careful. ;)
+
+
+
+------------------------------------------------------------------------------
+9... Supported ROM/RAM/Cartridge Types (WLA-GB)
+------------------------------------------------------------------------------
+
+
+9.1. ROM Size
+
+GB-Z80 version of WLA supports the following ROM bank sizes. There's no such
+limit in the Z80/6502/65C02/6510/65816/HUC6280/SPC-700 version of WLA. Supply
+one of the following values to .ROMBANKS.
+
+ $0 - 256Kbit =  32KByte =   2 banks
+ $1 - 512Kbit =  64KByte =   4 banks
+ $2 -   1Mbit = 128KByte =   8 banks
+ $3 -   2Mbit = 256KByte =  16 banks
+ $4 -   4Mbit = 512KByte =  32 banks
+ $5 -   8Mbit =   1MByte =  64 banks
+ $6 -  16Mbit =   2MByte = 128 banks
+$52 -   9Mbit = 1.1MByte =  72 banks
+$53 -  10Mbit = 1.2MByte =  80 banks
+$54 -  12Mbit = 1.5MByte =  96 banks
+
+
+9.2. RAM Size
+
+Supply one of the following hex values to .RAMSIZE in the GB-Z80 version
+of WLA.
+
+ $0 -    None
+ $1 -  16kbit =   2kByte =   1 bank
+ $2 -  64kbit =   8kByte =   1 bank
+ $3 - 256kbit =  32kByte =   4 banks
+ $4 -   1Mbit = 128kByte =  16 banks
+
+
+9.3. Cartridge Type
+
+It's up to the user to check that the cartridge type is valid and
+can be used combined with the supplied ROM and RAM sizes. Give
+one the the following values to .CARTRIDGETYPE in the GB-Z80 version of WLA.
+
+ $0 - ROM ONLY
+ $1 - ROM+MBC1
+ $2 - ROM+MBC1+RAM
+ $3 - ROM+MBC1+RAM+BATT
+ $5 - ROM+MBC2
+ $6 - ROM+MBC2+BATTERY
+ $8 - ROM+RAM
+ $9 - ROM+RAM+BATTERY
+ $B - ROM+MMM01
+ $C - ROM+MMM01+SRAM
+ $D - ROM+MMM01+SRAM+BATT
+ $F - ROM+MBC3+TIMER+BATT
+$10 - ROM+MBC3+TIMER+RAM+BATT
+$11 - ROM+MBC3
+$12 - ROM+MBC3+RAM
+$13 - ROM+MBC3+RAM+BATT
+$19 - ROM+MBC5
+$1A - ROM+MBC5+RAM
+$1B - ROM+MBC5+RAM+BATT
+$1C - ROM+MBC5+RUMBLE
+$1D - ROM+MBC5+RUMBLE+SRAM
+$1E - ROM+MBC5+RUMBLE+SRAM+BATT
+$1F - Pocket Camera
+$BE - Pocket Voice
+$FD - Bandai TAMA5
+$FE - Hudson HuC-3
+$FF - Hudson HuC-1
+
+
+
+------------------------------------------------------------------------------
+10.. Bugs
+------------------------------------------------------------------------------
+
+
+If you find bugs, please let me know asap. Anything, small or big, send
+me email! I won't eat you for reporting a bug. Probably your name just ends
+up in the thanks-section of this documentation. ;)
+
+
+
+------------------------------------------------------------------------------
+11.. Files
+------------------------------------------------------------------------------
+
+
+11.1. 'examples'
+
+The main purpose of the files in the 'examples' directory is to teach people
+few things about WLA. If you feel a little uncertain with the syntax check
+out this place.
+
+'examples' directory holds seven directories, 'gb-z80', 'z80', '6502', '65c02',
+'6510', '65816' and 'spc-700'. 'include' directory under 'gb-z80' could be very
+useful as the six include files there have all the Game Boy hardware register
+address and memory definitions you could ever need and more.
+
+
+11.2. 'examples/gb-z80/lib'
+
+This folder holds few very useful libraries for you to use in your Game Boy
+projects. Instead of reinventing the wheel, use the stuff found in here.
+Remember to compile the libraries right after you've installed WLA by
+executing 'make' in the 'lib' directory.
+
+
+
+------------------------------------------------------------------------------
+12.. Temporary Files
+------------------------------------------------------------------------------
+
+
+Note that WLA will generate two temporary files while it works. Both files
+are placed into the current working directory.
+
+Under Amiga: "wla_a.tmp"  and "wla_b.tmp".
+Under MSDOS: "wla_a.tmp"  and "wla_b.tmp".
+Under Win32: ".wla%PID%a" and ".wla%PID%b" (where %PID% is the process id).
+Under Unix:  ".wla%PID%a" and ".wla%PID%b" (where %PID% is the process id).
+
+When WLA finishes its work these two files are deleted as they serve
+of no further use.
+
+
+
+------------------------------------------------------------------------------
+13.. Compiling
+------------------------------------------------------------------------------
+
+
+13.1. Compiling Object Files
+
+To compile an object file use:
+
+"wla -[tvx]o [DEFINITIONS] <ASM FILE> [OUTPUT FILE]"
+
+These object files can be linked together (or with library files) later
+with "wlalink".
+
+Name object files so that they can be recognized as object files. Normal
+suffix is ".o" (WLA default). This can also be changed with .OUTNAME.
+
+With object files you can reduce the amount of compiling when editing
+small parts of the program. Note also the possibility of using local
+labels (starting with "_").
+
+Note! When you compile objects, group 1 directives are saved for linking
+time, when they are all compared and if they differ, an error message is
+shown. It is advisable to use something like an include file to hold all
+the group 1 directives for that particular project and include it to every
+object file.
+
+If you are interested in the WLA object file format, take a look at the
+file "txt/wla_file_formats.txt" which is included in the release archive.
+
+Here are some examples of definitions:
+
+-DIEXIST
+-DDAY=10
+-DBASE=$10
+-DNAME=elvis
+
+And here's an WLA example creating definitions on the command line:
+
+wla-gb -o -DDEBUG -DVERBOSE=5 -DNAME="math v1.0" math.s
+
+DEBUG's value will be 0, VERBOSE's 5 and NAME is a string definition
+with value "math v1.0".
+
+
+13.2. Compiling Library Files
+
+To compile a library file use:
+ 
+"wla -[tvx]l [DEFINITIONS] <ASM FILE> [OUTPUT FILE]"
+
+Name object files so that they can be recognized as library files. Normal
+suffix is ".lib" (WLA default).
+
+With library files you can reduce the amount of compiling. Library files
+are meant to hold general functions that can be used in different projects.
+Note also the possibility of using local labels (starting with "_").
+Library files consist only of FREE sections.
+
+
+
+------------------------------------------------------------------------------
+14.. Linking
+------------------------------------------------------------------------------
+
+
+After you have produced one or more object files and perhaps some library
+files, you might want to link them together to produce a ROM image / program
+file. "wlalink" is the program you use for that. Here's how you use it:
+
+"wlalink [-dvs]{b/r} <LINK FILE> <OUTPUT FILE>"
+
+Choose 'b' for program file or 'r' for ROM image linking.
+
+Link file is a text file which contains information about the files you want
+to link together. Here's the format:
+
+1. You must define the group for the files. Put the name of the group
+inside brackets. Valid group definitions are
+
+[objects]
+[libraries]
+[header]
+[footer]
+[definitions]
+
+2. Start to list the file names.
+
+[objects]
+main.o
+vbi.o
+level_01.o
+...
+
+3. Give parameters to the library files:
+
+[libraries]
+bank 0 slot 1 speed.lib
+bank 4 slot 2 map_data.lib
+...
+
+Here you can also use "base" to define the 65816 CPU bank number
+(like .BASE works in WLA):
+
+[libraries]
+bank 0 slot 1 base $80 speed.lib
+bank 4 slot 2 base $80 map_data.lib
+...
+
+You must tell WLALINK the bank and the slot for the library files.
+
+4. If you want to use header and/or footer in your project,
+you can type the following:
+
+[header]
+header.dat
+[footer]
+footer.dat
+
+5. If you want to make value definitions, here's your chance:
+
+[definitions]
+debug 1
+max_str_len 128
+start $150
+...
+
+If flag 'v' is used, WLALINK displays information about ROM file after a
+succesful linking.
+
+If flag 's' is used, WLALINK will produce a NO$GMB symbol file. It's useful
+when you work under MSDOS (NO$GMB is a very good Game Boy emulator for MSDOS/
+Windows) as it contains information about the labels in your project.
+
+If flag 'd' is used WLALINK discards all unreferenced sections. This way
+you can link big libraries to your project and WLALINK will choose only
+the used sections, so you won't be linking any dead code/data.
+
+Make sure you don't create duplicate labels in different places in the
+memory map as they break the linking loop. Duplicate labels are allowed when
+they overlap each other in the destination machine's memory. Look at the
+following example:
+
+...
+.BANK 0
+.ORG $150
+
+	...
+	LD	A, 1
+	CALL	LOAD_LEVEL
+	...
+
+LOAD_LEVEL:
+	LD	HL, $2000
+	LD	(HL), A
+	CALL	INIT_LEVEL
+	RET
+
+.BANK 1
+.ORG 0
+
+INIT_LEVEL:
+	...
+	RET
+
+.BANK 2
+.ORG $0
+
+INIT_LEVEL:
+	...
+	RET
+...
+
+
+Here duplicate INIT_LEVEL labels are accepted as they both point to the
+same memory address (in the program's point of view).
+
+
+
+------------------------------------------------------------------------------
+15.. Arithmetics
+------------------------------------------------------------------------------
+
+
+WLA is able to solve complex calculations like
+
+-((HELLO / 2) | 3)
+skeletor_end-skeletor
+
+so you can write something like
+
+LD HL, data_end-data
+LD A, (pointer + 1)
+CP (TEST + %100) & %10101010
+
+WLALINK also has this ability so it can compute the pending calculations
+WLA wasn't able to solve.
+
+The following operators are valid:
+
+(, ), | (or), & (and), ^ (power), << (shift left), >> (shift right), +, -,
+# (modulo), ~ (xor), * and /.
+
+Note that you can do NOT using XOR:
+
+VALUE_A ~ $FF   = 8bit NOT
+VALUE_B ~ $FFFF = 16bit NOT
+
+WLA computes internally with real numbers so (5/2)*2 produces 5, not 4.
+
+
+
+------------------------------------------------------------------------------
+16.. Disassembling
+------------------------------------------------------------------------------
+
+
+WLAD is a disassembler that can be used to disassemble an existing ROM image
+into a WLA-syntax compatible source file. It won't produce very readable
+code as all the labels etc. are discarded in the last phase of linking when
+the ROM image is made. In the current state WLAD doesn't generate labels,
+but it will in the future.
+
+Here's how you use it:
+
+"wlad [-dsa] <BIN FILE>"
+
+Give it the binary file (usually the extension is .gb or .cgb) and WLAD will
+output the source code into stdout (the shell you are using). Here's an
+example what you can do if you want the source code into a file instead
+of the screen:
+
+"wlad tbp.cgb > tbp.s"
+
+WLAD has three option flags:
+
+a - Disable address output.
+d - The upper banks (1->) are disassembled as data.
+s - The upper banks (1->) are disassembled as data with string detection
+    enabled.
+
+Use the 's'-flag if you intend to change texts in games. The flags 'd'
+and 's' cannot be used at the same time.
+
+Examples:
+
+[root@jaakkopotti parallax]# wlad -da parallax.gb > parallax.s
+[root@jaakkopotti parallax]# wlad -s parallax.gb > parallax.s
+
+WLAD supports both normal ROMs and Pocket Voice (tm) ROM images. Only WLAD
+GB-Z80 exists curently.
+
+
+
+------------------------------------------------------------------------------
+17.. Binary to DB Conversion
+------------------------------------------------------------------------------
+
+
+WLAB converts binary files to WLA's byte definition strings. Here's how
+you use it:
+
+"wlab -[ap]{bdh} <BIN FILE>"
+
+Give it the binary file and WLAB will output the WLA DB formatted data of it
+into stdout. Here's an example from real life:
+
+"wlad -da gayskeletor.bin > gayskeletor.s"
+
+WLAB has three command flags of which one must be given to WLAB:
+
+b - Output data in binary format.
+d - Output data in decimal format.
+h - Output data in hexadecimal format.
+
+WLAB has also two option flags:
+
+a - Print the address (relative to the beginning of the data).
+p - Don't print file header.
+
+Examples:
+
+[root@jaakkopotti src]# wlab -bap iscandar.bin > iscandar.s
+[root@jaakkopotti src]# wlab -h starsha.bin > starsha.s
+
+
+
+------------------------------------------------------------------------------
+18.. Things you should know about coding for...
+------------------------------------------------------------------------------
+
+
+Please check out the source code examples (in 'examples' directory) for
+quick target system specific information.
+
+
+18.1. Z80
+
+Check the Z80 specific directives. All SMS/GG coders should find .SMSTAG, 
+.SDSCTAG and .COMPUTESMSCHECKSUM very useful...
+
+
+18.2. 6502
+
+For example mnemonics ADC, AND, ASL, etc... cause problems to WLA, because
+they take different sized arguments. Take a look at this:
+
+LSR 11       ; $46 $0B
+LSR $A000    ; $4E $00 $A0
+
+The first one could also be
+
+LSR 11       ; $4E $0B $00
+
+To really get what you want, use .8BIT, .16BIT and .24BIT directives. Or
+even better, supply WLA the size of the argument in the operator:
+
+LSR.W 11     ; $4E $0B $00
+
+And what really is recommended is that you supply WLA the operand size
+with the operand itself:
+
+LSR 11.W     ; $4E $0B $00
+
+
+18.3. 65C02
+
+Read 18.2. as the information applies also to 65C02 coding...
+
+
+18.4. 6510
+
+Read 18.2. as the information applies also to 6510 coding...
+
+
+18.5. 65816
+
+Read 18.2. as the information applies also to 65816 coding...
+
+WLA-65816 has also few SNES specific directives which are all very
+helpful. Remember that when you use .LOROM, .HIROM, SLOWROM and .FASTROM
+WLA automatically writes the information into ROM address $FFD5.
+
+Use .BASE to get the 24bit addresses.
+
+If possible, use descriptive operands to specify the size of the
+operand (WLA is able to deduce the cpu mode to some extent from REP/SEP
+-mnemonics, but just to be sure, use .B and .W):
+
+AND #10     ; can be two different things, depending on the cpu mode.
+AND #10.B   ; forces 8bit immediate value.
+AND #10.W   ; forces 16bit immediate value.
+
+
+18.6. HUC6280
+
+Read 18.2. as the information applies also to HUC6280 coding...
+
+
+18.7. SPC-700
+
+Nothing so far...
+
+
+18.8. Pocket Voice (GB-Z80)
+
+Pocket Voice uses its own MBC. You can enable Pocket Voice mode by selecting
+Pocket Voice cartridge type ($BE in $0147) and defining correct
+.ROMBANKMAP and .MEMORYMAP. In PV mode bank 0 is 24KB and the rest are 8KB.
+Note that WLA assumes that ROM offset is all the time 0. If you use
+something else as the offset, make sure to compute the jumps by hand as WLA
+cannot do that.
+
+Check out examples/gb-z80/include/pocket_voice.i for more information.
+
+
+
+------------------------------------------------------------------------------
+19.. WLA Flags
+------------------------------------------------------------------------------
+
+
+Here are short descriptions for the flags you can give to WLA:
+
+You can supply WLA with some (or all or none) of the following option flags.
+
+t - Test compile. Doesn't output any files.
+v - Verbose mode. Shows a lot of information about the compiling process.
+x - Extra compile time definitions. WLA does extra work by creating
+    few helpful definitions on the fly.
+
+One (and only one) of the following command flags must be defined.
+
+l - Output a library file.
+o - Output an object file.
+
+Examples:
+
+[root@jaakkopotti tbp]# wla -vo testa.s
+[root@jaakkopotti tbp]# wla -l testb.s testb.lib
+
+Note that the first example produces file named "testa.o".
+
+
+
+------------------------------------------------------------------------------
+20.. Extra compile time definitions
+------------------------------------------------------------------------------
+
+
+When you supply WLA with the flag 'x' it will maintain few useful definitions
+while compiling your source codes. Please use the enhanced error reporting
+engine (so don't use flag 'f') in conjunction with flag 'x' as some of the
+definitions require extra information about the flow of the data which isn't
+available when using the old, crippled error reporting engine.
+
+Here's a list of what you get when you use flag 'x':
+
+WLA_FILENAME - A string definition holding the file name WLA is currently
+               processing.
+WLA_TIME     - A string definition holding the calendar time (obtained using
+               C's ctime()).
+WLA_VERSION  - A string definition holding the version number of WLA.
+
+So you can do for example something like
+
+.DB WLA_TIME
+
+to store the time when the build process started into the ROM file you
+are compiling.
+
+
+
+------------------------------------------------------------------------------
+21.. Good things to know about WLA
+------------------------------------------------------------------------------
+
+
+- Want more stack depth (.REPT and .MACRO)? Check out "REPEAT_STACK_DEPTH"
+  and "MACRO_STACK_DEPTH" in defines.h.
+- Is 64 bytes too little for a string (file names, labels, definition labels,
+  etc)? Check out "MAX_NAME_LENGTH" in defines.h.
+- WLA preprocessor doesn't expand macros and repetitions. Those are actually
+  traversed in the assembling phase.
+
+
+
+------------------------------------------------------------------------------
+22.. Author
+------------------------------------------------------------------------------
+
+
+Ville Helin, the author of Wzonka-Lad, a Game Boy emulator for the Amiga
+machines. I have 24 years behind me, many more to travel through. I study
+information technology at the Helsinki University of Technology
+(http://www.hut.fi). I like Game Boy (goes without saying), anime soap operas,
+gym and hardcore video gaming.
+
+email: vhelin@cc.hut.fi
+hpage: http://www.hut.fi/~vhelin
+smail: Ville Helin
+       Dagmarinkatu 8 C 38
+       00100 Helsinki
+       Finland
+
+
+
+------------------------------------------------------------------------------
+23.. Thanks
+------------------------------------------------------------------------------
+
+
+- Gaelan Griffin for endless suggestions and fast bug reports!
+  Take one feature from WLA and you have a 40% propability that Gaelan
+  bugged me to implement it. ;)
+- Aleksi Eeben with lots of good bug reports and feature ideas!
+- Nicolas Warren for few some serious bug reports (and even
+  fixes to them!) and for the good ideas!
+- Madonna MkII (Matra Computer Corp.), Mike Blum, Anders Montonen,
+  Robert Kihl, Martin Konrad, Arto Salmi, Maxim and Yoshiaki Ishida
+  for reporting bugs in WLA and providing me with great ideas.
+- Mark Knox, Igor Wronsky and Anders Montonen for helping me with
+  the MSDOS port!
+- Gaelan Griffin for the Amiga port and valuable SPC-700 information!
+- Christophe Iasci for the Win32 port!
+- Marc Dünster and Kevin Mantey for the help and suggestions with wla-65816
+  and wla-spc700!
+- John Schneider for makefile enhancements!
+- Timo Jantunen for helping me with makefiles.
+- Adam Klotblix for documentation improvements and bug reports.
+- People at gameboy@vip.co.za, gameboydev@listbot.com,
+  gbadev@yahoogroups.com and s8-dev for keeping up the good work! ;)
+
+
+
+------------------------------------------------------------------------------
+24.. Future
+------------------------------------------------------------------------------
+
+
+Future enhancements (if I get really inspired):
+
+- Much more features to WLAD (I already know of three) and
+  Z80/6502/65C02/6510/65816/HUC6280/SPC-700 support.
+- Other optimizations, bug fixes and new features.
+- You tell me.
+
+
+
+------------------------------------------------------------------------------
+25.. Support
+------------------------------------------------------------------------------
+
+
+The currently supported systems are MSDOS/x86, Win32/x86, AmigaOS/680x0 and
+Unix/xyz. If you'd like to see WLA for other platforms/configurations, send
+me email and we'll see what I can do about it (if compiling WLA DX binaries
+from the source release archive doesn't work for some reason).
+
+
+
+------------------------------------------------------------------------------
+26.. Legal Note
+------------------------------------------------------------------------------
+
+
+WLA DX (the whole package) was written by Ville Helin in 1998-2002.
+
+Game Boy and Game Boy Color are copyrighted by Nintendo.
+
+Pocket Voice is copyrighted by Bung HK.

+ 27 - 0
files/docs/snes/yoshi/READ.ME

@@ -0,0 +1,27 @@
+*****************************************************************************
+SNES Documentation v2.30: Written by Yoshi
+*****************************************************************************
+Previous version: v2.21
+The follow files are included (or should be!) in this archive:
+[* = Updated since previous version]
+
+*       snes.0.............Introduction
+*       snes.1.............SNES Register section
+*       snes.2.............SNES Colour section
+*       snes.3.............SNES Graphics section
+*       snes.4.............SNES Screen-mode section
+*       snes.5.............SNES OAM/Sprite section
+*       snes.6.............Super Magicomm disk registers
+-=NEW=- snes.7.............SNES Memory map
+-=NEW=- snes.8.............Those boring credits/thank-yous/hellos! :-)
+        sound.doc..........SPC-700 (sound) documentation by Antitrack
+        sprite.doc.........OBJ/OAM documentation
+-=NEW=- test.lzh...........Mini "demo" by yours-truly. Comes with source,
+			   music, graphics, and the SMC file.
+-=NEW=- sid-spc.src........C64 sound emulator documentation/code by Antitrack
+*****************************************************************************
+All sections are formatted using whitespaces vs. actual tab characters. This
+is due to the fact that some people have their tabs set to 4 or 5 spaces
+rather than the vi-standard of 8.
+
+'sound.doc', 'sprite.doc', and 'sid-spc.src' are not formatted this way.

+ 1072 - 0
files/docs/snes/yoshi/SID-SPC.SRC

@@ -0,0 +1,1072 @@
+; The following program is a reassembly of the c64-soundchip emulation routines
+; written by Alfatech/Triad ooops I mean Alfatech/Censor. I have tried to make
+; this code as readable as possible in order to help people get started with
+; snes SPC700 sound programming.
+
+ÚÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄ¿
+³ THANKS TO ABSOLUTELY EVERYONE FOR BEING SUCH A LACK OF A HELP!!!!  (grrrr) ³
+ÀÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÄÙ
+
+; especially you guys on #snes, #snes!, famidev; Corsair, Pothead, Sir Jinx,
+; and the rest of the Internet!
+; or in other words, i had to find out everything myself again.  :(
+; And no, I still dont have an assembler for the spc700, just a disassembler :(
+; thats why you will notice the big lack of pseudoopcodes, macros etc.   :((
+
+;----------------------------------------------------------------------------
+
+; Well first let us remember how a sound usually works on the C64. The C64
+; sound chip is located at memory $d400 to $d41b, with these memory locations
+; having the following (registers) meaning:
+
+hexadec.
+address     meaning;  /bit7/bit6/bit5/bit4/bit3/bit2/bit1/bit0/
+
+d400        frequency to play lobyte      voice 1
+d401        frequency to play hibyte      voice 1
+d402        pulsewidth        lobyte
+d403        pulsewidth        hibyte bit 7-4 unused: max width:=$07ff
+d404        Waveform: noise/pulse/sawtooth/triangle/test/ringmod/syncmod/gate
+d405        attack decay    (4 bit attack,  4bit decay)
+d406        sustain release (4 bit sustain, 4bit release)
+
+d407        frequency to play lobyte      voice 2
+d408        frequency to play hibyte      voice 2
+d409        pulsewidth        lobyte
+d40a        pulsewidth        hibyte bit 7-4 unused: max width:=$07ff
+d40b        Waveform: noise/pulse/sawtooth/triangle/test/ringmod/syncmod/gate
+d40c        attack decay    (4 bit attack,  4bit decay)
+d40d        sustain release (4 bit sustain, 4bit release)
+
+d40e        frequency to play lobyte      voice 3
+d40f        frequency to play hibyte      voice 3
+d410        pulsewidth        lobyte
+d411        pulsewidth        hibyte bit 7-4 unused: max width:=$07ff
+d412        Waveform: noise/pulse/sawtooth/triangle/test/ringmod/syncmod/gate
+d413        attack decay    (4 bit attack,  4bit decay)
+d414        sustain release (4 bit sustain, 4bit release)
+
+d415        filter frequency lowbyte. bit 7-3 unused...
+d416        filter frequency highbyte
+d417        filter resonance upper 4 bits/filtex/filt3,2,1 (=select filter type)
+d418        3off/highpass/medpass/lowpass/vol3/vol2/vol1/vol0
+d419        unused
+d41a        unused
+d41b        unused too for this case ;)
+d41c        unused too for this case ;)
+
+
+A typical C64 sound routine consist of two parts, an INIT subroutine and a
+PLAYER subroutine. The INIT routine clears the sound chip registers and
+initializes all kind of pointers and variables for the PLAYER routine.
+The PLAYER routine is typically being called once every time the screen makes
+the vertical blank (VBL), thus, once the 24th part of a second.
+
+SO, if one emulates the c64 SID, he has at least to do the following:
+
+- move the C64 sound routine to ram at $7f0000  (64 k ram)
+- call the C64 sound PLAYER routine every VBL. The NMI of the SNES is
+  perfectly suitable to do this, but you can also do an IRQ routine of
+  your own.
+- Immidately afterwards, you should send the memory loactions $7fd400 to $7fd418
+  from SNES RAM memory to SPC RAM memory, using send (65c18) and receive
+  (spc700) routines of your own.
+- After receiving and putting in his own RAM memory, the SPC700 shall
+  evaluate the new RAM data, set its own DSP registers accordingly and
+  start playing, if appropriate.
+
+
+; Before you jump at the supposedly source code, let me warn that my
+; SPC disassembler seems to have some slight bugs, as well as my SPC manual.
+; the opcode $8f (mov $xx, #$yy) seems, accordingly to this sourcecode
+; move the value xx into the mem location yy. Thus the real syntax of this
+; command should be:  mov #$xx, $yy
+; e.g  8f 00 f6   mov #$00, $f6  ; move the value "00" into memory location $f6.
+; take note of this when reading this source code.
+
+
+
+;-------------------------------------------------
+;SPC700 Disassembler v0.1
+;Loading Blocks
+;Block 00: start $0400 length $07DB
+;Execution Address: $0400
+;-------------------------------------------------
+
+
+
+;------------------------------------------------------------------
+; Reassembly work (c) Antitrack Oct-17-1994
+;------------------------------------------------------------------
+
+
+
+0400 20         CLRP                  ;  clear direct page flag
+0401 CD CF      MOV     X,#$CF        ;  x:=$cf
+0403 BD         MOV     SP,X          ;  stack pointer := x
+0404 8F FF F4   MOV     $FF,#$F4      ;  2140 = ff
+0407 E8 00      MOV     A,#$00        ;  a := 0
+0409 5D         MOV     X,A           ;  x := 0
+040A AF         MOV     (X)+,A        ; Ä¿   clear 0000-00ef
+040B C8 F0      CMP     X,#$F0        ;  ³
+040D D0 FB      BNE     $040A         ; ÄÙ
+040F 5D         MOV     X,A           ;  x := 0
+0410 D5 00 01   MOV     $0100+X,A     ; ÄÄ¿  clear 0100-03ff
+0413 D5 00 02   MOV     $0200+X,A     ;   ³
+0416 D5 00 03   MOV     $0300+X,A     ;   ³
+0419 3D         INC     X             ;   ³
+041A D0 F4      BNE     $0410         ; ÄÄÙ
+041C 8F 00 F1   MOV     $00,#$F1      ;  port clear reg: do not clear ports.
+041F 8F 30 F1   MOV     $30,#$F1      ;  clear 2140-2143 aka 00f4-00f7
+0422 3F 4C 0A   CALL    $0A4C         ;  init and clear all dsp registers
+
+; if you have read the comments at $0a4c , you remembered I had told you we
+will have some very important data at $0200 real soon now. This data is the
+table of pointers to the start of each sample, so indeed its important. :)
+The following loop below will move the table from $09fc to $0200 and make
+it more appropriate, that is, if you consider the bytes at $09fc being:
+
+09fc:    $ww $xx $yy $zz
+
+the table at $0200 will be like the following:
+
+0200:    $ww $xx $ww $xx $yy $zz $yy $zz   and so on.
+
+or in other words, each 16 bit that appreared at $09fc (a word) will now
+appear twice at 0200:
+
+09fc:  dc.w  word1, word2, word3, word4....
+
+0200:  dc.w  word1, word1, word2, word2, word3, word3, word4, word4
+
+
+This table at $09fc contains the start pointers of all samples.  When you
+e.g. use sample 10, the DSP now looks at $0200+10 and finds the pointer to
+the sample. Neat innit?
+
+
+0425 CD 00      MOV     X,#$00        ;  I think this is understood now. :)
+0427 8D 00      MOV     Y,#$00        ;
+0429 F5 FC 09   MOV     A,$09FC+X     ;
+042C D6 00 02   MOV     $0200+Y,A     ;
+042F D6 02 02   MOV     $0202+Y,A     ;
+0432 3D         INC     X             ;
+0433 FC         INC     Y             ;
+0434 F5 FC 09   MOV     A,$09FC+X     ;
+0437 D6 00 02   MOV     $0200+Y,A     ;
+043A D6 02 02   MOV     $0202+Y,A     ;
+043D 3D         INC     X             ;
+043E FC         INC     Y             ;
+043F FC         INC     Y             ;
+0440 FC         INC     Y             ;
+0441 C8 50      CMP     X,#$50        ; this means we have got $25 samples,
+0443 D0 E4      BNE     $0429         ; which is decimal 37 samples. Makes
+                                      ; perfect sense if you look at the
+                                      ; sample table where we start at
+                                      ; sample 0 and end with sample 36.
+
+;-----------------------------------------------------------------
+; Anyway now we really have finished initializing a lot. We initialized
+; the DSP, we set up the sample pointer table, etc. etc.  now its time
+; for the real action.... hopefully (bleugh, sweat, cough, etc....)
+; The real action is: First we have to get the SID data from the 65c816 to
+; the SPC's ram; we will receive the data through the ports 2140-43 (from
+; the 65c816's point of view) and $f4-f7 (from the spc700's point).
+;-----------------------------------------------------------------
+
+
+0445 8F 00 F6   MOV     $00,#$F6      ;  00 into 2142
+
+; At 0448 is the (endless) main loop. Endless, that is, except a reset code
+; was received through the ports.
+
+0448 8F FD F4   MOV     $FD,#$F4      ;  fd into 2140
+044B 78 FE F4   CMP     $FE,#$F4      ;  wait till 2140=fe
+044E D0 FB      BNE     $044B         ;
+0450 8F FE F4   MOV     $FE,#$F4      ;  answer to the 65c816 by returning $fe
+0453 CD 00      MOV     X,#$00        ;  X:=0
+0455 3E F4      CMP     X,$F4         ;  wait for $00 in 2140 from the 65816
+0457 D0 FC      BNE     $0455         ;
+0459 E4 F5      MOV     A,$F5         ;  data ready in 2141
+045B D4 80      MOV     $80+X,A       ;  poke $d400-$d414 into $0080-$0095
+045D 3D         INC     X             ;     (7fd400/65c816)    (spc700)
+045E D8 F4      MOV     $F4,X         ; I guess this also means he doesnt emu-
+0460 C8 15      CMP     X,#$15        ; late the filter of the 64 soundchip !!
+0462 D0 F1      BNE     $0455         ;
+
+:----------------------------voice one emulation start here-----------------
+
+
+0464 E4 84      MOV     A,$84         ; $d404: check waveform
+0466 28 7F      AND     A,#$7F        ; mask out the 7th bit (noise waveform)
+0468 68 24      CMP     A,#$24        ; check for SAWTOOTH+RINGMODULATION wave
+046A D0 07      BNE     $0473         ; if no SAWTOOTH+RING, jmp to 0473
+046C 8F 34 F2   MOV     $34,#$F2      ; DSP register 34: voice 3, SAMPLE.
+046F C4 F3      MOV     $F3,A         ; we select sample $24 for SAWT+RING
+0471 2F 48      BRA     $04BB         ; sample $24 (36 dec.) is empty, SAW+RING is
+                                      ; thus not implemented here!!!
+
+0473 5D         MOV     X,A           ; This code is exec if NO SAW+RING.
+                                      ; X=A=actual waveform.
+0474 28 20      AND     A,#$20        ; check for waveform=SAWTOOTH.
+0476 F0 16      BEQ     $048E         ; NO sawtooth, continue at 048e
+0478 E4 84      MOV     A,$84         ; get voice1 waveform register again(d404)
+047A 8F 90 72   MOV     $90,#$72      ; 72/73 now point to $0990 ! which is the
+047D 8F 09 73   MOV     $09,#$73      ; sample #37's memory location.
+0480 FA 83 7A   MOV     $83<d>,$7A<s> ; well this seems to be another bug of
+                                      ; either the disassembler or the manual,
+; or both. Let me explain. The only thing that makes sense and that happens
+; here is: the contents of ram location $0083 is being moved to
+; 007a. or to speak BASIC: poke $7a, peek($83) / poke $7b, peek 84 (not sure)
+
+; This implies the <d> and <s> should be vice versa, shoudnt they.
+; Explanation: 83 contains the pulseHI width value, a backup of the pulse
+; width value is being made to mem loc 7a - the subroutine that will
+; be called soon (0b61) needs it that way. Akku still contains the waveform
+; register, d404.
+
+
+0483 3F 61 0B   CALL    $0B61         ;  calculate sample 37 (see there)
+0486 8F 34 F2   MOV     $34,#$F2      ;  voice 3, byte 4, source number: select
+0489 8F 25 F3   MOV     $25,#$F3      ;  sample #37, much to noones surprise :)
+048C 2F 1E      BRA     $04AC         ;  and go to 04ac
+
+;
+; Here we go if there is no sawtooth to play...
+;
+
+048E 7D         MOV     A,X           ;  a=x=d404=(waveform and #$7f) (bit7=0)
+048F 68 03      CMP     A,#$03        ;  all wave off, sync+gate on?
+0491 D0 09      BNE     $049C         ;  if not, goto 049c
+
+;
+; This is the code we execute if there is no(?) waveform to play but the
+; gate and syncronisation bits are both set....
+;
+
+0493 18 08 7B   OR      $08,#$7B     ; if sync+gate on, select random wave-
+                                     ; form for the DSP and lower the volume
+                                     ; by shifting SID's sustain/release.
+
+
+
+0496 4B 86      LSR     $86           ; shifting c64's sustain/release
+0498 4B 86      LSR     $86           ; right by two.
+                                      ; if the old bits were ssssrrrr, they
+                                      ; are now      00ssssrr.
+                                      ; (2 zerobits, 4 bit sustain , 2 release)
+049A 2F 1F      BRA     $04BB         ; jmp to 04bb
+
+
+049C 68 02      CMP     A,#$02        ; Syncronsisation on , gate off, ?
+049E D0 03      BNE     $04A3         ; no, goto 04a3
+04A0 60         CLRC                  ;
+04A1 84 83      ADC     A,$83         ; YES: add pulseHIbyte  to accu
+
+
+
+; remember here we also jump if the sync bit is not set at all. (bit1 of wave)
+04A3 8F 34 F2   MOV     $34,#$F2      ; voice 3, byte 4: source number
+04A6 1C         ASL     A             ; multiply accu by 2
+04A7 60         CLRC                  ;
+04A8 84 82      ADC     A,$82         ; add pulselow byte to accu
+04AA C4 F3      MOV     $F3,A         ; resulting in the Selected sample value.
+
+; now I really wonder if there could go something wrong. Imagine a tune
+; playing waveform $41: (pulse wave + gate bit on); lets say its pulse low is
+; $01. This would make us play sample ($41*2)+$01 = $83.
+; This is a nonexistant sample value coz we have only got samples from $00
+; to 50. I wonder if this is an actual bug in the routine here or
+; if I am wrong.   :-)
+
+
+
+
+04AC 8F 32 F2   MOV     $32,#$F2      ; voice 3, byte 2: pitch low!
+04AF E4 80      MOV     A,$80         ; get d400: frequency low
+04B1 28 F0      AND     A,#$F0        ; and it w $f0
+04B3 C4 F3      MOV     $F3,A         ; resulting in the pitch low value!
+04B5 8F 33 F2   MOV     $33,#$F2      ; voice 3, byte 3: pitch hi!
+04B8 FA 81 F3   MOV     $81<d>,$F3<s> ; poke $f3, peek($81): pitch hi=d401!!!
+
+
+
+04BB 8F 30 F2   MOV     $30,#$F2      ; voice 3, volume left:
+04BE FA 86 F3   MOV     $86<d>,$F3<s> ; set volume left to c64 Sustain/Release?!
+04C1 8F 31 F2   MOV     $31,#$F2      ; voice 3, volume right:
+04C4 FA 86 F3   MOV     $86<d>,$F3<s> ; set volume right to c64 Sus/Release ??!!
+
+; We seem to be finished w the emulation of voice1 of the 64's SID chip here.
+; If SAWTOOTH was selected, the precalculated sample #37 is played.
+
+; Whatever waveform it was anyway, we will use
+; the same frequency that the c64 uses, except they dont call it frequency,
+; they call it pitch.  :-)
+; Puzzling things happen to the sustain/release bytes of the 64, they are
+; nearly directly being poked into the _volume_ registers of the DSP.
+; I am still speaking what should happen most of the time, i am not talking
+; about syncronisation effect.
+; The sync effect is obvioulsy included whilst the RINGMODULATION seems
+; not to be included at all, which is a pity.
+
+;-----------------------voice 2 emulation start here --------------------
+
+
+04C7 E4 8B      MOV     A,$8B         ; accu=$8b=$d40b=waveform voice 2
+04C9 28 7F      AND     A,#$7F        ; mask out noise bit
+04CB 68 24      CMP     A,#$24        ; sawtooth+ringmod selected?
+04CD D0 07      BNE     $04D6         ; if no, goto 04d6
+04CF 8F 44 F2   MOV     $44,#$F2      ; voice 4, source number:
+04D2 C4 F3      MOV     $F3,A         ; play sample #$24 = 36 = empty
+                                ; thus we can see SAWT+RING is not implemented.
+04D4 2F 48      BRA     $051E         ;  jmp to end of routine
+
+
+04D6 5D         MOV     X,A           ; X=a, note that noise (bit7)=0    ?!!
+04D7 28 20      AND     A,#$20        ; is the sawtooth bit on?
+04D9 F0 16      BEQ     $04F1         ; NO, goto 04f1
+
+04DB E4 8B      MOV     A,$8B         ; get $d40b (waveform reg) again into acc
+04DD 8F B4 72   MOV     $B4,#$72      ; 72/73 point to 09b4: sample #38
+04E0 8F 09 73   MOV     $09,#$73      ;
+04E3 FA 8A 7A   MOV     $8A<d>,$7A<s> ; poke 7a, peek(8a): pulse hi voice 2
+04E6 3F 61 0B   CALL    $0B61         ; calculate sample 38
+04E9 8F 44 F2   MOV     $44,#$F2      ; voice 2 , source sample number
+04EC 8F 26 F3   MOV     $26,#$F3      ; is #38, no surprise .
+04EF 2F 1E      BRA     $050F         ; play sawtooth sample #38, end of routine
+
+04F1 7D         MOV     A,X           ; no sawtooth
+04F2 68 03      CMP     A,#$03        ; sync and gate on?
+04F4 D0 09      BNE     $04FF         ; if no sync+gate, goto 04ff
+04F6 18 10 7B   OR      $10,#$7B      ; Select Random samples YES
+04F9 4B 8D      LSR     $8D           ; shift right sustain/release
+04FB 4B 8D      LSR     $8D           ; ssssrrrr -> 00ssssrr
+04FD 2F 1F      BRA     $051E         ; end of routine
+
+04FF 68 02      CMP     A,#$02        ; sync on, gate off?`
+0501 D0 03      BNE     $0506         ; no, goto 0506
+0503 60         CLRC                  ;
+0504 84 8A      ADC     A,$8A         ; add pulse hi to accu (to 02)
+0506 8F 44 F2   MOV     $44,#$F2      ; voice 4 source number
+0509 1C         ASL     A             ; multiply (pulsehi+2) * 2
+050A 60         CLRC                  ;
+050B 84 89      ADC     A,$89         ; add pulse low
+050D C4 F3      MOV     $F3,A         ; and select it as sample # to play
+050F 8F 42 F2   MOV     $42,#$F2      ; volume left
+0512 E4 87      MOV     A,$87         ; frequency low
+0514 28 F0      AND     A,#$F0        ; and freq low w %11110000
+0516 C4 F3      MOV     $F3,A         ; put frequency low into pitch of voice4
+0518 8F 43 F2   MOV     $43,#$F2      ; select voice 4, pitch high
+051B FA 88 F3   MOV     $88<d>,$F3<s> ; put frequency hi into pitchhi of voice4
+051E 8F 40 F2   MOV     $40,#$F2      ; select voice 4 volume left
+0521 FA 8D F3   MOV     $8D<d>,$F3<s> ; put sustain/rel into voice 4 vol left
+0524 8F 41 F2   MOV     $41,#$F2      ; select volume right voice 4
+0527 FA 8D F3   MOV     $8D<d>,$F3<s> ; put sustain/rel into voice 4 vol right
+
+
+;------------------------------------------voice 3 emulation start here
+
+
+052A E4 92      MOV     A,$92         ; accu=$92=$d412=waveform voice 3
+052C 28 7F      AND     A,#$7F        ; mask out noise bit (bit 7)
+052E 68 24      CMP     A,#$24        ; sawtooth+ringmod selected?
+0530 D0 07      BNE     $0539         ; if no, goto 0539
+0532 8F 24 F2   MOV     $24,#$F2      ; voice 4, source number:
+0535 C4 F3      MOV     $F3,A         ; play sample #$24 = 36 = empty
+0537 2F 4A      BRA     $0583         ; we can see SAWT+RING is not implemented.
+0539 5D         MOV     X,A           ; X=a, note that noise (bit7)=0    ?!!
+053A 28 20      AND     A,#$20        ; is the sawtooth bit on?
+053C F0 16      BEQ     $0554         ; NO, goto 04f1
+053E E4 92      MOV     A,$92         ; get waveform of SIDvoice3 again
+0540 8F D8 72   MOV     $D8,#$72      ; set 0072/0073 to point to 09d8
+0543 8F 09 73   MOV     $09,#$73      ; 09d8 is sample #39
+0546 FA 91 7A   MOV     $91<d>,$7A<s> ; make a backup of pulse hi in $007a
+0549 3F 61 0B   CALL    $0B61         ; calculate sample #39
+054C 8F 24 F2   MOV     $24,#$F2      ; select DSPvoice2, source number:
+054F 8F 27 F3   MOV     $27,#$F3      ; set source number to #39, sample #39
+0552 2F 20      BRA     $0574         ; end of routine
+0554 7D         MOV     A,X           ; a=x=waveform SIDvoice3 and #$7f(bit7=0)
+0555 68 03      CMP     A,#$03        ; is the gatebit and sync on?
+0557 D0 09      BNE     $0562         ; no, end of routine
+0559 18 04 7B   OR      $04,#$7B      ; yes: select NOISE for this voice and...
+055C 4B 94      LSR     $94           ; change SID's sustain release bits from
+055E 4B 94      LSR     $94           ; ssssrrrr to 00ssssrr by shifting, thus
+                                      ; lowering the volume!
+0560 2F 21      BRA     $0583         ; end of routine
+0562 68 02      CMP     A,#$02        ; gatebit off, sync on?
+0564 D0 04      BNE     $056A         ; no, end of routine
+0566 60         CLRC                  ;
+0567 84 91      ADC     A,$91         ; add SID pulse hi to accu (which=01)
+0569 00         NOP                   ;
+056A 1C         ASL     A             ; multiply by 2
+056B 60         CLRC                  ;
+056C 84 90      ADC     A,$90         ; add SID's pulse low
+056E 5D         MOV     X,A           ; and store it in x register
+056F 8F 24 F2   MOV     $24,#$F2      ; select DSPvoice2, sample #
+0572 C4 F3      MOV     $F3,A         ; akku=sample #
+0574 8F 22 F2   MOV     $22,#$F2      ; select DSPvoice2, reg2: pitch low
+0577 E4 8E      MOV     A,$8E         ; SID frequency low
+0579 28 F0      AND     A,#$F0        ; is anded with %11110000, and gives....
+057B C4 F3      MOV     $F3,A         ; ...the value for DSPvoice2 pitch low
+057D 8F 23 F2   MOV     $23,#$F2      ; select DSP voice 2 reg3: pitch hi
+0580 FA 8F F3   MOV     $8F<d>,$F3<s> ; DSP pitch hi := SID freq hi
+0583 8F 20 F2   MOV     $20,#$F2      ; select DSP voice 2 reg 0: volume left
+0586 FA 94 F3   MOV     $94<d>,$F3<s> ; DSP vol left := SID Sustain/Release
+0589 8F 21 F2   MOV     $21,#$F2      ; select DSP voice 2 reg 1: volume right
+058C FA 94 F3   MOV     $94<d>,$F3<s> ; DSP vol right := SID Sustain/Release
+058F 8F 3D F2   MOV     $3D,#$F2      ; !!! DSP noise on/off register
+
+; now i understand! $7b is a ram memory location that is zeroed at the
+; beginning. Some bits of $7b will contain either 0 or 1 , depending if
+; a NOISE (random) waveform shall be played or not. These bits
+; are being set during the emulation routines, watch for  "or xx, $7b".
+
+
+0592 FA 7B F3   MOV     $7B<d>,$F3<s> ; set SID noise emulation if necessary
+0595 FA 92 F6   MOV     $92<d>,$F6<s> ; DSP f6=2142, send a signal to 65c816
+0598 D8 F7      MOV     $F7,X         ; send signal to 2143 / 65c816
+059A 8F 00 7B   MOV     $00,#$7B      ; clear noise emulation bits
+059D E4 F6      MOV     A,$F6         ; get a value from port 2142
+059F 68 40      CMP     A,#$40        ; is it $40 ?
+05A1 D0 15      BNE     $05B8         ; no, goto main loop
+05A3 C4 F6      MOV     $F6,A         ; send value #$40 back to 2142/65c816
+05A5 3F 4C 0A   CALL    $0A4C         ; init the sound chip registers!
+05A8 CD 00      MOV     X,#$00        ;
+05AA F5 9B 0B   MOV     A,$0B9B+X     ; move the reset routine to $ffc0
+05AD D5 C0 FF   MOV     $FFC0+X,A     ; (needless coz its ROM and should
+05B0 3D         INC     X             ; stay ROM anyway?!)
+05B1 C8 40      CMP     X,#$40        ; move $40 bytes
+05B3 D0 F5      BNE     $05AA         ;
+05B5 5F C0 FF   JMP     $FFC0         ; make sound chip reset.
+05B8 5F 48 04   JMP     $0448         ; main endless loop here
+
+;-------------------------------------------------------------------------
+;-------------------------------------------------------------------------
+;------------------------THE SAMPLE DATA----------------------------------
+;-------------------------------------------------------------------------
+;-------------------------------------------------------------------------
+
+; Here is the data area where all the samples start. They are grouped to-
+; gether in groups of nine bytes, where the first byte contains header
+; information, which is, in the following cases, either $b0 or $b3.
+; It is $b0 all the time at the start of each sample, and $b3 to indicate
+; that it is the last 9-byte-group of sample data.
+; I dont know too much myself about the samples, so look up your manual
+; will you  :)
+
+; take note, below you will find sample 5 , sample 7, sample 9 etc up to
+; sample 35 (giving 15 samples) and the difference between them is the
+; amount of "$88" sample values instead of "$77" sample values. If you
+; look at them you will easily see how each sample gets more and more
+; $88 bytes instead of $77 bytes. The meaning ? I dunno.  :-)
+
+
+;------------------------------------------------------------------
+; Reassembly work (c) Antitrack Oct-17-1994
+;------------------------------------------------------------------
+
+
+
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+
+
+; 05bb is sample 5
+05BB                                               B0   ....=.@.._.._H..
+05BC  77 77 77 77 77 77 77 77-B3 77 77 77 77 77 77 77   wwwwwwww.wwwwwww
+05CC  77
+
+
+; 05cd is sample #7
+05cd     B0 88 77 77 77 77 77-77 77 B3 77 77 77 77 77   w..wwwwwww.wwwww
+05DC  77 77 77
+
+
+; 05df is sample #9
+05df           B0 88 88 77 77-77 77 77 77 B3 77 77 77   www...wwwwww.www
+05EC  77 77 77 77 77
+
+
+; 05f1 is sample #11
+05f1                 B0 88 88-88 77 77 77 77 77 B3 77   wwwww....wwwww.w
+05FC  77 77 77 77 77 77 77
+
+; 0603 is sample #13
+0603                       B0-88 88 88 88 77 77 77 77   wwwwwww.....wwww
+060C  B3 77 77 77 77 77 77 77-77
+
+; 0615 is sample #15
+0615                             B0 88 88 88 88 88 77   .wwwwwwww......w
+061C  77 77 B3 77 77 77 77 77-77 77 77
+
+; 0627 is sample #17
+0627                                   B0 88 88 88 88   ww.wwwwwwww.....
+062C  88 88 77 77 B3 77 77 77-77 77 77 77 77
+
+; 0639 is sample #19
+0639                                         B0 88 88   ..ww.wwwwwwww...
+063C  88 88 88 88 88 77 B3 77-77 77 77 77 77 77 77
+
+; 064b is sample #21
+064b                                               B0   .....w.wwwwwwww.
+064C  88 88 88 88 88 88 88 88-B3 77 77 77 77 77 77 77   .........wwwwwww
+065C  77
+
+; 065d is sample #23
+065d     B0 88 88 88 88 88 88-88 88 B3 88 77 77 77 77   w...........wwww
+066C  77 77 77
+
+; sample #25
+066f           B0 88 88 88 88-88 88 88 88 B3 88 88 77   www............w
+067C  77 77 77 77 77
+
+; sample#27
+0681                 B0 88 88-88 88 88 88 88 88 B3 88   wwwww...........
+068C  88 88 77 77 77 77 77
+
+; sample#29
+0693                       B0-88 88 88 88 88 88 88 88   ..wwwww.........
+069C  B3 88 88 88 88 77 77 77-77
+
+; sample#31
+06a5                             B0 88 88 88 88 88 88   .....wwww.......
+06AC  88 88 B3 88 88 88 88 88-77 77 77
+
+; sample#33
+06b7                                   B0 88 88 88 88   ........www.....
+06BC  88 88 88 88 B3 88 88 88-88 88 88 77 77
+
+; sample#35
+06c9                                         B0 88 88   ...........ww...
+06CC  88 88 88 88 88 88 B3 88-88 88 88 88 88 88 77
+
+;------------------------------------------------------------------------
+; this was sample 5 to sample 35, a kinda important sequence of samples or so
+; i think it might emulate one effect only but dont ask which one.
+; -----------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+
+
+
+; 06db is sample #3
+06db                                               B0   ..............w.
+06DC  00 11 22 33 44 55 66 77-B3 88 99 AA BB CC DD EE   .."3DUfw........
+06EC  FF
+
+
+; 06ed is the sample #1 data according to the table at $09fd...
+06ed     B0 01 23 45 67 65 43-21 0F B3 FE DC BA 98 89   ...#EgeC!.......
+06FC  AB CD EF
+
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+
+; here is sample 4 up to sample 34. very much like in sample 5 to sample
+; 35, the samples here are quite similar to each other. This is another
+; indicator for my theory that sample 4 up to sample 35 (31 samples alltoge-
+; ther!) are being used to emulate one effect only.  (Or one waveform, or
+; one  WHATEVER. I will still have to figure....)
+
+; 06ff is sample #4
+06ff           B0 77 77 77 77-77 77 77 77 B0 77 77 77   ....wwwwwwww.www
+070C  77 77 77 77 77 B0 77 77-77 77 77 77 77 77 B3 77   wwwww.wwwwwwww.w
+071C  77 77 77 77 77 77 77
+
+
+; 0723 is sample #6
+0723                       B0-88 88 77 77 77 77 77 77   wwwwwww...wwwwww
+072C  B0 77 77 77 77 77 77 77-77 B0 77 77 77 77 77 77   .wwwwwwww.wwwwww
+073C  77 77 B3 77 77 77 77 77-77 77 77
+
+; 0747 is sample #8
+0747                                   B0 88 88 88 88   ww.wwwwwwww.....
+074C  77 77 77 77 B0 77 77 77-77 77 77 77 77 B0 77 77   wwww.wwwwwwww.ww
+075C  77 77 77 77 77 77 B3 77-77 77 77 77 77 77 77
+
+; 076b is sample #10
+076b                                               B0   wwwwww.wwwwwwww.
+076C  88 88 88 88 88 88 77 77-B0 77 77 77 77 77 77 77   ......ww.wwwwwww
+077C  77 B0 77 77 77 77 77 77-77 77 B3 77 77 77 77 77   w.wwwwwwww.wwwww
+078C  77 77 77
+
+; 078f is sample #12
+078f           B0 88 88 88 88-88 88 88 88 B0 77 77 77   www..........www
+079C  77 77 77 77 77 B0 77 77-77 77 77 77 77 77 B3 77   wwwww.wwwwwwww.w
+07AC  77 77 77 77 77 77 77
+
+
+; 07b3 is sample #14
+07b3                       B0-88 88 88 88 88 88 88 88   wwwwwww.........
+07BC  B0 88 88 77 77 77 77 77-77 B0 77 77 77 77 77 77   ...wwwwww.wwwwww
+07CC  77 77 B3 77 77 77 77 77-77 77 77
+
+
+; 07d7 is sample #16
+07d7                                   B0 88 88 88 88   ww.wwwwwwww.....
+07DC  88 88 88 88 B0 88 88 88-88 77 77 77 77 B0 77 77   .........wwww.ww
+07EC  77 77 77 77 77 77 B3 77-77 77 77 77 77 77 77
+
+; 07fb is sample #18
+07fb                                               B0   wwwwww.wwwwwwww.
+07FC  88 88 88 88 88 88 88 88-B0 88 88 88 88 88 88 77   ...............w
+080C  77 B0 77 77 77 77 77 77-77 77 B3 77 77 77 77 77   w.wwwwwwww.wwwww
+081C  77 77 77
+
+; 081f is sample #20
+081f           B0 88 88 88 88-88 88 88 88 B0 88 88 88   www.............
+082C  88 88 88 88 88 B0 77 77-77 77 77 77 77 77 B3 77   ......wwwwwwww.w
+083C  77 77 77 77 77 77 77
+
+; 0843 is sample #22
+0843                       B0-88 88 88 88 88 88 88 88   wwwwwww.........
+084C  B0 88 88 88 88 88 88 88-88 B0 88 88 77 77 77 77   ............wwww
+085C  77 77 B3 77 77 77 77 77-77 77 77
+
+; 0867 is sample #24
+0867                                   B0 88 88 88 88   ww.wwwwwwww.....
+086C  88 88 88 88 B0 88 88 88-88 88 88 88 88 B0 88 88   ................
+087C  88 88 77 77 77 77 B3 77-77 77 77 77 77 77 77
+
+; 088b is sample #26
+088b                                               B0   ..wwww.wwwwwwww.
+088C  88 88 88 88 88 88 88 88-B0 88 88 88 88 88 88 88   ................
+089C  88 B0 88 88 88 88 88 88-77 77 B3 77 77 77 77 77   ........ww.wwwww
+08AC  77 77 77
+
+; 08af is sample #28
+08af           B0 88 88 88 88-88 88 88 88 B0 88 88 88   www.............
+08BC  88 88 88 88 88 B0 88 88-88 88 88 88 88 88 B3 77   ...............w
+08CC  77 77 77 77 77 77 77
+
+; 08d3 is sample #30
+08d3                       B0-88 88 88 88 88 88 88 88   wwwwwww.........
+08DC  B0 88 88 88 88 88 88 88-88 B0 88 88 88 88 88 88   ................
+08EC  88 88 B3 88 88 77 77 77-77 77 77
+
+
+; 08f7 is sample #32
+08f7                                   B0 88 88 88 88   .....wwwwww.....
+08FC  88 88 88 88 B0 88 88 88-88 88 88 88 88 B0 88 88   ................
+090C  88 88 88 88 88 88 B3 88-88 88 88 77 77 77 77
+
+; 091b  is sample #34
+091b                                               B0   ...........wwww.
+091C  88 88 88 88 88 88 88 88-B0 88 88 88 88 88 88 88   ................
+092C  88 B0 88 88 88 88 88 88-88 88 B3 88 88 88 88 88   ................
+093C  88 77 77
+
+
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+
+
+
+; 093f is sample #2...
+
+               B0 00 00 11 11-22 22 33 33 B0 44 44 55   .ww.....""33.DDU
+094C  55 66 66 77 77 B0 88 88-99 99 AA AA BB BB B3 CC   Uffww...........
+095C  CC DD DD EE EE FF FF
+
+
+; 0963 seems to be sample 0.
+
+                           B0-00 11 22 33 44 55 66 77   .........."3DUfw
+096C  B0 77 66 55 44 33 22 11-00 B0 FF EE DD CC BB AA   .wfUD3".........
+097C  99 88 B3 88 99 AA BB CC-DD EE FF 03
+
+
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;------------------------------------------------------------------
+; Reassembly work (c) Antitrack Oct-17-1994
+;------------------------------------------------------------------
+
+
+
+0987 is either sample #36 or i am mistaken?  :-)
+0987                                      00 00 00 00   ................
+098C  00 00 00 00
+
+; well this IS sample 36 and should be sawtooth+ring modulation. Something
+; that *is* actually very rarely used together on the 64, coz it sounds
+; so faint that its nearly not there (if you ever tried it on the 64).
+;
+
+
+
+0990 is either sample #37 . it is getting calculated in realtime.... (voice1)
+0990              00 00 00 00-00 00 00 00 00 00 00 00   ................
+099C  00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00   ................
+09AC  00 00 00 00 00 00 00 00-
+
+09b4 seems to be sample #38. its real values are being calculated in realtime
+; it is used to emulate the 64's voice 2.
+09b4                          00 00 00 00 00 00 00 00   ................
+09BC  00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00   ................
+09CC  00 00 00 00 00 00 00 00-00 00 00 00
+
+09d8 is sample #39. calculated in realtime, used for voice3 emulation.
+09d8                                      00 00 00 00   ................
+09DC  00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00   ................
+09EC  00 00 00 00 00 00 00 00-00 00 00 00 00 00 00 00   ................
+
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;------------------------------------------------------------------
+; Reassembly work (c) Antitrack Oct-17-1994
+;------------------------------------------------------------------
+
+
+
+; let us do a little summary of the samples here. If you recall,
+; sample 0,1,2,3 seem to be independent. Sample 4 up to sample 35 (31 samples)
+; are very similar to each other. Sample 36 is not being
+; used for the obvious reason that it consists of zerobytes only and doesn't
+; make too much sense.
+
+; Sample 37, 38 and 39 are being calculated in realtime before being played.
+
+; My guess is that samples 0,1,2,3 emulate noise, sawtooth, pulse and
+; triangle, and the rest of the samples (31 of them, sample4 to sample35)
+; are trying to emulate the ring modulation, or the sync modulation, or
+; some special effect like that.
+
+; Well lets look again at sample 0, 1, 2, 3 here:
+
+; 0963 seems to be sample 0.
+
+                           B0-00 11 22 33 44 55 66 77   .........."3DUfw
+096C  B0 77 66 55 44 33 22 11-00 B0 FF EE DD CC BB AA   .wfUD3".........
+097C  99 88 B3 88 99 AA BB CC-DD EE FF 03
+
+; 06ed is the sample #1..
+06ed     B0 01 23 45 67 65 43-21 0F B3 FE DC BA 98 89   ...#EgeC!.......
+06FC  AB CD EF
+
+; 093f is sample #2...
+
+               B0 00 00 11 11-22 22 33 33 B0 44 44 55   .ww.....""33.DDU
+094C  55 66 66 77 77 B0 88 88-99 99 AA AA BB BB B3 CC   Uffww...........
+095C  CC DD DD EE EE FF FF
+
+; 06db is sample #3
+06db                                               B0   ..............w.
+06DC  00 11 22 33 44 55 66 77-B3 88 99 AA BB CC DD EE   .."3DUfw........
+06EC  FF
+
+; damn they are similar to each other too! ..... ?? Dunno what to say
+; about it. If thats one effect only too, then the SID got two
+; effects only, yea rite?  ;-)
+; I am not getting smart out of it...at the moment. Sorry....
+
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+
+
+; here at 09fc is the pointer table for the samples. they point to the
+; start of each sample.
+
+
+09FC  63 09 ED 06 3F 09 DB 06-FF 06 BB 05 23 07 CD 05   c...?.......#...
+0A0C  47 07 DF 05 6B 07 F1 05-8F 07 03 06 B3 07 15 06   G...k...........
+0A1C  D7 07 27 06 FB 07 39 06-1F 08 4B 06 43 08 5D 06   ..'...9...K.C.].
+0A2c  67 08 6F 06 8B 08 81 06-AF 08 93 06 D3 08 A5 06   g.o.............
+0A3c  F7 08 B7 06 1B 09 C9 06-87 09 90 09 B4 09 D8 09   ................
+
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+
+;------------------------------------------------------------------
+; Reassembly work (c) Antitrack Oct-17-1994
+;------------------------------------------------------------------
+
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+;--------------------------------------------------------------------------
+
+;
+;  init all DSP sound chip registers
+;
+
+0A4C CD 00      MOV     X,#$00        ; ***init dsp registers***
+0A4E 60         CLRC                  ; clear carry
+0A4F 7D         MOV     A,X           ; a=x=0
+0A50 C4 F2      MOV     $F2,A         ; dsp register 0, VOL Left voice 0
+0A52 8F 00 F3   MOV     $00,#$F3      ; dsp register VALUE, e.g VOL left = 0
+0A55 88 10      ADC     A,#$10        ; a= 10 : dsp register $10, vol left
+0A57 C4 F2      MOV     $F2,A         ; ../of voice 1  !
+0A59 8F 00 F3   MOV     $00,#$F3      ; voice 1 VOL left = 0
+0A5C 88 10      ADC     A,#$10        ; a= 10 : dsp register $20, vol left
+0A5E C4 F2      MOV     $F2,A         ; ../of voice 2  !
+0A60 8F 00 F3   MOV     $00,#$F3      ; voice 2 VOL left = 0
+0A63 88 10      ADC     A,#$10        ; a= 10 : dsp register $30, vol left
+0A65 C4 F2      MOV     $F2,A         ; ../of voice 3  !
+0A67 8F 00 F3   MOV     $00,#$F3      ; voice 3 VOL left = 0
+0A6A 88 10      ADC     A,#$10        ; a= 10 : dsp register $40, vol left
+0A6C C4 F2      MOV     $F2,A         ; ../of voice 4  !
+0A6E 8F 00 F3   MOV     $00,#$F3      ; voice 4 VOL left = 0
+0A71 88 10      ADC     A,#$10        ; a= 10 : dsp register $50, vol left
+0A73 C4 F2      MOV     $F2,A         ; ../of voice 5  !
+0A75 8F 00 F3   MOV     $00,#$F3      ; voice 5 VOL left = 0
+0A78 88 10      ADC     A,#$10        ; a= 10 : dsp register $60, vol left
+0A7A C4 F2      MOV     $F2,A         ; ../of voice 6  !
+0A7C 8F 00 F3   MOV     $00,#$F3      ; voice 6 VOL left = 0
+0A7F 88 10      ADC     A,#$10        ; a= 10 : dsp register $70, vol left
+0A81 C4 F2      MOV     $F2,A         ; ../of voice 7  !
+0A83 8F 00 F3   MOV     $00,#$F3      ; voice 7 VOL left = 0
+0A86 3D         INC     X             ; since this is a loop , we hereby
+0A87 C8 0A      CMP     X,#$0A        ; clear all DSP registers (00-09)
+0A89 D0 C4      BNE     $0A4F         ; of all voices!
+0A8B CD 0C      MOV     X,#$0C        ;
+0A8D 60         CLRC                  ;
+0A8E 7D         MOV     A,X           ; akku=x=$0c
+0A8F C4 F2      MOV     $F2,A         ;
+0A91 8F 00 F3   MOV     $00,#$F3      ; clear $0c, 0d, 0e, 0f
+0A94 88 10      ADC     A,#$10        ;
+0A96 C4 F2      MOV     $F2,A         ;
+0A98 8F 00 F3   MOV     $00,#$F3      ; clear $1c, 1d, 1e, 1f
+0A9B 88 10      ADC     A,#$10        ;
+0A9D C4 F2      MOV     $F2,A         ;
+0A9F 8F 00 F3   MOV     $00,#$F3      ; clear $2c, 2d, 2e, 2f
+0AA2 88 10      ADC     A,#$10        ;
+0AA4 C4 F2      MOV     $F2,A         ;
+0AA6 8F 00 F3   MOV     $00,#$F3      ; clear $3c, 3d, 3e, 3f
+0AA9 88 10      ADC     A,#$10        ;
+0AAB C4 F2      MOV     $F2,A         ;
+0AAD 8F 00 F3   MOV     $00,#$F3      ; clear $4c, 4d, 4e, 4f
+0AB0 88 10      ADC     A,#$10        ;
+0AB2 C4 F2      MOV     $F2,A         ;
+0AB4 8F 00 F3   MOV     $00,#$F3      ; clear $5c, 5d, 5e, 5f
+0AB7 88 10      ADC     A,#$10        ;
+0AB9 C4 F2      MOV     $F2,A         ;
+0ABB 8F 00 F3   MOV     $00,#$F3      ; clear $6c, 6d, 6e, 6f
+0ABE 88 10      ADC     A,#$10        ;
+0AC0 C4 F2      MOV     $F2,A         ;
+0AC2 8F 00 F3   MOV     $00,#$F3      ; clear $7c, 7d, 7e, 7f
+0AC5 3D         INC     X             ;
+0AC6 C8 10      CMP     X,#$10        ;
+0AC8 D0 C4      BNE     $0A8E         ; loop.
+0ACA 8F 3D F2   MOV     $3D,#$F2      ; register 3d: noise on/off.
+0ACD 8F 00 F3   MOV     $00,#$F3      ; in this case: noise for all voices off
+0AD0 8F 4D F2   MOV     $4D,#$F2      ; register 4d: echo on/off.
+0AD3 8F 00 F3   MOV     $00,#$F3      ; in this case: echo for all voices off
+0AD6 8F 6C F2   MOV     $6C,#$F2      ; reg 6c: ECEN: d5=0 means echo enable,
+0AD9 8F 20 F3   MOV     $20,#$F3      ; so d5=1 means echo disable, yea rite?
+0ADC 8F 0C F2   MOV     $0C,#$F2      ; main volume left = 7f
+0ADF 8F 7F F3   MOV     $7F,#$F3      ;
+0AE2 8F 1C F2   MOV     $1C,#$F2      ; main volume right = 7f
+0AE5 8F 7F F3   MOV     $7F,#$F3      ;
+0AE8 8F 5D F2   MOV     $5D,#$F2      ; this is tricky, its called "offset
+0AEB 8F 02 F3   MOV     $02,#$F3      ; address of source directory".
+
+; Basically it means that we have an important table at $0200 in this case
+; and i will describe the table: each table entry at $0200 contains a pointer
+; to the sampled data that your voice should play! The sampled data must be
+; in a special format called "BRR" (bit rate reductio) format, which I will
+; describe whenever we discuss the samples .
+
+0AEE 8F 30 F2   MOV     $30,#$F2      ;  voice 3 volume left = 7f
+0AF1 8F 7F F3   MOV     $7F,#$F3      ;
+0AF4 8F 31 F2   MOV     $31,#$F2      ;  voice 3 volume right = 7f
+0AF7 8F 7F F3   MOV     $7F,#$F3      ;
+0AFA 8F 35 F2   MOV     $35,#$F2      ;  ADSR(1) voice 3 = 67  (bit7=0 !!!)
+
+; bit7 = 0 of adsr(1) is very important. it tells us that the GAIN byte
+; gets operable. The gain byte is byte 7 of each voice, which will be used
+; soon... watch out... :-) Anyway I dont feel like typing in so much , but,
+
+            bit7  bit6  bit5  bit4  bit3  bit2  bit1  bit0
+
+ADSR(1) :   GAIN  DR2   DR1   DR0   AR3   AR2   AR1   AR0
+ADSR(2) :   SL2   SL1   SL0   SR4   SR3   SR2   SR1   SR0
+
+AR3-0 is Attack time,  DR0-2 is Decay time, SL0-2 Sustain low(?), SR0-4
+is Sustain/Release. (Hopefully. You gotta play around with these for quite
+a while till you get results, believe me...)
+
+
+0AFD 8F 67 F3   MOV     $67,#$F3      ;   67=01100111; DR=110, AR=0111
+0B00 8F 36 F2   MOV     $36,#$F2      ;  ADSR(2) voice 3 = 18
+0B03 8F 18 F3   MOV     $18,#$F3      ;  18=00011000  ratio=000, SR=11000=180ms
+0B06 8F 37 F2   MOV     $37,#$F2      ;  voice 3 gain!
+0B09 8F 7F F3   MOV     $7F,#$F3      ;  the GAIN value is set to %1111111
+
+; Now this was the gain stuff. Since bit 7 of reg 7, voice 3, is zero, it means
+; "direct designation": the value of GAIN is set directly according to
+; the rest of the bits in this byte. Thus, all to 1. Thus, maximum GAIN. What
+; ever GAIN was.
+
+0B0C 8F 40 F2   MOV     $40,#$F2      ; volume left voice 4 = 7f
+0B0F 8F 7F F3   MOV     $7F,#$F3      ;
+0B12 8F 41 F2   MOV     $41,#$F2      ; volume rite voice 4 = 7f
+0B15 8F 7F F3   MOV     $7F,#$F3      ;
+0B18 8F 45 F2   MOV     $45,#$F2      ; adsr voice 4 same like voice 3
+0B1B 8F 67 F3   MOV     $67,#$F3      ; adsr voice 4 same like voice 3
+0B1E 8F 46 F2   MOV     $46,#$F2      ; adsr voice 4 same like voice 3
+0B21 8F 18 F3   MOV     $18,#$F3      ; adsr voice 4 same like voice 3
+0B24 8F 47 F2   MOV     $47,#$F2      ; gain voice 4 7f , same like voice 3
+0B27 8F 7F F3   MOV     $7F,#$F3      ;
+0B2A 8F 20 F2   MOV     $20,#$F2      ; volume voice 2 left = 7f
+0B2D 8F 7F F3   MOV     $7F,#$F3      ;
+0B30 8F 21 F2   MOV     $21,#$F2      ; volume voice 2 rite = 7f (max, eh)
+0B33 8F 7F F3   MOV     $7F,#$F3      ;
+0B36 8F 25 F2   MOV     $25,#$F2      ; adsr voice 2 same like voice 3
+0B39 8F 67 F3   MOV     $67,#$F3      ; adsr voice 2 same like voice 3
+0B3C 8F 26 F2   MOV     $26,#$F2      ; adsr voice 2 same like voice 3
+0B3F 8F 18 F3   MOV     $18,#$F3      ; adsr voice 2 same like voice 3
+0B42 8F 27 F2   MOV     $27,#$F2      ; gain voice 4 same like voice 3
+0B45 8F 7F F3   MOV     $7F,#$F3      ; ----- end of DSP init
+0B48 8F 00 7C   MOV     $00,#$7C      ; clear mem 7c-7f of spc RAM memory
+0B4B 8F 00 7D   MOV     $00,#$7D      ;
+0B4E 8F 00 7E   MOV     $00,#$7E      ;
+0B51 8F 00 7F   MOV     $00,#$7F      ;
+0B54 8F 6C F2   MOV     $6C,#$F2      ; DSP register 6c:
+0B57 8F 38 F3   MOV     $38,#$F3      ;
+
+; 38: = %01101100  bit 7: soft reset is off, DSP ready to play or so
+                       6: =1  "MUTE" is turned on
+                       5: =1  ECEN (echo enable)   =1, means echo disabled
+                       4-0: 01100: Noise clock generator speed. Impessive, huh
+
+
+
+0B5A 8F 4C F2   MOV     $4C,#$F2      ; DSP register 4c, KEY ON
+0B5D 8F 1C F3   MOV     $1C,#$F3      ;
+
+; Now this is the important part, its the KEY ON thingie. :-) $1c is
+; binary %11100 and what does this tell you? It tells you that they use voice
+; 2, 3 and 4 for the emulation. Oh yeah! :)
+
+0B60 6F         RET                   ;
+
+;-------------------------------------------------------------------------
+;-------------------------------------------------------------------------
+;-------------------------------------------------------------------------
+
+The following routine calculates a new sample and puts it at sample #37's
+memory location (0990-09b4), or into sample #38's memory location if
+we are currently calculating for voice2, or into sample #39's memory location
+if we are calculating the data for voice3.
+
+The calculations are based on whatever waveform bits are set or not.
+
+
+0B61 8F FC 78   MOV     $FC,#$78      ; 78/79 points to 09fc which is the
+0B64 8F 09 79   MOV     $09,#$79      ; array of sample pointers
+0B67 5D         MOV     X,A           ; x=a=actual waveform
+0B68 5C         LSR     A             ; shift waveform left 4 bits
+0B69 5C         LSR     A             ; noise, pulse, sawtooth and triangle
+0B6A 5C         LSR     A             ; will now be at bit 3, bit 2, bit 1 and
+0B6B 5C         LSR     A             ; bit 0 of the akku
+0B6C C4 7C      MOV     $7C,A         ; 007c now gets the val of akku
+0B6E 7D         MOV     A,X           ; akku gets old val back
+0B6F 28 03      AND     A,#$03        ; check for bit 0/1: bit0:gate on/off,
+0B71 60         CLRC                  ; ...bit1: sync modulation bit
+0B72 84 7A      ADC     A,$7A         ; we add 00-03 (depending if the gate
+                                      ; and the sync bit are set) to the pulse
+                                      ; hi value.
+
+0B74 1C         ASL     A             ; and multiply by 4.
+0B75 1C         ASL     A             ; this value now is the index of which
+0B76 FD         MOV     Y,A           ; sample pointer to grab from the sample
+0B77 F7 78      MOV     A,[$78]+Y     ; pointer table!
+0B79 C4 74      MOV     $74,A         ; 74/75=pointer to acual sample
+0B7B FC         INC     Y             ; actual sample=[samplearray+index]
+0B7C F7 78      MOV     A,[$78]+Y     ;
+0B7E C4 75      MOV     $75,A         ;
+0B80 E4 7C      MOV     A,$7C         ; noise/pulse/saw/triangl  (bits3-0)
+                                      ; this command seems to be useless since
+                                      ; the accu soon gets a completely new
+                                      ; value.
+0B82 8D 00      MOV     Y,#$00        ;
+0B84 F7 78      MOV     A,[$78]+Y     ; put address of sample 0 into 76/77
+0B86 C4 76      MOV     $76,A         ;
+0B88 FC         INC     Y             ;
+0B89 F7 78      MOV     A,[$78]+Y     ;
+0B8B C4 77      MOV     $77,A         ;
+0B8D 8D 00      MOV     Y,#$00        ;
+0B8F F7 74      MOV     A,[$74]+Y     ;the 1stbyte of the actual sample 74/75...
+0B91 37 76      AND     A,[$76]+Y     ;..is ANDED w/ the first byte of sample 0
+0B93 D7 72      MOV     [$72]+Y,A     ;the RESULTING SAMPLE is being moved
+0B95 FC         INC     Y             ;to sample 37+x (72/73 point to it, they
+0B96 AD 24      CMP     Y,#$24        ;point to 0990 ....)
+                                      ; "sample 37+x" where x is voice number
+                                      ; -1 of the 64
+
+; let me sum up and recall here what happened. An *acutal sample* was being
+; chosen and calculated from the waveform bits noise/pulse/saw and triangle,
+; as well as from the wave bits SYNC and GATE. A pointer, 74/75, is set to this
+; calculated actual sample. Another pointer, 72/73, points to the very first
+; sample always. The *actual sample*'s bytes are ANDed with all the bytes from
+; sample 0, the resulting sample is located at sample #37/8/9's memory location,
+; from 0990-09b4 ($24 bytes as the loop says).
+
+; Its my guess that this resulting sample #37/8/9 is gonna be played sooner or
+; later!  :-)
+
+
+
+0B98 D0 F5      BNE     $0B8F         ;
+0B9A 6F         RET                   ;
+
+;-------------------------------------------------------------------------
+;-------------------------------------------------------------------------
+;-------------------------------------------------------------------------
+
+
+; this routine is a copy of the SPC700's RESET routine, which was discussed
+; in the famidev development group intensely already.
+; It basically gets the SPC data from the CPU (65c816)'s RAM into the
+; SPC700's ram.
+
+
+0B9B CD EF      MOV     X,#$EF        ;  normal start is $ffc0
+0B9D BD         MOV     SP,X          ;
+0B9E E8 00      MOV     A,#$00        ;
+0BA0 C6         MOV     (X),A         ;
+0BA1 1D         DEC     X             ;
+0BA2 D0 FC      BNE     $0BA0         ;
+0BA4 8F AA F4   MOV     $AA,#$F4      ;
+0BA7 8F BB F5   MOV     $BB,#$F5      ;
+0BAA 78 CC F4   CMP     $CC,#$F4      ;
+0BAD D0 FB      BNE     $0BAA         ;
+0BAF 2F 19      BRA     $0BCA         ;
+0BB1 EB F4      MOV     Y,$F4         ;
+0BB3 D0 FC      BNE     $0BB1         ;
+0BB5 7E F4      CMP     Y,$F4         ;
+0BB7 D0 0B      BNE     $0BC4         ;
+0BB9 E4 F5      MOV     A,$F5         ;
+0BBB CB F4      MOV     $F4,Y         ;
+0BBD D7 00      MOV     [$00]+Y,A     ;
+0BBF FC         INC     Y             ;
+0BC0 D0 F3      BNE     $0BB5         ;
+0BC2 AB 01      INC     $01           ;
+0BC4 10 EF      BPL     $0BB5         ;
+0BC6 7E F4      CMP     Y,$F4         ;
+0BC8 10 EB      BPL     $0BB5         ;
+0BCA BA F6      MOVW    YA,$F6        ;
+0BCC DA 00      MOVW    $00,YA        ;
+0BCE BA F4      MOVW    YA,$F4        ;
+0BD0 C4 F4      MOV     $F4,A         ;
+0BD2 DD         MOV     A,Y           ;
+0BD3 5D         MOV     X,A           ;
+0BD4 D0 DB      BNE     $0BB1         ;
+0BD6 1F 00 00   JMP     [$0000+X]     ;
+0BD9 C0         DI                    ;   reset vector
+0BDA FF         STOP                  ;
+
+
+;------------------------------------------------------------------
+; Reassembly work (c) Antitrack Oct-17-1994
+;------------------------------------------------------------------
+
+

+ 70 - 0
files/docs/snes/yoshi/SNES.0

@@ -0,0 +1,70 @@
+ _________________  _________________  _________________  _________________
+|                 ||                 ||                 ||                 |
+|                 ||                 ||                 ||                 |
+|       __________||                 ||        _________||      ___________|
+|                  |        |        ||             /    |
+|                 ||        |        ||            /     |                 |
+ __________       ||        |        ||        ___/_____  ___________      |
+|                 ||        |        ||                 ||                 |
+|                 ||        |        ||                 ||                 |
+|_________________||________|________||_________________||_________________|
+****************************************************************************
+SNES Documentation v2.30: Written by Yoshi
+****************************************************************************
+        Well, seems like you're interested in the SNES programming world.
+ 
+        First off, learn 65c816 assembly. This document will probably be
+        WAY over your head if you don't even understand basic opcodes. I
+        don't plan on adding a "how.to.code.in.65c816" section to this
+        document, *EVER*. Learn it yourself. I can help you with it, but
+        you need to learn the basics yourself. It's worth it in the long-
+        run, trust me.
+ 
+        This document currently covers more than ANY other document i've
+        ever seen: No, i'm not bragging. I'm stating a fact. I'm proud to be
+        the one to release this information, too. I feel everyone has the
+        right to know about all of this, especially if they're interested in
+        getting a career in the SNES-world.
+ 
+        If you have any information to send me, such as typo comments, or
+        information which is "wrong" or *NEW* information, do so! I'm always
+        updating this thing: the more the better. It's looking great so
+        far, and I plan on keeping the rate-of-progress steady.
+ 
+        For more information about moi, read on! :-)
+****************************************************************************
+        I'm 17 years old; brown hair, blue/grey eyes. 5 foot 10 inches
+        tall (175cm), 145 pounds (62.25kg). I am currently in my 5th
+        year of high school (I failed my senior year), attending Corvallis
+        High School in Corvallis, Oregon.
+ 
+        I'm currently without a job, but i'd love to do development work
+        in a CS-related job, ESPECIALLY SNES-related. I'm available! :-)
+ 
+        In my spare time, I enjoy writing stories (books, if you must know.
+        I love writing, so...), SNES documentation (ha ha ha), programming
+        (in just about anything and everything), biking, sleeping, sketch-
+        ing, and IRCing. You can *ALWAYS* find me on IRC at just about ANY
+        time of the day. Leave me a /MSG -info note (which is sent to me
+        via EMail, FYI), and i'll get it when I log in to check my mail.
+
+        As of January 24th, 1995, I will be 18 years old. I'm not employed
+        (vs. unemployed, where you've actually HAD a job). Dunno what'll
+        happen to me. Maybe i'll die. Who knows. I hope to move in with
+        a good friend of mine, but i'm too chicken to ask. I'd rather be
+        out on the street w/out foot than be told "No you can't" - it's a
+        huge flaw in my philosophy... Sorry.
+
+        You can reach via the following ways:
+                  InterNET: yoshi@CSOS.ORST.EDU (fast, and is preferred)
+                            yoshi@drift.winternet.com
+                       IRC: Yoshi
+                     Phone: 1+ 503-753-2431
+                 SnailMail: Jeremy Chadwick
+                            33811 Twin Maple Lane
+                            Corvallis, OR  97333
+                            USA
+****************************************************************************
+
+                                    December 28th, 1994
+                                                                - Yoshi

+ 606 - 0
files/docs/snes/yoshi/SNES.1

@@ -0,0 +1,606 @@
+ ----------------------------------------------------------------------------
+|rwd2?|Address|Title & Explanation                                           |
+||||||-----------------------------------------------------------------------|
+||||||                                                                       |
+||||||__  ?: Don't know what the statistics on this register are             |
+|||||____ 2: 2 byte (1 word) length register                                 |
+||||_____ d: Double-byte write required when writing to this register        |
+|||______ w: Writable register                                               |
+||_______ r: Readable register                                               |
+|                                                                            |
+|Words in brackets ( [] ) are the official "names" of the registers          |
+|Words in braces ( {} ) are different from the "real" SNES manual            |
+|Bits define 1 as "ON/ENABLE" and 0 as "OFF/DISABLE," unless otherwise stated|
+|Registers without any bits/defined-data can be assumed to be 8 bits in size |
+|and should only be read once.                                               |
+|----------------------------------------------------------------------------|
+|NOTE! I have renamed all occurances of "Plane {x}" to "BG{x+1}." This means |
+|stuff like "Plane 2" is now referred to as "BG3" - This is how it is done   |
+|(so i'm told) in the official SNES documentation, so for compatibility and  |
+|comprehension, i've renamed everything.                                     |
+|                                                                            |
+|I have also renamed "Sprites" to "OBJ", "objects," or "OAM" for the same    |
+|reason that I renamed "Plane" to "BG."                                      |
+|----------------------------------------------------------------------------|
+|rwd2?|Address|Title & Explanation                                           |
+|----------------------------------------------------------------------------|
+| w   |$2100  |Screen display register [INIDISP]                             |
+|     |       |x000bbbb              x: 0 = Screen on.                       |
+|     |       |                         1 = Screen off.                      |
+|     |       |                   bbbb: Brightness ($0-$F).                  |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2101  |OAM size register [OBSEL]                                     |
+|     |       |sssnnbbb              s: 000 =  8x8  or 16x16.                |
+|     |       |                         001 =  8x8  or 32x32.                |
+|     |       |                         010 =  8x8  or 64x64.                |
+|     |       |                         011 = 16x16 or 32x32.                |
+|     |       |                         100 = 16x16 or 64x64.                |
+|     |       |                         101 = 32x32 or 64x64.                |
+|     |       |                      n: Name selection (upper 4k word addr). |
+|     |       |                      b: Base selection (8k word seg. addr).  |
+|     |       |                                                              |
+|     |       |                                                              |
+| w 2 |$2102  |OAM address register [OAMADDL/OAMADDH]                        |
+|     |       |aaaaaaaa r000000m     a: OAM address.                         |
+|     |       |                      r: OAM priority rotation.               |
+|     |       |                      m: OAM address MSB.                     |
+|     |       |                                                              |
+|     |       |                                                              |
+| wd  |$2104  |OAM data register [OAMDATA]                                   |
+|     |       |???????? ????????                                             |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2105  |Screen mode register [BGMODE]                                 |
+|     |       |abcdefff              a: BG4 tile size (0=8x8, 1=16x16).      |
+|     |       |                      b: BG3 tile size (0=8x8, 1=16x16).      |
+|     |       |                      c: BG2 tile size (0=8x8, 1=16x16).      |
+|     |       |                      d: BG1 tile size (0=8x8, 1=16x16).      |
+|     |       |                      e: Highest priority for BG3 in MODE 1.  |
+|     |       |                      f: MODE definition.                     |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2106  |Screen pixelation register [MOSAIC]                           |
+|     |       |xxxxabcd              x: Pixel size (0=Smallest, $F=Largest). |
+|     |       |                      a: Affect BG4.                          |
+|     |       |                      b: Affect BG3.                          |
+|     |       |                      c: Affect BG2.                          |
+|     |       |                      d: Affect BG1.                          |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2107  |BG1 VRAM location register [BG1SC]                            |
+|     |       |xxxxxxab              x: Base address                         |
+|     |       |                     ab: SC size                              |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2108  |BG2 VRAM location register [BG2SC] -|                         |
+| w   |$2109  |BG3 VRAM location register [BG3SC]  |- Same as $2107.         |
+| w   |$210A  |BG4 VRAM location register [BG4SC] -|                         |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$210B  |BG1 & BG2 VRAM location register [BG12NBA]                    |
+|     |       |aaaabbbb              a: Base address for BG2.                |
+|     |       |                      b: Base address for BG1.                |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$210C  |BG3 & BG4 VRAM location register [BG34NBA]                    |
+|     |       |aaaabbbb              a: Base address for BG4.                |
+|     |       |                      b: Base address for BG3.                |
+|     |       |                                                              |
+|     |       |                                                              |
+| wd  |$210D  |BG1 horizontal scroll register [BG1HOFS]                      |
+|     |       |mmmmmaaa aaaaaaaa              a: Horizontal offset.          |
+|     |       |                               m: Only set with MODE 7.       |
+|     |       |                                                              |
+|     |       |This is an intruiging register. Like the types define, it has |
+|     |       |to be written to twice: The first byte holds the first 8 bits,|
+|     |       |and the second byte holds the last 3 bits. This makes a total |
+|     |       |of 11 bits for information. This only proves true for MODes   |
+|     |       |0 to 6. MODE 7 uses 13 bits instead of 11. As long as you're  |
+|     |       |not in MODE 7, you can store $00 in the 2nd byte for a smooth |
+|     |       |scrolling background.                                         |
+|     |       |                                                              |
+|     |       |                                                              |
+| wd  |$210E  |BG1 vertical scroll register   [BG1VOFS] -|                   |
+| wd  |$210F  |BG2 horizontal scroll register [BG2HOFS]  |                   |
+| wd  |$2110  |BG3 vertical scroll register   [BG2VOFS]  |                   |
+| wd  |$2111  |BG3 horizontal scroll register [BG3HOFS]  |- Same as $210D.   |
+| wd  |$2112  |BG3 vertical scroll register   [BG3VOFS]  |                   |
+| wd  |$2113  |BG4 horizontal scroll register [BG4HOFS]  |                   |
+| wd  |$2114  |BG4 vertical scroll register   [BG4VOFS] -|                   |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2115  |Video port control [VMAIN]                                    |
+|     |       |i000abcd              i: 0 = Addr-inc after writing to $2118  |
+|     |       |                             or reading from $2139.           |
+|     |       |                         1 = Addr-inc after writing to $2119  |
+|     |       |                             or reading from $213A.           |
+|     |       |                     ab: Full graphic (see table below).      |
+|     |       |                     cd: SC increment (see table below).      |
+|     |       |abcd|Result                                                   |
+|     |       |----|---------------------------------------------------------|
+|     |       |0100|Increment by 8 for 32 times (2-bit formation).           |
+|     |       |1000|Increment by 8 for 64 times (4-bit formation).           |
+|     |       |1100|Increment by 8 for 128 times (8-bit formation).          |
+|     |       |0000|Address increments 1x1.                                  |
+|     |       |0001|Address increments 32x32.                                |
+|     |       |0010|Address increments 64x64.                                |
+|     |       |0011|Address increments 128x128.                              |
+|     |       |----|---------------------------------------------------------|
+|     |       |                                                              |
+|     |       |                                                              |
+| w 2 |$2116  |Video port address [VMADDL/VMADDH]                            |
+|     |       |???????? ????????                                             |
+|     |       |                                                              |
+|     |       |                                                              |
+| w 2 |$2118  |Video port data [VMDATAL/VMDATAH]                             |
+|     |       |???????? ????????                                             |
+|     |       |                                                              |
+|     |       |According to bit 7 of $2115, the data can be stored as:       |
+|     |       |                                                              |
+|     |       |Bit 7|Register                   |Result                      |
+|     |       |-----|---------------------------|----------------------------|
+|     |       |  0  |Write to $2118 only.       |Lower 8-bits written then   |
+|     |       |     |                           |address is increased.       |
+|     |       |  0  |Write to $2119 then $2118. |Address increased when both |
+|     |       |     |                           |are written to (in order).  |
+|     |       |  1  |Write to $2119 only.       |Upper 8-bits written, then  |
+|     |       |     |                           |address is increased.       |
+|     |       |  1  |Write to $2118 then $2119. |Address increased when both |
+|     |       |     |                           |are written to (in order).  |
+|     |       |-----|---------------------------|----------------------------|
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$211A  |MODE7 settings register [M7SEL]                               |
+|     |       |ab0000yx             ab: (see table below).                   |
+|     |       |                      y: Vertical screen flip (1=flip).       |
+|     |       |                      x: Horizontal screen flip (1=flip).     |
+|     |       |                                                              |
+|     |       |ab|Result                                                     |
+|     |       |--|-----------------------------------------------------------|
+|     |       |00|Screen repetition if outside of screen area.               |
+|     |       |10|Character 0x00 repetition if outside of screen area.       |
+|     |       |11|Outside of screen area is back-drop screen in 1 colour.    |
+|     |       |--|-----------------------------------------------------------|
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$211B  |COS (COSINE) rotate angle / X Expansion [M7A]                 |
+| w   |$211C  |SIN (SIN)    rotate angle / X Expansion [M7B]                 |
+| w   |$211D  |SIN (SIN)    rotate angle / Y Expansion [M7C]                 |
+| w   |$211E  |COS (COSINE) rotate angle / Y Expansion [M7D]                 |
+| wd  |$211F  |Center position X (13-bit data only)    [M7X]                 |
+| wd  |$2120  |Center position Y (13-bit data only)    [M7Y]                 |
+|     |       |                                                              |
+|     |       |MODE 7 formulae for rotation/enlargement/reduction:           |
+|     |       |                                                              |
+|     |       |X2 = AB * X1-X0 + X0                                          |
+|     |       |Y2 = CD * Y1-Y0 + Y0                                          |
+|     |       |                                                              |
+|     |       |A = COS(GAMMA)*(1/ALPHA)      B = SIN(GAMMA)*(1/ALPHA)        |
+|     |       |C = SIN(GAMMA)*(1/BETA)       D = COS(GAMMA)*(1/BETA)         |
+|     |       |                                                              |
+|     |       |  GAMMA: Rotation angle.                                      |
+|     |       |  ALPHA: Reduction rates for X (horizontal).                  |
+|     |       |   BETA: Reduction rates for Y (vertical).                    |
+|     |       |X0 & Y0: Center coordinate.                                   |
+|     |       |X1 & Y1: Display coordinate.                                  |
+|     |       |X2 & Y2: Coordinate before calculation.                       |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2121  |Colour # (or pallete) selection register [CGADD]              |
+|     |       |xxxxxxxx              x: Address (color #).                   |
+|     |       |                                                              |
+|     |       |                                                              |
+| wd  |$2122  |Colour data register [CGDATA]                                 |
+|     |       |xxxxxxxx              x: Value of colour.                     |
+|     |       |                                                              |
+|     |       |SNES colour is 15 bit; 5 bits for red, green, and blue. The   |
+|     |       |order isn't RGB though: It's BGR (RGB reversed!).             |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2123  |Window mask settings register [W12SEL]                        |
+|     |       |abcdefgh              a: Disable/enable BG2 Window 2.         |
+|     |       |                      b: BG2 Window 2 I/O (0=IN).             |
+|     |       |                      c: Disable/enable BG2 Window 1.         |
+|     |       |                      d: BG2 Window 1 I/O (0=IN).             |
+|     |       |                      e: Disable/enable BG1 Window 2.         |
+|     |       |                      f: BG1 Window 2 I/O (0=IN).             |
+|     |       |                      g: Disable/enable BG1 Window 1.         |
+|     |       |                      h: BG1 Window 1 I/O (0=IN).             |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2124  |Window mask settings register [W34SEL]                        |
+|     |       |abcdefgh              a: Disable/enable BG4 Window 2.         |
+|     |       |                      b: BG4 Window 2 I/O (0=IN).             |
+|     |       |                      c: Disable/enable BG4 Window 1.         |
+|     |       |                      d: BG4 Window 1 I/O (0=IN).             |
+|     |       |                      e: Disable/enable BG3 Window 2.         |
+|     |       |                      f: BG3 Window 2 I/O (0=IN).             |
+|     |       |                      g: Disable/enable BG3 Window 1.         |
+|     |       |                      h: BG3 Window 1 I/O (0=IN).             |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2125  |Window mask settings register [WOBJSEL]                       |
+|     |       |abcdefgh              a: Disable/enable colour Window 2.      |
+|     |       |                      b: Colour Window 2 I/O (0=IN).          |
+|     |       |                      c: Disable/enable colour Window 1.      |
+|     |       |                      d: Colour Window 1 I/O (0=IN).          |
+|     |       |                      e: Disable/enable OBJ Window 2.         |
+|     |       |                      f: OBJ Window 2 I/O (0=IN).             |
+|     |       |                      g: Disable/enable OBJ Window 1.         |
+|     |       |                      h: OBJ Window 1 I/O (0=IN).             |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2126  |Window 1 left position register [WH0]                         |
+|     |       |aaaaaaaa              a: Position.                            |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2127  |Window 1 right position register [WH1] -|                     |
+| w   |$2128  |Window 2 left position register [WH2]   |- Same as $2126.     |
+| w   |$2129  |Window 2 right position register [WH3] -|                     |
+|     |       |                                                              |
+|     |       |I may have the Window numbers reversed; as in, $2126 may be   |
+|     |       |for Window 2, not Window 1; $2127 may be for Window 2, not    |
+|     |       |Window 1... and so on...                                      |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$212A  |Mask logic settings for Window 1 & 2 per screen [WBGLOG]      |
+|     |       |aabbccdd              a: BG4 parms -|                         |
+|     |       |                      b: BG3 parms  |- See table in $212B.    |
+|     |       |                      c: BG2 parms  |                         |
+|     |       |                      d: BG1 parms -|                         |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$212B  |Mask logic settings for Colour Windows & OBJ Windows [WOBJLOG]|
+|     |       |0000aabb              a: Colour Window parms (see table below)|
+|     |       |                      b: OBJ Window parms (see table below).  |
+|     |       |                                                              |
+|     |       |Hi-bit|Lo-bit|Logic                                           |
+|     |       |------|------|------------------------------------------------|
+|     |       |   0  |   0  |OR                                              |
+|     |       |   0  |   1  |AND                                             |
+|     |       |   1  |   0  |XOR                                             |
+|     |       |   1  |   1  |XNOR                                            |
+|     |       |------|------|------------------------------------------------|
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$212C  |Main screen designation [TM]                                  |
+|     |       |000abcde              a: OBJ/OAM disable/enable.              |
+|     |       |                      b: Disable/enable BG4.                  |
+|     |       |                      c: Disable/enable BG3.                  |
+|     |       |                      d: Disable/enable BG2.                  |
+|     |       |                      e: Disable/enable BG1.                  |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$212D  |Sub-screen designation [TD]                                   |
+|     |       |*** Same as $212C, but for the sub-screens, not the main.     |
+|     |       |                                                              |
+|     |       |Remember: When screen addition/subtraction is enabled, the    |
+|     |       |sub screen is added/subtracted against the main screen.       |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$212E  |Window mask main screen designation register [TMW]            |
+|     |       |*** Same as $212C, but for window-masks.                      |
+|     |       |                                                              |
+| w   |$212F  |Window mask sub screen designation register [TSW]             |
+|     |       |*** Same as $212E, but for the sub screen.                    |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2130  |Fixed color addition or screen addition register [CGWSEL]     |
+|     |       |abcd00ef             ab: Main (see table below).              |
+|     |       |                     cd: Sub (see table below).               |
+|     |       |                      e: 0 = Enable +/- for fixed colour.     |
+|     |       |                         1 = Enable +/- for sub screen.       |
+|     |       |                      f: Colour & char-data = direct color    |
+|     |       |                         data (MODE 3, 4 & 7 only).           |
+|     |       |                                                              |
+|     |       |ab|Result                                                     |
+|     |       |--|-----------------------------------------------------------|
+|     |       |00|All the time.                                              |
+|     |       |01|Inside window only.                                        |
+|     |       |10|Outside window only.                                       |
+|     |       |11|All the time.                                              |
+|     |       |--|-----------------------------------------------------------|
+|     |       |                                                              |
+| w   |$2131  |Addition/subtraction for screens, BGs, & OBJs [CGADSUB]       |
+|     |       |mrgsabcd              m: 0 = Enable + colour-data mode.       |
+|     |       |                         1 = Enable - colour-data mode.       |
+|     |       |                      r: See below for more info.             |
+|     |       |                      g: Affect back-area.                    |
+|     |       |                      s: Affect OBJs.                         |
+|     |       |                      a: Affect BG4.                          |
+|     |       |                      b: Affect BG3.                          |
+|     |       |                      c: Affect BG2.                          |
+|     |       |                      d: Affect BG1.                          |
+|     |       |                                                              |
+|     |       |*** 'r' is some sort-of "1/2 of colour data" on/off bit. When |
+|     |       |    the colour constant +/- or screen +/- is performed, desig-|
+|     |       |    nate whether the RGB result in the +/- area should be 1/2 |
+|     |       |    or not; the back-area is not affected.                    |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2132  |Fixed colour data for fixed colour +/- [COLDATA]              |
+|     |       |bgrdddddd             b: Set to change blue.                  |
+|     |       |                      g: Set to change green.                 |
+|     |       |                      r: Set to change red.                   |
+|     |       |                      d: Set colour constant data for +/-.    |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$2133  |Screen mode/video select register [SETINI]                    |
+|     |       |sn00pvshi                                                     |
+|     |       |                      s: Super-impose SFX graphics over ex-   |
+|     |       |                         ternal video (usually 0).            |
+|     |       |                      n: External mode (screen expand). When  |
+|     |       |                         sing MODE 7, enable.                 |
+|     |       |                      p: 0 = 256 resolution.                  |
+|     |       |                         1 = 512 sub screen resolution.       |
+|     |       |                      v: 0 = 224 vertical resolution.         |
+|     |       |                         1 = 239 vertical resolution.         |
+|     |       |                      s: See below for more info.             |
+|     |       |                      i: 0 = No interlace.                    |
+|     |       |                         1 = Interlaced display.              |
+|     |       |                                                              |
+|     |       |*** When in interlace mode, select either the 1-dot per line  |
+|     |       |    mode or the 1-dot repeated every 2-lines mode. If '1' is  |
+|     |       |    set in this bit, the OBJ seems to be reduced vertically   |
+|     |       |    by 1/2.                                                   |
+|     |       |                                                              |
+|     |       |*** Interlaced mode is used in the SNES test cartridge. It    |
+|     |       |    does flicker, but it gives a FULL 480 vertical resolution.|
+|     |       |                                                              |
+|     |       |                                                              |
+|r    |$2134  |Multiplication result register (low) [MPYL]                   |
+|r    |$2135  |Multiplication result register (middle) [MPYM]                |
+|r    |$2136  |Multiplication result register (high) [MPYH]                  |
+|     |       |*** Result is 8 bits long for $2134, $2135, and $2136.        |
+|     |       |                                                              |
+|     |       |                                                              |
+|r    |$2137  |Software latch for horizontal/vertical counter [SLHV]         |
+|     |       |aaaaaaaa                 a: Result.                           |
+|     |       |                                                              |
+|     |       |The counter value at the point when $2137 is read can be      |
+|     |       |latched. Data read is meaningless.                            |
+|     |       |                                                              |
+|     |       |                                                              |
+|r    |$2138  |Read data from OAM {OAMDATAREAD}                              |
+|r  2 |$2139  |Read data from VRAM {VMDATALREAD/VMDATAHREAD}                 |
+|r    |$213B  |Read data from CG-RAM (colour) {CGDATAREAD}                   |
+|r d  |$213C  |Horizontal scanline location [OPHCT]                          |
+|r d  |$213D  |Vertical scanline location  [OPVCT]                           |
+|     |       |*** Registers $213C and $213D are 9-bits in length.           |
+|     |       |                                                              |
+|     |       |                                                              |
+|r    |$213E  |PPU status flag & version number [STAT77]                     |
+|     |       |trm0vvvv              t: Time over (see below).               |
+|     |       |                      r: Range over (see below).              |
+|     |       |                      m: Master/slave mode select. Usually 0. |
+|     |       |                      v: Version # ($5C77 (???)).             |
+|     |       |                                                              |
+|     |       |*** Range: When the quantity of the OBJ (size is non-relevant)|
+|     |       |           becomes 33 pieces or more, '1' is set.             |
+|     |       |     Time: When the quantity of the OBJ which is converted to |
+|     |       |           8x8 is 35 pieces or more, '1' will be set.         |
+|     |       |                                                              |
+|     |       |                                                              |
+|r    |$213F  |PPU status flag & version number [STAT78]                     |
+|     |       |fl0mvvvv              f: Field # scanned in int. mode (0=1st).|
+|     |       |                      l: Set if external signal (light pen,   |
+|     |       |                         etc.) is installed/applied.          |
+|     |       |                      m: NTSC/PAL mode (0=NTSC, 1=PAL).       |
+|     |       |                      v: Version # ($5C78 (???)).             |
+|     |       |                                                              |
+|     |       |                                                              |
+|rw   |$2140  |[APUI00] -|                                                   |
+|rw   |$2141  |[APUI01]  |- Audio registers. See sound.doc and sid-spc.src.  |
+|rw   |$2142  |[APUI02]  |                                                   |
+|rw   |$2143  |[APUI03] -|                                                   |
+|     |       |                                                              |
+|     |       |                                                              |
+|rw   |$2180  |Read/write WRAM register [WMDATA]                             |
+|rw   |$2181  |WRAM data register (low byte) [WMADDL]                        |
+|rw   |$2182  |WRAM data register (middle byte) [WMADDM]                     |
+|rw   |$2183  |WRAM data register (high byte) [WMADDH]                       |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$4200  |Counter enable [NMITIMEN]                                     |
+|     |       |a0yx000b              a: NMI/VBlank interrupt.                |
+|     |       |                      y: Vertical counter.                    |
+|     |       |                      x: Horizontal counter.                  |
+|     |       |                      b: Joypad read-enable.                  |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$4201  |Programmable I/O port (out-port) [WRIO]                       |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$4202  |Multiplicand 'A' [WRMPYA]                                     |
+| w   |$4203  |Multiplier 'B' [WRMPYB]                                       |
+|     |       |*** Absolute multiplication used when using the two above reg-|
+|     |       |    isters. Formulae is: 'A (8-bit) * B (8-bit) = C (16-bit)'.|
+|     |       |    Result can be read from $4216.                            |
+|     |       |                                                              |
+|     |       |                                                              |
+| w 2 |$4204  |Dividend C [WRDIVL/WRDIVH]                                    |
+| w   |$4205  |Divisor B [WRDIVB]                                            |
+|     |       |*** Absolute division used when using the two above registers.|
+|     |       |    Formulae is 'C (16-bit) / B (8-bit) = A (16-bit)'.        |
+|     |       |    Result can be read from $4214, and the remainder read from|
+|     |       |    $4216.                                                    |
+|     |       |*** Operation will start when $4205 is set, and will be com-  |
+|     |       |    pleted after 16 machine cycles.                           |
+|     |       |                                                              |
+|     |       |                                                              |
+| w 2 |$4207  |Video horizontal IRQ beam position/pointer [HTIMEL/HTIMEH]    |
+|     |       |0000000x xxxxxxxx     x: Beam position.                       |
+|     |       |                                                              |
+|     |       |Valid values for x range from 0 to 339, due to overscan. The  |
+|     |       |timer is reset every scanline, so unless it's disabled, you'll|
+|     |       |receive an interrupt every time the beam hits the value given.|
+|     |       |                                                              |
+|     |       |                                                              |
+| w 2 |$4209  |Video vertical IRQ beam position/pointer [VTIMEL/VTIMEH]      |
+|     |       |0000000y yyyyyyyy     y: Beam position.                       |
+|     |       |                                                              |
+|     |       |Same as $4207, but valid values for y are 0 to 261 (based from|
+|     |       |overscan at the top of the screen).                           |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$420B  |DMA enable register [MDMAEN]                                  |
+|     |       |abcdefgh              a: DMA channel #7.                      |
+|     |       |                      b: DMA channel #6.                      |
+|     |       |                      c: DMA channel #5.                      |
+|     |       |                      d: DMA channel #4.                      |
+|     |       |                      e: DMA channel #3.                      |
+|     |       |                      f: DMA channel #2.                      |
+|     |       |                      g: DMA channel #1.                      |
+|     |       |                      h: DMA channel #0.                      |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$420C  |HDMA enable register.                                         |
+|     |       |*** Same as $420B, virtually.                                 |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$420D  |Cycle speed register [MEMSEL]                                 |
+|     |       |0000000x              x: 0 = Normal (2.68MHz).                |
+|     |       |                         1 = Fast (3.58MHz).                  |
+|     |       |                                                              |
+|     |       |Note that using the fast mode requires 120ns or faster EPROMs.|
+|     |       |                                                              |
+|     |       |                                                              |
+|r    |$4210  |NMI register [RDNMI]                                          |
+|     |       |x000vvvv              x: Disable/enable NMI.                  |
+|     |       |                      v: Version # ($5A22 (???))              |
+|     |       |                                                              |
+|     |       |Bit 7 can be reset to 0 by reading this register.             |
+|     |       |                                                              |
+|     |       |                                                              |
+|rw   |$4211  |Video IRQ register [TIMEUP]                                   |
+|     |       |i0000000              i: 0 = IRQ is not enabled.              |
+|     |       |                         1 = IRQ is enabled.                  |
+|     |       |                                                              |
+|     |       |This location MUST be read to clear a horizontal or vertical  |
+|     |       |raster interrupt. It's all relative to $4200. If the horiz-   |
+|     |       |ontal timer interrupt (bit 4, $4200) is set then the interrupt|
+|     |       |will be generated according to the position in $4207. Same    |
+|     |       |thing is for vertical timing (bit 5, $4200) but the position  |
+|     |       |will be read from $4209, not $4207.                           |
+|     |       |                                                              |
+|     |       |                                                              |
+|rw   |$4212  |Status register [HVBJOY]                                      |
+|     |       |xy00000a              x: 0 = Not in VBlank state.             |
+|     |       |                         1 = In VBlank state.                 |
+|     |       |                      y: 0 = Not in HBlank state.             |
+|     |       |                         1 = In HBlank state.                 |
+|     |       |                      a: 0 = Joypad not ready.                |
+|     |       |                         1 = Joypad ready.                    |
+|     |       |                                                              |
+|     |       |                                                              |
+|r    |$4213  |Programmable I/O port (in-port) [RDIO]                        |
+|     |       |                                                              |
+|     |       |                                                              |
+|r  2 |$4214  |Quotient of divide result [RDDIVL/RDDIVH]                     |
+|     |       |                                                              |
+|     |       |                                                              |
+|r  2 |$4216  |Multiplication or divide result [RDMPYL/RDMPYH]               |
+|     |       |                                                              |
+|     |       |                                                              |
+|r    |$4218  |Joypad #1 status register [JOY1L]                             |
+|     |       |abcd0000              a: A button (1=pressed).                |
+|     |       |                      b: X button (1=pressed).                |
+|     |       |                      c: Top-Left (1=pressed).                |
+|     |       |                      d: Top-Rght (1=pressed).                |
+|     |       |                                                              |
+|r    |$4219  |Joypad #1 status register [JOY1H]                             |
+|     |       |abcdefgh              a: B button (1=pressed).                |
+|     |       |                      b: Y button (1=pressed).                |
+|     |       |                      c: Select   (1=pressed).                |
+|     |       |                      d: Start    (1=pressed).                |
+|     |       |                      e: Up       (1=pressed).                |
+|     |       |                      f: Down     (1=pressed).                |
+|     |       |                      g: Left     (1=pressed).                |
+|     |       |                      h: Right    (1=pressed).                |
+|     |       |                                                              |
+|r    |$421A  |Joypad #2 status register [JOY2L] -|                          |
+|r    |$421B  |Joypad #2 status register [JOY2H]  |                          |
+|r    |$421C  |Joypad #3 status register [JOY3L]  |- Same as $4218 & $4219.  |
+|r    |$421D  |Joypad #3 status register [JOY3H]  |                          |
+|r    |$421E  |Joypad #4 status register [JOY4L]  |                          |
+|r    |$421F  |Joypad #4 status register [JOY4H] -|                          |
+|     |       |*** Joypad registers can be read w/ a 16-bit accum/X/Y and    |
+|     |       |    both the high and low bytes will received valid data.     |
+|     |       |                                                              |
+|     |       |                                                              |
+|----------------------------------------------------------------------------|
+|The following data is for DMA-transfers. 'x' represents the DMA channel #,  |
+|which ranges from 0 to 7. So, the following would represent each section:   |
+|DMA #0: $4300-$4305.                                                        |
+|DMA #1: $4310-$4315.                                                        |
+|....................                                                        |
+|DMA #7: $4370-$4375.                                                        |
+|----------------------------------------------------------------------------|
+| w   |$43x0  |DMA Control register [DMAPX]                                  |
+|     |       |vh0cbaaa              v: 0 = CPU memory -> PPU.               |
+|     |       |                         1 = PPU -> CPU memory.               |
+|     |       |                      h: For HDMA only:                       |
+|     |       |                         0 = Absolute addressing.             |
+|     |       |                         1 = Indirect addressing.             |
+|     |       |                      c: 0 = Auto address inc/decrement.      |
+|     |       |                         1 = Fixed address (for VRAM, etc.).  |
+|     |       |                      b: 0 = Automatic increment.             |
+|     |       |                         1 = Automatic decrement.             |
+|     |       |                      a: Transfer type:
+|     |       |                         000 = 1 address write twice: LH.     |
+|     |       |                         001 = 2 addresses: LH.               |
+|     |       |                         010 = 1 address write once.          |
+|     |       |                         011 = 2 addresses write twice: LLHH  |
+|     |       |                         100 = 4 addresses: LHLH              |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$43x1  |DMA Destination register [BBADX]                              |
+|     |       |xxxxxxxx              x: Low-byte address.                    |
+|     |       |                                                              |
+|     |       |*** The upper-byte address is assumed to be $21, making your  |
+|     |       |    access addresses $2100 to $21FF.                          |
+|     |       |                                                              |
+|     |       |                                                              |
+| w 2 |$43x2  |Source address [A1TXL/A1TXH]                                  |
+| w   |$43x4  |Source bank address [A1BX]                                    |
+| w 2 |$43x5  |DMA transfer size & HDMA address register [DASXL/DASXH]       |
+|     |       |*** When using DMA, $43x5 defines the # of bytes to be trans- |
+|     |       |    ferred via DMA itself. When using HDMA, $43x5 defines the |
+|     |       |    data address ($43x5 = low byte, $43x6 = hi byte).         |
+|     |       |                                                              |
+|     |       |                                                              |
+| w   |$43xA  |Number of lines for HDMA transfer [NTRLX]                     |
+|     |       |cxxxxxxx              c: Continue (0=yes, 1=no (???)).        |
+|     |       |                      x: # of lines to transfer.              |
+|----------------------------------------------------------------------------|
+|Additional information follows.                                             |
+|Most of the following information is for SMC files, and where the header    |
+|info is kept in memory, etc. etc. etc...                                    |
+|----------------------------------------------------------------------------|
+|rw   |$FEED  |UNDOCUMENTED REGISTER: Felon's banana register [FBNANACNT]    |
+|     |       |rcnnnnnn              r: Ripe bit (0=ripe, 1=rotten).         |
+|     |       |                      c: Colour bit (0=yellow, 1=green).      |
+|     |       |                      n: Number of bananas.                   |
+|     |       |                                                              |
+|     |       |*** This register counts the number of bananas Felon currently|
+|     |       |    has in his possession... (Who the hell is Felon?!).       |
+|     |       |                                                              |
+|     |       |*** According to numerous sources, this register can be used  |
+|     |       |    to calculate pi to the 5-billionth digit in 20 clock      |
+|     |       |    cycles. The number of cycles corresponds to Felon's age,  |
+|     |       |    increasing by 1 every 365 days (1 year). It is increased  |
+|     |       |    by 2 every leap year.                                     |
+|     |       |                                                              |
+|     |       |                                                              |
+|rw   |$FFC0  |Cartridge title.                                              |
+|rw   |$FFD6  |ROM/RAM information on cart.                                  |
+|rw   |$FFD7  |ROM size.                                                     |
+|rw   |$FFD8  |RAM size.                                                     |
+|rw   |$FFD9  |Developer ID code.                                            |
+|rw   |$FFDB  |Version number.                                               |
+|rw   |$FFDC  |Checksum complement.                                          |
+|rw   |$FFDE  |Checksum.                                                     |
+|rw   |$FFEA  |NMI vector/VBL interrupt.                                     |
+|rw   |$FFEC  |Reset vector.                                                 |
+ ----------------------------------------------------------------------------

+ 21 - 0
files/docs/snes/yoshi/SNES.2

@@ -0,0 +1,21 @@
+ ----------------------------------------------------------------------------
+|The SNES has some interesting colour characteristics. The colour, theoret-  |
+|ically is 15 bit; each RGB value (Red, Green, and Blue) has 5 bits for each |
+|colour.                                                                     |
+|                                                                            |
+|When it comes to putting the colour data into $2122, the format (in binary) |
+|is the following:                                                           |
+|  b: Blue                   ?bbbbbgg gggrrrrr                               |
+|  g: Green                                                                  |
+|  r: Red                                                                    |
+|  ?: The infamous bit-of-confusion. :-)                                     |
+|                                                                            |
+|A quick colour chart could be the following:                                |
+|  $7FFF [0111 1111 1111 1111]: White.                                       |
+|  $001F [0000 0000 0001 1111]: Red.                                         |
+|  $03E0 [0000 0011 1110 0000]: Green.                                       |
+|  $7C00 [0111 1100 0000 0000]: Blue.                                        |
+|  $7C1F [0111 1100 0001 1111]: Purple.                                      |
+|  $7FE0 [0111 1111 1110 0000]: Aqua.                                        |
+|  $03FF [0000 0011 1111 1111]: Yellow.                                      |
+ ----------------------------------------------------------------------------

+ 89 - 0
files/docs/snes/yoshi/SNES.3

@@ -0,0 +1,89 @@
+ ----------------------------------------------------------------------------
+|For those of you who don't know how the SNES does do it's graphics, it      |
+|uses tiles (surprise surprise!).                                            |
+|                                                                            | 
+|There are different MODEs on the SNES; the most famous being MODE 7.        |
+|Most people think that $2106 (Screen Pixelation: Look in SNES.1 for an ex-  |
+|planation on this register) is MODE 7. *** THIS IS NOT MODE 7!!! ***.       |
+|So, the next time the pixels get really "big" (almost making them look like |
+|look like IBM-clone 320x200x256 MODE 13h graphics), and your friend says    |
+|"WOW! MODE 7 is really awesome," punch him/her in the nose for me. Just     |
+|joking. :-)                                                                 |
+|                                                                            |
+|I'll be explaining MODE 1. I know how MODE 7 works, but since i've never    |
+|used it, don't plan on me explaining it in the near future. Sorry to those  |
+|who were looking for a MODE 7 document. Look elsewhere...                   |
+|                                                                            |
+|MODE   # of BGs       MaxColour/Tile  Palettes      Colours                 |
+|----------------------------------------------------------------------------|
+|0      4              4               8             32                      |
+|1      3              16/16/4         8             128                     |
+|                                                                            |
+|MODE 0 is good for geometric shapes (if you were going to rotate a wire-    |
+|frame cube, or something like that), basic star scrolls, or a very 'bland'  |
+|text scroller... it's pretty cool and doesn't take up much space.           |
+|                                                                            |
+|I'm going to explain MODE 1, since MODE 0 is the same thing but with less   |
+|bitplanes. :-)                                                              |
+|                                                                            |
+|MODE 1 is really best for things; detailed star scrolls, text scrollers,    |
+|geometric shapes, and filled objects. It's the most common used MODE in the |
+|the professional SNES programming world.                                    |
+|                                                                            |
+|You need to "setup the plane" to tell it what tile goes where. If you want  |
+|demo-code, check out 'test.asm' in 'test.lzh'.                              |
+|----------------------------------------------------------------------------|
+|So, lets assume we have a character (a 8x8 tile) which we want to work with |
+|to figure out the SNES's colour scheme:                                     |
+|                                                                            |
+|TestCHR1       dcb $00,$00,$00,$00,$00,$00,$00,$00 ; '@'                    |
+|TestCHR2       dcb $00,$3C,$4E,$5E,$5E,$40,$3C,$00 ; '@'                    |
+|                                                                            |
+|You're probably wondering how the two lines above turn into actual graphic  |
+|data on your monitor or television set. Very simple. Consider each byte     |
+|(each new $xx statement) a new pixel line. Tile size is 8x8.                |
+|                                                                            |
+|      %00000000          = $00                                              |
+|      %00000000          = $00    This is TestCHR1                          |
+|      %00000000          = $00                                              |
+|      %00000000          = $00                                              |
+|      %00000000          = $00                                              |
+|      %00000000          = $00                                              |
+|      %00000000          = $00                                              |
+|      %00000000          = $00                                              |
+|                                                                            |
+|      %00000000          = $00                                              |
+|      %00111100          = $3C    This is TestCHR2                          |
+|      %01001110          = $4E                                              |
+|      %01011110          = $5E                                              |
+|      %01011110          = $5E                                              |
+|      %01000000          = $40                                              |
+|      %00111100          = $3C                                              |
+|      %00000000          = $00                                              |
+|                                                                            |
+|The at-symbol ('@') is visible in TestCHR2. Now you're probably wondering   |
+|"Well, that tells me how to define a pixel on and off; what about the colour|
+|itself!" Once again, very simple, but a tad more complex:                   |
+|                                                                            |
+|If you have a 0 for bitplane 0, a 0 for bitplane 1, a 0 for bitplane 2,     |
+|and a 0 for bitplane 3, you get color #0; eg.:                              |
+|                       0000 = Color #0                                      |
+|                       ||||___________Bitplane 0                            |
+|                       |||__________Bitplane 1                              |
+|                       ||_________Bitplane 2                                |
+|                       |________Bitplane 3                                  |
+|                                                                            |
+|So, now, think about a 0 for bitplane 0, a 1 for bitplane 1 and 2, and a 0  |
+|for bitplane 3:                                                             |
+|                       0110 = Color #6                                      |
+|                       ||||___________Bitplane 0                            |
+|                       |||__________Bitplane 1                              |
+|                       |_________Bitplane 2                                 |
+|                       |________Bitplane 3                                  |
+|                                                                            |
+|Keep in mind, this is the best explanation i've ever seen done about SNES   |
+|pixel color definition. Until I see better, I'd have to say this is the     |
+|best it's gonna get.                                                        |
+|The result above gives you the color # per pixel; it's interesting. It's an |
+|"overlay" method, so-to-speak, not to confuse this w/ main and sub-screens. |
+ ----------------------------------------------------------------------------

+ 23 - 0
files/docs/snes/yoshi/SNES.4

@@ -0,0 +1,23 @@
+ ----------------------------------------------------------------------------
+|MODE   # of BGs       MaxColour/Tile  Palettes      Colours                 |
+|----------------------------------------------------------------------------|
+|0      4              4               8             32                      |
+|1      3              16/16/4         8             128                     |
+|2      ?              ???             ?             ???                     |
+|3      2              256 & 16        1 & 8         256 & 32                |
+|4      2              256 & 4         1 & 8         256 & 32                |
+|5      ?              ???             ?             ???                     |
+|6      ?              16              8             128 (Interlaced mode)   |
+|7      ?              256             1             256                     |
+|----------------------------------------------------------------------------|
+|Parms which have question marks ("?") mean that I don't know their stats.   |
+|Any information would be greatly appreciated! I have personally tested some |
+|of the MODEs (MODE 0, 1, and 3), but none of the rest.                      |
+|----------------------------------------------------------------------------|
+|MODE 1's "16/16/4" means you can have 16 colours per tile on BG1 and BG2,   |
+|but on BG3 you can only have 4.                                             |
+|----------------------------------------------------------------------------|
+|MODE 3 can have 256 colours on the first plane, but only 16 on the second.  |
+|MODE 4 isn't the exact same as MODE 3 (as v2.20 of my document stated), but |
+|i'm waiting for someone to tell me the differences...                       |
+ ----------------------------------------------------------------------------

+ 48 - 0
files/docs/snes/yoshi/SNES.5

@@ -0,0 +1,48 @@
+ ----------------------------------------------------------------------------
+|The OBJs use a lookup table that contains info on their X and Y position on |
+|the screen, their size, if they're flipped vertically or horizontally, their|
+|colour, and the actual data.                                                |
+|                                                                            |
+|The format you need to make the table is as follows:                        |
+|                                                                            |
+|                                                                            |
+|Spr. #   Size   Offset        Explanation                                   |
+|----------------------------------------------------------------------------|
+|   0     Byte   0             xxxxxxxx           x: X-location.             |
+|         Byte   1             yyyyyyyy           y: Y-location.             |
+|         Byte   2             abcdeeeC           a: Vertical flip.          |
+|                                                 b: Horizontal flip.        |
+|                                                 c: Playfield priority.     |
+|                                                 d: Playfield priority.     |
+|                                                 e: Pallete #.              |
+|         Byte   3             CCCCCCCC           C: Character data.         |
+|                                                                            |
+|   1     Byte   4             xxxxxxxx           x: X-location.             |
+|         Byte   5             yyyyyyyy           y: Y-location.             |
+|         Byte   6             abcdeeeC           a: Vertical flip.          |
+|                                                 b: Horizontal flip.        |
+|                                                 c: Playfield priority.     |
+|                                                 d: Playfield priority.     |
+|                                                 e: Pallete #.              |
+|         Byte   7             CCCCCCCC           C: Character data.         |
+|...and so on...                                                             |
+|----------------------------------------------------------------------------|
+|Continue this table all the way down to OBJ #127 (out of 128). Don't think  |
+|you're finished quite yet: There is one more table of data required.        |
+|                                                                            |
+|2 bits are defined for each OBJ (eg. byte #0 holds the info for OBJ 0, 1, 2,|
+|and 3; byte #1 holds the info for OBJ 4, 5, 6, and 7). Therefore, 128/4 is  |
+|32 bytes of data for the following table:                                   |
+|                                  ab                                        |
+|                                  ||____Size toggle bit.                    |
+|                                  |_____MSB of X-position bit.              |
+|                                                                            |
+|So, the 4 bytes/sprites + the block are put into the OAM table by consec-   |
+|utive writes to the OAM data register. You first should set the OAM address |
+|to $0000, then shove your data into it.                                     |
+|                                                                            |
+|If you don't set the block after the OAM as well, the results are bad. All  |
+|the data for the MSB stuff wouldn't be defined correctly, which would result|
+|in your entire OBJ table being wacko. Have atleast some 0's there or a table|
+|which you really want to use in the long run.                               |
+ ----------------------------------------------------------------------------

+ 19 - 0
files/docs/snes/yoshi/SNES.6

@@ -0,0 +1,19 @@
+ ----------------------------------------------------------------------------
+|I have never used an actual Super MagiComm before, and I would strongly re- |
+|commend not using these unless you know what each one does for sure. If you |
+|decide to write any sort-of operating system for the SNES, please do get in |
+|touch with me.                                                              |
+|                                                                            |
+|The below registers i've never tested, or had tested. If you end up killing |
+|your console unit because of this, I TAKE NO RESPONSIBILITY.                |
+|                                                                            |
+|Location    Value returned when read         Value input when written       |
+|----------------------------------------------------------------------------|
+|$C000:      Input Register                                                  |
+|$C002:                                       Digital Output Register        |
+|$C004:      Main Status Register                                            |
+|$C005:      Data Register                    Data Register                  |
+|$C007:      Digital Input Register           Disk Control Register          |
+|$C008:      Parallel Data                    Parallel Data                  |
+|$C009:      Parallel Status                                                 |
+ ----------------------------------------------------------------------------

+ 15 - 0
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+ ----------------------------------------------------------------------------
+|Here's a really basic memory map of the SNES's memory. Thanks to Geggin of  |
+|Censor for supplying this. Reminder: this is a memory map in MODE 20.       |
+|----------------------------------------------------------------------------|
+|Bank   |Address       |Description                                          |
+|-------|--------------|-----------------------------------------------------|
+|$00-$3F|$0000-$1FFF   |Scratchpad RAM. Set D-reg here if you'd like (I do)  |
+|       |$2000-$5FFF   |Reserved (PPU, DMA)                                  |
+|       |$6000-$7FFF   |Expand (???)                                         |
+|       |$8000-$FFFF   |ROM (for code, graphics, etc.)                       |
+|$70    |$0000-$7FFF   |SRAM (BRAM) - Battery RAM                            |
+|$7E    |$0000-$1FFF   |Scratchpad RAM (same as bank $00 to $3F)             |
+|       |$2000-$FFFF   |RAM (for music, or whatever)                         |
+|$7F    |$0000-$FFFF   |RAM (for whatever)                                   |
+ ----------------------------------------------------------------------------

+ 22 - 0
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+I'd like to thank the following people:
+
+        Jeremy Gordon: Thanks for supplying me your sprite documentation. I
+                       don't think this doc. would be complete without it!
+                       Also for 65816 v2.0! Excellent assembler.
+            AntiTrack: Thanks for the source! Next time, i'll ask! (grin)
+                Toshi: I know you can't say much due to your job, but I
+                       really appreciate all the moral support you've given
+                       me. I wish I could show you how much it means to me.
+                minus: Work on TRASM some more! Fix' dem bugs! :-)
+                 Jehu: Keep in touch. Get back to me about the job!
+              Clay C.: Without you, who knows where i'd be.
+                Troy_: I appreciate the logos!
+     Geggin of Censor: Thanks for the memory map!
+    D. Messiah of PiR: ...for all the EMail, long talks, 'n all that jazz.
+                       You're like a brother to me.
+
+Hellos and "HEY! You're important too!"s go out to:
+
+        III_Demon, JackRippr, Amos, Norm, Hardware, Skywalkr, KingPhish,
+        felon, AntiTrack, IRSMan, sendog, SHORYUKEN, _grazzt, RuGalz, and
+        all the rest of the #SNES and famidev-gang.

+ 450 - 0
files/docs/snes/yoshi/SOUND.DOC

@@ -0,0 +1,450 @@
+From PARADIS@htu.tu-graz.ac.at Fri Mar 25 08:41:08 1994
+
+        The Bloody SPC-700
+        ------------------
+
+
+A try to stumble into the inner secret of a nasty chip.
+
+By Antitrack exclusively for the FAMIDEV development group.
+
+
+Chapter 1:
+----------
+
+
+FACTS
+
+* The SPC 700 is a very stupid sound chip with about the worst 
+handling
+  that you have seen in your lifetime.
+
+* This chip is a co processor. He has a quite large instruction set
+  (contrary to the Amiga's COPPER, who has a very small one) and 64KB 
+RAM
+  memory, of which you can use atleast 32KB.  (or so)
+
+* All program and data that is supposed to be run by this chip must 
+be'
+  moved to the SPC's own ram with a small loop that pokes each byte of
+  your SPC assembler program and (e.g. sample-)data into four memory
+  locations : $2140 - $2143. They are your only chance to communicate 
+with
+  the SPC.
+
+* These four memory locations have different meanings for read and 
+write;
+  if you read (LDA) $2140, you get the data from memory loc. 00f4 (or 
+so)
+  of the sound chip.
+
+* On power-on, the SPC 700 jumps (much like the main processor) to a 
+very
+  small ROM area that resides from $ffc0 to $ffff inside the SPC.
+  (This chip REALLY follows the black box principle, eh...) This 
+program
+  at $ffc0 is waiting to get the data in the right format on his 
+input ports
+  at $00f4/5/6/7 , which are $2140/1/2/3 from the 65c816's (e.g. 
+your's )
+  point of view.
+
+* Your main program will therefore have to follow the SPC's 
+conditions and
+  poke all the program and data for the SPC into 2140/1/2/3 in a 
+special
+  order.
+
+* When transmission is completed, you will also have transmitted the 
+start
+  address of your SPC code, and the SPC will start to execute your 
+program
+  there.
+
+
+
+--------------------QUESTIONS.
+
+
+Q: How do I move my program and data to the SPC then, what format do 
+I have
+to use?
+
+
+A: First, your SPC data/code has to be moved from ROM to the extra 
+RAM at
+e.g. $7f0000 . Dont ask me why it has to be in RAM, probably it doesnt
+but all the existing routines that send data to the SPC do something 
+like
+that.
+
+Your data/code has to be in groups which I will call "chunks". A 
+valid chunk
+looks like that:
+
+first word: number of bytes to transmit to SPC           -+
+sec. word : start address where to move data to the SPC   |  one chunk
+byte 4-???? : your data/code                             -+
+
+You can have as many chunks as you want to , but the last chunk must 
+be like
+that:
+
+first word : $0000
+second word: Start address of your code.
+
+
+Q: So if you are right, this means: After I transmitted all my code 
+and
+data, and my own SPC code takes over the control, I might encounter 
+problems
+if my SPC program has to communicate with the outer world (the 
+65c816).
+What if the main program wants to change sounds? What if a background 
+melody
+shall always play on two voices, and extra two voices will be used for
+sound effects whenever the player sprite e.g. picks up an object?
+
+A: That is sure a point. Your own code will have to look at memory 
+locations
+$00f4/00f5/00f6/00f7 , because they are the only accessible from 
+outside
+at $2140/1/2/3. The easiest way would be: As soon as any of $f4-$f7 
+change,
+jump into the Boot ROM at $ffc0 (?) so the SPC is executing his 
+receive
+routine again. Then you *probably* can send another SPC chunk with new
+sound and code to the SPC....
+
+Q: This only helps if a complete new tune is to be played, this 
+doesnt help
+if a melody using two voices shall still remain....
+
+A: Thats true. The best approach is to send own command bytes to the 
+SPC and
+your SPC code has to check out $f4-$f7 constantly and react to it.....
+A command byte like $00 could mean: sound off,
+                    $01           : play tune 1
+                    .
+                    .
+                    .
+                    $0f          : play tune $0f
+                    $10           : play jingle (fx) 01
+                    .
+                    .
+                    .
+                    $ff           : jump to $ffc0 (??) the receive 
+ROM routine
+
+
+
+Q: is there another approach?
+
+A: Yes there is. As you probably know, all important addresses of the
+SPC 700 reside inside its own RAM's zeropage:
+
+Address         / register          / usage
+0000            Volume left
+0001            Volume right
+0002            Pitch low
+0003            Pitch high          (The total 14 bits of pitch 
+height)
+0004            SRCN                Designates source number from 0-
+255
+0005            ADSR 1
+0006            ADSR 2
+0007            GAIN            Envelope can be freely designated by 
+your code
+0008            ENVX            Present val of envelope with DSP 
+rewrites
+0009            VALX            Present wave height val
+
+(and so on...)
+
+Your approach would be to move only sample data there, and/or (lots 
+of) very
+small chunks of data with a target address in the zeropage, and a 
+starting
+address of e.g. $ffc0. The small chunks would access zeropage 
+addresses e.g.
+for the volume etc and thus result in tones; if this is done every 
+frame
+you might end up with a music player quite similar to the C64 styled 
+ones.
+
+
+Q: So anyway, in what format exactly do I have to move data to the 
+SPC?
+
+A: I have the following source code for you, but let me explain it a 
+bit
+BEFORE you start to dig into it.
+
+I've already mentioned the general "chunk" format. The loop does the 
+following:
+
+
+- move ram destination address to $2142/3 (akku: 16 bit)
+- move either #$00 or #$01 into 2141, this depends if you have more 
+than $0100
+  bytes of data for the SPC;
+
+- first time (first chunk you transmit): move constant #$cc into 2140
+
+- loop: poke each byte that you want to be transmitted into 2140 
+(word)
+  the higher 7-15 bits of your accu-word contain the number of bytes 
+already
+  moved (e.g. 00 on the start)
+
+- cmp $2140 with this number of bytes already moved (lower 8 bits of 
+this
+  number only!) and wait if its not equal.
+
+- until the loop is over.
+
+- for the next chunk header this is repeated, but not #$cc is moved 
+into
+  2140 but "nn" (lobyte of number of bytes moved) +3 or +6 if it was 
+00 when
+  +3 was used.
+
+EXAMPLE:
+
+        move #$0400 to 2142 /word access
+
+        move #$01 to 2141
+        move #$cc to 2140
+
+        move "gg00" to 2140 where "gg" is the first real code/data 
+byte for
+                            the SPC
+
+        wait till 2140 is #$00
+
+        move hh01 to 2140 where "hh" is the second byte of code or 
+data for SPC
+
+        wait till 2140 is #$01
+
+        move ii02 to 2140 where "ii" is the 3rd byte of data for the 
+SPC....
+
+        wait till 2140 is #$02
+
+
+       lets say "ii" was the last byte. Now we add #$04 (3+carry) to 
+#$02
+       (#$02 being the number-1 of how many bytes we moved to the 
+SPC), we
+       will push it onto the stack), now :
+
+       fetch the next header , poke target RAM address into $2142 
+(word)
+       poke 00 or 01 into 2141 depending of how many bytes to send,
+       poke #$06 into 2140 (06 : number of bytes sent from last chunk-
+1 + 3 )
+
+
+I think I got this scheme pretty much right this time. Now, is PLEASE 
+someone
+going to donate their home-brewed SPC dis/assemblers to me? Oh pretty 
+please,
+I hate silent SNES's !  :)
+
+
+Source code follows, reassembled from a PAN/Baseline demo "xmas wish 
+92/93":
+----------------------------------------------------------------------
+------
+
+
+; entry to the code starts here
+
+
+            SEP #$30       ; x y a set to 8 bit length
+            LDA #$FF       ; ff into audio0w (write)
+            STA $2140
+            REP #$10       ; x,y: 16 bit length
+            LDX #$7FFF
+l0DB5B      LDA $018000,X  ; move rom music data to ram at $7f0000
+            STA $7F0000,X
+            LDA $028000,X  ; move rom music data to ram at $7f0000
+            STA $7F8000,X
+            DEX
+            BPL l0DB5B
+            LDA #$80       ; screen on , probably not important at all
+            STA $2100
+            LDA #$00       ; 00fd/00fe/00ff point to the data that is 
+now
+            STA $00FD      ; in ram at $7f0000
+            LDA #$00
+            STA $00FE
+            LDA #$7F
+            STA $00FF
+            STZ $4200      ; disable nmi and timer h/v count
+            SEI            ; disable irq
+
+            JSR l0DBCD     ; unknown sub routine, labeled "RESTART" 
+by PAN/ATX
+
+            SEP #$30       ; all regs 8 bit
+l0DB8B      LDA $2140      ; wait for reply from sound chip ?
+            BNE l0DB8B
+            LDA #$E0       ; audio3w ?
+            STA $2143
+            LDA #$FF       ; send data to sound chip ?
+            STA $2142      ; $ffe0 this could be an address within the
+                           ; sound chip ROM between $ffc0 and $ffff 
+in the
+                           ; ROM mask.......
+            LDA #$01       ; send data to sound chip ?
+            STA $2141
+            LDA #$01       ; send data to sound chip ?
+            STA $2140
+
+l0DBA4      LDA $2140      ; wait for reply from sound chip ?
+            CMP #$01       ; what a fuck of a protocol .... :(
+            BNE l0DBA4
+
+l0DBAB      LDA $2140      ; wait again for reply from soundchip ?
+            CMP #$55
+            BNE l0DBAB
+
+            LDA $0207       ; aha ... move $0207 to sound chip ?
+            STA $2141       ; probably sound number selector
+            LDA #$07
+            STA $2140       ; send data to sound chip
+l0DBBD      LDA $2140       ; wait until sound chip accepted data?
+            CMP #$07
+            BNE l0DBBD
+l0DBC4      LDA $2140       ; wait for reply ?
+            CMP #$55
+            BNE l0DBC4
+            CLI
+            RTS
+
+l0DBCD      PHP            ; labeled "RESTART" by pan/ATX
+            JSR l0DBD8     ;
+            PLP
+            LDA #$00       ; 00 into audio0w
+            STA $2140
+            RTS
+
+l0DBD8      PHP
+            REP #$30       ; a,x,y 16 bit regs
+            LDY #$0000     ; needed first time at lda [$fd],y : 
+pointer to ram
+            LDA #$BBAA
+l0DBE1      CMP $2140      ; wait for sound chip $2140/2141 ?
+            BNE l0DBE1
+            SEP #$20      ; akku  8 bit
+            LDA #$CC
+            BRA l0DC12    ;  oh well, another mystery  :-)
+
+
+; jump here if overflow is set  e.g. if more than $0100 data to move
+l0DBEC      LDA [$FD],Y   ; get data from ram pointer
+            INY           ; the accumulator is about to get "xx00" 
+where
+            XBA           ;    /"xx" is the byte from [fd],y (first 
+data byte)
+            LDA #$00      ;    /and resides into bit 15-7 of accu, 
+and 00 is
+            BRA l0DBFF    ;    /#$00 (8bit number of bytes already 
+sent)
+
+
+l0DBF4      XBA           ; accu is now "nn??" ?? is old data from 
+last loop
+            LDA [$FD],Y   ; accu is now "nnxx" with xx the newest 
+data byte
+            INY           ;                                   /for 
+the SPC!
+            XBA           ; accu is now "xxnn"
+l0DBF9      CMP $2140     ; wait for sound chip to reply with "nn" !!
+            BNE l0DBF9
+            INC A         ; increment number of bytes that were 
+sent...
+                          ; accu is now "xxnn" with newest val for 
+nn:=nn+1
+
+l0DBFF      REP #$20      ; akku 16 bit
+            STA $2140     ; poke "xxnn" to soundchip. xx is actual 
+data,
+            SEP #$20      ; akku 8 bit  ! nn is the 8-bit cutted 
+number of bytes
+            DEX                         ! which were already sent!!
+            BNE l0DBF4    ; as many times as xreg says...
+
+
+l0DC09      CMP $2140     ; byte "nn" will be replied from the SPC if 
+data
+            BNE l0DC09    ; received correctly!
+l0DC0E      ADC #$03      ; compare accu with #$fb  ADC WILL ADD #$04 
+COZ
+                          ; CARRY IS ALWAYS SET AFTER THE CMP!!! 
+ATTENTION!
+            BEQ l0DC0E    ; if accu was $fb then accu := $03 . (what 
+for?)
+
+l0DC12      PHA           ; push value accu+$04 to stack (or 
+beginning: #$cc)
+            REP #$20      ; accu = 16 bit
+            LDA [$FD],Y   ; get ram data 2 bytes
+            INY           ; point to next word
+            INY
+            TAX           ; x:=a : number of bytes to transmit
+            LDA [$FD],Y   ; get ram data
+            INY
+            INY
+            STA $2142     ; audio2w  : possibly the dest. area in the 
+spc700
+            SEP #$20      ; accu 8 bit
+            CPX #$0100    ; set carry if first ram data was >= 0100
+            lda #$00      ;
+            ROL           ;
+            STA $2141     ; if ram data >= 0100, poke "1" into reg 1 
+otherw 0
+            ADC #$7F      ; SET OVERFLOW FLAG IF X>=$0100 !!!! (nice 
+trick!)
+            PLA
+            STA $2140     ; $cc in the first case , nn+4 on all later 
+cases
+
+l0DC32      CMP $2140    ; wait for snd chip reply
+            BNE l0DC32
+            BVS l0DBEC   ; if there were more than $0100 data for the 
+spc's RAM
+                         ; move them where they R supposed to belong 
+to!
+            PLP
+            RTS
+
+
+            PLA
+            STA $2140    ; same shit, never been jumped into
+l0DC3F      CMP $2140
+            BNE l0DC3F
+            BVS l0DBF9
+            PLP
+            RTS
+
+
+
+
+
+
+; also lets look at 7f0000: the first few bytes at 7f0000 are:
+
+7f0000: b7 0e 00 04 20 cd cf bd e8 00 5d af c8 f0 d0 fb 5d d5 00 01 
+d5 00 02
+
+b7 0e should be number of bytes to transmit, 0400 the destination 
+inside the
+spc....
+at this point I really need an SPC dis/assembler.....  :(((
+
+Okay well my first source was incompetent, sure thing. But I think I 
+could
+solve a lot of questions meanwhile.

+ 201 - 0
files/docs/snes/yoshi/SPRITE.DOC

@@ -0,0 +1,201 @@
+SPRITE DOC
+------------------------------------------------------------
+
+if you haven't already obtained "yoshi doc", get it and read it before you
+read this doc....
+
+
+Part I - the bitplane representation of a 16 color 8x8 pixel tile
+-----------------------------------------------------------------
+
+sprites are made of tiles, in particular 4-bitplane tiles, 4-bitplane 
+tiles, means that the tiles are made of 4-bit color values, so this means 
+that the tiles can have a maximum of 16 colors.
+
+in many graphics formats, this type of data would be stored as follows 
+(assuming a 8 pixel by 8 pixel tile)
+
+			$1 $0 $2 $8 $2 $4 $5
+			$2 $0 $6 $1 $f $e $1
+			$a $2 $2 $2 $6 $7 $0
+			$1 $0 $2 $8 $2 $4 $5
+			$1 $0 $2 $8 $2 $4 $5
+			$1 $0 $2 $8 $2 $4 $5
+			$1 $0 $2 $8 $2 $4 $5
+			$1 $0 $2 $8 $2 $4 $5
+
+where each hex number represents a color, so pixel (0,0) would be color 
+number "1", and pixel (4,2) would be color "6"....this is <not> the case 
+on the super nintendo....for reasons having to do with the implementation 
+of the graphics engine, the super nintendo represents its image data in 
+the "bitplane" format, assuming and 8 pixel by 8 pixel tile with 16 
+colors, this data would have four bitplanes (0-3) of monochrome, binary 
+image data:
+
+
+		   	0 0 0 0 0 0 0 0
+     			0 0 0 0 0 0 0 0 1
+     			0 0 0 0 0 0 0 0 1 2
+     			0 0 0 0 0 0 0 0 1 2 3
+     			0 0 0 0 0 0 0 0 1 2 3
+     			0 0 0 0 0 0 0 0 1 2 3
+     			0 0 0 0 0 0 0 0 1 2 3
+     			0 0 0 0 0 0 0 0 1 2 3
+       			  1 1 1 1 1 1 1 1 2 3
+         		    2 2 2 2 2 2 2 2 3
+           		      3 3 3 3 3 3 3 3
+
+
+four monochrome 8x8 pixel images stacked on top of each other. if you 
+wanted pixel (4,2) to have the color "6" you would have to put a "1" in 
+bitplane one, and a "1" in bitplane two, with the bitplane zero and three 
+having "0"'s.  this is because the binary representation of "6" is "0110".
+
+ok, so it is obviously possible to store each monochrome bitplane in 8 
+bytes, each byte representing a row in the bitplane. so a single tile 
+takes up 32 bytes (8 bytes per row * 8 rows * 4 bitplanes) of memory.
+
+
+Part II - the way tiles are stored in vram for sprite data
+---------------------------------------------------------
+
+in vram you store a tile 16 bits at a time as follows:
+
+		<-------2 bytes at a time------>
+		<--1 byte wide-><--1 byte wide->
+
+		[plane 0, row 0][plane 1, row 0]
+		[plane 0, row 1][plane 1, row 1] 
+		[plane 0, row 2][plane 1, row 2]
+               		       ..
+                               ..
+                               ..
+		[plane 0, row 7][plane 1, row 7]
+		[plane 2, row 0][plane 2, row 0]
+		[plane 2, row 1][plane 2, row 1]
+		[plane 2, row 2][plane 2, row 2]
+                               ..
+	                       ..
+                               ..
+		[plane 2, row 7][plane 2, row 7]
+
+
+the super nintendo can have two different sizes of sprite on the screen 
+at one time, you can choose from the following combinations:
+	
+      [value]      [sprite size 0][sprite size 1]
+	000	      8x8 pixel	    16x16 pixel
+	001	      8x8 pixel	    32x32 pixel
+        010	      8x8 pixel	    64x64 pixel
+        011          16x16 pixel    32x32 pixel
+        100          16x16 pixel    64x64 pixel
+        101	     32x32 pixel    64x64 pixel
+
+it is set in the upper three bits of address $2101....so to use 8x8 pixel 
+sprites, and 32x32 pixel sprites, you would load $2101 with the value
+"001xxxxx" (where x is don't care)
+
+the lower five bits of address $2101 are also very important, these bits 
+tell the super nintendo where in vram your sprites are located. the 
+lowest three bits are the "name base", and the fourth and fifth bits are the 
+"name". the "name" bits specify the upper 4k word of the sprite address, 
+and the "name base" specfies the offset. so if put you tile data in vram 
+$0000 you would set these bits all to zero.
+
+suppose you want to have four 32 pixel by 32 pixel sprites; each would be  
+composed of 16 tiles, each tile is numbered, tiles $0-$3f
+
+			[sprite 0]
+		        0  1  2  3
+			4  5  6  7
+			8  9  a  b
+		        c  d  e  f
+	
+			    ..		
+			    ..
+
+			[sprite 3]
+			30 31 32 33
+			34 35 36 37
+			38 39 3a 3b
+			3c 3d 3e 3f
+			
+in vram, these tiles, $0 through tile $3f would be store in an interlaced 
+fashion as follows:
+
+
+$0  $1  $2  $3  $10 $11 $12 $13 $20 $21 $22 $23 $30 $31 $32 $33
+$4  $5  $6  $7  $14 $15 $16 $17 $24 $25 $26 $27 $34 $35 $36 $37
+
+do you see the pattern? you must store the first row (four tiles) of each
+sprite, and then the second row, then the third, etc....
+
+if you were dealing with 8x8 sprites, you would have to store the first
+row of 16 sprites, then the second row of the 16 sprites, etc....
+
+if you were dealing with 16x16 sprites, you have to store the first row
+of 8 sprites, then the second, then the third, etc...
+
+with 64x64, yep, you guessed it, the first row of two sprites, then the
+second row, etc....
+
+
+
+Part III  - setting up the OAM table for your sprites
+-----------------------------------------------------
+
+for each sprite in the sprite table (maximum of 128 sprites, numbered 0-127)
+you must have four bytes of information, the first byte is the low 8 bits of
+the horizontal position of the sprite, the second byte is the vertical
+position of the sprite, the third byte is the "address" of the sprite...
+it is not the actual vram address, it is the tile number, that is to say,
+the physical vram address of the sprite can be obtained by the following:
+multiply the sprite "address" by 32 (because each tile is 32 bytes) and add it
+to the starting vram address that you set in the $2101 register.
+this tile number points to the first tile in the sprite...the snes expects the
+rest of tiles to follow in the order described in the previous section...
+the next byte containes the 9th bit of the tile "address" and a few attributes
+
+				bit 0   = 9th bit
+				bit 1-3 = palette number
+				bit 4,5 = playfield priority
+				bit 6   = horizontal flip
+				bit 7   = horizonal flip
+
+the palette number is not a 4 bit number, so obviously, you can only choose
+between 8 of the 16 palettes....if you set these bits to all 0, you will be
+selecting the eigth palette (palette 7), if you set them to "001" it is the
+ninth palette etc...it was trial and error, and some <serious> frustration
+before i figured this one out :) 
+
+to set these bytes in the OAM table, you must first setup the OAM "address"
+on the 16 bit register $2102 (and $2103). again this is not a real address,
+you use the 7 lowest bits of this address to select which sprite you
+would like to set the data for (sprite 0 to sprite 127)
+
+then you can write the four bytes discussed above to the register $2104, its
+like the color register, auto incrementing...
+
+so....what are all the other bits for??? (the remaining 9) well, i know about
+only two others, the highest bit (bit 15) is a sprite priority bit, it is
+basically the bit you set to "turn on" the sprite, and keep it being redrawn
+on the screen...its a little more than this, but thats all i know about its
+behavior.  so when you setup your table, (and periodically throughout the 
+sprites' display lifecycle) you must set this bit high....(for any sprite being
+displayed)
+
+there is another small table (32 bytes) that you must load into the OAM, these
+consist of two bits for every sprite, one of the bits being the 9th horizontal
+position bit, and the other is the size select bit (remember we can pick from
+two different size sprites on the screen at once) the first bit is the
+most significant horizontal location, and the second is the size toggle
+bit...
+
+to write this table the OAM, you must set the 9th bit of the "address" in $2103
+to one....then write the bytes, again it is an auto incrementing register 
+
+make sure that you have enabled the sprites to be on a particular plane (see
+the yoshi doc, on $212C....and make sure that you have set your palette
+correctly (remember sprite palette 0 is the 8th palette!!!)
+
+			good luck....

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