mmio.txt 45 KB

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  1. I have no idea where this document came from (EPR? Who knows..), there's no credits anywhere
  2. or anything... weird. Anyways, it was really hard with my eyes so I told Wordperfect to convert it
  3. to initial caps' since there was no Capitalize the first word of each line or sentence and leave
  4. abbreviations the way they are' option.
  5. - Qwertie
  6. Address : $2100
  7. Name : Inidisp
  8. Contents : Initial Settings for Screen
  9. D7 Blanking:
  10. Forced Blanking, 0:non-blanking,1:blanking.
  11. D6-d4 ---
  12. D3-d0 Fade In/out:
  13. 0000-darkest,1111-brightest.
  14. Address : $2101
  15. Name : Obsel
  16. Contents : Object Size & Object Data Area Designation
  17. D7-d5 Size Select:
  18. D7 D6 D5 0 1 (Size Large/small)
  19. 0 0 0 8 16
  20. 0 0 1 8 32
  21. 0 1 0 8 64
  22. 0 1 1 16 32
  23. 1 0 0 16 64
  24. 1 0 1 32 64 (Dots.)
  25. D4-d3 Name Select
  26. The Upper 4k-word Out of the Area (8k-word)
  27. Designated by "Object Base Address" is Assigned
  28. As the Base Area, and the Area of the Lower 4k-
  29. Word Combined with its Base Area Can Be
  30. Selected. (See Appendix 1 & 2)
  31. D2-d0 Name Base Select (Upper-3 Bit)
  32. Designate the Segment (8k-word) Address Which
  33. The Obj Data is Stored in Vram. (Appendix 1 & 2)
  34. Address : $2102/$2103
  35. Name : Oamaddl/oamaddh
  36. Contents : Address for Accessing Oam
  37. D7-d0 Oam Address (A7-a0) 2102h
  38. D7 Oam Priority Rotation 2103h
  39. D6-d1 ---
  40. D0 Oam Address Msb (A8)
  41. This is the Initial Address to Be Set in Advance When Reading
  42. Reading From the Oam Or Writing to the Oam.
  43. By Writing "1" to D7 of Register <2103h> and Setting the Oam-
  44. Address the Obj for the Address Set Has Highest Priority.
  45. The Address Which Has Been Set Just Before Every Field
  46. (Beginning of V-blank) Will Be Set Again to Registers <2102h>
  47. <2103h> Automatically. But, the Address Can Not Be Set
  48. Automatically During Forced Blank Period.
  49. Address : $2104
  50. Name : Oamdata
  51. Contents : Data for Oam Write
  52. D7-d0 Oam Data (Low,high)
  53. This is the Oam Data to Be Writting At Any Address of the Oam.
  54. (See Appendix-3)
  55. After Register <2102h> Or <2103h> is Accessed, the Data Must
  56. Be Written in the Order of Lower 8-bit & Upper 8-bit of Register
  57. <2104h>.
  58. The Data Can Be Written Only During V-blank Or Forced Blank
  59. Period.
  60. Address : $2105
  61. Name : Bgmode
  62. Contents : Bg Mode & Character Size Settings
  63. D7-d4 Bg Size Designation (Bg4-bg1)
  64. 0: 8 X 8 Dot/character
  65. 1: 16 X 16 Dot/character
  66. D3 Highest Priority Designation for Bg-3 in Mode 1
  67. 0: Off (See Appendix-16)
  68. 1: on
  69. D2-d0 Bg Screen Mode Select (See Appendix-5)
  70. Address : $2106
  71. Name : Mosaic
  72. Contents : Size & Screen Designation for Mosaic Display
  73. D7-d4 Mosaic Size (See Appendix-6)
  74. 1111 - Largest, 0000 - Smallest.
  75. D3-d0 Mosaic Enable (Bg4-b1)
  76. 0: Off
  77. 1: on
  78. Address : $2107/$2108/$2109/$210a
  79. Name : Bg1sc/bg2sc/bg3sc/bg4sc
  80. Contents : Address for Storing Sc-data of Each Bg & Sc Size Designation
  81. D7-d2 Sc Base Address
  82. Designate the Segment Which Bg-sc in the Vram
  83. Is Stored. (1k-word/segment)
  84. D1-d0 Sc Size
  85. Designate Background Screen Size (Appendix-18 & 19)
  86. 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 1
  87. 0 0 1 1 0 1 2 3
  88. Address : $210b/$210c
  89. Name : Bg12nba/bg34nba
  90. Contents : Bg Character Data Are Designation
  91. D7-d4 Bg2 Base Address 210bh
  92. D3-d0 Bg1 Base Address
  93. D7-d4 Bg4 Base Address 210ch
  94. D3-d0 Bg3 Base Address
  95. Background Name Base Address (Upper 4-bit), Segment Address
  96. In the Vram Where Bg Character Data is Stored. (4k-word/segment)
  97. Address : $210d/$210e/$210f/$2110/$2111/$2112/$2113/$2114
  98. Name : Bg1hofs/bg1vofs/bg2hofs/bg2vofs/bg3hofs/bg3vofs/bg4hofs/bg4vofs
  99. Contents : H/v Scroll Value Designation for Bg
  100. D7-d0 H-offset (Low,high) Hofs
  101. D7-d0 V-offset (Low,high) Vofs
  102. 10 Bit Maximum (0-1023) Can Be Designated for H/v Scroll Value.
  103. [The Size of 13-bit Maximum (-4096->4095) Can Be Designated in
  104. Mode 7] (See Appendix-8 & 9)
  105. By Writing to the Register Twice, the Data Can Be Set in Order
  106. Of Low & High.
  107. Address : $2115
  108. Name : Vmain
  109. Contents : Vram Address Increment Value Designation
  110. D7 H/l Inc (Word Or Byte Vram Access)
  111. Designate the Increment Timing for the Address
  112. 0: the Address Will Be Increased After the Data Has
  113. Been Written to Register <2118h> Or the Data
  114. Has Been Read From Register <2139h>.
  115. This Will Result in Byte Vram Access, I.e. for
  116. Mode 7 Tile Map Change.
  117. 1: the Address Will Be Increased After the Data Has
  118. Been Written to Register <2119h> Or the Data
  119. Has Been Read From Register <213ah>.
  120. This Will Result in Word Vram Access, I.e. for
  121. Mode 1 Tile Map Change.
  122. D6-d4 ---
  123. D3-d2 Full Graphic (G1 & G0)
  124. D1-d0 Sc Increment (I1 & I0)
  125. G1 G0 I1 I0 | Increment Value
  126. ----------------------------
  127. 0 1 0 0 | Increment by 8 for 32 Times (2-bit Formation)
  128. 1 0 0 0 | Increment by 8 for 64 Times (4-bit Formation)
  129. 1 1 0 0 | Increment by 8 for 128 Times (8-bit Formation)
  130. 0 0 0 0 | Address Increments 1 by 1
  131. 0 0 0 1 | Address Increments 32 by 32
  132. 0 0 1 0 | Address Increments 64 by 64
  133. 0 0 1 1 | Address Increments 128 by 128
  134. Address : $2116/$2117
  135. Name : Vmaddl/vmaddh
  136. Contents : Address for Vram Read
  137. D7-d0 Vram Address (Low) 2116h
  138. D7-d0 Vram Address (High) 2117h
  139. This is the Initial Address for Reading From the Vram Or Writing
  140. To the Vram.
  141. The Data is Read Or Written by the Address Set Initially, and
  142. Every Time the Data is Read the Address Wil Be Increased
  143. Automatically.
  144. The Value to Be Increased is Determined by "Sc Increment" of
  145. Register <2115h> and the Setting Value of the "Full Graphic".
  146. Address : $2118/$2119
  147. Name : Vmdatal/vmdatah
  148. Contents : Data for Vram Write
  149. D7-d0 Vram Data (Low) 2118h
  150. D7-d0 Vram Data (High) 2119h
  151. This is the Screen Data and Character Data (Bg & Obj), Which
  152. Can Write At Any Address of the Vram.
  153. According to the Setting of Register <2115h> "H/l Inc.", the
  154. Data Can Be Written to the Vram As Follows:
  155. H/l Inc | Write to Register | Operation
  156. --------------------------------------------------------------
  157. 0 | Write to <2118h> | the Data is Written to Lower 8bit
  158. | Only. | of the Vram & the Address Will Be
  159. | | Increased Automatically.
  160. 1 | Write to <2119h> | the Data is Written to Upper 8bit
  161. | Only. | of the Vram & the Address Will Be
  162. | | Increased Automatically.
  163. 0 | Write in Order of | When the Data is Set in the Order
  164. | <2119h> & <2118h> | of Upper & Lower the Address Will
  165. | | Be Increased.
  166. 1 | Write in Order of | When the Data is Set in the Order
  167. | <2118h> & <2119h> | of Lower & Upper the Address Will
  168. | | Be Increased.
  169. Note: the Data Can Only Be Written During V-blank Or Forced Blank
  170. ~~~~~ Period.
  171. Address : $211a
  172. Name : M7sel
  173. Contents : Initial Setting in Screen Mode-7
  174. D7-d6 Screen Over (O1 & O0)
  175. Process Made If the Screen to Be Displayed is
  176. Outside of the Screen Area. (See Below)
  177. D5-d2 ---
  178. D1-d0 Screen Flip (V/h)
  179. 0: Normal
  180. 1: Flipped
  181. O1 O0 | Process Out of Area
  182. --------------------------------------------------------------
  183. 0 0 | Screen Repetition If Outside of Screen Area
  184. 1 0 | Character 0x00 Repetition If Outside of Screen Area
  185. 1 1 | Outside of the Screen Area is the Back Drop Screen in
  186. | Single Color
  187. Address : $211b/$211c/$211d/$211e/$211f/$2120
  188. Name : M7a/m7b/m7c/m7d/m7x/m7y
  189. Contents : Rotation/enlargement/reduction in Mode-7, Center Coordinate
  190. Settings & Multiplicand/multiplier Settings of Complementary
  191. Multiplication.
  192. D7-d0 Matrix Parameter A (Low[mp7-mp0],High[mp15-mp8])211bh
  193. D7-d0 Matrix Parameter B (Low[mp7-mp0],High[mp15-mp8])211ch
  194. D7-d0 Matrix Parameter C (Low[mp7-mp0],High[mp15-mp8])211dh
  195. D7-d0 Matrix Parameter D (Low[mp7-mp0],High[mp15-mp8])211eh
  196. The 8-bit Data Should Be Written Twice in the Order of Lower &
  197. Upper. Then, the Parameter of Rotation, Enlargement and Reduction
  198. Should Be Set by its 16-bit Area.
  199. The Value Down to A Decimal Point Should Be Set to the Lower
  200. 8-bit. The Most Significant Bit of the Upper 8-bit is for the
  201. Signed Bit. (Mp15 is the Signed Bit. There is A Decimal Point
  202. Between M7 & M8)
  203. Formula for Rotaion/enlargement/reduction (See Appendix-13)
  204. / X2 \ / A B \ / X1-x0 \ / X0 \
  205. | | = | | | | + | |
  206. \ Y2 / \ C D / \ Y1-y0 / \ Y0 /
  207. A=cos(gamma)*(1/alpha), B=sin(gamma)*(1/alpha)
  208. C=-sin(gamma)*(1/beta), D=cos(gamma)*(1/beta)
  209. Gamma: Rotation Angle
  210. Alpha: Reduction Rates for X(h)
  211. Beta : Reduction Rates for Y(v)
  212. X0&y0: Center Coordinate
  213. X1&y1: Display Coordinate
  214. X2&y2: Coordinate Before Calculation
  215. Set the Value of "A" to Register <211bh>. In the Same Way,
  216. Set "B-d" to the Registers <211ch>-<211eh>.
  217. * the Complementary Multiplication (16bit X 8bit) Can Be Done by
  218. Using Registers <211bh> <211c>.
  219. When Setting 16 Bit Data to Register <211bh> and 8bit Data to
  220. Register <211ch>, the Multiplication Result Can Be Indicated
  221. Rapidly by Reading Registers <2134h>-<2136h>.
  222. D7-d0 Center Position X0 (Low[x7-x0],High[x12-x8]) 211fh
  223. D7-d0 Center Position Y0 (Low[y7-x0],High[y12-x8]) 2120h
  224. The Center Coordinate (X0,y0) for Rotation/enlargement/reduction
  225. Can Be Designated by this Register.
  226. The Coordinate Value of X0 & Y0 Can Be Designated by 13-bit
  227. (Complement of 2).
  228. The Register Requires That the Lower 8-bit is Set First and the
  229. Upper 5-bit is Set. Therefore, 13-bit Data in Total Can Be Set.
  230. Address : $2121
  231. Name : Cgadd
  232. Contents : Address for Cg-ram Write
  233. D7-d0 Cg-ram Address
  234. This is the Initial Address for Reading From the Cg-ram Or
  235. Writing to the Cg-ram
  236. The Data is Read by the Address Set Initially, and Every Time
  237. The Data is Read Or Written the Address Will Be Increased
  238. Automatically.
  239. Address : $2122
  240. Name : Cgdata
  241. Contents : Data for Cg-ram Write
  242. D7-d0 Cg-ram Data (Low[d7-d0],High[d14-d8])
  243. This is the Color Generater Data to Be Written At Any Address
  244. Of the Cg-ram.
  245. The Mapping of Bg1-bg4 and Obj Data in Cg-ram Will Be Determined,
  246. Which is Performed by Every Mode Selected by "Bg Mode" of
  247. Register <2105h>. (See Appendix-14)
  248. There Area the Color Data of 8-palettes for Each Screen of
  249. Bg1-bg4. The Palette Selection is Determined by 3-bit of the
  250. Sc Data "Color"
  251. Because the Cg-ram Data is 15-bit/word, it is Necessary to Set
  252. Lower 8-bit First to this Register and the the Upper 7-bit.
  253. When Both Lower & Upper Are Set, the Address Will Be Increased
  254. By 1 Automatically.
  255. Note: After the Address is Set, the Data Should Be Written From
  256. ~~~~~ the Lower As Well As the Oam.
  257. Note: the Data Can Be Written Only During H/v Blank Or Forced-
  258. ~~~~~ Blank Period.
  259. Address : $2123/$2124/$2125
  260. Name : W12sel/w34sel/wobjsel
  261. Contents : Window Mask Settins (Bg1-bg4, Obj, Color)
  262. D7 Bg2 Window-2 Enable 2123h
  263. 0: Off
  264. 1: on
  265. D6 Bg2 Window-2 In/out
  266. The Window Mask Area Can Be Designated Whether
  267. Inside Or Outside of the Frame Designated by the
  268. Window Position.
  269. 0: in
  270. 1: Out
  271. D5 Bg2 Window-1 Enable
  272. D4 Bg2 Window-1 In/out
  273. D3 Bg1 Window-2 Enable
  274. D2 Bg1 Window-2 In/out
  275. D1 Bg1 Window-1 Enable
  276. D0 Bg1 Window-1 In/out
  277. D7 Color Window-2 Enable 2125h
  278. D6 Color Window-2 In/out
  279. D5 Color Window-1 Enable
  280. D4 Color Window-1 In/out
  281. D3 Obj Window-2 Enable
  282. D2 Obj Window-2 In/out
  283. D1 Obj Window-1 Enable
  284. D0 Obj Window-1 In/out
  285. The Color Window is A Window for Main & Sub Screen (It is
  286. Related to Register <2130h>.
  287. Address : $2126/$2127/$2128/$2129
  288. Name : Wh0/wh1/wh2/wh3
  289. Contents : Window Position Designation (See Appendix-15)
  290. D7-d0 Window Pposition
  291. H0,h2 Left Position Designation
  292. H1,h3 Right Position Designation
  293. Note: If "Left Position Setting Value > Right Position Value"
  294. ~~~~~ is Assumed, There Will Be No Range of the Window.
  295. Address : $212a/$212b
  296. Name : Wbglog/wobjlog
  297. Contents : Mask Logic Settings for Window-1 & 2 on Each Screen
  298. D7-d6 Bg4 D1/d0 212ah
  299. D5-d4 Bg3 D1/d0
  300. D3-d2 Bg2 D1/d0
  301. D1-d0 Bg1 D1/d0
  302. D7-d4 --- 212bh
  303. D3-d2 Colorwindow D1/d0
  304. D1-d0 Objwindow D1/d0
  305. D1 D0 | Logic
  306. ------------------
  307. 0 0 | Or
  308. 0 1 | and
  309. 1 0 | Xor
  310. 1 1 | Xnor
  311. Note: "In/out" of Registers <2123h>-<2125h> Becomes the
  312. ~~~~~ "Not-logic" for Each Window-1 & Window-2.
  313. Address : $212c
  314. Name : Tm
  315. Contents : Main Screen, Designation
  316. D7-d5 ---
  317. D4 Obj
  318. D3 Bg4
  319. D2 Bg3
  320. D1 Bg2
  321. D0 Bg1
  322. Main Screen Designation:
  323. Designate the Screen (Bg1-bg4, Obj) to Be Displayed
  324. As the Main Screen. Designate the Screen to Be Added
  325. for the Screen Addition/subtraction
  326. 0: Disable
  327. 1: Enable
  328. Address : $212d
  329. Name : Ts
  330. Contents : Sub Screen Designation
  331. D7-d5 ---
  332. D4 Obj
  333. D3 Bg4
  334. D2 Bg3
  335. D1 Bg2
  336. D0 Bg1
  337. Sub Screen Designation:
  338. Designate the Screen (Bg1-bg4, Obj) to Be Displayed
  339. As Sub Screen. Designate the Addition/subtraction
  340. Screen At the Point When the Screen Addition/subtraction
  341. is Functioning.
  342. 0: Disable
  343. 1: Enable
  344. * When the Screen Addition/subtraction is Functioning, the Sub
  345. Screen is A Screen to Be Added Or Subtracted Against the Main
  346. Screen.
  347. Address : $212e
  348. Name : Tmw
  349. Contents : Window Mask Designation for Main Screen
  350. D7-d5 ---
  351. D4 Obj
  352. D3 Bg4
  353. D2 Bg3
  354. D1 Bg2
  355. D0 Bg1
  356. Window Mask Designation for Main Screen:
  357. In the Window Area Designated by Register <2123h>-<2129h>,
  358. the Screen to Be Displayed Can Be Designated, Which is
  359. Selected Among the Main Screen Designated by Register
  360. <212ch>.
  361. 0: Disable
  362. 1: Enable
  363. Address : $212f
  364. Name : Tsw
  365. Contents : Window Mask Designation for Sub Screen
  366. D7-d5 ---
  367. D4 Obj
  368. D3 Bg4
  369. D2 Bg3
  370. D1 Bg2
  371. D0 Bg1
  372. Window Mask Designation for Sub Screen:
  373. In the Window Area Designated by Register <2123h>-<2129h>,
  374. the Screen to Be Displayed Can Be Designated, Which is
  375. Selected Among the Sub Screen Designated by Register
  376. <212ch>.
  377. 0: Disable
  378. 1: Enable
  379. * When the Screen Addition/subtraction is Functioning, the Sub
  380. Screen is A Screen to Be Added Or Subtracted Against the Main
  381. Screen.
  382. Address : $2130
  383. Name : Cgwsel
  384. Contents : Initial Settings for Fixed Color Addition Or Screen Addition
  385. D7-d6 Main Sw (M1/m0)
  386. D5-d4 Sub Sw (S1/s0)
  387. D3-d2 ---
  388. D1 Cc Add Enable, Fixed Color Addition/subtraction Enable
  389. Designate Whether 2 Kinds of the Data Should
  390. Be Added/subtracted Each Other Or Not, Which Are
  391. The Fixed Color Set by Register <2132h>, and
  392. The Color Data Which is Set to Cgram.
  393. 0: Addition/subtraction for Fixed Color
  394. 1: Addition/subtraction for Sub Screen
  395. D0 Direct Select (See Appendix-14)
  396. The Vram Data (Color & Character Data) Become the
  397. Color Data Directly. [Only When Mode-3,4 & 7]
  398. 0: Disable
  399. 1: Enable
  400. M1(s1) M0(s0) | Normal Display Is:
  401. --------------------------------------------------------------
  402. 0 0 | All the Time
  403. 0 1 | Inside Window Only
  404. 1 0 | Outside Window Only
  405. 1 1 | All the Time
  406. Address : $2131
  407. Name : Cgadsub
  408. Contents : Addition/subtraction & Subtraction Designation for Each Screen,
  409. Obj & Background Color
  410. D7 Color Data Addition/subtraction Select
  411. Designate the Selection Either of the Addition
  412. Or the Subtraction Mode.
  413. 0: Addition Mode Select
  414. 1: Subtraction Mode Select
  415. D6 "1/2 of Color Data" Designation
  416. When the Color Constant Addition/subtraction Or the
  417. Screen Addition/subtraction is Performed, Designate
  418. Whether the Rgb Result in the Addition/subtraction
  419. Area Should Be "1/2" Or Not. However, in the Back
  420. Color Constant Area on the Sub Screen, it Does Not
  421. Become "1/2"
  422. 0: Disable
  423. 1: Enable
  424. D5 Back
  425. D4 Obj
  426. D3 Bg4
  427. D2 Bg3
  428. D1 Bg2
  429. D0 Bg1
  430. Color Data Addition/subtraction Enable
  431. 0: Disable
  432. 1: Enable
  433. Address : $2132
  434. Name : Coldata
  435. Contents : Fixed Color Data for Fixed Color Addition/subtraction
  436. D7 Blue
  437. D6 Green
  438. D5 Red
  439. Bit for Selecting Desired Color
  440. D4-d0 Color Brilliance Data
  441. Set the Color Constant Data for Color Constant
  442. Addition/subtraction
  443. * R/g/b Brightness Should Be Set by the Data of Each 5-bit.
  444. [Example] Red : C0h, 3fh (B=00h, G=00h, R=1fh)
  445. Green : A0h, 5fh (B=00h, G=1fh, R=00h)
  446. Blue : 60h, 9fh (B=1fh, G=00h, R=00h)
  447. White : Ffh
  448. Black : 00h
  449. Address : $2133
  450. Name : Setini
  451. Contents : Screen Initial Setting
  452. D7 External Synchronization
  453. It is Used for Super Impose and Etc. Normally,
  454. "0" Should Be Written.
  455. D6 Extbg Mode (Screen Expand)
  456. Enable the Data Supplied From the External Lsi.
  457. For the Sfx, Enable When the Screen with Priority
  458. Is Used on Mode-7.
  459. D5-d4 ---
  460. D3 Horizontal Pseudo 512 Mode
  461. 512 Imaginary Resolution (Horizontal Can Be Made
  462. By Shifting the Subscreen Half Dot to the Left.)
  463. 0: Disable
  464. 1: Enable
  465. D2 Bg V-direction Display
  466. Switch the Display Line of A Field to 224 Line Or
  467. 239 Line. (In Case of Interalace it Will Be
  468. Doubled Dot.)
  469. 0: 224 Line
  470. 1: 239 Line
  471. D1 Obj V-direction Display
  472. In the Interlace Mode, Select Either of 1-dot Per
  473. Line Or 1-dot Repeated Every 2-lines. If "1" is
  474. Written, the Obj Seems Reduced Half Vertically in
  475. Appearance.
  476. D0 Scanning
  477. Interlace/non-interlace Selection (It Relates to
  478. <2105h>.
  479. 0: Non Interlace
  480. 1: Interlace
  481. Address : $2134/$2135/$2136
  482. Name : *Mpyl/*mpym/*mpyh
  483. Contents : Multiplication Result
  484. D7-d0 Mpy (Low) 2134h
  485. D7-d0 Mpy (Mid) 2135h
  486. D7-d0 Mpy (High) 2136h
  487. This is A Multiplication Result (Complement of 2) Can Be Read
  488. By Setting 16-bit to Register <211bh> and Setting 8 Bit to
  489. Register <211ch>
  490. Address : $2137
  491. Name : *Slhv
  492. Contents : Software Latch for H/v Counter
  493. D7-d0 Soft Latch for H/v Counter
  494. This is A Register, Which Generate the Pulse for Latching the H/v
  495. Counter Value.
  496. The H/v Counter Value At the Point When Register <2137h> is Read
  497. Can Be Latched. The Data Which Was Read is Meaningless Data.
  498. The H/v Counter Value Latched Can Be Reffered by Registers
  499. <213ch> & <213dh>.
  500. Address : $2138
  501. Name : Oamdataread (Name Differs From Snes Manual)
  502. Contents : Read Data From Oam
  503. D7-d0 Oam Data (Low,high)
  504. This is A Register, Which Can Read the Data At Any Address of
  505. The Oam.
  506. When the Address is Set to Register <2102h><2103h> and Register
  507. <2138h> is Also Accessed the Data Can Be Read in the Order of
  508. Low 8-bit/high 8-bit.
  509. Afterward, the Address Will Be Increased Automatically, and the
  510. Data of the Next Address Can Be Read.
  511. Note: the Data Can Be Read Only During H/v Blank Or Forced
  512. ~~~~~ Blank Period.
  513. Address : $2139/$213a
  514. Name : Vmdatalread/vmdatahread (Names Differ From Snes Manual)
  515. Contents : Read Data From Vram
  516. D7-d0 Vram Data (Low) 2139h
  517. D7-d0 Vram Data (High) 213ah
  518. This is A Register, Which Can Read the Data At Any Address of
  519. The Vram.
  520. The Initial Address Should Be Set by Registers <2116h> and
  521. <2117h>. The Data Can Be Read by the Address Which Has Been Set
  522. Initially.
  523. When Reading the Data Continously, the First Data for the Address
  524. Increment Should Be Read As A Dummy Data After the Address Has
  525. Been Set.
  526. Quantity to Be Increased Will Be Determined by "Sc Increment" of
  527. Register <2115h> and the Setting Value of the "Full Graphic".
  528. Note: the Data Can Be Read Only During H/v Blank Or Forced
  529. ~~~~~ Blank Period.
  530. Address : $213b
  531. Name : Cgdataread (Name Differs From Snes Manual)
  532. Contents : Read Data From Cg-ram
  533. D7-d0 Cg Data (Low,high)
  534. This is A Register, Which Can Read the Data At Any Address of
  535. The Cg-ram.
  536. The Initial Address Should Be Set by Register <2121h>. The Lower
  537. 8-bit is Read First, and the the Upper 7-bit Will Be Read by
  538. Accessing this Register. The Current Address Will Be Increased
  539. To the Next Address At the Same Time the Upper 7-bit is Read.
  540. Note: the Data Can Be Read Only During H/v Blank Or Forced
  541. ~~~~~ Blank Period.
  542. Address : $213c/$213d
  543. Name : *Ophct/*opvct
  544. Contents : H/v Counter Data by External Or Software Latch
  545. D7-d0 Output Data of H-counter [9-bit] 213ch
  546. D7-d0 Output Data of V-counter [9-bit] 213dh
  547. The H/v Counter is Latched by Reading Register <2137h>, and its
  548. H/v Counter Value Can Be Read by this Register.
  549. The H/v Counter is Also Latched by the External Latch, and its
  550. Value Can Be Read by this Register.
  551. If Register <213ch> Or <213dh> is Read After Register <213fh> Has
  552. Been Read, the Lower 8-bit Data Will Be Read First, and Then the
  553. Upper 1-bit Will Be Read by Reading the Register.
  554. Address : $213e
  555. Name : *Stat77
  556. Contents : Ppu Status Flag & Version Number
  557. D7 Time Over \
  558. D6 Range Over /
  559. Obj Display Status (On A Horizontal Line)
  560. Range: When Quantity of the Obj (Regardless of
  561. The Size) Becomes 33 Pcs Or More, "1"
  562. Will Be Set.
  563. Time: When Quantity of the Obj Which is Converted
  564. To "8 X 8-size" is 35 Pcs Or More, "1"
  565. Will Be Set.
  566. D5 Master/slave Mode Select. Lsi Mode (Normally "0" is Set.)
  567. D4 ---
  568. D3-d0 5c77 Version Number
  569. Note: the Flag Will Be Reset At the End of the V-blank Period.
  570. ~~~~~
  571. Address : $213f
  572. Name : *Stat78
  573. Contents : Ppu Status Flag & Version Number
  574. D7 Field
  575. This is A Status Flag, Which Indicated Whether 1st
  576. Field is Scanned Or 2nd Field is Scanned in Inter-
  577. Lace Mode. (The Definition is Different From the
  578. Field of Ntsc.)
  579. 0: 1st Field
  580. 1: 2nd Field
  581. D6 External Latch Flag
  582. When the External Signal (Light Pen, Etc.) Is
  583. Applied, it Enables to Latch the H/v Counter Value.
  584. D5 ---
  585. D4 Ntsc/pal Mode
  586. 0: Ntsc
  587. 1: Pal
  588. D3-d0 5c78 Version Number
  589. Note: When this Register is Read, Registers <213ch><213dh> Will
  590. ~~~~~ Be Initialized Individually in the Order of Low & High.
  591. Address : $2140/$2141/$2142/$2143
  592. Name : Apui00/apui01/apui02/apui03
  593. Contents : Communication Port with Apu
  594. D7-d0 Apu I/o Port
  595. This Port Provides More Registers for the Purpose of In/out,
  596. Which Are 8 Registers in Total in the Apu. Therefore, the
  597. Different Register Will Be Accessed, Whether Reading Or
  598. Writing for the Same Address.
  599. See "Apu Manual" for the Details of the Communication Method.
  600. Address : $2180
  601. Name : Wmdata
  602. Contents : Data to Consecutivley Read From and Write to Wram
  603. D7-d0 Work Ram Data
  604. Data to Consecutivley Read From and Write to Wram
  605. Data is Read and Written At Address Set by Register <2181h>-<2183h>,
  606. And Address Automatically Increases Each Time Data is Read Or Written.
  607. Address : $2181/$2182/$2183
  608. Name : Wmaddl/wmaddm/wmaddh
  609. Contents : Address to Consecutively Read and Write Wram
  610. D7-d0 Wram Data (Low) 2181h
  611. D7-d0 Wram Data (Mid) 2182h
  612. D0 Wram Data (High) 2183h
  613. Address to Be Set Before Wram is Consecutivley Read Or Written.
  614. A0 Trough A16 At Register <2181h>-<2183h> is Lower 17 Bit Address
  615. To Show Address $7e0000-$7fffff in Memory.
  616. Address : $4200
  617. Name : Nmitimen
  618. Contents : Enable Flag for V-blank, Timer Interrupt & Joy Controller Read
  619. D7 Nmi Enable
  620. Enable Nmi At the Point When V-blank Begins
  621. (When Power is Turned on Or the Reset Signal is
  622. Applied, it Will Be "0".)
  623. 0: Nmi Disabled
  624. 1: Nmi Enabled
  625. D6 ---
  626. D5-d4 Timer Enable (V-en/h-en)
  627. D3-d1 ---
  628. D0 Joy-c Enable
  629. 0: Disable Automatic Reading of the Joy-controller.
  630. 1: Enable Automatic Reading of the Joy-controller.
  631. V-en H-en | Function
  632. --------------------------------------------------------
  633. 0 0 | Disable Both H & V
  634. 0 1 | Enable H Only, Irq Applied by H-count Timer Value Designated
  635. 1 0 | Enable V Only, Irq Applied by V-count Timer Value Designated
  636. 1 1 | Enable Both V & H, Irq Applied by Both H & V Count Timer Val
  637. | Designated.
  638. * Reading the Data Can Be Started At the Beginning of V-blank
  639. Period, But it Takes About for 3 Or 4 Scanning Period Until
  640. Completion of Reading.
  641. Address : $4201
  642. Name : Wrio
  643. Contents : Programmable I/o Port (Out-port)
  644. D7-d0 I/o Port
  645. This is A Programmable I/o Port (Out-port). The Written Data
  646. Will Be Output Directly From the Out-port.
  647. When this is Used As A Inport. "1" Should Be Written to the
  648. Particular Bit Which Will Be Used As in Port. The Input Can
  649. Be Read by Register <4213h>.
  650. Address : $4202/$4203
  651. Name : Wrmpya/wrmpyb
  652. Contents : Multiplier & Multiplicand by Multiplication
  653. D7-d0 Multiplicand-a 4202h
  654. D7-d0 Multiplier-b 4203h
  655. This is A Register, Which Can Set A Mulitplicand (A) and A
  656. Multiplier (B) for Absolute Multiplication of
  657. "A (8-bit) * B (8-bit)=c (16-bit)"
  658. A Product (C) Can Be Read by Registers <4216h><4217h>
  659. Set in the Order of (A) and (B). The Operation Will Start As
  660. Soon As (B) Has Been Set, and it Will Be Completed Right After
  661. 8-machine Cycle Period.
  662. Once the Data of the A-register is Set, it Will Not Be Destroyed
  663. Until New Data is Set.
  664. Address : $4204/$4205/$4206
  665. Name : Wrdivl/wrdivh/wrdivb
  666. Contents : Divisor & Dividend Divide
  667. D7-d0 Multiplier-c (Low) 4204h
  668. D7-d0 Multiplier-c (High) 4205h
  669. D7-d0 Divisor-b 4206h
  670. This is A Register, Which Can Set A Dividend (C) and A Divisor (B)
  671. For Absolute Divide of
  672. "C (16-bit) / B (8-bit)=a (16-bit)"
  673. The Divisor (A) Can Be Read by Registers <4214h><4215h>, and the
  674. Remainder Can Also Be Read by Registers <4216h><4217h>.
  675. Set in the Order of (C) and (B). The Operation Will Start As Soon
  676. As (B) Has Been Set, and it Will Be Completed Right After 16-
  677. Machine Cycle Period.
  678. Once the Data of the A-register is Set, it Will Not Be Destroyed
  679. Until New Data is Set.
  680. Address : $4207/$4208
  681. Name : Htimel/htimeh
  682. Contents : H-count Timer Settings
  683. D7-d0 H Count Timer (H7-h0) 4207h
  684. D7-d1 ---
  685. D0 H Count Timer (H8) 4208h
  686. This is A Register, Which Can Set the H-count Timer Value.
  687. The Setting Value Should Be From 0 Through 339, Which is Counted
  688. From the Far Left on the Screen.
  689. Hwen the Coordinate Counter Becomes the Count Value Set, the Irq
  690. Will Be Applied. And At the Same Time. "1" Will Be Written to
  691. "Timer Irq" of Register <4211h>. (Read Reset)
  692. Enable/disable of the Interrupt Will Be Determined by Setting
  693. Register <4200h>
  694. * this Continous Counter is Reset Every Scanning Line, Therefore
  695. Once the Count Value is Set, it is Possible to Apply the Irq
  696. Every Time the Scanning Line Comes to the Same Horizontal
  697. Position on the Screen.
  698. Address : $4209/$420ah
  699. Name : Vtimel/vtimeh
  700. Contents : V-count Timer Settings
  701. D7-d0 V Count Timer (V7-v0) 4209h
  702. D7-d1 ---
  703. D0 V Count Timer (V8) 420ah
  704. This is A Register, Which Can Set the V-count Timer Value.
  705. The Setting Value Should Be From 0 Through 261(262), Which is
  706. Counted From the Far Top of the Screen. [The Line Number Described
  707. Is Different From the Actual Line Number on the Screen.]
  708. Hwen the Coordinate Counter Becomes the Count Value Set, the Irq
  709. Will Be Applied. And At the Same Time. "1" Will Be Written to
  710. "Timer Irq" of Register <4211h>. (Read Reset)
  711. Enable/disable of the Interrupt Will Be Determined by Setting
  712. Register <4200h>
  713. * this is A Continous Counter Same As H-counter, and it Will Be
  714. Reset Every Time 262(263) Line Are Scanned. Once the Count
  715. Value is Set, it is Possible to Apply the Irq Every Time the
  716. Scanning Line Comes to the Same Vertical Line on the Screen.
  717. Address : $420b
  718. Name : Mdmaen
  719. Contents : Channel Designation for General Purpose Dma & Trigger (Start)
  720. D7-d0 General Purpose Ch7-ch0 Enable
  721. The General Purpose Dma Consists of 8-channels in Total.
  722. This Register is Used to Designate the Channel Out of 8-channels.
  723. The Channel Which Should Be Used Can Be Designated by Writing "1"
  724. To the Bit of this Channel. As Soon As "1" is Written to the
  725. Bit (After A Few Cycles Passed), the General Purpose Dma Transfer
  726. Will Be Started.
  727. When the General Purpose Dma of the Designated Channel is
  728. Completed, the Flag Will Be Cleared.
  729. Note: Because the Data Area (Register <4300>-) of Each Channel
  730. ~~~~~ is Held in Common with the Data of Each H-dma Channel, the
  731. Channel Designated by the H-dma Channel Designation
  732. Register <420ch> Can Not Be Used.
  733. (It is Prohibited to Write "1" to the Bit of the Channel)
  734. Therefore, 8 Channels (Ch0-ch7) Should Be Assigned by the
  735. H-dma and the General Purpose Dma)
  736. Note: If the H-blank Come During the Operation of the General
  737. ~~~~~ Purpose Dma and the H-dma is Started, the General Purpose
  738. Dma Will Be Discontinued in the Middle, and Re-started Right
  739. After the H-dma is Complete.
  740. Note: If 2 Or More Channels Are Designated, the Dma Transfer Will
  741. ~~~~~ Be Performed Continously According to the Priority Described
  742. in Appendix-1.
  743. And Also, the Cpu Stops Operation Until All the General
  744. Purpose Dma Are Completed.
  745. Address : $420c
  746. Name : Hdmaen
  747. Contents : Channel Designation for H-dma
  748. D7-d0 H-dma Ch7-dh0 Enable
  749. The H-dma Consists of 8-channels in Total
  750. This Register is Used to Designate the Channel Out of 8-channels
  751. The Channel Which Should Be Used Can Be Designated by Writing
  752. "1" to the Bit of this Channel. As Soon As H-blank Begins (After
  753. A Few Cycles Passed), the H-dma Transfer Will Be Started.
  754. Note: Once this Flag is Set, it Will Not Be Destroyed (Cleared)
  755. ~~~~~ Until New Data is Set. Therefore, the Initial Settings Are
  756. Done Automatically Every Field, and the Same Transfer
  757. Pattern Will Be Repeated.
  758. And Also, the Flag is Set Out of V-blank Period, the Dma-
  759. Transfer Will Be Performed Properly From Next Screen Frame.
  760. Address : $420d
  761. Name : Memsel
  762. Contents : Access Cycle Designation in Memory (2) Area
  763. D7-d1 ---
  764. D0 Access Cycle Designation in Memory (2) Area
  765. 0: 2.68mhz Access Cycle
  766. 1: 3.58mhz Access Cycle (Only When High Speed
  767. Memory is Used.)
  768. Memory (2) Shows the Address (8000h-ffffh) of the Bank (80h-bfh)
  769. And All the Address of the Bank (C0h-ffh).
  770. When Power is Turned on Or the Reset Signal is Applied it Becomes
  771. "0".
  772. High Speed Memory Requiers 120ns Or Faster Eproms.
  773. Address : $4210
  774. Name : *Rdnmi
  775. Contents : Nmi Flag by V-blank & Version Number
  776. D7 Nmi Flag by V-blank
  777. When "1" is Written to "Nmi Enable" of Register
  778. <4200h>, this Flag Will Show Nmi Status.
  779. 0: Nmi Status is "Disable"
  780. 1: Nmi Status is "Enable"
  781. D6-d4 ---
  782. D3-d0 5a22 Version Number
  783. * "1" is Set to this Flag At Beginning of V-blank, and "0" is
  784. Set At End of V-blank. Also, it Can Be Set by Reading this
  785. Register.
  786. Note: it is Necessary to Reset by Reading this Flag During
  787. ~~~~~ Nmi Processing. (See Appendix-3)
  788. Address : $4211
  789. Name : *Timeup
  790. Contents : Irq Flag by H/v Count Timer
  791. D7 Irq Flag by H/v Count Timer
  792. [In Case the Time Enable is Set by "Timer Enable"
  793. Of Register <4200h>] As Soon As H/v Counter Timer
  794. Becomes the Count Value Set, Irq Will Be Applied
  795. And "1" Will Be Set to this Flag.
  796. This Flag is "Read-reset".
  797. D6-d0 ---
  798. * Even If V-en="0" and H-en="0" Are Set by "Timer Enable" of
  799. Register <4200h>, this Flag Will Be Reset.
  800. 0: Either H/v Counter is in Active Or Disable.
  801. 1: H/v Count Timer is Time Up.
  802. Address : $4212
  803. Name : Hvbjoy
  804. Contents : H/v Blank Flag & Joy Controller Enable Flag
  805. D7 V-blank Period Flag
  806. 0: Out of V-blank Period
  807. 1: in V-blank Period
  808. D6 H-blank Period Flag
  809. 0: Out of H-blank Period
  810. 1: in H-blank Period
  811. D5-d1 ---
  812. D0 Joy Controller Enable Flag
  813. This Flag Shows the Timing to Read the Data of the
  814. Joy Controller. (However, it is Limited to the Case
  815. Which the "Joy-c Enable" of Register <4200h> is Set
  816. To "1".
  817. Address : $4213
  818. Name : *Rdio
  819. Contents : Programmable I/o Port (In-port)
  820. D7-d0 I/o Port
  821. This is A Programmable I/o Port (In Port). The Data Which is Set
  822. To the In-port Should Be Read Directly.
  823. The Bit Which "1" is Written by Register <4201h> is Used As the
  824. In Port.
  825. Address : $4114/$4115
  826. Name : *Rddivl/*rddivh
  827. Contents : Quotient of Divide Result
  828. D7-d0 Quotent-a (Low) 4114h
  829. D7-d0 Quotent-a (High) 4115h
  830. This is A Quotent (A), Which is A Result for Absolute Divide of
  831. "C (16-bit) / B (8-bit) = A (16-bit)".
  832. Dividend (C) and Divisor (B) Are Set by Registers <4204h>-<4206h>.
  833. Address : $4216/$4217
  834. Name : *Rdmpyl/*rdmpyh
  835. Contents : Product of Multiplication Result Or Remainder of Divide Result
  836. D7-d0 Product-c [Mul] / Remainder [Div] (Low) 4216h
  837. D7-d0 Product-c [Mul] / Remainder [Div] (High) 4217h
  838. (1) in Case of Multiplication
  839. This is A Product (C) Which is A Result for Absolute
  840. Multiplication of "A (8-bit) * B (8-bit) = C (16-bit)".
  841. A Multiplicand (A) and A Multiplier (B) Are Set by Registers
  842. <4202h> & <4203h>.
  843. (2) in Case of Divide
  844. This is the Remainder, Which is A Result for the Absolute
  845. Divide of "C (16-bit) / B (8-bit) = A (16-bit)".
  846. A Dividend (C) and Divisor (B) Are Set by the Registers
  847. <4204h><4205h> & <4206h>.
  848. Address : $4218/$4219/$421a/$421b/$421c/$421d/$421e/$421f
  849. Name : Joy1l/joy1h/joy2l/joy2h/joy3l/joy3h/joy4l/joy4h
  850. Contents : Data for Joy Controller I, Ii, Iii & Iv
  851. D7 X Button Low
  852. D6 Y Button
  853. D5 Tl Button
  854. D4 Tr Button
  855. D3-d0 ----
  856. D7 A Button High
  857. D6 B Button
  858. D5 Select Button
  859. D4 Start Button
  860. D3 Up
  861. D2 Down
  862. D1 Left
  863. D0 Right
  864. Registers <4016h><4017h> Can Be Used the Same As the Family
  865. Computer.
  866. 4016h-rd
  867. D0 : Data for Controller I
  868. D1 : Data for Controller Iii
  869. 4016h-wr
  870. Out0,out1,out2
  871. 4017h-rd
  872. D0 : Data for Controller Ii
  873. D1 : Data for Controller Iv
  874. Note: Whether the Standard Joy Controllers Are Connected to the
  875. ~~~~~ Sfx Or Not Can Be Reffered by Reading 17th Bit of <4016h>
  876. and <4017h> (See Page 22).
  877. 0: Connected
  878. 1: Not Connected
  879. Address : $43x0 (X: Channel Number 0-7)
  880. Name : Dmapx
  881. Contents : Parameter for Dma Transfer
  882. D7 Transfer Origination Designation (See Appendix-1)
  883. Transfer Direction A-bus -> B-bus
  884. B-bus -> A-bus Designation
  885. 0: A-bus -> B-bus (Cpu Memory -> Ppu)
  886. 1: B-bus -> A-bus (Ppu -> Cpu Memory)
  887. D6 Type Designation (H-dma Only)
  888. Addressing Mode Designation When Accessing the
  889. Data (See Appendix-2).
  890. 0: Absolute Addressing
  891. 1: Indirect Addressing
  892. D5 ---
  893. D4-d3 Fixed Address for A-bus & Automatic Inc./dec. Select.
  894. D3 0: Automatic Address Increment/decrement
  895. 1: Fixed Address <To Be Used When Clearing
  896. Vram Etc.>
  897. D4 0: Automatic Increment
  898. 1: Automatic Decrement (In Case "0" is
  899. Written to D3)
  900. D2-d0 Dma Transfer Word Select
  901. General Purpose Dma: B-address Change Method
  902. D2 D1 D0 | Address to Be Written
  903. ---------------------------------
  904. 0 0 0 | 1-address
  905. 0 0 1 | 2-address (Vram Etc.) L,h
  906. 0 1 0 | 1-address
  907. 0 1 1 | 2-address (Write Twice) L,l,h,h
  908. 1 0 0 | 4-address L,h,l,h
  909. H-dma: the Number of Byte to Be Transfered Per Line
  910. And Write Method Designation
  911. D2 D1 D0 | Address to Be Written
  912. ---------------------------------
  913. 0 0 0 | 1-address (1)
  914. 0 0 1 | 2-address (Vram Etc.) L,h (2)
  915. 0 1 0 | Write Twice L,l (1)
  916. 0 1 1 | 2-address/write Twice L,l,h,h(2)
  917. 1 0 0 | 4-address L,h,l,h(4)
  918. Address : $43x1 (X: Channel Number 0-7)
  919. Name : Bbadx
  920. Contents : B-bus Address for Dma
  921. D7-d0 B-address
  922. This is A Register, Which Can Set the Address of B-bus.
  923. Whether this is the Address of the "Transfer Destination" Or
  924. The Address of the "Transfer Origination" Can Be Determined by
  925. D7 (Transfer Origination) of Register <4300h>.
  926. * When the H-dma is Performed, it Will Be Address of "Transfer
  927. Destination".
  928. Address : $43x2/$43x3/$43x4 (X: Channel Number 0-7)
  929. Name : A1txl/a1txh/a1bx
  930. Contents : Table Address of A-bus for Dma <A1 Table Address>
  931. D7-d0 A1 Table Address (Low) 43x2h
  932. D7-d0 A1 Table Address (High) 43x3h
  933. D7-d0 A1 Table Bank 43x4h
  934. This is A Register, Which Can Set the Address of A-bus
  935. Whether this is the Address of the "Transfer Destination" Or
  936. The Address of the "Transfer Origination" Can Be Determined by
  937. D7 (Transfer Origination) of Register <4300h>.
  938. "0" Should Be Written to D7 Except A Special Case.
  939. In the H-dma Mode, the Address of the Transfer Origination is
  940. Designated by this Address, the Data (Appendix-2) Must Be
  941. Set by the Absolute Addressing Mode Or the Indirect Addressing
  942. Mode.
  943. This Address Becomes the Basic Address on the A-bus During Dma
  944. Transfer Period, and the Address Will Be Increased Or Decreased
  945. Based on this Address. (When the General Purpose Dma is Performed
  946. It Will Be Decreased.)
  947. Address : $43x5/$43x6/$43x7 (X: Channel Number 0-7)
  948. Name : Dasxl/dasxh/dasbx
  949. Contents : Data Address Store by H-dma & Number of Byte to Be Transfered
  950. Settings by General Purpose Dma
  951. D7-d0 Data Address (Low) H-dma 43x5h
  952. Number of Bytes to Be Transfered (Low) Gp-dma
  953. D7-d0 Data Address (High) H-dma 43x6h
  954. Number of Bytes to Be Transfered (High) Gp-dma
  955. D7-d0 Data Bank 43x7h
  956. In Case of H-dma
  957. this is A Register Which the Indirect Address Will Be
  958. Stored Automatically in the Indirect Addressing Mode.
  959. The Indirect Address Means the Data Address Described
  960. on Appendix-2. It is Not Necessary to Read Or Write
  961. Directly by the Cpu Except in Special Cases.
  962. In Case of General Purpose Dma
  963. this is the Register, Which Can Set the Number of Byte
  964. to Transfer Or to Be Transfered. However, the Number of
  965. Byte "0000h" Means "10000h".
  966. Address : $43x8/$43x9 (X: Channel Number 0-7)
  967. Name : A2axl/a2axh
  968. Contents : Table Address of A-bus by Dma < A2 Table Address
  969. D7-d0 A2 Table Address (Low) 43x8h
  970. D7-d0 A2 Table Address (High) 43x9h
  971. These Are the Addresses, Which Are Used to Access the Cpu & Ram,
  972. And it Will Be Increased Automatically. (See Appendix-2)
  973. The Data of These Registers Are Used As the Basic Address Which
  974. Is the Addresss Set by the "A1 Table Address". Afterwards,
  975. Because it Will Be Increased Or Decreased Automatically, it is
  976. Necessary to Set the Address Into this Register by the Cpu
  977. Directly.
  978. Following Apply to H-dma Only:
  979. However, If the Data Which is Transfered Need to Be Changed
  980. by Force, it Can Be Done by Setting the Cpu Memory Address
  981. to this Register. And Also, the Address of the Cpu Which is
  982. Accessed Currently Will Be Changed by Reading this Register.
  983. Address : $43xa (X: Channel Number 0-7)
  984. Name : Ntrlx
  985. Contents : the Number of Lines to Be Transfered by H-dma›0;31;40m
  986. D7 Continue
  987. D6-d0 Number of Lines to Be Transfered
  988. This is A Register Which Shows Number of Lines for H-dma Transfer
  989. (See Appendix-2)
  990. The Number of Lines Written to the Cpu Memory Will Be the Basic
  991. Number of Line, it is Not Necessary to Set the Address Into
  992. This Register Directly.