SNES.1 47 KB

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  1. ----------------------------------------------------------------------------
  2. |rwd2?|Address|Title & Explanation |
  3. ||||||-----------------------------------------------------------------------|
  4. |||||| |
  5. ||||||__ ?: Don't know what the statistics on this register are |
  6. |||||____ 2: 2 byte (1 word) length register |
  7. ||||_____ d: Double-byte write required when writing to this register |
  8. |||______ w: Writable register |
  9. ||_______ r: Readable register |
  10. | |
  11. |Words in brackets ( [] ) are the official "names" of the registers |
  12. |Words in braces ( {} ) are different from the "real" SNES manual |
  13. |Bits define 1 as "ON/ENABLE" and 0 as "OFF/DISABLE," unless otherwise stated|
  14. |Registers without any bits/defined-data can be assumed to be 8 bits in size |
  15. |and should only be read once. |
  16. |----------------------------------------------------------------------------|
  17. |NOTE! I have renamed all occurances of "Plane {x}" to "BG{x+1}." This means |
  18. |stuff like "Plane 2" is now referred to as "BG3" - This is how it is done |
  19. |(so i'm told) in the official SNES documentation, so for compatibility and |
  20. |comprehension, i've renamed everything. |
  21. | |
  22. |I have also renamed "Sprites" to "OBJ", "objects," or "OAM" for the same |
  23. |reason that I renamed "Plane" to "BG." |
  24. |----------------------------------------------------------------------------|
  25. |rwd2?|Address|Title & Explanation |
  26. |----------------------------------------------------------------------------|
  27. | w |$2100 |Screen display register [INIDISP] |
  28. | | |x000bbbb x: 0 = Screen on. |
  29. | | | 1 = Screen off. |
  30. | | | bbbb: Brightness ($0-$F). |
  31. | | | |
  32. | | | |
  33. | w |$2101 |OAM size register [OBSEL] |
  34. | | |sssnnbbb s: 000 = 8x8 or 16x16. |
  35. | | | 001 = 8x8 or 32x32. |
  36. | | | 010 = 8x8 or 64x64. |
  37. | | | 011 = 16x16 or 32x32. |
  38. | | | 100 = 16x16 or 64x64. |
  39. | | | 101 = 32x32 or 64x64. |
  40. | | | n: Name selection (upper 4k word addr). |
  41. | | | b: Base selection (8k word seg. addr). |
  42. | | | |
  43. | | | |
  44. | w 2 |$2102 |OAM address register [OAMADDL/OAMADDH] |
  45. | | |aaaaaaaa r000000m a: OAM address. |
  46. | | | r: OAM priority rotation. |
  47. | | | m: OAM address MSB. |
  48. | | | |
  49. | | | |
  50. | wd |$2104 |OAM data register [OAMDATA] |
  51. | | |???????? ???????? |
  52. | | | |
  53. | | | |
  54. | w |$2105 |Screen mode register [BGMODE] |
  55. | | |abcdefff a: BG4 tile size (0=8x8, 1=16x16). |
  56. | | | b: BG3 tile size (0=8x8, 1=16x16). |
  57. | | | c: BG2 tile size (0=8x8, 1=16x16). |
  58. | | | d: BG1 tile size (0=8x8, 1=16x16). |
  59. | | | e: Highest priority for BG3 in MODE 1. |
  60. | | | f: MODE definition. |
  61. | | | |
  62. | | | |
  63. | w |$2106 |Screen pixelation register [MOSAIC] |
  64. | | |xxxxabcd x: Pixel size (0=Smallest, $F=Largest). |
  65. | | | a: Affect BG4. |
  66. | | | b: Affect BG3. |
  67. | | | c: Affect BG2. |
  68. | | | d: Affect BG1. |
  69. | | | |
  70. | | | |
  71. | w |$2107 |BG1 VRAM location register [BG1SC] |
  72. | | |xxxxxxab x: Base address |
  73. | | | ab: SC size |
  74. | | | |
  75. | | | |
  76. | w |$2108 |BG2 VRAM location register [BG2SC] -| |
  77. | w |$2109 |BG3 VRAM location register [BG3SC] |- Same as $2107. |
  78. | w |$210A |BG4 VRAM location register [BG4SC] -| |
  79. | | | |
  80. | | | |
  81. | w |$210B |BG1 & BG2 VRAM location register [BG12NBA] |
  82. | | |aaaabbbb a: Base address for BG2. |
  83. | | | b: Base address for BG1. |
  84. | | | |
  85. | | | |
  86. | w |$210C |BG3 & BG4 VRAM location register [BG34NBA] |
  87. | | |aaaabbbb a: Base address for BG4. |
  88. | | | b: Base address for BG3. |
  89. | | | |
  90. | | | |
  91. | wd |$210D |BG1 horizontal scroll register [BG1HOFS] |
  92. | | |mmmmmaaa aaaaaaaa a: Horizontal offset. |
  93. | | | m: Only set with MODE 7. |
  94. | | | |
  95. | | |This is an intruiging register. Like the types define, it has |
  96. | | |to be written to twice: The first byte holds the first 8 bits,|
  97. | | |and the second byte holds the last 3 bits. This makes a total |
  98. | | |of 11 bits for information. This only proves true for MODes |
  99. | | |0 to 6. MODE 7 uses 13 bits instead of 11. As long as you're |
  100. | | |not in MODE 7, you can store $00 in the 2nd byte for a smooth |
  101. | | |scrolling background. |
  102. | | | |
  103. | | | |
  104. | wd |$210E |BG1 vertical scroll register [BG1VOFS] -| |
  105. | wd |$210F |BG2 horizontal scroll register [BG2HOFS] | |
  106. | wd |$2110 |BG3 vertical scroll register [BG2VOFS] | |
  107. | wd |$2111 |BG3 horizontal scroll register [BG3HOFS] |- Same as $210D. |
  108. | wd |$2112 |BG3 vertical scroll register [BG3VOFS] | |
  109. | wd |$2113 |BG4 horizontal scroll register [BG4HOFS] | |
  110. | wd |$2114 |BG4 vertical scroll register [BG4VOFS] -| |
  111. | | | |
  112. | | | |
  113. | w |$2115 |Video port control [VMAIN] |
  114. | | |i000abcd i: 0 = Addr-inc after writing to $2118 |
  115. | | | or reading from $2139. |
  116. | | | 1 = Addr-inc after writing to $2119 |
  117. | | | or reading from $213A. |
  118. | | | ab: Full graphic (see table below). |
  119. | | | cd: SC increment (see table below). |
  120. | | |abcd|Result |
  121. | | |----|---------------------------------------------------------|
  122. | | |0100|Increment by 8 for 32 times (2-bit formation). |
  123. | | |1000|Increment by 8 for 64 times (4-bit formation). |
  124. | | |1100|Increment by 8 for 128 times (8-bit formation). |
  125. | | |0000|Address increments 1x1. |
  126. | | |0001|Address increments 32x32. |
  127. | | |0010|Address increments 64x64. |
  128. | | |0011|Address increments 128x128. |
  129. | | |----|---------------------------------------------------------|
  130. | | | |
  131. | | | |
  132. | w 2 |$2116 |Video port address [VMADDL/VMADDH] |
  133. | | |???????? ???????? |
  134. | | | |
  135. | | | |
  136. | w 2 |$2118 |Video port data [VMDATAL/VMDATAH] |
  137. | | |???????? ???????? |
  138. | | | |
  139. | | |According to bit 7 of $2115, the data can be stored as: |
  140. | | | |
  141. | | |Bit 7|Register |Result |
  142. | | |-----|---------------------------|----------------------------|
  143. | | | 0 |Write to $2118 only. |Lower 8-bits written then |
  144. | | | | |address is increased. |
  145. | | | 0 |Write to $2119 then $2118. |Address increased when both |
  146. | | | | |are written to (in order). |
  147. | | | 1 |Write to $2119 only. |Upper 8-bits written, then |
  148. | | | | |address is increased. |
  149. | | | 1 |Write to $2118 then $2119. |Address increased when both |
  150. | | | | |are written to (in order). |
  151. | | |-----|---------------------------|----------------------------|
  152. | | | |
  153. | | | |
  154. | w |$211A |MODE7 settings register [M7SEL] |
  155. | | |ab0000yx ab: (see table below). |
  156. | | | y: Vertical screen flip (1=flip). |
  157. | | | x: Horizontal screen flip (1=flip). |
  158. | | | |
  159. | | |ab|Result |
  160. | | |--|-----------------------------------------------------------|
  161. | | |00|Screen repetition if outside of screen area. |
  162. | | |10|Character 0x00 repetition if outside of screen area. |
  163. | | |11|Outside of screen area is back-drop screen in 1 colour. |
  164. | | |--|-----------------------------------------------------------|
  165. | | | |
  166. | | | |
  167. | w |$211B |COS (COSINE) rotate angle / X Expansion [M7A] |
  168. | w |$211C |SIN (SIN) rotate angle / X Expansion [M7B] |
  169. | w |$211D |SIN (SIN) rotate angle / Y Expansion [M7C] |
  170. | w |$211E |COS (COSINE) rotate angle / Y Expansion [M7D] |
  171. | wd |$211F |Center position X (13-bit data only) [M7X] |
  172. | wd |$2120 |Center position Y (13-bit data only) [M7Y] |
  173. | | | |
  174. | | |MODE 7 formulae for rotation/enlargement/reduction: |
  175. | | | |
  176. | | |X2 = AB * X1-X0 + X0 |
  177. | | |Y2 = CD * Y1-Y0 + Y0 |
  178. | | | |
  179. | | |A = COS(GAMMA)*(1/ALPHA) B = SIN(GAMMA)*(1/ALPHA) |
  180. | | |C = SIN(GAMMA)*(1/BETA) D = COS(GAMMA)*(1/BETA) |
  181. | | | |
  182. | | | GAMMA: Rotation angle. |
  183. | | | ALPHA: Reduction rates for X (horizontal). |
  184. | | | BETA: Reduction rates for Y (vertical). |
  185. | | |X0 & Y0: Center coordinate. |
  186. | | |X1 & Y1: Display coordinate. |
  187. | | |X2 & Y2: Coordinate before calculation. |
  188. | | | |
  189. | | | |
  190. | w |$2121 |Colour # (or pallete) selection register [CGADD] |
  191. | | |xxxxxxxx x: Address (color #). |
  192. | | | |
  193. | | | |
  194. | wd |$2122 |Colour data register [CGDATA] |
  195. | | |xxxxxxxx x: Value of colour. |
  196. | | | |
  197. | | |SNES colour is 15 bit; 5 bits for red, green, and blue. The |
  198. | | |order isn't RGB though: It's BGR (RGB reversed!). |
  199. | | | |
  200. | | | |
  201. | w |$2123 |Window mask settings register [W12SEL] |
  202. | | |abcdefgh a: Disable/enable BG2 Window 2. |
  203. | | | b: BG2 Window 2 I/O (0=IN). |
  204. | | | c: Disable/enable BG2 Window 1. |
  205. | | | d: BG2 Window 1 I/O (0=IN). |
  206. | | | e: Disable/enable BG1 Window 2. |
  207. | | | f: BG1 Window 2 I/O (0=IN). |
  208. | | | g: Disable/enable BG1 Window 1. |
  209. | | | h: BG1 Window 1 I/O (0=IN). |
  210. | | | |
  211. | | | |
  212. | w |$2124 |Window mask settings register [W34SEL] |
  213. | | |abcdefgh a: Disable/enable BG4 Window 2. |
  214. | | | b: BG4 Window 2 I/O (0=IN). |
  215. | | | c: Disable/enable BG4 Window 1. |
  216. | | | d: BG4 Window 1 I/O (0=IN). |
  217. | | | e: Disable/enable BG3 Window 2. |
  218. | | | f: BG3 Window 2 I/O (0=IN). |
  219. | | | g: Disable/enable BG3 Window 1. |
  220. | | | h: BG3 Window 1 I/O (0=IN). |
  221. | | | |
  222. | | | |
  223. | w |$2125 |Window mask settings register [WOBJSEL] |
  224. | | |abcdefgh a: Disable/enable colour Window 2. |
  225. | | | b: Colour Window 2 I/O (0=IN). |
  226. | | | c: Disable/enable colour Window 1. |
  227. | | | d: Colour Window 1 I/O (0=IN). |
  228. | | | e: Disable/enable OBJ Window 2. |
  229. | | | f: OBJ Window 2 I/O (0=IN). |
  230. | | | g: Disable/enable OBJ Window 1. |
  231. | | | h: OBJ Window 1 I/O (0=IN). |
  232. | | | |
  233. | | | |
  234. | w |$2126 |Window 1 left position register [WH0] |
  235. | | |aaaaaaaa a: Position. |
  236. | | | |
  237. | | | |
  238. | w |$2127 |Window 1 right position register [WH1] -| |
  239. | w |$2128 |Window 2 left position register [WH2] |- Same as $2126. |
  240. | w |$2129 |Window 2 right position register [WH3] -| |
  241. | | | |
  242. | | |I may have the Window numbers reversed; as in, $2126 may be |
  243. | | |for Window 2, not Window 1; $2127 may be for Window 2, not |
  244. | | |Window 1... and so on... |
  245. | | | |
  246. | | | |
  247. | w |$212A |Mask logic settings for Window 1 & 2 per screen [WBGLOG] |
  248. | | |aabbccdd a: BG4 parms -| |
  249. | | | b: BG3 parms |- See table in $212B. |
  250. | | | c: BG2 parms | |
  251. | | | d: BG1 parms -| |
  252. | | | |
  253. | | | |
  254. | w |$212B |Mask logic settings for Colour Windows & OBJ Windows [WOBJLOG]|
  255. | | |0000aabb a: Colour Window parms (see table below)|
  256. | | | b: OBJ Window parms (see table below). |
  257. | | | |
  258. | | |Hi-bit|Lo-bit|Logic |
  259. | | |------|------|------------------------------------------------|
  260. | | | 0 | 0 |OR |
  261. | | | 0 | 1 |AND |
  262. | | | 1 | 0 |XOR |
  263. | | | 1 | 1 |XNOR |
  264. | | |------|------|------------------------------------------------|
  265. | | | |
  266. | | | |
  267. | w |$212C |Main screen designation [TM] |
  268. | | |000abcde a: OBJ/OAM disable/enable. |
  269. | | | b: Disable/enable BG4. |
  270. | | | c: Disable/enable BG3. |
  271. | | | d: Disable/enable BG2. |
  272. | | | e: Disable/enable BG1. |
  273. | | | |
  274. | | | |
  275. | w |$212D |Sub-screen designation [TD] |
  276. | | |*** Same as $212C, but for the sub-screens, not the main. |
  277. | | | |
  278. | | |Remember: When screen addition/subtraction is enabled, the |
  279. | | |sub screen is added/subtracted against the main screen. |
  280. | | | |
  281. | | | |
  282. | w |$212E |Window mask main screen designation register [TMW] |
  283. | | |*** Same as $212C, but for window-masks. |
  284. | | | |
  285. | w |$212F |Window mask sub screen designation register [TSW] |
  286. | | |*** Same as $212E, but for the sub screen. |
  287. | | | |
  288. | | | |
  289. | w |$2130 |Fixed color addition or screen addition register [CGWSEL] |
  290. | | |abcd00ef ab: Main (see table below). |
  291. | | | cd: Sub (see table below). |
  292. | | | e: 0 = Enable +/- for fixed colour. |
  293. | | | 1 = Enable +/- for sub screen. |
  294. | | | f: Colour & char-data = direct color |
  295. | | | data (MODE 3, 4 & 7 only). |
  296. | | | |
  297. | | |ab|Result |
  298. | | |--|-----------------------------------------------------------|
  299. | | |00|All the time. |
  300. | | |01|Inside window only. |
  301. | | |10|Outside window only. |
  302. | | |11|All the time. |
  303. | | |--|-----------------------------------------------------------|
  304. | | | |
  305. | w |$2131 |Addition/subtraction for screens, BGs, & OBJs [CGADSUB] |
  306. | | |mrgsabcd m: 0 = Enable + colour-data mode. |
  307. | | | 1 = Enable - colour-data mode. |
  308. | | | r: See below for more info. |
  309. | | | g: Affect back-area. |
  310. | | | s: Affect OBJs. |
  311. | | | a: Affect BG4. |
  312. | | | b: Affect BG3. |
  313. | | | c: Affect BG2. |
  314. | | | d: Affect BG1. |
  315. | | | |
  316. | | |*** 'r' is some sort-of "1/2 of colour data" on/off bit. When |
  317. | | | the colour constant +/- or screen +/- is performed, desig-|
  318. | | | nate whether the RGB result in the +/- area should be 1/2 |
  319. | | | or not; the back-area is not affected. |
  320. | | | |
  321. | | | |
  322. | w |$2132 |Fixed colour data for fixed colour +/- [COLDATA] |
  323. | | |bgrdddddd b: Set to change blue. |
  324. | | | g: Set to change green. |
  325. | | | r: Set to change red. |
  326. | | | d: Set colour constant data for +/-. |
  327. | | | |
  328. | | | |
  329. | w |$2133 |Screen mode/video select register [SETINI] |
  330. | | |sn00pvshi |
  331. | | | s: Super-impose SFX graphics over ex- |
  332. | | | ternal video (usually 0). |
  333. | | | n: External mode (screen expand). When |
  334. | | | sing MODE 7, enable. |
  335. | | | p: 0 = 256 resolution. |
  336. | | | 1 = 512 sub screen resolution. |
  337. | | | v: 0 = 224 vertical resolution. |
  338. | | | 1 = 239 vertical resolution. |
  339. | | | s: See below for more info. |
  340. | | | i: 0 = No interlace. |
  341. | | | 1 = Interlaced display. |
  342. | | | |
  343. | | |*** When in interlace mode, select either the 1-dot per line |
  344. | | | mode or the 1-dot repeated every 2-lines mode. If '1' is |
  345. | | | set in this bit, the OBJ seems to be reduced vertically |
  346. | | | by 1/2. |
  347. | | | |
  348. | | |*** Interlaced mode is used in the SNES test cartridge. It |
  349. | | | does flicker, but it gives a FULL 480 vertical resolution.|
  350. | | | |
  351. | | | |
  352. |r |$2134 |Multiplication result register (low) [MPYL] |
  353. |r |$2135 |Multiplication result register (middle) [MPYM] |
  354. |r |$2136 |Multiplication result register (high) [MPYH] |
  355. | | |*** Result is 8 bits long for $2134, $2135, and $2136. |
  356. | | | |
  357. | | | |
  358. |r |$2137 |Software latch for horizontal/vertical counter [SLHV] |
  359. | | |aaaaaaaa a: Result. |
  360. | | | |
  361. | | |The counter value at the point when $2137 is read can be |
  362. | | |latched. Data read is meaningless. |
  363. | | | |
  364. | | | |
  365. |r |$2138 |Read data from OAM {OAMDATAREAD} |
  366. |r 2 |$2139 |Read data from VRAM {VMDATALREAD/VMDATAHREAD} |
  367. |r |$213B |Read data from CG-RAM (colour) {CGDATAREAD} |
  368. |r d |$213C |Horizontal scanline location [OPHCT] |
  369. |r d |$213D |Vertical scanline location [OPVCT] |
  370. | | |*** Registers $213C and $213D are 9-bits in length. |
  371. | | | |
  372. | | | |
  373. |r |$213E |PPU status flag & version number [STAT77] |
  374. | | |trm0vvvv t: Time over (see below). |
  375. | | | r: Range over (see below). |
  376. | | | m: Master/slave mode select. Usually 0. |
  377. | | | v: Version # ($5C77 (???)). |
  378. | | | |
  379. | | |*** Range: When the quantity of the OBJ (size is non-relevant)|
  380. | | | becomes 33 pieces or more, '1' is set. |
  381. | | | Time: When the quantity of the OBJ which is converted to |
  382. | | | 8x8 is 35 pieces or more, '1' will be set. |
  383. | | | |
  384. | | | |
  385. |r |$213F |PPU status flag & version number [STAT78] |
  386. | | |fl0mvvvv f: Field # scanned in int. mode (0=1st).|
  387. | | | l: Set if external signal (light pen, |
  388. | | | etc.) is installed/applied. |
  389. | | | m: NTSC/PAL mode (0=NTSC, 1=PAL). |
  390. | | | v: Version # ($5C78 (???)). |
  391. | | | |
  392. | | | |
  393. |rw |$2140 |[APUI00] -| |
  394. |rw |$2141 |[APUI01] |- Audio registers. See sound.doc and sid-spc.src. |
  395. |rw |$2142 |[APUI02] | |
  396. |rw |$2143 |[APUI03] -| |
  397. | | | |
  398. | | | |
  399. |rw |$2180 |Read/write WRAM register [WMDATA] |
  400. |rw |$2181 |WRAM data register (low byte) [WMADDL] |
  401. |rw |$2182 |WRAM data register (middle byte) [WMADDM] |
  402. |rw |$2183 |WRAM data register (high byte) [WMADDH] |
  403. | | | |
  404. | | | |
  405. | w |$4200 |Counter enable [NMITIMEN] |
  406. | | |a0yx000b a: NMI/VBlank interrupt. |
  407. | | | y: Vertical counter. |
  408. | | | x: Horizontal counter. |
  409. | | | b: Joypad read-enable. |
  410. | | | |
  411. | | | |
  412. | w |$4201 |Programmable I/O port (out-port) [WRIO] |
  413. | | | |
  414. | | | |
  415. | w |$4202 |Multiplicand 'A' [WRMPYA] |
  416. | w |$4203 |Multiplier 'B' [WRMPYB] |
  417. | | |*** Absolute multiplication used when using the two above reg-|
  418. | | | isters. Formulae is: 'A (8-bit) * B (8-bit) = C (16-bit)'.|
  419. | | | Result can be read from $4216. |
  420. | | | |
  421. | | | |
  422. | w 2 |$4204 |Dividend C [WRDIVL/WRDIVH] |
  423. | w |$4205 |Divisor B [WRDIVB] |
  424. | | |*** Absolute division used when using the two above registers.|
  425. | | | Formulae is 'C (16-bit) / B (8-bit) = A (16-bit)'. |
  426. | | | Result can be read from $4214, and the remainder read from|
  427. | | | $4216. |
  428. | | |*** Operation will start when $4205 is set, and will be com- |
  429. | | | pleted after 16 machine cycles. |
  430. | | | |
  431. | | | |
  432. | w 2 |$4207 |Video horizontal IRQ beam position/pointer [HTIMEL/HTIMEH] |
  433. | | |0000000x xxxxxxxx x: Beam position. |
  434. | | | |
  435. | | |Valid values for x range from 0 to 339, due to overscan. The |
  436. | | |timer is reset every scanline, so unless it's disabled, you'll|
  437. | | |receive an interrupt every time the beam hits the value given.|
  438. | | | |
  439. | | | |
  440. | w 2 |$4209 |Video vertical IRQ beam position/pointer [VTIMEL/VTIMEH] |
  441. | | |0000000y yyyyyyyy y: Beam position. |
  442. | | | |
  443. | | |Same as $4207, but valid values for y are 0 to 261 (based from|
  444. | | |overscan at the top of the screen). |
  445. | | | |
  446. | | | |
  447. | w |$420B |DMA enable register [MDMAEN] |
  448. | | |abcdefgh a: DMA channel #7. |
  449. | | | b: DMA channel #6. |
  450. | | | c: DMA channel #5. |
  451. | | | d: DMA channel #4. |
  452. | | | e: DMA channel #3. |
  453. | | | f: DMA channel #2. |
  454. | | | g: DMA channel #1. |
  455. | | | h: DMA channel #0. |
  456. | | | |
  457. | | | |
  458. | w |$420C |HDMA enable register. |
  459. | | |*** Same as $420B, virtually. |
  460. | | | |
  461. | | | |
  462. | w |$420D |Cycle speed register [MEMSEL] |
  463. | | |0000000x x: 0 = Normal (2.68MHz). |
  464. | | | 1 = Fast (3.58MHz). |
  465. | | | |
  466. | | |Note that using the fast mode requires 120ns or faster EPROMs.|
  467. | | | |
  468. | | | |
  469. |r |$4210 |NMI register [RDNMI] |
  470. | | |x000vvvv x: Disable/enable NMI. |
  471. | | | v: Version # ($5A22 (???)) |
  472. | | | |
  473. | | |Bit 7 can be reset to 0 by reading this register. |
  474. | | | |
  475. | | | |
  476. |rw |$4211 |Video IRQ register [TIMEUP] |
  477. | | |i0000000 i: 0 = IRQ is not enabled. |
  478. | | | 1 = IRQ is enabled. |
  479. | | | |
  480. | | |This location MUST be read to clear a horizontal or vertical |
  481. | | |raster interrupt. It's all relative to $4200. If the horiz- |
  482. | | |ontal timer interrupt (bit 4, $4200) is set then the interrupt|
  483. | | |will be generated according to the position in $4207. Same |
  484. | | |thing is for vertical timing (bit 5, $4200) but the position |
  485. | | |will be read from $4209, not $4207. |
  486. | | | |
  487. | | | |
  488. |rw |$4212 |Status register [HVBJOY] |
  489. | | |xy00000a x: 0 = Not in VBlank state. |
  490. | | | 1 = In VBlank state. |
  491. | | | y: 0 = Not in HBlank state. |
  492. | | | 1 = In HBlank state. |
  493. | | | a: 0 = Joypad not ready. |
  494. | | | 1 = Joypad ready. |
  495. | | | |
  496. | | | |
  497. |r |$4213 |Programmable I/O port (in-port) [RDIO] |
  498. | | | |
  499. | | | |
  500. |r 2 |$4214 |Quotient of divide result [RDDIVL/RDDIVH] |
  501. | | | |
  502. | | | |
  503. |r 2 |$4216 |Multiplication or divide result [RDMPYL/RDMPYH] |
  504. | | | |
  505. | | | |
  506. |r |$4218 |Joypad #1 status register [JOY1L] |
  507. | | |abcd0000 a: A button (1=pressed). |
  508. | | | b: X button (1=pressed). |
  509. | | | c: Top-Left (1=pressed). |
  510. | | | d: Top-Rght (1=pressed). |
  511. | | | |
  512. |r |$4219 |Joypad #1 status register [JOY1H] |
  513. | | |abcdefgh a: B button (1=pressed). |
  514. | | | b: Y button (1=pressed). |
  515. | | | c: Select (1=pressed). |
  516. | | | d: Start (1=pressed). |
  517. | | | e: Up (1=pressed). |
  518. | | | f: Down (1=pressed). |
  519. | | | g: Left (1=pressed). |
  520. | | | h: Right (1=pressed). |
  521. | | | |
  522. |r |$421A |Joypad #2 status register [JOY2L] -| |
  523. |r |$421B |Joypad #2 status register [JOY2H] | |
  524. |r |$421C |Joypad #3 status register [JOY3L] |- Same as $4218 & $4219. |
  525. |r |$421D |Joypad #3 status register [JOY3H] | |
  526. |r |$421E |Joypad #4 status register [JOY4L] | |
  527. |r |$421F |Joypad #4 status register [JOY4H] -| |
  528. | | |*** Joypad registers can be read w/ a 16-bit accum/X/Y and |
  529. | | | both the high and low bytes will received valid data. |
  530. | | | |
  531. | | | |
  532. |----------------------------------------------------------------------------|
  533. |The following data is for DMA-transfers. 'x' represents the DMA channel #, |
  534. |which ranges from 0 to 7. So, the following would represent each section: |
  535. |DMA #0: $4300-$4305. |
  536. |DMA #1: $4310-$4315. |
  537. |.................... |
  538. |DMA #7: $4370-$4375. |
  539. |----------------------------------------------------------------------------|
  540. | w |$43x0 |DMA Control register [DMAPX] |
  541. | | |vh0cbaaa v: 0 = CPU memory -> PPU. |
  542. | | | 1 = PPU -> CPU memory. |
  543. | | | h: For HDMA only: |
  544. | | | 0 = Absolute addressing. |
  545. | | | 1 = Indirect addressing. |
  546. | | | c: 0 = Auto address inc/decrement. |
  547. | | | 1 = Fixed address (for VRAM, etc.). |
  548. | | | b: 0 = Automatic increment. |
  549. | | | 1 = Automatic decrement. |
  550. | | | a: Transfer type:
  551. | | | 000 = 1 address write twice: LH. |
  552. | | | 001 = 2 addresses: LH. |
  553. | | | 010 = 1 address write once. |
  554. | | | 011 = 2 addresses write twice: LLHH |
  555. | | | 100 = 4 addresses: LHLH |
  556. | | | |
  557. | | | |
  558. | w |$43x1 |DMA Destination register [BBADX] |
  559. | | |xxxxxxxx x: Low-byte address. |
  560. | | | |
  561. | | |*** The upper-byte address is assumed to be $21, making your |
  562. | | | access addresses $2100 to $21FF. |
  563. | | | |
  564. | | | |
  565. | w 2 |$43x2 |Source address [A1TXL/A1TXH] |
  566. | w |$43x4 |Source bank address [A1BX] |
  567. | w 2 |$43x5 |DMA transfer size & HDMA address register [DASXL/DASXH] |
  568. | | |*** When using DMA, $43x5 defines the # of bytes to be trans- |
  569. | | | ferred via DMA itself. When using HDMA, $43x5 defines the |
  570. | | | data address ($43x5 = low byte, $43x6 = hi byte). |
  571. | | | |
  572. | | | |
  573. | w |$43xA |Number of lines for HDMA transfer [NTRLX] |
  574. | | |cxxxxxxx c: Continue (0=yes, 1=no (???)). |
  575. | | | x: # of lines to transfer. |
  576. |----------------------------------------------------------------------------|
  577. |Additional information follows. |
  578. |Most of the following information is for SMC files, and where the header |
  579. |info is kept in memory, etc. etc. etc... |
  580. |----------------------------------------------------------------------------|
  581. |rw |$FEED |UNDOCUMENTED REGISTER: Felon's banana register [FBNANACNT] |
  582. | | |rcnnnnnn r: Ripe bit (0=ripe, 1=rotten). |
  583. | | | c: Colour bit (0=yellow, 1=green). |
  584. | | | n: Number of bananas. |
  585. | | | |
  586. | | |*** This register counts the number of bananas Felon currently|
  587. | | | has in his possession... (Who the hell is Felon?!). |
  588. | | | |
  589. | | |*** According to numerous sources, this register can be used |
  590. | | | to calculate pi to the 5-billionth digit in 20 clock |
  591. | | | cycles. The number of cycles corresponds to Felon's age, |
  592. | | | increasing by 1 every 365 days (1 year). It is increased |
  593. | | | by 2 every leap year. |
  594. | | | |
  595. | | | |
  596. |rw |$FFC0 |Cartridge title. |
  597. |rw |$FFD6 |ROM/RAM information on cart. |
  598. |rw |$FFD7 |ROM size. |
  599. |rw |$FFD8 |RAM size. |
  600. |rw |$FFD9 |Developer ID code. |
  601. |rw |$FFDB |Version number. |
  602. |rw |$FFDC |Checksum complement. |
  603. |rw |$FFDE |Checksum. |
  604. |rw |$FFEA |NMI vector/VBL interrupt. |
  605. |rw |$FFEC |Reset vector. |
  606. ----------------------------------------------------------------------------