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- ADDRESS : $2100
- NAME : INIDISP
- CONTENTS : INITIAL SETTINGS FOR SCREEN
- D7 BLANKING:
- FORCED BLANKING, 0:NON-BLANKING,1:BLANKING.
- D6-D4 ---
- D3-D0 FADE IN/OUT:
- 0000-DARKEST,1111-BRIGHTEST.
- ADDRESS : $2101
- NAME : OBSEL
- CONTENTS : OBJECT SIZE & OBJECT DATA AREA DESIGNATION
- D7-D5 SIZE SELECT:
- D7 D6 D5 0 1 (SIZE LARGE/SMALL)
- 0 0 0 8 16
- 0 0 1 8 32
- 0 1 0 8 64
- 0 1 1 16 32
- 1 0 0 16 64
- 1 0 1 32 64 (DOTS.)
- D4-D3 NAME SELECT
- THE UPPER 4K-WORD OUT OF THE AREA (8K-WORD)
- DESIGNATED BY "OBJECT BASE ADDRESS" IS ASSIGNED
- AS THE BASE AREA, AND THE AREA OF THE LOWER 4K-
- WORD COMBINED WITH ITS BASE AREA CAN BE
- SELECTED. (SEE APPENDIX 1 & 2)
- D2-D0 NAME BASE SELECT (UPPER-3 BIT)
- DESIGNATE THE SEGMENT (8K-WORD) ADDRESS WHICH
- THE OBJ DATA IS STORED IN VRAM. (APPENDIX 1 & 2)
- ADDRESS : $2102/$2103
- NAME : OAMADDL/OAMADDH
- CONTENTS : ADDRESS FOR ACCESSING OAM
- D7-D0 OAM ADDRESS (A7-A0) 2102H
- D7 OAM PRIORITY ROTATION 2103H
- D6-D1 ---
- D0 OAM ADDRESS MSB (A8)
- THIS IS THE INITIAL ADDRESS TO BE SET IN ADVANCE WHEN READING
- READING FROM THE OAM OR WRITING TO THE OAM.
- BY WRITING "1" TO D7 OF REGISTER <2103H> AND SETTING THE OAM-
- ADDRESS THE OBJ FOR THE ADDRESS SET HAS HIGHEST PRIORITY.
- THE ADDRESS WHICH HAS BEEN SET JUST BEFORE EVERY FIELD
- (BEGINNING OF V-BLANK) WILL BE SET AGAIN TO REGISTERS <2102H>
- <2103H> AUTOMATICALLY. BUT, THE ADDRESS CAN NOT BE SET
- AUTOMATICALLY DURING FORCED BLANK PERIOD.
- ADDRESS : $2104
- NAME : OAMDATA
- CONTENTS : DATA FOR OAM WRITE
- D7-D0 OAM DATA (LOW,HIGH)
- THIS IS THE OAM DATA TO BE WRITTING AT ANY ADDRESS OF THE OAM.
- (SEE APPENDIX-3)
- AFTER REGISTER <2102H> OR <2103H> IS ACCESSED, THE DATA MUST
- BE WRITTEN IN THE ORDER OF LOWER 8-BIT & UPPER 8-BIT OF REGISTER
- <2104H>.
- THE DATA CAN BE WRITTEN ONLY DURING V-BLANK OR FORCED BLANK
- PERIOD.
- ADDRESS : $2105
- NAME : BGMODE
- CONTENTS : BG MODE & CHARACTER SIZE SETTINGS
- D7-D4 BG SIZE DESIGNATION (BG4-BG1)
- 0: 8 x 8 DOT/CHARACTER
- 1: 16 x 16 DOT/CHARACTER
- D3 HIGHEST PRIORITY DESIGNATION FOR BG-3 IN MODE 1
- 0: OFF (SEE APPENDIX-16)
- 1: ON
- D2-D0 BG SCREEN MODE SELECT (SEE APPENDIX-5)
- ADDRESS : $2106
- NAME : MOSAIC
- CONTENTS : SIZE & SCREEN DESIGNATION FOR MOSAIC DISPLAY
- D7-D4 MOSAIC SIZE (SEE APPENDIX-6)
- 1111 - LARGEST, 0000 - SMALLEST.
- D3-D0 MOSAIC ENABLE (BG4-B1)
- 0: OFF
- 1: ON
- ADDRESS : $2107/$2108/$2109/$210A
- NAME : BG1SC/BG2SC/BG3SC/BG4SC
- CONTENTS : ADDRESS FOR STORING SC-DATA OF EACH BG & SC SIZE DESIGNATION
- D7-D2 SC BASE ADDRESS
- DESIGNATE THE SEGMENT WHICH BG-SC IN THE VRAM
- IS STORED. (1K-WORD/SEGMENT)
- D1-D0 SC SIZE
- DESIGNATE BACKGROUND SCREEN SIZE (APPENDIX-18 & 19)
- 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 1
- 0 0 1 1 0 1 2 3
- ADDRESS : $210B/$210C
- NAME : BG12NBA/BG34NBA
- CONTENTS : BG CHARACTER DATA ARE DESIGNATION
- D7-D4 BG2 BASE ADDRESS 210BH
- D3-D0 BG1 BASE ADDRESS
- D7-D4 BG4 BASE ADDRESS 210CH
- D3-D0 BG3 BASE ADDRESS
- BACKGROUND NAME BASE ADDRESS (UPPER 4-BIT), SEGMENT ADDRESS
- IN THE VRAM WHERE BG CHARACTER DATA IS STORED. (4K-WORD/SEGMENT)
- ADDRESS : $210D/$210E/$210F/$2110/$2111/$2112/$2113/$2114
- NAME : BG1HOFS/BG1VOFS/BG2HOFS/BG2VOFS/BG3HOFS/BG3VOFS/BG4HOFS/BG4VOFS
- CONTENTS : H/V SCROLL VALUE DESIGNATION FOR BG
- D7-D0 H-OFFSET (LOW,HIGH) HOFS
- D7-D0 V-OFFSET (LOW,HIGH) VOFS
- 10 BIT MAXIMUM (0-1023) CAN BE DESIGNATED FOR H/V SCROLL VALUE.
- [THE SIZE OF 13-BIT MAXIMUM (-4096->4095) CAN BE DESIGNATED IN
- MODE 7] (SEE APPENDIX-8 & 9)
- BY WRITING TO THE REGISTER TWICE, THE DATA CAN BE SET IN ORDER
- OF LOW & HIGH.
- ADDRESS : $2115
- NAME : VMAIN
- CONTENTS : VRAM ADDRESS INCREMENT VALUE DESIGNATION
- D7 H/L INC (WORD OR BYTE VRAM ACCESS)
- DESIGNATE THE INCREMENT TIMING FOR THE ADDRESS
- 0: THE ADDRESS WILL BE INCREASED AFTER THE DATA HAS
- BEEN WRITTEN TO REGISTER <2118H> OR THE DATA
- HAS BEEN READ FROM REGISTER <2139H>.
- THIS WILL RESULT IN BYTE VRAM ACCESS, I.E. FOR
- MODE 7 TILE MAP CHANGE.
- 1: THE ADDRESS WILL BE INCREASED AFTER THE DATA HAS
- BEEN WRITTEN TO REGISTER <2119H> OR THE DATA
- HAS BEEN READ FROM REGISTER <213AH>.
- THIS WILL RESULT IN WORD VRAM ACCESS, I.E. FOR
- MODE 1 TILE MAP CHANGE.
- D6-D4 ---
- D3-D2 FULL GRAPHIC (G1 & G0)
- D1-D0 SC INCREMENT (I1 & I0)
- G1 G0 I1 I0 | INCREMENT VALUE
- ----------------------------
- 0 1 0 0 | INCREMENT BY 8 FOR 32 TIMES (2-BIT FORMATION)
- 1 0 0 0 | INCREMENT BY 8 FOR 64 TIMES (4-BIT FORMATION)
- 1 1 0 0 | INCREMENT BY 8 FOR 128 TIMES (8-BIT FORMATION)
- 0 0 0 0 | ADDRESS INCREMENTS 1 BY 1
- 0 0 0 1 | ADDRESS INCREMENTS 32 BY 32
- 0 0 1 0 | ADDRESS INCREMENTS 64 BY 64
- 0 0 1 1 | ADDRESS INCREMENTS 128 BY 128
- ADDRESS : $2116/$2117
- NAME : VMADDL/VMADDH
- CONTENTS : ADDRESS FOR VRAM READ
- D7-D0 VRAM ADDRESS (LOW) 2116H
- D7-D0 VRAM ADDRESS (HIGH) 2117H
- THIS IS THE INITIAL ADDRESS FOR READING FROM THE VRAM OR WRITING
- TO THE VRAM.
- THE DATA IS READ OR WRITTEN BY THE ADDRESS SET INITIALLY, AND
- EVERY TIME THE DATA IS READ THE ADDRESS WIL BE INCREASED
- AUTOMATICALLY.
- THE VALUE TO BE INCREASED IS DETERMINED BY "SC INCREMENT" OF
- REGISTER <2115H> AND THE SETTING VALUE OF THE "FULL GRAPHIC".
- ADDRESS : $2118/$2119
- NAME : VMDATAL/VMDATAH
- CONTENTS : DATA FOR VRAM WRITE
- D7-D0 VRAM DATA (LOW) 2118H
- D7-D0 VRAM DATA (HIGH) 2119H
- THIS IS THE SCREEN DATA AND CHARACTER DATA (BG & OBJ), WHICH
- CAN WRITE AT ANY ADDRESS OF THE VRAM.
- ACCORDING TO THE SETTING OF REGISTER <2115H> "H/L INC.", THE
- DATA CAN BE WRITTEN TO THE VRAM AS FOLLOWS:
- H/L INC | WRITE TO REGISTER | OPERATION
- --------------------------------------------------------------
- 0 | WRITE TO <2118H> | THE DATA IS WRITTEN TO LOWER 8BIT
- | ONLY. | OF THE VRAM & THE ADDRESS WILL BE
- | | INCREASED AUTOMATICALLY.
- 1 | WRITE TO <2119H> | THE DATA IS WRITTEN TO UPPER 8BIT
- | ONLY. | OF THE VRAM & THE ADDRESS WILL BE
- | | INCREASED AUTOMATICALLY.
- 0 | WRITE IN ORDER OF | WHEN THE DATA IS SET IN THE ORDER
- | <2119H> & <2118H> | OF UPPER & LOWER THE ADDRESS WILL
- | | BE INCREASED.
- 1 | WRITE IN ORDER OF | WHEN THE DATA IS SET IN THE ORDER
- | <2118H> & <2119H> | OF LOWER & UPPER THE ADDRESS WILL
- | | BE INCREASED.
- NOTE: THE DATA CAN ONLY BE WRITTEN DURING V-BLANK OR FORCED BLANK
- ~~~~~ PERIOD.
- ADDRESS : $211A
- NAME : M7SEL
- CONTENTS : INITIAL SETTING IN SCREEN MODE-7
- D7-D6 SCREEN OVER (O1 & O0)
- PROCESS MADE IF THE SCREEN TO BE DISPLAYED IS
- OUTSIDE OF THE SCREEN AREA. (SEE BELOW)
- D5-D2 ---
- D1-D0 SCREEN FLIP (V/H)
- 0: NORMAL
- 1: FLIPPED
- O1 O0 | PROCESS OUT OF AREA
- --------------------------------------------------------------
- 0 0 | SCREEN REPETITION IF OUTSIDE OF SCREEN AREA
- 1 0 | CHARACTER 0x00 REPETITION IF OUTSIDE OF SCREEN AREA
- 1 1 | OUTSIDE OF THE SCREEN AREA IS THE BACK DROP SCREEN IN
- | SINGLE COLOR
- ADDRESS : $211B/$211C/$211D/$211E/$211F/$2120
- NAME : M7A/M7B/M7C/M7D/M7X/M7Y
- CONTENTS : ROTATION/ENLARGEMENT/REDUCTION IN MODE-7, CENTER COORDINATE
- SETTINGS & MULTIPLICAND/MULTIPLIER SETTINGS OF COMPLEMENTARY
- MULTIPLICATION.
- D7-D0 MATRIX PARAMETER A (LOW[MP7-MP0],HIGH[MP15-MP8])211BH
- D7-D0 MATRIX PARAMETER B (LOW[MP7-MP0],HIGH[MP15-MP8])211CH
- D7-D0 MATRIX PARAMETER C (LOW[MP7-MP0],HIGH[MP15-MP8])211DH
- D7-D0 MATRIX PARAMETER D (LOW[MP7-MP0],HIGH[MP15-MP8])211EH
- THE 8-BIT DATA SHOULD BE WRITTEN TWICE IN THE ORDER OF LOWER &
- UPPER. THEN, THE PARAMETER OF ROTATION, ENLARGEMENT AND REDUCTION
- SHOULD BE SET BY ITS 16-BIT AREA.
- THE VALUE DOWN TO A DECIMAL POINT SHOULD BE SET TO THE LOWER
- 8-BIT. THE MOST SIGNIFICANT BIT OF THE UPPER 8-BIT IS FOR THE
- SIGNED BIT. (MP15 IS THE SIGNED BIT. THERE IS A DECIMAL POINT
- BETWEEN M7 & M8)
- FORMULA FOR ROTAION/ENLARGEMENT/REDUCTION (SEE APPENDIX-13)
- / X2 \ / A B \ / X1-X0 \ / X0 \
- | | = | | | | + | |
- \ Y2 / \ C D / \ Y1-Y0 / \ Y0 /
- A=COS(GAMMA)*(1/ALPHA), B=SIN(GAMMA)*(1/ALPHA)
- C=-SIN(GAMMA)*(1/BETA), D=COS(GAMMA)*(1/BETA)
- GAMMA: ROTATION ANGLE
- ALPHA: REDUCTION RATES FOR X(H)
- BETA : REDUCTION RATES FOR Y(V)
- X0&Y0: CENTER COORDINATE
- X1&Y1: DISPLAY COORDINATE
- X2&Y2: COORDINATE BEFORE CALCULATION
- SET THE VALUE OF "A" TO REGISTER <211BH>. IN THE SAME WAY,
- SET "B-D" TO THE REGISTERS <211CH>-<211EH>.
- * THE COMPLEMENTARY MULTIPLICATION (16BIT X 8BIT) CAN BE DONE BY
- USING REGISTERS <211BH> <211C>.
- WHEN SETTING 16 BIT DATA TO REGISTER <211BH> AND 8BIT DATA TO
- REGISTER <211CH>, THE MULTIPLICATION RESULT CAN BE INDICATED
- RAPIDLY BY READING REGISTERS <2134H>-<2136H>.
- D7-D0 CENTER POSITION X0 (LOW[X7-X0],HIGH[X12-X8]) 211FH
- D7-D0 CENTER POSITION Y0 (LOW[Y7-X0],HIGH[Y12-X8]) 2120H
- THE CENTER COORDINATE (X0,Y0) FOR ROTATION/ENLARGEMENT/REDUCTION
- CAN BE DESIGNATED BY THIS REGISTER.
- THE COORDINATE VALUE OF X0 & Y0 CAN BE DESIGNATED BY 13-BIT
- (COMPLEMENT OF 2).
- THE REGISTER REQUIRES THAT THE LOWER 8-BIT IS SET FIRST AND THE
- UPPER 5-BIT IS SET. THEREFORE, 13-BIT DATA IN TOTAL CAN BE SET.
- ADDRESS : $2121
- NAME : CGADD
- CONTENTS : ADDRESS FOR CG-RAM WRITE
- D7-D0 CG-RAM ADDRESS
- THIS IS THE INITIAL ADDRESS FOR READING FROM THE CG-RAM OR
- WRITING TO THE CG-RAM
- THE DATA IS READ BY THE ADDRESS SET INITIALLY, AND EVERY TIME
- THE DATA IS READ OR WRITTEN THE ADDRESS WILL BE INCREASED
- AUTOMATICALLY.
- ADDRESS : $2122
- NAME : CGDATA
- CONTENTS : DATA FOR CG-RAM WRITE
- D7-D0 CG-RAM DATA (LOW[D7-D0],HIGH[D14-D8])
- THIS IS THE COLOR GENERATER DATA TO BE WRITTEN AT ANY ADDRESS
- OF THE CG-RAM.
- THE MAPPING OF BG1-BG4 AND OBJ DATA IN CG-RAM WILL BE DETERMINED,
- WHICH IS PERFORMED BY EVERY MODE SELECTED BY "BG MODE" OF
- REGISTER <2105H>. (SEE APPENDIX-14)
- THERE AREA THE COLOR DATA OF 8-PALETTES FOR EACH SCREEN OF
- BG1-BG4. THE PALETTE SELECTION IS DETERMINED BY 3-BIT OF THE
- SC DATA "COLOR"
- BECAUSE THE CG-RAM DATA IS 15-BIT/WORD, IT IS NECESSARY TO SET
- LOWER 8-BIT FIRST TO THIS REGISTER AND THE THE UPPER 7-BIT.
- WHEN BOTH LOWER & UPPER ARE SET, THE ADDRESS WILL BE INCREASED
- BY 1 AUTOMATICALLY.
- NOTE: AFTER THE ADDRESS IS SET, THE DATA SHOULD BE WRITTEN FROM
- ~~~~~ THE LOWER AS WELL AS THE OAM.
- NOTE: THE DATA CAN BE WRITTEN ONLY DURING H/V BLANK OR FORCED-
- ~~~~~ BLANK PERIOD.
- ADDRESS : $2123/$2124/$2125
- NAME : W12SEL/W34SEL/WOBJSEL
- CONTENTS : WINDOW MASK SETTINS (BG1-BG4, OBJ, COLOR)
- D7 BG2 WINDOW-2 ENABLE 2123H
- 0: OFF
- 1: ON
- D6 BG2 WINDOW-2 IN/OUT
- THE WINDOW MASK AREA CAN BE DESIGNATED WHETHER
- INSIDE OR OUTSIDE OF THE FRAME DESIGNATED BY THE
- WINDOW POSITION.
- 0: IN
- 1: OUT
- D5 BG2 WINDOW-1 ENABLE
- D4 BG2 WINDOW-1 IN/OUT
- D3 BG1 WINDOW-2 ENABLE
- D2 BG1 WINDOW-2 IN/OUT
- D1 BG1 WINDOW-1 ENABLE
- D0 BG1 WINDOW-1 IN/OUT
- D7 COLOR WINDOW-2 ENABLE 2125H
- D6 COLOR WINDOW-2 IN/OUT
- D5 COLOR WINDOW-1 ENABLE
- D4 COLOR WINDOW-1 IN/OUT
- D3 OBJ WINDOW-2 ENABLE
- D2 OBJ WINDOW-2 IN/OUT
- D1 OBJ WINDOW-1 ENABLE
- D0 OBJ WINDOW-1 IN/OUT
- THE COLOR WINDOW IS A WINDOW FOR MAIN & SUB SCREEN (IT IS
- RELATED TO REGISTER <2130H>.
- ADDRESS : $2126/$2127/$2128/$2129
- NAME : WH0/WH1/WH2/WH3
- CONTENTS : WINDOW POSITION DESIGNATION (SEE APPENDIX-15)
- D7-D0 WINDOW PPOSITION
- H0,H2 LEFT POSITION DESIGNATION
- H1,H3 RIGHT POSITION DESIGNATION
- NOTE: IF "LEFT POSITION SETTING VALUE > RIGHT POSITION VALUE"
- ~~~~~ IS ASSUMED, THERE WILL BE NO RANGE OF THE WINDOW.
- ADDRESS : $212A/$212B
- NAME : WBGLOG/WOBJLOG
- CONTENTS : MASK LOGIC SETTINGS FOR WINDOW-1 & 2 ON EACH SCREEN
- D7-D6 BG4 D1/D0 212AH
- D5-D4 BG3 D1/D0
- D3-D2 BG2 D1/D0
- D1-D0 BG1 D1/D0
- D7-D4 --- 212BH
- D3-D2 COLORWINDOW D1/D0
- D1-D0 OBJWINDOW D1/D0
- D1 D0 | LOGIC
- ------------------
- 0 0 | OR
- 0 1 | AND
- 1 0 | XOR
- 1 1 | XNOR
- NOTE: "IN/OUT" OF REGISTERS <2123H>-<2125H> BECOMES THE
- ~~~~~ "NOT-LOGIC" FOR EACH WINDOW-1 & WINDOW-2.
- ADDRESS : $212C
- NAME : TM
- CONTENTS : MAIN SCREEN, DESIGNATION
- D7-D5 ---
- D4 OBJ
- D3 BG4
- D2 BG3
- D1 BG2
- D0 BG1
- MAIN SCREEN DESIGNATION:
- DESIGNATE THE SCREEN (BG1-BG4, OBJ) TO BE DISPLAYED
- AS THE MAIN SCREEN. DESIGNATE THE SCREEN TO BE ADDED
- FOR THE SCREEN ADDITION/SUBTRACTION
- 0: DISABLE
- 1: ENABLE
- ADDRESS : $212D
- NAME : TS
- CONTENTS : SUB SCREEN DESIGNATION
- D7-D5 ---
- D4 OBJ
- D3 BG4
- D2 BG3
- D1 BG2
- D0 BG1
- SUB SCREEN DESIGNATION:
- DESIGNATE THE SCREEN (BG1-BG4, OBJ) TO BE DISPLAYED
- AS SUB SCREEN. DESIGNATE THE ADDITION/SUBTRACTION
- SCREEN AT THE POINT WHEN THE SCREEN ADDITION/SUBTRACTION
- IS FUNCTIONING.
- 0: DISABLE
- 1: ENABLE
- * WHEN THE SCREEN ADDITION/SUBTRACTION IS FUNCTIONING, THE SUB
- SCREEN IS A SCREEN TO BE ADDED OR SUBTRACTED AGAINST THE MAIN
- SCREEN.
- ADDRESS : $212E
- NAME : TMW
- CONTENTS : WINDOW MASK DESIGNATION FOR MAIN SCREEN
- D7-D5 ---
- D4 OBJ
- D3 BG4
- D2 BG3
- D1 BG2
- D0 BG1
- WINDOW MASK DESIGNATION FOR MAIN SCREEN:
- IN THE WINDOW AREA DESIGNATED BY REGISTER <2123H>-<2129H>,
- THE SCREEN TO BE DISPLAYED CAN BE DESIGNATED, WHICH IS
- SELECTED AMONG THE MAIN SCREEN DESIGNATED BY REGISTER
- <212CH>.
- 0: DISABLE
- 1: ENABLE
- ADDRESS : $212F
- NAME : TSW
- CONTENTS : WINDOW MASK DESIGNATION FOR SUB SCREEN
- D7-D5 ---
- D4 OBJ
- D3 BG4
- D2 BG3
- D1 BG2
- D0 BG1
- WINDOW MASK DESIGNATION FOR SUB SCREEN:
- IN THE WINDOW AREA DESIGNATED BY REGISTER <2123H>-<2129H>,
- THE SCREEN TO BE DISPLAYED CAN BE DESIGNATED, WHICH IS
- SELECTED AMONG THE SUB SCREEN DESIGNATED BY REGISTER
- <212CH>.
- 0: DISABLE
- 1: ENABLE
- * WHEN THE SCREEN ADDITION/SUBTRACTION IS FUNCTIONING, THE SUB
- SCREEN IS A SCREEN TO BE ADDED OR SUBTRACTED AGAINST THE MAIN
- SCREEN.
- ADDRESS : $2130
- NAME : CGWSEL
- CONTENTS : INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION
- D7-D6 MAIN SW (M1/M0)
- D5-D4 SUB SW (S1/S0)
- D3-D2 ---
- D1 CC ADD ENABLE, FIXED COLOR ADDITION/SUBTRACTION ENABLE
- DESIGNATE WHETHER 2 KINDS OF THE DATA SHOULD
- BE ADDED/SUBTRACTED EACH OTHER OR NOT, WHICH ARE
- THE FIXED COLOR SET BY REGISTER <2132H>, AND
- THE COLOR DATA WHICH IS SET TO CGRAM.
- 0: ADDITION/SUBTRACTION FOR FIXED COLOR
- 1: ADDITION/SUBTRACTION FOR SUB SCREEN
- D0 DIRECT SELECT (SEE APPENDIX-14)
- THE VRAM DATA (COLOR & CHARACTER DATA) BECOME THE
- COLOR DATA DIRECTLY. [ONLY WHEN MODE-3,4 & 7]
- 0: DISABLE
- 1: ENABLE
- M1(S1) M0(S0) | NORMAL DISPLAY IS:
- --------------------------------------------------------------
- 0 0 | ALL THE TIME
- 0 1 | INSIDE WINDOW ONLY
- 1 0 | OUTSIDE WINDOW ONLY
- 1 1 | ALL THE TIME
- ADDRESS : $2131
- NAME : CGADSUB
- CONTENTS : ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN,
- OBJ & BACKGROUND COLOR
- D7 COLOR DATA ADDITION/SUBTRACTION SELECT
- DESIGNATE THE SELECTION EITHER OF THE ADDITION
- OR THE SUBTRACTION MODE.
- 0: ADDITION MODE SELECT
- 1: SUBTRACTION MODE SELECT
- D6 "1/2 OF COLOR DATA" DESIGNATION
- WHEN THE COLOR CONSTANT ADDITION/SUBTRACTION OR THE
- SCREEN ADDITION/SUBTRACTION IS PERFORMED, DESIGNATE
- WHETHER THE RGB RESULT IN THE ADDITION/SUBTRACTION
- AREA SHOULD BE "1/2" OR NOT. HOWEVER, IN THE BACK
- COLOR CONSTANT AREA ON THE SUB SCREEN, IT DOES NOT
- BECOME "1/2"
- 0: DISABLE
- 1: ENABLE
- D5 BACK
- D4 OBJ
- D3 BG4
- D2 BG3
- D1 BG2
- D0 BG1
- COLOR DATA ADDITION/SUBTRACTION ENABLE
- 0: DISABLE
- 1: ENABLE
- ADDRESS : $2132
- NAME : COLDATA
- CONTENTS : FIXED COLOR DATA FOR FIXED COLOR ADDITION/SUBTRACTION
- D7 BLUE
- D6 GREEN
- D5 RED
- BIT FOR SELECTING DESIRED COLOR
- D4-D0 COLOR BRILLIANCE DATA
- SET THE COLOR CONSTANT DATA FOR COLOR CONSTANT
- ADDITION/SUBTRACTION
- * R/G/B BRIGHTNESS SHOULD BE SET BY THE DATA OF EACH 5-BIT.
- [EXAMPLE] RED : C0H, 3FH (B=00H, G=00H, R=1FH)
- GREEN : A0H, 5FH (B=00H, G=1FH, R=00H)
- BLUE : 60H, 9FH (B=1FH, G=00H, R=00H)
- WHITE : FFH
- BLACK : 00H
- ADDRESS : $2133
- NAME : SETINI
- CONTENTS : SCREEN INITIAL SETTING
- D7 EXTERNAL SYNCHRONIZATION
- IT IS USED FOR SUPER IMPOSE AND ETC. NORMALLY,
- "0" SHOULD BE WRITTEN.
- D6 EXTBG MODE (SCREEN EXPAND)
- ENABLE THE DATA SUPPLIED FROM THE EXTERNAL LSI.
- FOR THE SFX, ENABLE WHEN THE SCREEN WITH PRIORITY
- IS USED ON MODE-7.
- D5-D4 ---
- D3 HORIZONTAL PSEUDO 512 MODE
- 512 IMAGINARY RESOLUTION (HORIZONTAL CAN BE MADE
- BY SHIFTING THE SUBSCREEN HALF DOT TO THE LEFT.)
- 0: DISABLE
- 1: ENABLE
- D2 BG V-DIRECTION DISPLAY
- SWITCH THE DISPLAY LINE OF A FIELD TO 224 LINE OR
- 239 LINE. (IN CASE OF INTERALACE IT WILL BE
- DOUBLED DOT.)
- 0: 224 LINE
- 1: 239 LINE
- D1 OBJ V-DIRECTION DISPLAY
- IN THE INTERLACE MODE, SELECT EITHER OF 1-DOT PER
- LINE OR 1-DOT REPEATED EVERY 2-LINES. IF "1" IS
- WRITTEN, THE OBJ SEEMS REDUCED HALF VERTICALLY IN
- APPEARANCE.
- D0 SCANNING
- INTERLACE/NON-INTERLACE SELECTION (IT RELATES TO
- <2105H>.
- 0: NON INTERLACE
- 1: INTERLACE
- ADDRESS : $2134/$2135/$2136
- NAME : *MPYL/*MPYM/*MPYH
- CONTENTS : MULTIPLICATION RESULT
- D7-D0 MPY (LOW) 2134H
- D7-D0 MPY (MID) 2135H
- D7-D0 MPY (HIGH) 2136H
- THIS IS A MULTIPLICATION RESULT (COMPLEMENT OF 2) CAN BE READ
- BY SETTING 16-BIT TO REGISTER <211BH> AND SETTING 8 BIT TO
- REGISTER <211CH>
- ADDRESS : $2137
- NAME : *SLHV
- CONTENTS : SOFTWARE LATCH FOR H/V COUNTER
- D7-D0 SOFT LATCH FOR H/V COUNTER
- THIS IS A REGISTER, WHICH GENERATE THE PULSE FOR LATCHING THE H/V
- COUNTER VALUE.
- THE H/V COUNTER VALUE AT THE POINT WHEN REGISTER <2137H> IS READ
- CAN BE LATCHED. THE DATA WHICH WAS READ IS MEANINGLESS DATA.
- THE H/V COUNTER VALUE LATCHED CAN BE REFFERED BY REGISTERS
- <213CH> & <213DH>.
- ADDRESS : $2138
- NAME : OAMDATAREAD (name differs from SNES manual)
- CONTENTS : READ DATA FROM OAM
- D7-D0 OAM DATA (LOW,HIGH)
- THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF
- THE OAM.
- WHEN THE ADDRESS IS SET TO REGISTER <2102H><2103H> AND REGISTER
- <2138H> IS ALSO ACCESSED THE DATA CAN BE READ IN THE ORDER OF
- LOW 8-BIT/HIGH 8-BIT.
- AFTERWARD, THE ADDRESS WILL BE INCREASED AUTOMATICALLY, AND THE
- DATA OF THE NEXT ADDRESS CAN BE READ.
- NOTE: THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED
- ~~~~~ BLANK PERIOD.
- ADDRESS : $2139/$213A
- NAME : VMDATALREAD/VMDATAHREAD (names differ from SNES manual)
- CONTENTS : READ DATA FROM VRAM
- D7-D0 VRAM DATA (LOW) 2139H
- D7-D0 VRAM DATA (HIGH) 213AH
- THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF
- THE VRAM.
- THE INITIAL ADDRESS SHOULD BE SET BY REGISTERS <2116H> AND
- <2117H>. THE DATA CAN BE READ BY THE ADDRESS WHICH HAS BEEN SET
- INITIALLY.
- WHEN READING THE DATA CONTINOUSLY, THE FIRST DATA FOR THE ADDRESS
- INCREMENT SHOULD BE READ AS A DUMMY DATA AFTER THE ADDRESS HAS
- BEEN SET.
- QUANTITY TO BE INCREASED WILL BE DETERMINED BY "SC INCREMENT" OF
- REGISTER <2115H> AND THE SETTING VALUE OF THE "FULL GRAPHIC".
- NOTE: THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED
- ~~~~~ BLANK PERIOD.
- ADDRESS : $213B
- NAME : CGDATAREAD (name differs from SNES manual)
- CONTENTS : READ DATA FROM CG-RAM
- D7-D0 CG DATA (LOW,HIGH)
- THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF
- THE CG-RAM.
- THE INITIAL ADDRESS SHOULD BE SET BY REGISTER <2121H>. THE LOWER
- 8-BIT IS READ FIRST, AND THE THE UPPER 7-BIT WILL BE READ BY
- ACCESSING THIS REGISTER. THE CURRENT ADDRESS WILL BE INCREASED
- TO THE NEXT ADDRESS AT THE SAME TIME THE UPPER 7-BIT IS READ.
- NOTE: THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED
- ~~~~~ BLANK PERIOD.
- ADDRESS : $213C/$213D
- NAME : *OPHCT/*OPVCT
- CONTENTS : H/V COUNTER DATA BY EXTERNAL OR SOFTWARE LATCH
- D7-D0 OUTPUT DATA OF H-COUNTER [9-BIT] 213CH
- D7-D0 OUTPUT DATA OF V-COUNTER [9-BIT] 213DH
- THE H/V COUNTER IS LATCHED BY READING REGISTER <2137H>, AND ITS
- H/V COUNTER VALUE CAN BE READ BY THIS REGISTER.
- THE H/V COUNTER IS ALSO LATCHED BY THE EXTERNAL LATCH, AND ITS
- VALUE CAN BE READ BY THIS REGISTER.
- IF REGISTER <213CH> OR <213DH> IS READ AFTER REGISTER <213FH> HAS
- BEEN READ, THE LOWER 8-BIT DATA WILL BE READ FIRST, AND THEN THE
- UPPER 1-BIT WILL BE READ BY READING THE REGISTER.
- ADDRESS : $213E
- NAME : *STAT77
- CONTENTS : PPU STATUS FLAG & VERSION NUMBER
- D7 TIME OVER \
- D6 RANGE OVER /
- OBJ DISPLAY STATUS (ON A HORIZONTAL LINE)
- RANGE: WHEN QUANTITY OF THE OBJ (REGARDLESS OF
- THE SIZE) BECOMES 33 PCS OR MORE, "1"
- WILL BE SET.
- TIME: WHEN QUANTITY OF THE OBJ WHICH IS CONVERTED
- TO "8 x 8-SIZE" IS 35 PCS OR MORE, "1"
- WILL BE SET.
- D5 MASTER/SLAVE MODE SELECT. LSI MODE (NORMALLY "0" IS SET.)
- D4 ---
- D3-D0 5C77 VERSION NUMBER
- NOTE: THE FLAG WILL BE RESET AT THE END OF THE V-BLANK PERIOD.
- ~~~~~
- ADDRESS : $213F
- NAME : *STAT78
- CONTENTS : PPU STATUS FLAG & VERSION NUMBER
- D7 FIELD
- THIS IS A STATUS FLAG, WHICH INDICATED WHETHER 1ST
- FIELD IS SCANNED OR 2ND FIELD IS SCANNED IN INTER-
- LACE MODE. (THE DEFINITION IS DIFFERENT FROM THE
- FIELD OF NTSC.)
- 0: 1ST FIELD
- 1: 2ND FIELD
- D6 EXTERNAL LATCH FLAG
- WHEN THE EXTERNAL SIGNAL (LIGHT PEN, ETC.) IS
- APPLIED, IT ENABLES TO LATCH THE H/V COUNTER VALUE.
- D5 ---
- D4 NTSC/PAL MODE
- 0: NTSC
- 1: PAL
- D3-D0 5C78 VERSION NUMBER
- NOTE: WHEN THIS REGISTER IS READ, REGISTERS <213CH><213DH> WILL
- ~~~~~ BE INITIALIZED INDIVIDUALLY IN THE ORDER OF LOW & HIGH.
- ADDRESS : $2140/$2141/$2142/$2143
- NAME : APUI00/APUI01/APUI02/APUI03
- CONTENTS : COMMUNICATION PORT WITH APU
- D7-D0 APU I/O PORT
- THIS PORT PROVIDES MORE REGISTERS FOR THE PURPOSE OF IN/OUT,
- WHICH ARE 8 REGISTERS IN TOTAL IN THE APU. THEREFORE, THE
- DIFFERENT REGISTER WILL BE ACCESSED, WHETHER READING OR
- WRITING FOR THE SAME ADDRESS.
- SEE "APU MANUAL" FOR THE DETAILS OF THE COMMUNICATION METHOD.
- ADDRESS : $2180
- NAME : WMDATA
- CONTENTS : DATA TO CONSECUTIVLEY READ FROM AND WRITE TO WRAM
- D7-D0 WORK RAM DATA
- DATA TO CONSECUTIVLEY READ FROM AND WRITE TO WRAM
- DATA IS READ AND WRITTEN AT ADDRESS SET BY REGISTER <2181H>-<2183H>,
- AND ADDRESS AUTOMATICALLY INCREASES EACH TIME DATA IS READ OR WRITTEN.
- ADDRESS : $2181/$2182/$2183
- NAME : WMADDL/WMADDM/WMADDH
- CONTENTS : ADDRESS TO CONSECUTIVELY READ AND WRITE WRAM
- D7-D0 WRAM DATA (LOW) 2181H
- D7-D0 WRAM DATA (MID) 2182H
- D0 WRAM DATA (HIGH) 2183H
- ADDRESS TO BE SET BEFORE WRAM IS CONSECUTIVLEY READ OR WRITTEN.
- A0 TROUGH A16 AT REGISTER <2181H>-<2183H> IS LOWER 17 BIT ADDRESS
- TO SHOW ADDRESS $7E0000-$7FFFFF IN MEMORY.
- ADDRESS : $4200
- NAME : NMITIMEN
- CONTENTS : ENABLE FLAG FOR V-BLANK, TIMER INTERRUPT & JOY CONTROLLER READ
- D7 NMI ENABLE
- ENABLE NMI AT THE POINT WHEN V-BLANK BEGINS
- (WHEN POWER IS TURNED ON OR THE RESET SIGNAL IS
- APPLIED, IT WILL BE "0".)
- 0: NMI DISABLED
- 1: NMI ENABLED
- D6 ---
- D5-D4 TIMER ENABLE (V-EN/H-EN)
- D3-D1 ---
- D0 JOY-C ENABLE
- 0: DISABLE AUTOMATIC READING OF THE JOY-CONTROLLER.
- 1: ENABLE AUTOMATIC READING OF THE JOY-CONTROLLER.
- V-EN H-EN | FUNCTION
- --------------------------------------------------------
- 0 0 | DISABLE BOTH H & V
- 0 1 | ENABLE H ONLY, IRQ APPLIED BY H-COUNT TIMER VALUE DESIGNATED
- 1 0 | ENABLE V ONLY, IRQ APPLIED BY V-COUNT TIMER VALUE DESIGNATED
- 1 1 | ENABLE BOTH V & H, IRQ APPLIED BY BOTH H & V COUNT TIMER VAL
- | DESIGNATED.
- * READING THE DATA CAN BE STARTED AT THE BEGINNING OF V-BLANK
- PERIOD, BUT IT TAKES ABOUT FOR 3 OR 4 SCANNING PERIOD UNTIL
- COMPLETION OF READING.
- ADDRESS : $4201
- NAME : WRIO
- CONTENTS : PROGRAMMABLE I/O PORT (OUT-PORT)
- D7-D0 I/O PORT
- THIS IS A PROGRAMMABLE I/O PORT (OUT-PORT). THE WRITTEN DATA
- WILL BE OUTPUT DIRECTLY FROM THE OUT-PORT.
- WHEN THIS IS USED AS A INPORT. "1" SHOULD BE WRITTEN TO THE
- PARTICULAR BIT WHICH WILL BE USED AS IN PORT. THE INPUT CAN
- BE READ BY REGISTER <4213H>.
- ADDRESS : $4202/$4203
- NAME : WRMPYA/WRMPYB
- CONTENTS : MULTIPLIER & MULTIPLICAND BY MULTIPLICATION
- D7-D0 MULTIPLICAND-A 4202H
- D7-D0 MULTIPLIER-B 4203H
- THIS IS A REGISTER, WHICH CAN SET A MULITPLICAND (A) AND A
- MULTIPLIER (B) FOR ABSOLUTE MULTIPLICATION OF
- "A (8-BIT) * B (8-BIT)=C (16-BIT)"
- A PRODUCT (C) CAN BE READ BY REGISTERS <4216H><4217H>
- SET IN THE ORDER OF (A) AND (B). THE OPERATION WILL START AS
- SOON AS (B) HAS BEEN SET, AND IT WILL BE COMPLETED RIGHT AFTER
- 8-MACHINE CYCLE PERIOD.
- ONCE THE DATA OF THE A-REGISTER IS SET, IT WILL NOT BE DESTROYED
- UNTIL NEW DATA IS SET.
- ADDRESS : $4204/$4205/$4206
- NAME : WRDIVL/WRDIVH/WRDIVB
- CONTENTS : DIVISOR & DIVIDEND DIVIDE
- D7-D0 MULTIPLIER-C (LOW) 4204H
- D7-D0 MULTIPLIER-C (HIGH) 4205H
- D7-D0 DIVISOR-B 4206H
- THIS IS A REGISTER, WHICH CAN SET A DIVIDEND (C) AND A DIVISOR (B)
- FOR ABSOLUTE DIVIDE OF
- "C (16-BIT) / B (8-BIT)=A (16-BIT)"
- THE DIVISOR (A) CAN BE READ BY REGISTERS <4214H><4215H>, AND THE
- REMAINDER CAN ALSO BE READ BY REGISTERS <4216H><4217H>.
- SET IN THE ORDER OF (C) AND (B). THE OPERATION WILL START AS SOON
- AS (B) HAS BEEN SET, AND IT WILL BE COMPLETED RIGHT AFTER 16-
- MACHINE CYCLE PERIOD.
- ONCE THE DATA OF THE A-REGISTER IS SET, IT WILL NOT BE DESTROYED
- UNTIL NEW DATA IS SET.
- ADDRESS : $4207/$4208
- NAME : HTIMEL/HTIMEH
- CONTENTS : H-COUNT TIMER SETTINGS
- D7-D0 H COUNT TIMER (H7-H0) 4207H
- D7-D1 ---
- D0 H COUNT TIMER (H8) 4208H
- THIS IS A REGISTER, WHICH CAN SET THE H-COUNT TIMER VALUE.
- THE SETTING VALUE SHOULD BE FROM 0 THROUGH 339, WHICH IS COUNTED
- FROM THE FAR LEFT ON THE SCREEN.
- HWEN THE COORDINATE COUNTER BECOMES THE COUNT VALUE SET, THE IRQ
- WILL BE APPLIED. AND AT THE SAME TIME. "1" WILL BE WRITTEN TO
- "TIMER IRQ" OF REGISTER <4211H>. (READ RESET)
- ENABLE/DISABLE OF THE INTERRUPT WILL BE DETERMINED BY SETTING
- REGISTER <4200H>
- * THIS CONTINOUS COUNTER IS RESET EVERY SCANNING LINE, THEREFORE
- ONCE THE COUNT VALUE IS SET, IT IS POSSIBLE TO APPLY THE IRQ
- EVERY TIME THE SCANNING LINE COMES TO THE SAME HORIZONTAL
- POSITION ON THE SCREEN.
- ADDRESS : $4209/$420AH
- NAME : VTIMEL/VTIMEH
- CONTENTS : V-COUNT TIMER SETTINGS
- D7-D0 V COUNT TIMER (V7-V0) 4209H
- D7-D1 ---
- D0 V COUNT TIMER (V8) 420AH
- THIS IS A REGISTER, WHICH CAN SET THE V-COUNT TIMER VALUE.
- THE SETTING VALUE SHOULD BE FROM 0 THROUGH 261(262), WHICH IS
- COUNTED FROM THE FAR TOP OF THE SCREEN. [THE LINE NUMBER DESCRIBED
- IS DIFFERENT FROM THE ACTUAL LINE NUMBER ON THE SCREEN.]
- HWEN THE COORDINATE COUNTER BECOMES THE COUNT VALUE SET, THE IRQ
- WILL BE APPLIED. AND AT THE SAME TIME. "1" WILL BE WRITTEN TO
- "TIMER IRQ" OF REGISTER <4211H>. (READ RESET)
- ENABLE/DISABLE OF THE INTERRUPT WILL BE DETERMINED BY SETTING
- REGISTER <4200H>
- * THIS IS A CONTINOUS COUNTER SAME AS H-COUNTER, AND IT WILL BE
- RESET EVERY TIME 262(263) LINE ARE SCANNED. ONCE THE COUNT
- VALUE IS SET, IT IS POSSIBLE TO APPLY THE IRQ EVERY TIME THE
- SCANNING LINE COMES TO THE SAME VERTICAL LINE ON THE SCREEN.
- ADDRESS : $420B
- NAME : MDMAEN
- CONTENTS : CHANNEL DESIGNATION FOR GENERAL PURPOSE DMA & TRIGGER (START)
- D7-D0 GENERAL PURPOSE CH7-CH0 ENABLE
- THE GENERAL PURPOSE DMA CONSISTS OF 8-CHANNELS IN TOTAL.
- THIS REGISTER IS USED TO DESIGNATE THE CHANNEL OUT OF 8-CHANNELS.
- THE CHANNEL WHICH SHOULD BE USED CAN BE DESIGNATED BY WRITING "1"
- TO THE BIT OF THIS CHANNEL. AS SOON AS "1" IS WRITTEN TO THE
- BIT (AFTER A FEW CYCLES PASSED), THE GENERAL PURPOSE DMA TRANSFER
- WILL BE STARTED.
- WHEN THE GENERAL PURPOSE DMA OF THE DESIGNATED CHANNEL IS
- COMPLETED, THE FLAG WILL BE CLEARED.
- NOTE: BECAUSE THE DATA AREA (REGISTER <4300>-) OF EACH CHANNEL
- ~~~~~ IS HELD IN COMMON WITH THE DATA OF EACH H-DMA CHANNEL, THE
- CHANNEL DESIGNATED BY THE H-DMA CHANNEL DESIGNATION
- REGISTER <420CH> CAN NOT BE USED.
- (IT IS PROHIBITED TO WRITE "1" TO THE BIT OF THE CHANNEL)
- THEREFORE, 8 CHANNELS (CH0-CH7) SHOULD BE ASSIGNED BY THE
- H-DMA AND THE GENERAL PURPOSE DMA)
- NOTE: IF THE H-BLANK COME DURING THE OPERATION OF THE GENERAL
- ~~~~~ PURPOSE DMA AND THE H-DMA IS STARTED, THE GENERAL PURPOSE
- DMA WILL BE DISCONTINUED IN THE MIDDLE, AND RE-STARTED RIGHT
- AFTER THE H-DMA IS COMPLETE.
- NOTE: IF 2 OR MORE CHANNELS ARE DESIGNATED, THE DMA TRANSFER WILL
- ~~~~~ BE PERFORMED CONTINOUSLY ACCORDING TO THE PRIORITY DESCRIBED
- IN APPENDIX-1.
- AND ALSO, THE CPU STOPS OPERATION UNTIL ALL THE GENERAL
- PURPOSE DMA ARE COMPLETED.
- ADDRESS : $420C
- NAME : HDMAEN
- CONTENTS : CHANNEL DESIGNATION FOR H-DMA
- D7-D0 H-DMA CH7-DH0 ENABLE
- THE H-DMA CONSISTS OF 8-CHANNELS IN TOTAL
- THIS REGISTER IS USED TO DESIGNATE THE CHANNEL OUT OF 8-CHANNELS
- THE CHANNEL WHICH SHOULD BE USED CAN BE DESIGNATED BY WRITING
- "1" TO THE BIT OF THIS CHANNEL. AS SOON AS H-BLANK BEGINS (AFTER
- A FEW CYCLES PASSED), THE H-DMA TRANSFER WILL BE STARTED.
- NOTE: ONCE THIS FLAG IS SET, IT WILL NOT BE DESTROYED (CLEARED)
- ~~~~~ UNTIL NEW DATA IS SET. THEREFORE, THE INITIAL SETTINGS ARE
- DONE AUTOMATICALLY EVERY FIELD, AND THE SAME TRANSFER
- PATTERN WILL BE REPEATED.
- AND ALSO, THE FLAG IS SET OUT OF V-BLANK PERIOD, THE DMA-
- TRANSFER WILL BE PERFORMED PROPERLY FROM NEXT SCREEN FRAME.
- ADDRESS : $420D
- NAME : MEMSEL
- CONTENTS : ACCESS CYCLE DESIGNATION IN MEMORY (2) AREA
- D7-D1 ---
- D0 ACCESS CYCLE DESIGNATION IN MEMORY (2) AREA
- 0: 2.68MHz ACCESS CYCLE
- 1: 3.58MHz ACCESS CYCLE (ONLY WHEN HIGH SPEED
- MEMORY IS USED.)
- MEMORY (2) SHOWS THE ADDRESS (8000H-FFFFH) OF THE BANK (80H-BFH)
- AND ALL THE ADDRESS OF THE BANK (C0H-FFH).
- WHEN POWER IS TURNED ON OR THE RESET SIGNAL IS APPLIED IT BECOMES
- "0".
- HIGH SPEED MEMORY REQUIERS 120NS OR FASTER EPROMS.
- ADDRESS : $4210
- NAME : *RDNMI
- CONTENTS : NMI FLAG BY V-BLANK & VERSION NUMBER
- D7 NMI FLAG BY V-BLANK
- WHEN "1" IS WRITTEN TO "NMI ENABLE" OF REGISTER
- <4200H>, THIS FLAG WILL SHOW NMI STATUS.
- 0: NMI STATUS IS "DISABLE"
- 1: NMI STATUS IS "ENABLE"
- D6-D4 ---
- D3-D0 5A22 VERSION NUMBER
- * "1" IS SET TO THIS FLAG AT BEGINNING OF V-BLANK, AND "0" IS
- SET AT END OF V-BLANK. ALSO, IT CAN BE SET BY READING THIS
- REGISTER.
- NOTE: IT IS NECESSARY TO RESET BY READING THIS FLAG DURING
- ~~~~~ NMI PROCESSING. (SEE APPENDIX-3)
- ADDRESS : $4211
- NAME : *TIMEUP
- CONTENTS : IRQ FLAG BY H/V COUNT TIMER
- D7 IRQ FLAG BY H/V COUNT TIMER
- [IN CASE THE TIME ENABLE IS SET BY "TIMER ENABLE"
- OF REGISTER <4200H>] AS SOON AS H/V COUNTER TIMER
- BECOMES THE COUNT VALUE SET, IRQ WILL BE APPLIED
- AND "1" WILL BE SET TO THIS FLAG.
- THIS FLAG IS "READ-RESET".
- D6-D0 ---
- * EVEN IF V-EN="0" AND H-EN="0" ARE SET BY "TIMER ENABLE" OF
- REGISTER <4200H>, THIS FLAG WILL BE RESET.
- 0: EITHER H/V COUNTER IS IN ACTIVE OR DISABLE.
- 1: H/V COUNT TIMER IS TIME UP.
- ADDRESS : $4212
- NAME : HVBJOY
- CONTENTS : H/V BLANK FLAG & JOY CONTROLLER ENABLE FLAG
- D7 V-BLANK PERIOD FLAG
- 0: OUT OF V-BLANK PERIOD
- 1: IN V-BLANK PERIOD
- D6 H-BLANK PERIOD FLAG
- 0: OUT OF H-BLANK PERIOD
- 1: IN H-BLANK PERIOD
- D5-D1 ---
- D0 JOY CONTROLLER ENABLE FLAG
- THIS FLAG SHOWS THE TIMING TO READ THE DATA OF THE
- JOY CONTROLLER. (HOWEVER, IT IS LIMITED TO THE CASE
- WHICH THE "JOY-C ENABLE" OF REGISTER <4200H> IS SET
- TO "1".
- ADDRESS : $4213
- NAME : *RDIO
- CONTENTS : PROGRAMMABLE I/O PORT (IN-PORT)
- D7-D0 I/O PORT
- THIS IS A PROGRAMMABLE I/O PORT (IN PORT). THE DATA WHICH IS SET
- TO THE IN-PORT SHOULD BE READ DIRECTLY.
- THE BIT WHICH "1" IS WRITTEN BY REGISTER <4201H> IS USED AS THE
- IN PORT.
- ADDRESS : $4114/$4115
- NAME : *RDDIVL/*RDDIVH
- CONTENTS : QUOTIENT OF DIVIDE RESULT
- D7-D0 QUOTENT-A (LOW) 4114H
- D7-D0 QUOTENT-A (HIGH) 4115H
- THIS IS A QUOTENT (A), WHICH IS A RESULT FOR ABSOLUTE DIVIDE OF
- "C (16-BIT) / B (8-BIT) = A (16-BIT)".
- DIVIDEND (C) AND DIVISOR (B) ARE SET BY REGISTERS <4204H>-<4206H>.
- ADDRESS : $4216/$4217
- NAME : *RDMPYL/*RDMPYH
- CONTENTS : PRODUCT OF MULTIPLICATION RESULT OR REMAINDER OF DIVIDE RESULT
- D7-D0 PRODUCT-C [MUL] / REMAINDER [DIV] (LOW) 4216H
- D7-D0 PRODUCT-C [MUL] / REMAINDER [DIV] (HIGH) 4217H
- (1) IN CASE OF MULTIPLICATION
- THIS IS A PRODUCT (C) WHICH IS A RESULT FOR ABSOLUTE
- MULTIPLICATION OF "A (8-BIT) * B (8-BIT) = C (16-BIT)".
- A MULTIPLICAND (A) AND A MULTIPLIER (B) ARE SET BY REGISTERS
- <4202H> & <4203H>.
- (2) IN CASE OF DIVIDE
- THIS IS THE REMAINDER, WHICH IS A RESULT FOR THE ABSOLUTE
- DIVIDE OF "C (16-BIT) / B (8-BIT) = A (16-BIT)".
- A DIVIDEND (C) AND DIVISOR (B) ARE SET BY THE REGISTERS
- <4204H><4205H> & <4206H>.
- ADDRESS : $4218/$4219/$421A/$421B/$421C/$421D/$421E/$421F
- NAME : JOY1L/JOY1H/JOY2L/JOY2H/JOY3L/JOY3H/JOY4L/JOY4H
- CONTENTS : DATA FOR JOY CONTROLLER I, II, III & IV
- D7 X BUTTON LOW
- D6 Y BUTTON
- D5 TL BUTTON
- D4 TR BUTTON
- D3-D0 ----
- D7 A BUTTON HIGH
- D6 B BUTTON
- D5 SELECT BUTTON
- D4 START BUTTON
- D3 UP
- D2 DOWN
- D1 LEFT
- D0 RIGHT
- REGISTERS <4016H><4017H> CAN BE USED THE SAME AS THE FAMILY
- COMPUTER.
- 4016H-RD
- D0 : DATA FOR CONTROLLER I
- D1 : DATA FOR CONTROLLER III
- 4016H-WR
- OUT0,OUT1,OUT2
- 4017H-RD
- D0 : DATA FOR CONTROLLER II
- D1 : DATA FOR CONTROLLER IV
- NOTE: WHETHER THE STANDARD JOY CONTROLLERS ARE CONNECTED TO THE
- ~~~~~ SFX OR NOT CAN BE REFFERED BY READING 17TH BIT OF <4016H>
- AND <4017H> (SEE PAGE 22).
- 0: CONNECTED
- 1: NOT CONNECTED
- ADDRESS : $43X0 (X: CHANNEL NUMBER 0-7)
- NAME : DMAPX
- CONTENTS : PARAMETER FOR DMA TRANSFER
- D7 TRANSFER ORIGINATION DESIGNATION (SEE APPENDIX-1)
- TRANSFER DIRECTION A-BUS -> B-BUS
- B-BUS -> A-BUS DESIGNATION
- 0: A-BUS -> B-BUS (CPU MEMORY -> PPU)
- 1: B-BUS -> A-BUS (PPU -> CPU MEMORY)
- D6 TYPE DESIGNATION (H-DMA ONLY)
- ADDRESSING MODE DESIGNATION WHEN ACCESSING THE
- DATA (SEE APPENDIX-2).
- 0: ABSOLUTE ADDRESSING
- 1: INDIRECT ADDRESSING
- D5 ---
- D4-D3 FIXED ADDRESS FOR A-BUS & AUTOMATIC INC./DEC. SELECT.
- D3 0: AUTOMATIC ADDRESS INCREMENT/DECREMENT
- 1: FIXED ADDRESS <TO BE USED WHEN CLEARING
- VRAM ETC.>
- D4 0: AUTOMATIC INCREMENT
- 1: AUTOMATIC DECREMENT (IN CASE "0" IS
- WRITTEN TO D3)
- D2-D0 DMA TRANSFER WORD SELECT
- GENERAL PURPOSE DMA: B-ADDRESS CHANGE METHOD
- D2 D1 D0 | ADDRESS TO BE WRITTEN
- ---------------------------------
- 0 0 0 | 1-ADDRESS
- 0 0 1 | 2-ADDRESS (VRAM ETC.) L,H
- 0 1 0 | 1-ADDRESS
- 0 1 1 | 2-ADDRESS (WRITE TWICE) L,L,H,H
- 1 0 0 | 4-ADDRESS L,H,L,H
- H-DMA: THE NUMBER OF BYTE TO BE TRANSFERED PER LINE
- AND WRITE METHOD DESIGNATION
- D2 D1 D0 | ADDRESS TO BE WRITTEN
- ---------------------------------
- 0 0 0 | 1-ADDRESS (1)
- 0 0 1 | 2-ADDRESS (VRAM ETC.) L,H (2)
- 0 1 0 | WRITE TWICE L,L (1)
- 0 1 1 | 2-ADDRESS/WRITE TWICE L,L,H,H(2)
- 1 0 0 | 4-ADDRESS L,H,L,H(4)
- ADDRESS : $43X1 (X: CHANNEL NUMBER 0-7)
- NAME : BBADX
- CONTENTS : B-BUS ADDRESS FOR DMA
- D7-D0 B-ADDRESS
- THIS IS A REGISTER, WHICH CAN SET THE ADDRESS OF B-BUS.
- WHETHER THIS IS THE ADDRESS OF THE "TRANSFER DESTINATION" OR
- THE ADDRESS OF THE "TRANSFER ORIGINATION" CAN BE DETERMINED BY
- D7 (TRANSFER ORIGINATION) OF REGISTER <4300H>.
- * WHEN THE H-DMA IS PERFORMED, IT WILL BE ADDRESS OF "TRANSFER
- DESTINATION".
- ADDRESS : $43X2/$43X3/$43X4 (X: CHANNEL NUMBER 0-7)
- NAME : A1TXL/A1TXH/A1BX
- CONTENTS : TABLE ADDRESS OF A-BUS FOR DMA <A1 TABLE ADDRESS>
- D7-D0 A1 TABLE ADDRESS (LOW) 43X2H
- D7-D0 A1 TABLE ADDRESS (HIGH) 43X3H
- D7-D0 A1 TABLE BANK 43X4H
- THIS IS A REGISTER, WHICH CAN SET THE ADDRESS OF A-BUS
- WHETHER THIS IS THE ADDRESS OF THE "TRANSFER DESTINATION" OR
- THE ADDRESS OF THE "TRANSFER ORIGINATION" CAN BE DETERMINED BY
- D7 (TRANSFER ORIGINATION) OF REGISTER <4300H>.
- "0" SHOULD BE WRITTEN TO D7 EXCEPT A SPECIAL CASE.
- IN THE H-DMA MODE, THE ADDRESS OF THE TRANSFER ORIGINATION IS
- DESIGNATED BY THIS ADDRESS, THE DATA (APPENDIX-2) MUST BE
- SET BY THE ABSOLUTE ADDRESSING MODE OR THE INDIRECT ADDRESSING
- MODE.
- THIS ADDRESS BECOMES THE BASIC ADDRESS ON THE A-BUS DURING DMA
- TRANSFER PERIOD, AND THE ADDRESS WILL BE INCREASED OR DECREASED
- BASED ON THIS ADDRESS. (WHEN THE GENERAL PURPOSE DMA IS PERFORMED
- IT WILL BE DECREASED.)
- ADDRESS : $43X5/$43X6/$43X7 (X: CHANNEL NUMBER 0-7)
- NAME : DASXL/DASXH/DASBX
- CONTENTS : DATA ADDRESS STORE BY H-DMA & NUMBER OF BYTE TO BE TRANSFERED
- SETTINGS BY GENERAL PURPOSE DMA
- D7-D0 DATA ADDRESS (LOW) H-DMA 43X5H
- NUMBER OF BYTES TO BE TRANSFERED (LOW) GP-DMA
- D7-D0 DATA ADDRESS (HIGH) H-DMA 43X6H
- NUMBER OF BYTES TO BE TRANSFERED (HIGH) GP-DMA
- D7-D0 DATA BANK 43X7H
- IN CASE OF H-DMA
- THIS IS A REGISTER WHICH THE INDIRECT ADDRESS WILL BE
- STORED AUTOMATICALLY IN THE INDIRECT ADDRESSING MODE.
- THE INDIRECT ADDRESS MEANS THE DATA ADDRESS DESCRIBED
- ON APPENDIX-2. IT IS NOT NECESSARY TO READ OR WRITE
- DIRECTLY BY THE CPU EXCEPT IN SPECIAL CASES.
- IN CASE OF GENERAL PURPOSE DMA
- THIS IS THE REGISTER, WHICH CAN SET THE NUMBER OF BYTE
- TO TRANSFER OR TO BE TRANSFERED. HOWEVER, THE NUMBER OF
- BYTE "0000H" MEANS "10000H".
- ADDRESS : $43X8/$43X9 (X: CHANNEL NUMBER 0-7)
- NAME : A2AXL/A2AXH
- CONTENTS : TABLE ADDRESS OF A-BUS BY DMA < A2 TABLE ADDRESS
- D7-D0 A2 TABLE ADDRESS (LOW) 43X8H
- D7-D0 A2 TABLE ADDRESS (HIGH) 43X9H
- THESE ARE THE ADDRESSES, WHICH ARE USED TO ACCESS THE CPU & RAM,
- AND IT WILL BE INCREASED AUTOMATICALLY. (SEE APPENDIX-2)
- THE DATA OF THESE REGISTERS ARE USED AS THE BASIC ADDRESS WHICH
- IS THE ADDRESSS SET BY THE "A1 TABLE ADDRESS". AFTERWARDS,
- BECAUSE IT WILL BE INCREASED OR DECREASED AUTOMATICALLY, IT IS
- NECESSARY TO SET THE ADDRESS INTO THIS REGISTER BY THE CPU
- DIRECTLY.
- FOLLOWING APPLY TO H-DMA ONLY:
- HOWEVER, IF THE DATA WHICH IS TRANSFERED NEED TO BE CHANGED
- BY FORCE, IT CAN BE DONE BY SETTING THE CPU MEMORY ADDRESS
- TO THIS REGISTER. AND ALSO, THE ADDRESS OF THE CPU WHICH IS
- ACCESSED CURRENTLY WILL BE CHANGED BY READING THIS REGISTER.
- ADDRESS : $43XA (X: CHANNEL NUMBER 0-7)
- NAME : NTRLX
- CONTENTS : THE NUMBER OF LINES TO BE TRANSFERED BY H-DMA›0;31;40m
- D7 CONTINUE
- D6-D0 NUMBER OF LINES TO BE TRANSFERED
- THIS IS A REGISTER WHICH SHOWS NUMBER OF LINES FOR H-DMA TRANSFER
- (SEE APPENDIX-2)
- THE NUMBER OF LINES WRITTEN TO THE CPU MEMORY WILL BE THE BASIC
- NUMBER OF LINE, IT IS NOT NECESSARY TO SET THE ADDRESS INTO
- THIS REGISTER DIRECTLY.
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