SNESMAP2.TXT 41 KB

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  1. ADDRESS : $2100
  2. NAME : INIDISP
  3. CONTENTS : INITIAL SETTINGS FOR SCREEN
  4. D7 BLANKING:
  5. FORCED BLANKING, 0:NON-BLANKING,1:BLANKING.
  6. D6-D4 ---
  7. D3-D0 FADE IN/OUT:
  8. 0000-DARKEST,1111-BRIGHTEST.
  9. ADDRESS : $2101
  10. NAME : OBSEL
  11. CONTENTS : OBJECT SIZE & OBJECT DATA AREA DESIGNATION
  12. D7-D5 SIZE SELECT:
  13. D7 D6 D5 0 1 (SIZE LARGE/SMALL)
  14. 0 0 0 8 16
  15. 0 0 1 8 32
  16. 0 1 0 8 64
  17. 0 1 1 16 32
  18. 1 0 0 16 64
  19. 1 0 1 32 64 (DOTS.)
  20. D4-D3 NAME SELECT
  21. THE UPPER 4K-WORD OUT OF THE AREA (8K-WORD)
  22. DESIGNATED BY "OBJECT BASE ADDRESS" IS ASSIGNED
  23. AS THE BASE AREA, AND THE AREA OF THE LOWER 4K-
  24. WORD COMBINED WITH ITS BASE AREA CAN BE
  25. SELECTED. (SEE APPENDIX 1 & 2)
  26. D2-D0 NAME BASE SELECT (UPPER-3 BIT)
  27. DESIGNATE THE SEGMENT (8K-WORD) ADDRESS WHICH
  28. THE OBJ DATA IS STORED IN VRAM. (APPENDIX 1 & 2)
  29. ADDRESS : $2102/$2103
  30. NAME : OAMADDL/OAMADDH
  31. CONTENTS : ADDRESS FOR ACCESSING OAM
  32. D7-D0 OAM ADDRESS (A7-A0) 2102H
  33. D7 OAM PRIORITY ROTATION 2103H
  34. D6-D1 ---
  35. D0 OAM ADDRESS MSB (A8)
  36. THIS IS THE INITIAL ADDRESS TO BE SET IN ADVANCE WHEN READING
  37. READING FROM THE OAM OR WRITING TO THE OAM.
  38. BY WRITING "1" TO D7 OF REGISTER <2103H> AND SETTING THE OAM-
  39. ADDRESS THE OBJ FOR THE ADDRESS SET HAS HIGHEST PRIORITY.
  40. THE ADDRESS WHICH HAS BEEN SET JUST BEFORE EVERY FIELD
  41. (BEGINNING OF V-BLANK) WILL BE SET AGAIN TO REGISTERS <2102H>
  42. <2103H> AUTOMATICALLY. BUT, THE ADDRESS CAN NOT BE SET
  43. AUTOMATICALLY DURING FORCED BLANK PERIOD.
  44. ADDRESS : $2104
  45. NAME : OAMDATA
  46. CONTENTS : DATA FOR OAM WRITE
  47. D7-D0 OAM DATA (LOW,HIGH)
  48. THIS IS THE OAM DATA TO BE WRITTING AT ANY ADDRESS OF THE OAM.
  49. (SEE APPENDIX-3)
  50. AFTER REGISTER <2102H> OR <2103H> IS ACCESSED, THE DATA MUST
  51. BE WRITTEN IN THE ORDER OF LOWER 8-BIT & UPPER 8-BIT OF REGISTER
  52. <2104H>.
  53. THE DATA CAN BE WRITTEN ONLY DURING V-BLANK OR FORCED BLANK
  54. PERIOD.
  55. ADDRESS : $2105
  56. NAME : BGMODE
  57. CONTENTS : BG MODE & CHARACTER SIZE SETTINGS
  58. D7-D4 BG SIZE DESIGNATION (BG4-BG1)
  59. 0: 8 x 8 DOT/CHARACTER
  60. 1: 16 x 16 DOT/CHARACTER
  61. D3 HIGHEST PRIORITY DESIGNATION FOR BG-3 IN MODE 1
  62. 0: OFF (SEE APPENDIX-16)
  63. 1: ON
  64. D2-D0 BG SCREEN MODE SELECT (SEE APPENDIX-5)
  65. ADDRESS : $2106
  66. NAME : MOSAIC
  67. CONTENTS : SIZE & SCREEN DESIGNATION FOR MOSAIC DISPLAY
  68. D7-D4 MOSAIC SIZE (SEE APPENDIX-6)
  69. 1111 - LARGEST, 0000 - SMALLEST.
  70. D3-D0 MOSAIC ENABLE (BG4-B1)
  71. 0: OFF
  72. 1: ON
  73. ADDRESS : $2107/$2108/$2109/$210A
  74. NAME : BG1SC/BG2SC/BG3SC/BG4SC
  75. CONTENTS : ADDRESS FOR STORING SC-DATA OF EACH BG & SC SIZE DESIGNATION
  76. D7-D2 SC BASE ADDRESS
  77. DESIGNATE THE SEGMENT WHICH BG-SC IN THE VRAM
  78. IS STORED. (1K-WORD/SEGMENT)
  79. D1-D0 SC SIZE
  80. DESIGNATE BACKGROUND SCREEN SIZE (APPENDIX-18 & 19)
  81. 0 0 0 0 1 0 0 0 0 1 0 1 1 1 0 1
  82. 0 0 1 1 0 1 2 3
  83. ADDRESS : $210B/$210C
  84. NAME : BG12NBA/BG34NBA
  85. CONTENTS : BG CHARACTER DATA ARE DESIGNATION
  86. D7-D4 BG2 BASE ADDRESS 210BH
  87. D3-D0 BG1 BASE ADDRESS
  88. D7-D4 BG4 BASE ADDRESS 210CH
  89. D3-D0 BG3 BASE ADDRESS
  90. BACKGROUND NAME BASE ADDRESS (UPPER 4-BIT), SEGMENT ADDRESS
  91. IN THE VRAM WHERE BG CHARACTER DATA IS STORED. (4K-WORD/SEGMENT)
  92. ADDRESS : $210D/$210E/$210F/$2110/$2111/$2112/$2113/$2114
  93. NAME : BG1HOFS/BG1VOFS/BG2HOFS/BG2VOFS/BG3HOFS/BG3VOFS/BG4HOFS/BG4VOFS
  94. CONTENTS : H/V SCROLL VALUE DESIGNATION FOR BG
  95. D7-D0 H-OFFSET (LOW,HIGH) HOFS
  96. D7-D0 V-OFFSET (LOW,HIGH) VOFS
  97. 10 BIT MAXIMUM (0-1023) CAN BE DESIGNATED FOR H/V SCROLL VALUE.
  98. [THE SIZE OF 13-BIT MAXIMUM (-4096->4095) CAN BE DESIGNATED IN
  99. MODE 7] (SEE APPENDIX-8 & 9)
  100. BY WRITING TO THE REGISTER TWICE, THE DATA CAN BE SET IN ORDER
  101. OF LOW & HIGH.
  102. ADDRESS : $2115
  103. NAME : VMAIN
  104. CONTENTS : VRAM ADDRESS INCREMENT VALUE DESIGNATION
  105. D7 H/L INC (WORD OR BYTE VRAM ACCESS)
  106. DESIGNATE THE INCREMENT TIMING FOR THE ADDRESS
  107. 0: THE ADDRESS WILL BE INCREASED AFTER THE DATA HAS
  108. BEEN WRITTEN TO REGISTER <2118H> OR THE DATA
  109. HAS BEEN READ FROM REGISTER <2139H>.
  110. THIS WILL RESULT IN BYTE VRAM ACCESS, I.E. FOR
  111. MODE 7 TILE MAP CHANGE.
  112. 1: THE ADDRESS WILL BE INCREASED AFTER THE DATA HAS
  113. BEEN WRITTEN TO REGISTER <2119H> OR THE DATA
  114. HAS BEEN READ FROM REGISTER <213AH>.
  115. THIS WILL RESULT IN WORD VRAM ACCESS, I.E. FOR
  116. MODE 1 TILE MAP CHANGE.
  117. D6-D4 ---
  118. D3-D2 FULL GRAPHIC (G1 & G0)
  119. D1-D0 SC INCREMENT (I1 & I0)
  120. G1 G0 I1 I0 | INCREMENT VALUE
  121. ----------------------------
  122. 0 1 0 0 | INCREMENT BY 8 FOR 32 TIMES (2-BIT FORMATION)
  123. 1 0 0 0 | INCREMENT BY 8 FOR 64 TIMES (4-BIT FORMATION)
  124. 1 1 0 0 | INCREMENT BY 8 FOR 128 TIMES (8-BIT FORMATION)
  125. 0 0 0 0 | ADDRESS INCREMENTS 1 BY 1
  126. 0 0 0 1 | ADDRESS INCREMENTS 32 BY 32
  127. 0 0 1 0 | ADDRESS INCREMENTS 64 BY 64
  128. 0 0 1 1 | ADDRESS INCREMENTS 128 BY 128
  129. ADDRESS : $2116/$2117
  130. NAME : VMADDL/VMADDH
  131. CONTENTS : ADDRESS FOR VRAM READ
  132. D7-D0 VRAM ADDRESS (LOW) 2116H
  133. D7-D0 VRAM ADDRESS (HIGH) 2117H
  134. THIS IS THE INITIAL ADDRESS FOR READING FROM THE VRAM OR WRITING
  135. TO THE VRAM.
  136. THE DATA IS READ OR WRITTEN BY THE ADDRESS SET INITIALLY, AND
  137. EVERY TIME THE DATA IS READ THE ADDRESS WIL BE INCREASED
  138. AUTOMATICALLY.
  139. THE VALUE TO BE INCREASED IS DETERMINED BY "SC INCREMENT" OF
  140. REGISTER <2115H> AND THE SETTING VALUE OF THE "FULL GRAPHIC".
  141. ADDRESS : $2118/$2119
  142. NAME : VMDATAL/VMDATAH
  143. CONTENTS : DATA FOR VRAM WRITE
  144. D7-D0 VRAM DATA (LOW) 2118H
  145. D7-D0 VRAM DATA (HIGH) 2119H
  146. THIS IS THE SCREEN DATA AND CHARACTER DATA (BG & OBJ), WHICH
  147. CAN WRITE AT ANY ADDRESS OF THE VRAM.
  148. ACCORDING TO THE SETTING OF REGISTER <2115H> "H/L INC.", THE
  149. DATA CAN BE WRITTEN TO THE VRAM AS FOLLOWS:
  150. H/L INC | WRITE TO REGISTER | OPERATION
  151. --------------------------------------------------------------
  152. 0 | WRITE TO <2118H> | THE DATA IS WRITTEN TO LOWER 8BIT
  153. | ONLY. | OF THE VRAM & THE ADDRESS WILL BE
  154. | | INCREASED AUTOMATICALLY.
  155. 1 | WRITE TO <2119H> | THE DATA IS WRITTEN TO UPPER 8BIT
  156. | ONLY. | OF THE VRAM & THE ADDRESS WILL BE
  157. | | INCREASED AUTOMATICALLY.
  158. 0 | WRITE IN ORDER OF | WHEN THE DATA IS SET IN THE ORDER
  159. | <2119H> & <2118H> | OF UPPER & LOWER THE ADDRESS WILL
  160. | | BE INCREASED.
  161. 1 | WRITE IN ORDER OF | WHEN THE DATA IS SET IN THE ORDER
  162. | <2118H> & <2119H> | OF LOWER & UPPER THE ADDRESS WILL
  163. | | BE INCREASED.
  164. NOTE: THE DATA CAN ONLY BE WRITTEN DURING V-BLANK OR FORCED BLANK
  165. ~~~~~ PERIOD.
  166. ADDRESS : $211A
  167. NAME : M7SEL
  168. CONTENTS : INITIAL SETTING IN SCREEN MODE-7
  169. D7-D6 SCREEN OVER (O1 & O0)
  170. PROCESS MADE IF THE SCREEN TO BE DISPLAYED IS
  171. OUTSIDE OF THE SCREEN AREA. (SEE BELOW)
  172. D5-D2 ---
  173. D1-D0 SCREEN FLIP (V/H)
  174. 0: NORMAL
  175. 1: FLIPPED
  176. O1 O0 | PROCESS OUT OF AREA
  177. --------------------------------------------------------------
  178. 0 0 | SCREEN REPETITION IF OUTSIDE OF SCREEN AREA
  179. 1 0 | CHARACTER 0x00 REPETITION IF OUTSIDE OF SCREEN AREA
  180. 1 1 | OUTSIDE OF THE SCREEN AREA IS THE BACK DROP SCREEN IN
  181. | SINGLE COLOR
  182. ADDRESS : $211B/$211C/$211D/$211E/$211F/$2120
  183. NAME : M7A/M7B/M7C/M7D/M7X/M7Y
  184. CONTENTS : ROTATION/ENLARGEMENT/REDUCTION IN MODE-7, CENTER COORDINATE
  185. SETTINGS & MULTIPLICAND/MULTIPLIER SETTINGS OF COMPLEMENTARY
  186. MULTIPLICATION.
  187. D7-D0 MATRIX PARAMETER A (LOW[MP7-MP0],HIGH[MP15-MP8])211BH
  188. D7-D0 MATRIX PARAMETER B (LOW[MP7-MP0],HIGH[MP15-MP8])211CH
  189. D7-D0 MATRIX PARAMETER C (LOW[MP7-MP0],HIGH[MP15-MP8])211DH
  190. D7-D0 MATRIX PARAMETER D (LOW[MP7-MP0],HIGH[MP15-MP8])211EH
  191. THE 8-BIT DATA SHOULD BE WRITTEN TWICE IN THE ORDER OF LOWER &
  192. UPPER. THEN, THE PARAMETER OF ROTATION, ENLARGEMENT AND REDUCTION
  193. SHOULD BE SET BY ITS 16-BIT AREA.
  194. THE VALUE DOWN TO A DECIMAL POINT SHOULD BE SET TO THE LOWER
  195. 8-BIT. THE MOST SIGNIFICANT BIT OF THE UPPER 8-BIT IS FOR THE
  196. SIGNED BIT. (MP15 IS THE SIGNED BIT. THERE IS A DECIMAL POINT
  197. BETWEEN M7 & M8)
  198. FORMULA FOR ROTAION/ENLARGEMENT/REDUCTION (SEE APPENDIX-13)
  199. / X2 \ / A B \ / X1-X0 \ / X0 \
  200. | | = | | | | + | |
  201. \ Y2 / \ C D / \ Y1-Y0 / \ Y0 /
  202. A=COS(GAMMA)*(1/ALPHA), B=SIN(GAMMA)*(1/ALPHA)
  203. C=-SIN(GAMMA)*(1/BETA), D=COS(GAMMA)*(1/BETA)
  204. GAMMA: ROTATION ANGLE
  205. ALPHA: REDUCTION RATES FOR X(H)
  206. BETA : REDUCTION RATES FOR Y(V)
  207. X0&Y0: CENTER COORDINATE
  208. X1&Y1: DISPLAY COORDINATE
  209. X2&Y2: COORDINATE BEFORE CALCULATION
  210. SET THE VALUE OF "A" TO REGISTER <211BH>. IN THE SAME WAY,
  211. SET "B-D" TO THE REGISTERS <211CH>-<211EH>.
  212. * THE COMPLEMENTARY MULTIPLICATION (16BIT X 8BIT) CAN BE DONE BY
  213. USING REGISTERS <211BH> <211C>.
  214. WHEN SETTING 16 BIT DATA TO REGISTER <211BH> AND 8BIT DATA TO
  215. REGISTER <211CH>, THE MULTIPLICATION RESULT CAN BE INDICATED
  216. RAPIDLY BY READING REGISTERS <2134H>-<2136H>.
  217. D7-D0 CENTER POSITION X0 (LOW[X7-X0],HIGH[X12-X8]) 211FH
  218. D7-D0 CENTER POSITION Y0 (LOW[Y7-X0],HIGH[Y12-X8]) 2120H
  219. THE CENTER COORDINATE (X0,Y0) FOR ROTATION/ENLARGEMENT/REDUCTION
  220. CAN BE DESIGNATED BY THIS REGISTER.
  221. THE COORDINATE VALUE OF X0 & Y0 CAN BE DESIGNATED BY 13-BIT
  222. (COMPLEMENT OF 2).
  223. THE REGISTER REQUIRES THAT THE LOWER 8-BIT IS SET FIRST AND THE
  224. UPPER 5-BIT IS SET. THEREFORE, 13-BIT DATA IN TOTAL CAN BE SET.
  225. ADDRESS : $2121
  226. NAME : CGADD
  227. CONTENTS : ADDRESS FOR CG-RAM WRITE
  228. D7-D0 CG-RAM ADDRESS
  229. THIS IS THE INITIAL ADDRESS FOR READING FROM THE CG-RAM OR
  230. WRITING TO THE CG-RAM
  231. THE DATA IS READ BY THE ADDRESS SET INITIALLY, AND EVERY TIME
  232. THE DATA IS READ OR WRITTEN THE ADDRESS WILL BE INCREASED
  233. AUTOMATICALLY.
  234. ADDRESS : $2122
  235. NAME : CGDATA
  236. CONTENTS : DATA FOR CG-RAM WRITE
  237. D7-D0 CG-RAM DATA (LOW[D7-D0],HIGH[D14-D8])
  238. THIS IS THE COLOR GENERATER DATA TO BE WRITTEN AT ANY ADDRESS
  239. OF THE CG-RAM.
  240. THE MAPPING OF BG1-BG4 AND OBJ DATA IN CG-RAM WILL BE DETERMINED,
  241. WHICH IS PERFORMED BY EVERY MODE SELECTED BY "BG MODE" OF
  242. REGISTER <2105H>. (SEE APPENDIX-14)
  243. THERE AREA THE COLOR DATA OF 8-PALETTES FOR EACH SCREEN OF
  244. BG1-BG4. THE PALETTE SELECTION IS DETERMINED BY 3-BIT OF THE
  245. SC DATA "COLOR"
  246. BECAUSE THE CG-RAM DATA IS 15-BIT/WORD, IT IS NECESSARY TO SET
  247. LOWER 8-BIT FIRST TO THIS REGISTER AND THE THE UPPER 7-BIT.
  248. WHEN BOTH LOWER & UPPER ARE SET, THE ADDRESS WILL BE INCREASED
  249. BY 1 AUTOMATICALLY.
  250. NOTE: AFTER THE ADDRESS IS SET, THE DATA SHOULD BE WRITTEN FROM
  251. ~~~~~ THE LOWER AS WELL AS THE OAM.
  252. NOTE: THE DATA CAN BE WRITTEN ONLY DURING H/V BLANK OR FORCED-
  253. ~~~~~ BLANK PERIOD.
  254. ADDRESS : $2123/$2124/$2125
  255. NAME : W12SEL/W34SEL/WOBJSEL
  256. CONTENTS : WINDOW MASK SETTINS (BG1-BG4, OBJ, COLOR)
  257. D7 BG2 WINDOW-2 ENABLE 2123H
  258. 0: OFF
  259. 1: ON
  260. D6 BG2 WINDOW-2 IN/OUT
  261. THE WINDOW MASK AREA CAN BE DESIGNATED WHETHER
  262. INSIDE OR OUTSIDE OF THE FRAME DESIGNATED BY THE
  263. WINDOW POSITION.
  264. 0: IN
  265. 1: OUT
  266. D5 BG2 WINDOW-1 ENABLE
  267. D4 BG2 WINDOW-1 IN/OUT
  268. D3 BG1 WINDOW-2 ENABLE
  269. D2 BG1 WINDOW-2 IN/OUT
  270. D1 BG1 WINDOW-1 ENABLE
  271. D0 BG1 WINDOW-1 IN/OUT
  272. D7 COLOR WINDOW-2 ENABLE 2125H
  273. D6 COLOR WINDOW-2 IN/OUT
  274. D5 COLOR WINDOW-1 ENABLE
  275. D4 COLOR WINDOW-1 IN/OUT
  276. D3 OBJ WINDOW-2 ENABLE
  277. D2 OBJ WINDOW-2 IN/OUT
  278. D1 OBJ WINDOW-1 ENABLE
  279. D0 OBJ WINDOW-1 IN/OUT
  280. THE COLOR WINDOW IS A WINDOW FOR MAIN & SUB SCREEN (IT IS
  281. RELATED TO REGISTER <2130H>.
  282. ADDRESS : $2126/$2127/$2128/$2129
  283. NAME : WH0/WH1/WH2/WH3
  284. CONTENTS : WINDOW POSITION DESIGNATION (SEE APPENDIX-15)
  285. D7-D0 WINDOW PPOSITION
  286. H0,H2 LEFT POSITION DESIGNATION
  287. H1,H3 RIGHT POSITION DESIGNATION
  288. NOTE: IF "LEFT POSITION SETTING VALUE > RIGHT POSITION VALUE"
  289. ~~~~~ IS ASSUMED, THERE WILL BE NO RANGE OF THE WINDOW.
  290. ADDRESS : $212A/$212B
  291. NAME : WBGLOG/WOBJLOG
  292. CONTENTS : MASK LOGIC SETTINGS FOR WINDOW-1 & 2 ON EACH SCREEN
  293. D7-D6 BG4 D1/D0 212AH
  294. D5-D4 BG3 D1/D0
  295. D3-D2 BG2 D1/D0
  296. D1-D0 BG1 D1/D0
  297. D7-D4 --- 212BH
  298. D3-D2 COLORWINDOW D1/D0
  299. D1-D0 OBJWINDOW D1/D0
  300. D1 D0 | LOGIC
  301. ------------------
  302. 0 0 | OR
  303. 0 1 | AND
  304. 1 0 | XOR
  305. 1 1 | XNOR
  306. NOTE: "IN/OUT" OF REGISTERS <2123H>-<2125H> BECOMES THE
  307. ~~~~~ "NOT-LOGIC" FOR EACH WINDOW-1 & WINDOW-2.
  308. ADDRESS : $212C
  309. NAME : TM
  310. CONTENTS : MAIN SCREEN, DESIGNATION
  311. D7-D5 ---
  312. D4 OBJ
  313. D3 BG4
  314. D2 BG3
  315. D1 BG2
  316. D0 BG1
  317. MAIN SCREEN DESIGNATION:
  318. DESIGNATE THE SCREEN (BG1-BG4, OBJ) TO BE DISPLAYED
  319. AS THE MAIN SCREEN. DESIGNATE THE SCREEN TO BE ADDED
  320. FOR THE SCREEN ADDITION/SUBTRACTION
  321. 0: DISABLE
  322. 1: ENABLE
  323. ADDRESS : $212D
  324. NAME : TS
  325. CONTENTS : SUB SCREEN DESIGNATION
  326. D7-D5 ---
  327. D4 OBJ
  328. D3 BG4
  329. D2 BG3
  330. D1 BG2
  331. D0 BG1
  332. SUB SCREEN DESIGNATION:
  333. DESIGNATE THE SCREEN (BG1-BG4, OBJ) TO BE DISPLAYED
  334. AS SUB SCREEN. DESIGNATE THE ADDITION/SUBTRACTION
  335. SCREEN AT THE POINT WHEN THE SCREEN ADDITION/SUBTRACTION
  336. IS FUNCTIONING.
  337. 0: DISABLE
  338. 1: ENABLE
  339. * WHEN THE SCREEN ADDITION/SUBTRACTION IS FUNCTIONING, THE SUB
  340. SCREEN IS A SCREEN TO BE ADDED OR SUBTRACTED AGAINST THE MAIN
  341. SCREEN.
  342. ADDRESS : $212E
  343. NAME : TMW
  344. CONTENTS : WINDOW MASK DESIGNATION FOR MAIN SCREEN
  345. D7-D5 ---
  346. D4 OBJ
  347. D3 BG4
  348. D2 BG3
  349. D1 BG2
  350. D0 BG1
  351. WINDOW MASK DESIGNATION FOR MAIN SCREEN:
  352. IN THE WINDOW AREA DESIGNATED BY REGISTER <2123H>-<2129H>,
  353. THE SCREEN TO BE DISPLAYED CAN BE DESIGNATED, WHICH IS
  354. SELECTED AMONG THE MAIN SCREEN DESIGNATED BY REGISTER
  355. <212CH>.
  356. 0: DISABLE
  357. 1: ENABLE
  358. ADDRESS : $212F
  359. NAME : TSW
  360. CONTENTS : WINDOW MASK DESIGNATION FOR SUB SCREEN
  361. D7-D5 ---
  362. D4 OBJ
  363. D3 BG4
  364. D2 BG3
  365. D1 BG2
  366. D0 BG1
  367. WINDOW MASK DESIGNATION FOR SUB SCREEN:
  368. IN THE WINDOW AREA DESIGNATED BY REGISTER <2123H>-<2129H>,
  369. THE SCREEN TO BE DISPLAYED CAN BE DESIGNATED, WHICH IS
  370. SELECTED AMONG THE SUB SCREEN DESIGNATED BY REGISTER
  371. <212CH>.
  372. 0: DISABLE
  373. 1: ENABLE
  374. * WHEN THE SCREEN ADDITION/SUBTRACTION IS FUNCTIONING, THE SUB
  375. SCREEN IS A SCREEN TO BE ADDED OR SUBTRACTED AGAINST THE MAIN
  376. SCREEN.
  377. ADDRESS : $2130
  378. NAME : CGWSEL
  379. CONTENTS : INITIAL SETTINGS FOR FIXED COLOR ADDITION OR SCREEN ADDITION
  380. D7-D6 MAIN SW (M1/M0)
  381. D5-D4 SUB SW (S1/S0)
  382. D3-D2 ---
  383. D1 CC ADD ENABLE, FIXED COLOR ADDITION/SUBTRACTION ENABLE
  384. DESIGNATE WHETHER 2 KINDS OF THE DATA SHOULD
  385. BE ADDED/SUBTRACTED EACH OTHER OR NOT, WHICH ARE
  386. THE FIXED COLOR SET BY REGISTER <2132H>, AND
  387. THE COLOR DATA WHICH IS SET TO CGRAM.
  388. 0: ADDITION/SUBTRACTION FOR FIXED COLOR
  389. 1: ADDITION/SUBTRACTION FOR SUB SCREEN
  390. D0 DIRECT SELECT (SEE APPENDIX-14)
  391. THE VRAM DATA (COLOR & CHARACTER DATA) BECOME THE
  392. COLOR DATA DIRECTLY. [ONLY WHEN MODE-3,4 & 7]
  393. 0: DISABLE
  394. 1: ENABLE
  395. M1(S1) M0(S0) | NORMAL DISPLAY IS:
  396. --------------------------------------------------------------
  397. 0 0 | ALL THE TIME
  398. 0 1 | INSIDE WINDOW ONLY
  399. 1 0 | OUTSIDE WINDOW ONLY
  400. 1 1 | ALL THE TIME
  401. ADDRESS : $2131
  402. NAME : CGADSUB
  403. CONTENTS : ADDITION/SUBTRACTION & SUBTRACTION DESIGNATION FOR EACH SCREEN,
  404. OBJ & BACKGROUND COLOR
  405. D7 COLOR DATA ADDITION/SUBTRACTION SELECT
  406. DESIGNATE THE SELECTION EITHER OF THE ADDITION
  407. OR THE SUBTRACTION MODE.
  408. 0: ADDITION MODE SELECT
  409. 1: SUBTRACTION MODE SELECT
  410. D6 "1/2 OF COLOR DATA" DESIGNATION
  411. WHEN THE COLOR CONSTANT ADDITION/SUBTRACTION OR THE
  412. SCREEN ADDITION/SUBTRACTION IS PERFORMED, DESIGNATE
  413. WHETHER THE RGB RESULT IN THE ADDITION/SUBTRACTION
  414. AREA SHOULD BE "1/2" OR NOT. HOWEVER, IN THE BACK
  415. COLOR CONSTANT AREA ON THE SUB SCREEN, IT DOES NOT
  416. BECOME "1/2"
  417. 0: DISABLE
  418. 1: ENABLE
  419. D5 BACK
  420. D4 OBJ
  421. D3 BG4
  422. D2 BG3
  423. D1 BG2
  424. D0 BG1
  425. COLOR DATA ADDITION/SUBTRACTION ENABLE
  426. 0: DISABLE
  427. 1: ENABLE
  428. ADDRESS : $2132
  429. NAME : COLDATA
  430. CONTENTS : FIXED COLOR DATA FOR FIXED COLOR ADDITION/SUBTRACTION
  431. D7 BLUE
  432. D6 GREEN
  433. D5 RED
  434. BIT FOR SELECTING DESIRED COLOR
  435. D4-D0 COLOR BRILLIANCE DATA
  436. SET THE COLOR CONSTANT DATA FOR COLOR CONSTANT
  437. ADDITION/SUBTRACTION
  438. * R/G/B BRIGHTNESS SHOULD BE SET BY THE DATA OF EACH 5-BIT.
  439. [EXAMPLE] RED : C0H, 3FH (B=00H, G=00H, R=1FH)
  440. GREEN : A0H, 5FH (B=00H, G=1FH, R=00H)
  441. BLUE : 60H, 9FH (B=1FH, G=00H, R=00H)
  442. WHITE : FFH
  443. BLACK : 00H
  444. ADDRESS : $2133
  445. NAME : SETINI
  446. CONTENTS : SCREEN INITIAL SETTING
  447. D7 EXTERNAL SYNCHRONIZATION
  448. IT IS USED FOR SUPER IMPOSE AND ETC. NORMALLY,
  449. "0" SHOULD BE WRITTEN.
  450. D6 EXTBG MODE (SCREEN EXPAND)
  451. ENABLE THE DATA SUPPLIED FROM THE EXTERNAL LSI.
  452. FOR THE SFX, ENABLE WHEN THE SCREEN WITH PRIORITY
  453. IS USED ON MODE-7.
  454. D5-D4 ---
  455. D3 HORIZONTAL PSEUDO 512 MODE
  456. 512 IMAGINARY RESOLUTION (HORIZONTAL CAN BE MADE
  457. BY SHIFTING THE SUBSCREEN HALF DOT TO THE LEFT.)
  458. 0: DISABLE
  459. 1: ENABLE
  460. D2 BG V-DIRECTION DISPLAY
  461. SWITCH THE DISPLAY LINE OF A FIELD TO 224 LINE OR
  462. 239 LINE. (IN CASE OF INTERALACE IT WILL BE
  463. DOUBLED DOT.)
  464. 0: 224 LINE
  465. 1: 239 LINE
  466. D1 OBJ V-DIRECTION DISPLAY
  467. IN THE INTERLACE MODE, SELECT EITHER OF 1-DOT PER
  468. LINE OR 1-DOT REPEATED EVERY 2-LINES. IF "1" IS
  469. WRITTEN, THE OBJ SEEMS REDUCED HALF VERTICALLY IN
  470. APPEARANCE.
  471. D0 SCANNING
  472. INTERLACE/NON-INTERLACE SELECTION (IT RELATES TO
  473. <2105H>.
  474. 0: NON INTERLACE
  475. 1: INTERLACE
  476. ADDRESS : $2134/$2135/$2136
  477. NAME : *MPYL/*MPYM/*MPYH
  478. CONTENTS : MULTIPLICATION RESULT
  479. D7-D0 MPY (LOW) 2134H
  480. D7-D0 MPY (MID) 2135H
  481. D7-D0 MPY (HIGH) 2136H
  482. THIS IS A MULTIPLICATION RESULT (COMPLEMENT OF 2) CAN BE READ
  483. BY SETTING 16-BIT TO REGISTER <211BH> AND SETTING 8 BIT TO
  484. REGISTER <211CH>
  485. ADDRESS : $2137
  486. NAME : *SLHV
  487. CONTENTS : SOFTWARE LATCH FOR H/V COUNTER
  488. D7-D0 SOFT LATCH FOR H/V COUNTER
  489. THIS IS A REGISTER, WHICH GENERATE THE PULSE FOR LATCHING THE H/V
  490. COUNTER VALUE.
  491. THE H/V COUNTER VALUE AT THE POINT WHEN REGISTER <2137H> IS READ
  492. CAN BE LATCHED. THE DATA WHICH WAS READ IS MEANINGLESS DATA.
  493. THE H/V COUNTER VALUE LATCHED CAN BE REFFERED BY REGISTERS
  494. <213CH> & <213DH>.
  495. ADDRESS : $2138
  496. NAME : OAMDATAREAD (name differs from SNES manual)
  497. CONTENTS : READ DATA FROM OAM
  498. D7-D0 OAM DATA (LOW,HIGH)
  499. THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF
  500. THE OAM.
  501. WHEN THE ADDRESS IS SET TO REGISTER <2102H><2103H> AND REGISTER
  502. <2138H> IS ALSO ACCESSED THE DATA CAN BE READ IN THE ORDER OF
  503. LOW 8-BIT/HIGH 8-BIT.
  504. AFTERWARD, THE ADDRESS WILL BE INCREASED AUTOMATICALLY, AND THE
  505. DATA OF THE NEXT ADDRESS CAN BE READ.
  506. NOTE: THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED
  507. ~~~~~ BLANK PERIOD.
  508. ADDRESS : $2139/$213A
  509. NAME : VMDATALREAD/VMDATAHREAD (names differ from SNES manual)
  510. CONTENTS : READ DATA FROM VRAM
  511. D7-D0 VRAM DATA (LOW) 2139H
  512. D7-D0 VRAM DATA (HIGH) 213AH
  513. THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF
  514. THE VRAM.
  515. THE INITIAL ADDRESS SHOULD BE SET BY REGISTERS <2116H> AND
  516. <2117H>. THE DATA CAN BE READ BY THE ADDRESS WHICH HAS BEEN SET
  517. INITIALLY.
  518. WHEN READING THE DATA CONTINOUSLY, THE FIRST DATA FOR THE ADDRESS
  519. INCREMENT SHOULD BE READ AS A DUMMY DATA AFTER THE ADDRESS HAS
  520. BEEN SET.
  521. QUANTITY TO BE INCREASED WILL BE DETERMINED BY "SC INCREMENT" OF
  522. REGISTER <2115H> AND THE SETTING VALUE OF THE "FULL GRAPHIC".
  523. NOTE: THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED
  524. ~~~~~ BLANK PERIOD.
  525. ADDRESS : $213B
  526. NAME : CGDATAREAD (name differs from SNES manual)
  527. CONTENTS : READ DATA FROM CG-RAM
  528. D7-D0 CG DATA (LOW,HIGH)
  529. THIS IS A REGISTER, WHICH CAN READ THE DATA AT ANY ADDRESS OF
  530. THE CG-RAM.
  531. THE INITIAL ADDRESS SHOULD BE SET BY REGISTER <2121H>. THE LOWER
  532. 8-BIT IS READ FIRST, AND THE THE UPPER 7-BIT WILL BE READ BY
  533. ACCESSING THIS REGISTER. THE CURRENT ADDRESS WILL BE INCREASED
  534. TO THE NEXT ADDRESS AT THE SAME TIME THE UPPER 7-BIT IS READ.
  535. NOTE: THE DATA CAN BE READ ONLY DURING H/V BLANK OR FORCED
  536. ~~~~~ BLANK PERIOD.
  537. ADDRESS : $213C/$213D
  538. NAME : *OPHCT/*OPVCT
  539. CONTENTS : H/V COUNTER DATA BY EXTERNAL OR SOFTWARE LATCH
  540. D7-D0 OUTPUT DATA OF H-COUNTER [9-BIT] 213CH
  541. D7-D0 OUTPUT DATA OF V-COUNTER [9-BIT] 213DH
  542. THE H/V COUNTER IS LATCHED BY READING REGISTER <2137H>, AND ITS
  543. H/V COUNTER VALUE CAN BE READ BY THIS REGISTER.
  544. THE H/V COUNTER IS ALSO LATCHED BY THE EXTERNAL LATCH, AND ITS
  545. VALUE CAN BE READ BY THIS REGISTER.
  546. IF REGISTER <213CH> OR <213DH> IS READ AFTER REGISTER <213FH> HAS
  547. BEEN READ, THE LOWER 8-BIT DATA WILL BE READ FIRST, AND THEN THE
  548. UPPER 1-BIT WILL BE READ BY READING THE REGISTER.
  549. ADDRESS : $213E
  550. NAME : *STAT77
  551. CONTENTS : PPU STATUS FLAG & VERSION NUMBER
  552. D7 TIME OVER \
  553. D6 RANGE OVER /
  554. OBJ DISPLAY STATUS (ON A HORIZONTAL LINE)
  555. RANGE: WHEN QUANTITY OF THE OBJ (REGARDLESS OF
  556. THE SIZE) BECOMES 33 PCS OR MORE, "1"
  557. WILL BE SET.
  558. TIME: WHEN QUANTITY OF THE OBJ WHICH IS CONVERTED
  559. TO "8 x 8-SIZE" IS 35 PCS OR MORE, "1"
  560. WILL BE SET.
  561. D5 MASTER/SLAVE MODE SELECT. LSI MODE (NORMALLY "0" IS SET.)
  562. D4 ---
  563. D3-D0 5C77 VERSION NUMBER
  564. NOTE: THE FLAG WILL BE RESET AT THE END OF THE V-BLANK PERIOD.
  565. ~~~~~
  566. ADDRESS : $213F
  567. NAME : *STAT78
  568. CONTENTS : PPU STATUS FLAG & VERSION NUMBER
  569. D7 FIELD
  570. THIS IS A STATUS FLAG, WHICH INDICATED WHETHER 1ST
  571. FIELD IS SCANNED OR 2ND FIELD IS SCANNED IN INTER-
  572. LACE MODE. (THE DEFINITION IS DIFFERENT FROM THE
  573. FIELD OF NTSC.)
  574. 0: 1ST FIELD
  575. 1: 2ND FIELD
  576. D6 EXTERNAL LATCH FLAG
  577. WHEN THE EXTERNAL SIGNAL (LIGHT PEN, ETC.) IS
  578. APPLIED, IT ENABLES TO LATCH THE H/V COUNTER VALUE.
  579. D5 ---
  580. D4 NTSC/PAL MODE
  581. 0: NTSC
  582. 1: PAL
  583. D3-D0 5C78 VERSION NUMBER
  584. NOTE: WHEN THIS REGISTER IS READ, REGISTERS <213CH><213DH> WILL
  585. ~~~~~ BE INITIALIZED INDIVIDUALLY IN THE ORDER OF LOW & HIGH.
  586. ADDRESS : $2140/$2141/$2142/$2143
  587. NAME : APUI00/APUI01/APUI02/APUI03
  588. CONTENTS : COMMUNICATION PORT WITH APU
  589. D7-D0 APU I/O PORT
  590. THIS PORT PROVIDES MORE REGISTERS FOR THE PURPOSE OF IN/OUT,
  591. WHICH ARE 8 REGISTERS IN TOTAL IN THE APU. THEREFORE, THE
  592. DIFFERENT REGISTER WILL BE ACCESSED, WHETHER READING OR
  593. WRITING FOR THE SAME ADDRESS.
  594. SEE "APU MANUAL" FOR THE DETAILS OF THE COMMUNICATION METHOD.
  595. ADDRESS : $2180
  596. NAME : WMDATA
  597. CONTENTS : DATA TO CONSECUTIVLEY READ FROM AND WRITE TO WRAM
  598. D7-D0 WORK RAM DATA
  599. DATA TO CONSECUTIVLEY READ FROM AND WRITE TO WRAM
  600. DATA IS READ AND WRITTEN AT ADDRESS SET BY REGISTER <2181H>-<2183H>,
  601. AND ADDRESS AUTOMATICALLY INCREASES EACH TIME DATA IS READ OR WRITTEN.
  602. ADDRESS : $2181/$2182/$2183
  603. NAME : WMADDL/WMADDM/WMADDH
  604. CONTENTS : ADDRESS TO CONSECUTIVELY READ AND WRITE WRAM
  605. D7-D0 WRAM DATA (LOW) 2181H
  606. D7-D0 WRAM DATA (MID) 2182H
  607. D0 WRAM DATA (HIGH) 2183H
  608. ADDRESS TO BE SET BEFORE WRAM IS CONSECUTIVLEY READ OR WRITTEN.
  609. A0 TROUGH A16 AT REGISTER <2181H>-<2183H> IS LOWER 17 BIT ADDRESS
  610. TO SHOW ADDRESS $7E0000-$7FFFFF IN MEMORY.
  611. ADDRESS : $4200
  612. NAME : NMITIMEN
  613. CONTENTS : ENABLE FLAG FOR V-BLANK, TIMER INTERRUPT & JOY CONTROLLER READ
  614. D7 NMI ENABLE
  615. ENABLE NMI AT THE POINT WHEN V-BLANK BEGINS
  616. (WHEN POWER IS TURNED ON OR THE RESET SIGNAL IS
  617. APPLIED, IT WILL BE "0".)
  618. 0: NMI DISABLED
  619. 1: NMI ENABLED
  620. D6 ---
  621. D5-D4 TIMER ENABLE (V-EN/H-EN)
  622. D3-D1 ---
  623. D0 JOY-C ENABLE
  624. 0: DISABLE AUTOMATIC READING OF THE JOY-CONTROLLER.
  625. 1: ENABLE AUTOMATIC READING OF THE JOY-CONTROLLER.
  626. V-EN H-EN | FUNCTION
  627. --------------------------------------------------------
  628. 0 0 | DISABLE BOTH H & V
  629. 0 1 | ENABLE H ONLY, IRQ APPLIED BY H-COUNT TIMER VALUE DESIGNATED
  630. 1 0 | ENABLE V ONLY, IRQ APPLIED BY V-COUNT TIMER VALUE DESIGNATED
  631. 1 1 | ENABLE BOTH V & H, IRQ APPLIED BY BOTH H & V COUNT TIMER VAL
  632. | DESIGNATED.
  633. * READING THE DATA CAN BE STARTED AT THE BEGINNING OF V-BLANK
  634. PERIOD, BUT IT TAKES ABOUT FOR 3 OR 4 SCANNING PERIOD UNTIL
  635. COMPLETION OF READING.
  636. ADDRESS : $4201
  637. NAME : WRIO
  638. CONTENTS : PROGRAMMABLE I/O PORT (OUT-PORT)
  639. D7-D0 I/O PORT
  640. THIS IS A PROGRAMMABLE I/O PORT (OUT-PORT). THE WRITTEN DATA
  641. WILL BE OUTPUT DIRECTLY FROM THE OUT-PORT.
  642. WHEN THIS IS USED AS A INPORT. "1" SHOULD BE WRITTEN TO THE
  643. PARTICULAR BIT WHICH WILL BE USED AS IN PORT. THE INPUT CAN
  644. BE READ BY REGISTER <4213H>.
  645. ADDRESS : $4202/$4203
  646. NAME : WRMPYA/WRMPYB
  647. CONTENTS : MULTIPLIER & MULTIPLICAND BY MULTIPLICATION
  648. D7-D0 MULTIPLICAND-A 4202H
  649. D7-D0 MULTIPLIER-B 4203H
  650. THIS IS A REGISTER, WHICH CAN SET A MULITPLICAND (A) AND A
  651. MULTIPLIER (B) FOR ABSOLUTE MULTIPLICATION OF
  652. "A (8-BIT) * B (8-BIT)=C (16-BIT)"
  653. A PRODUCT (C) CAN BE READ BY REGISTERS <4216H><4217H>
  654. SET IN THE ORDER OF (A) AND (B). THE OPERATION WILL START AS
  655. SOON AS (B) HAS BEEN SET, AND IT WILL BE COMPLETED RIGHT AFTER
  656. 8-MACHINE CYCLE PERIOD.
  657. ONCE THE DATA OF THE A-REGISTER IS SET, IT WILL NOT BE DESTROYED
  658. UNTIL NEW DATA IS SET.
  659. ADDRESS : $4204/$4205/$4206
  660. NAME : WRDIVL/WRDIVH/WRDIVB
  661. CONTENTS : DIVISOR & DIVIDEND DIVIDE
  662. D7-D0 MULTIPLIER-C (LOW) 4204H
  663. D7-D0 MULTIPLIER-C (HIGH) 4205H
  664. D7-D0 DIVISOR-B 4206H
  665. THIS IS A REGISTER, WHICH CAN SET A DIVIDEND (C) AND A DIVISOR (B)
  666. FOR ABSOLUTE DIVIDE OF
  667. "C (16-BIT) / B (8-BIT)=A (16-BIT)"
  668. THE DIVISOR (A) CAN BE READ BY REGISTERS <4214H><4215H>, AND THE
  669. REMAINDER CAN ALSO BE READ BY REGISTERS <4216H><4217H>.
  670. SET IN THE ORDER OF (C) AND (B). THE OPERATION WILL START AS SOON
  671. AS (B) HAS BEEN SET, AND IT WILL BE COMPLETED RIGHT AFTER 16-
  672. MACHINE CYCLE PERIOD.
  673. ONCE THE DATA OF THE A-REGISTER IS SET, IT WILL NOT BE DESTROYED
  674. UNTIL NEW DATA IS SET.
  675. ADDRESS : $4207/$4208
  676. NAME : HTIMEL/HTIMEH
  677. CONTENTS : H-COUNT TIMER SETTINGS
  678. D7-D0 H COUNT TIMER (H7-H0) 4207H
  679. D7-D1 ---
  680. D0 H COUNT TIMER (H8) 4208H
  681. THIS IS A REGISTER, WHICH CAN SET THE H-COUNT TIMER VALUE.
  682. THE SETTING VALUE SHOULD BE FROM 0 THROUGH 339, WHICH IS COUNTED
  683. FROM THE FAR LEFT ON THE SCREEN.
  684. HWEN THE COORDINATE COUNTER BECOMES THE COUNT VALUE SET, THE IRQ
  685. WILL BE APPLIED. AND AT THE SAME TIME. "1" WILL BE WRITTEN TO
  686. "TIMER IRQ" OF REGISTER <4211H>. (READ RESET)
  687. ENABLE/DISABLE OF THE INTERRUPT WILL BE DETERMINED BY SETTING
  688. REGISTER <4200H>
  689. * THIS CONTINOUS COUNTER IS RESET EVERY SCANNING LINE, THEREFORE
  690. ONCE THE COUNT VALUE IS SET, IT IS POSSIBLE TO APPLY THE IRQ
  691. EVERY TIME THE SCANNING LINE COMES TO THE SAME HORIZONTAL
  692. POSITION ON THE SCREEN.
  693. ADDRESS : $4209/$420AH
  694. NAME : VTIMEL/VTIMEH
  695. CONTENTS : V-COUNT TIMER SETTINGS
  696. D7-D0 V COUNT TIMER (V7-V0) 4209H
  697. D7-D1 ---
  698. D0 V COUNT TIMER (V8) 420AH
  699. THIS IS A REGISTER, WHICH CAN SET THE V-COUNT TIMER VALUE.
  700. THE SETTING VALUE SHOULD BE FROM 0 THROUGH 261(262), WHICH IS
  701. COUNTED FROM THE FAR TOP OF THE SCREEN. [THE LINE NUMBER DESCRIBED
  702. IS DIFFERENT FROM THE ACTUAL LINE NUMBER ON THE SCREEN.]
  703. HWEN THE COORDINATE COUNTER BECOMES THE COUNT VALUE SET, THE IRQ
  704. WILL BE APPLIED. AND AT THE SAME TIME. "1" WILL BE WRITTEN TO
  705. "TIMER IRQ" OF REGISTER <4211H>. (READ RESET)
  706. ENABLE/DISABLE OF THE INTERRUPT WILL BE DETERMINED BY SETTING
  707. REGISTER <4200H>
  708. * THIS IS A CONTINOUS COUNTER SAME AS H-COUNTER, AND IT WILL BE
  709. RESET EVERY TIME 262(263) LINE ARE SCANNED. ONCE THE COUNT
  710. VALUE IS SET, IT IS POSSIBLE TO APPLY THE IRQ EVERY TIME THE
  711. SCANNING LINE COMES TO THE SAME VERTICAL LINE ON THE SCREEN.
  712. ADDRESS : $420B
  713. NAME : MDMAEN
  714. CONTENTS : CHANNEL DESIGNATION FOR GENERAL PURPOSE DMA & TRIGGER (START)
  715. D7-D0 GENERAL PURPOSE CH7-CH0 ENABLE
  716. THE GENERAL PURPOSE DMA CONSISTS OF 8-CHANNELS IN TOTAL.
  717. THIS REGISTER IS USED TO DESIGNATE THE CHANNEL OUT OF 8-CHANNELS.
  718. THE CHANNEL WHICH SHOULD BE USED CAN BE DESIGNATED BY WRITING "1"
  719. TO THE BIT OF THIS CHANNEL. AS SOON AS "1" IS WRITTEN TO THE
  720. BIT (AFTER A FEW CYCLES PASSED), THE GENERAL PURPOSE DMA TRANSFER
  721. WILL BE STARTED.
  722. WHEN THE GENERAL PURPOSE DMA OF THE DESIGNATED CHANNEL IS
  723. COMPLETED, THE FLAG WILL BE CLEARED.
  724. NOTE: BECAUSE THE DATA AREA (REGISTER <4300>-) OF EACH CHANNEL
  725. ~~~~~ IS HELD IN COMMON WITH THE DATA OF EACH H-DMA CHANNEL, THE
  726. CHANNEL DESIGNATED BY THE H-DMA CHANNEL DESIGNATION
  727. REGISTER <420CH> CAN NOT BE USED.
  728. (IT IS PROHIBITED TO WRITE "1" TO THE BIT OF THE CHANNEL)
  729. THEREFORE, 8 CHANNELS (CH0-CH7) SHOULD BE ASSIGNED BY THE
  730. H-DMA AND THE GENERAL PURPOSE DMA)
  731. NOTE: IF THE H-BLANK COME DURING THE OPERATION OF THE GENERAL
  732. ~~~~~ PURPOSE DMA AND THE H-DMA IS STARTED, THE GENERAL PURPOSE
  733. DMA WILL BE DISCONTINUED IN THE MIDDLE, AND RE-STARTED RIGHT
  734. AFTER THE H-DMA IS COMPLETE.
  735. NOTE: IF 2 OR MORE CHANNELS ARE DESIGNATED, THE DMA TRANSFER WILL
  736. ~~~~~ BE PERFORMED CONTINOUSLY ACCORDING TO THE PRIORITY DESCRIBED
  737. IN APPENDIX-1.
  738. AND ALSO, THE CPU STOPS OPERATION UNTIL ALL THE GENERAL
  739. PURPOSE DMA ARE COMPLETED.
  740. ADDRESS : $420C
  741. NAME : HDMAEN
  742. CONTENTS : CHANNEL DESIGNATION FOR H-DMA
  743. D7-D0 H-DMA CH7-DH0 ENABLE
  744. THE H-DMA CONSISTS OF 8-CHANNELS IN TOTAL
  745. THIS REGISTER IS USED TO DESIGNATE THE CHANNEL OUT OF 8-CHANNELS
  746. THE CHANNEL WHICH SHOULD BE USED CAN BE DESIGNATED BY WRITING
  747. "1" TO THE BIT OF THIS CHANNEL. AS SOON AS H-BLANK BEGINS (AFTER
  748. A FEW CYCLES PASSED), THE H-DMA TRANSFER WILL BE STARTED.
  749. NOTE: ONCE THIS FLAG IS SET, IT WILL NOT BE DESTROYED (CLEARED)
  750. ~~~~~ UNTIL NEW DATA IS SET. THEREFORE, THE INITIAL SETTINGS ARE
  751. DONE AUTOMATICALLY EVERY FIELD, AND THE SAME TRANSFER
  752. PATTERN WILL BE REPEATED.
  753. AND ALSO, THE FLAG IS SET OUT OF V-BLANK PERIOD, THE DMA-
  754. TRANSFER WILL BE PERFORMED PROPERLY FROM NEXT SCREEN FRAME.
  755. ADDRESS : $420D
  756. NAME : MEMSEL
  757. CONTENTS : ACCESS CYCLE DESIGNATION IN MEMORY (2) AREA
  758. D7-D1 ---
  759. D0 ACCESS CYCLE DESIGNATION IN MEMORY (2) AREA
  760. 0: 2.68MHz ACCESS CYCLE
  761. 1: 3.58MHz ACCESS CYCLE (ONLY WHEN HIGH SPEED
  762. MEMORY IS USED.)
  763. MEMORY (2) SHOWS THE ADDRESS (8000H-FFFFH) OF THE BANK (80H-BFH)
  764. AND ALL THE ADDRESS OF THE BANK (C0H-FFH).
  765. WHEN POWER IS TURNED ON OR THE RESET SIGNAL IS APPLIED IT BECOMES
  766. "0".
  767. HIGH SPEED MEMORY REQUIERS 120NS OR FASTER EPROMS.
  768. ADDRESS : $4210
  769. NAME : *RDNMI
  770. CONTENTS : NMI FLAG BY V-BLANK & VERSION NUMBER
  771. D7 NMI FLAG BY V-BLANK
  772. WHEN "1" IS WRITTEN TO "NMI ENABLE" OF REGISTER
  773. <4200H>, THIS FLAG WILL SHOW NMI STATUS.
  774. 0: NMI STATUS IS "DISABLE"
  775. 1: NMI STATUS IS "ENABLE"
  776. D6-D4 ---
  777. D3-D0 5A22 VERSION NUMBER
  778. * "1" IS SET TO THIS FLAG AT BEGINNING OF V-BLANK, AND "0" IS
  779. SET AT END OF V-BLANK. ALSO, IT CAN BE SET BY READING THIS
  780. REGISTER.
  781. NOTE: IT IS NECESSARY TO RESET BY READING THIS FLAG DURING
  782. ~~~~~ NMI PROCESSING. (SEE APPENDIX-3)
  783. ADDRESS : $4211
  784. NAME : *TIMEUP
  785. CONTENTS : IRQ FLAG BY H/V COUNT TIMER
  786. D7 IRQ FLAG BY H/V COUNT TIMER
  787. [IN CASE THE TIME ENABLE IS SET BY "TIMER ENABLE"
  788. OF REGISTER <4200H>] AS SOON AS H/V COUNTER TIMER
  789. BECOMES THE COUNT VALUE SET, IRQ WILL BE APPLIED
  790. AND "1" WILL BE SET TO THIS FLAG.
  791. THIS FLAG IS "READ-RESET".
  792. D6-D0 ---
  793. * EVEN IF V-EN="0" AND H-EN="0" ARE SET BY "TIMER ENABLE" OF
  794. REGISTER <4200H>, THIS FLAG WILL BE RESET.
  795. 0: EITHER H/V COUNTER IS IN ACTIVE OR DISABLE.
  796. 1: H/V COUNT TIMER IS TIME UP.
  797. ADDRESS : $4212
  798. NAME : HVBJOY
  799. CONTENTS : H/V BLANK FLAG & JOY CONTROLLER ENABLE FLAG
  800. D7 V-BLANK PERIOD FLAG
  801. 0: OUT OF V-BLANK PERIOD
  802. 1: IN V-BLANK PERIOD
  803. D6 H-BLANK PERIOD FLAG
  804. 0: OUT OF H-BLANK PERIOD
  805. 1: IN H-BLANK PERIOD
  806. D5-D1 ---
  807. D0 JOY CONTROLLER ENABLE FLAG
  808. THIS FLAG SHOWS THE TIMING TO READ THE DATA OF THE
  809. JOY CONTROLLER. (HOWEVER, IT IS LIMITED TO THE CASE
  810. WHICH THE "JOY-C ENABLE" OF REGISTER <4200H> IS SET
  811. TO "1".
  812. ADDRESS : $4213
  813. NAME : *RDIO
  814. CONTENTS : PROGRAMMABLE I/O PORT (IN-PORT)
  815. D7-D0 I/O PORT
  816. THIS IS A PROGRAMMABLE I/O PORT (IN PORT). THE DATA WHICH IS SET
  817. TO THE IN-PORT SHOULD BE READ DIRECTLY.
  818. THE BIT WHICH "1" IS WRITTEN BY REGISTER <4201H> IS USED AS THE
  819. IN PORT.
  820. ADDRESS : $4114/$4115
  821. NAME : *RDDIVL/*RDDIVH
  822. CONTENTS : QUOTIENT OF DIVIDE RESULT
  823. D7-D0 QUOTENT-A (LOW) 4114H
  824. D7-D0 QUOTENT-A (HIGH) 4115H
  825. THIS IS A QUOTENT (A), WHICH IS A RESULT FOR ABSOLUTE DIVIDE OF
  826. "C (16-BIT) / B (8-BIT) = A (16-BIT)".
  827. DIVIDEND (C) AND DIVISOR (B) ARE SET BY REGISTERS <4204H>-<4206H>.
  828. ADDRESS : $4216/$4217
  829. NAME : *RDMPYL/*RDMPYH
  830. CONTENTS : PRODUCT OF MULTIPLICATION RESULT OR REMAINDER OF DIVIDE RESULT
  831. D7-D0 PRODUCT-C [MUL] / REMAINDER [DIV] (LOW) 4216H
  832. D7-D0 PRODUCT-C [MUL] / REMAINDER [DIV] (HIGH) 4217H
  833. (1) IN CASE OF MULTIPLICATION
  834. THIS IS A PRODUCT (C) WHICH IS A RESULT FOR ABSOLUTE
  835. MULTIPLICATION OF "A (8-BIT) * B (8-BIT) = C (16-BIT)".
  836. A MULTIPLICAND (A) AND A MULTIPLIER (B) ARE SET BY REGISTERS
  837. <4202H> & <4203H>.
  838. (2) IN CASE OF DIVIDE
  839. THIS IS THE REMAINDER, WHICH IS A RESULT FOR THE ABSOLUTE
  840. DIVIDE OF "C (16-BIT) / B (8-BIT) = A (16-BIT)".
  841. A DIVIDEND (C) AND DIVISOR (B) ARE SET BY THE REGISTERS
  842. <4204H><4205H> & <4206H>.
  843. ADDRESS : $4218/$4219/$421A/$421B/$421C/$421D/$421E/$421F
  844. NAME : JOY1L/JOY1H/JOY2L/JOY2H/JOY3L/JOY3H/JOY4L/JOY4H
  845. CONTENTS : DATA FOR JOY CONTROLLER I, II, III & IV
  846. D7 X BUTTON LOW
  847. D6 Y BUTTON
  848. D5 TL BUTTON
  849. D4 TR BUTTON
  850. D3-D0 ----
  851. D7 A BUTTON HIGH
  852. D6 B BUTTON
  853. D5 SELECT BUTTON
  854. D4 START BUTTON
  855. D3 UP
  856. D2 DOWN
  857. D1 LEFT
  858. D0 RIGHT
  859. REGISTERS <4016H><4017H> CAN BE USED THE SAME AS THE FAMILY
  860. COMPUTER.
  861. 4016H-RD
  862. D0 : DATA FOR CONTROLLER I
  863. D1 : DATA FOR CONTROLLER III
  864. 4016H-WR
  865. OUT0,OUT1,OUT2
  866. 4017H-RD
  867. D0 : DATA FOR CONTROLLER II
  868. D1 : DATA FOR CONTROLLER IV
  869. NOTE: WHETHER THE STANDARD JOY CONTROLLERS ARE CONNECTED TO THE
  870. ~~~~~ SFX OR NOT CAN BE REFFERED BY READING 17TH BIT OF <4016H>
  871. AND <4017H> (SEE PAGE 22).
  872. 0: CONNECTED
  873. 1: NOT CONNECTED
  874. ADDRESS : $43X0 (X: CHANNEL NUMBER 0-7)
  875. NAME : DMAPX
  876. CONTENTS : PARAMETER FOR DMA TRANSFER
  877. D7 TRANSFER ORIGINATION DESIGNATION (SEE APPENDIX-1)
  878. TRANSFER DIRECTION A-BUS -> B-BUS
  879. B-BUS -> A-BUS DESIGNATION
  880. 0: A-BUS -> B-BUS (CPU MEMORY -> PPU)
  881. 1: B-BUS -> A-BUS (PPU -> CPU MEMORY)
  882. D6 TYPE DESIGNATION (H-DMA ONLY)
  883. ADDRESSING MODE DESIGNATION WHEN ACCESSING THE
  884. DATA (SEE APPENDIX-2).
  885. 0: ABSOLUTE ADDRESSING
  886. 1: INDIRECT ADDRESSING
  887. D5 ---
  888. D4-D3 FIXED ADDRESS FOR A-BUS & AUTOMATIC INC./DEC. SELECT.
  889. D3 0: AUTOMATIC ADDRESS INCREMENT/DECREMENT
  890. 1: FIXED ADDRESS <TO BE USED WHEN CLEARING
  891. VRAM ETC.>
  892. D4 0: AUTOMATIC INCREMENT
  893. 1: AUTOMATIC DECREMENT (IN CASE "0" IS
  894. WRITTEN TO D3)
  895. D2-D0 DMA TRANSFER WORD SELECT
  896. GENERAL PURPOSE DMA: B-ADDRESS CHANGE METHOD
  897. D2 D1 D0 | ADDRESS TO BE WRITTEN
  898. ---------------------------------
  899. 0 0 0 | 1-ADDRESS
  900. 0 0 1 | 2-ADDRESS (VRAM ETC.) L,H
  901. 0 1 0 | 1-ADDRESS
  902. 0 1 1 | 2-ADDRESS (WRITE TWICE) L,L,H,H
  903. 1 0 0 | 4-ADDRESS L,H,L,H
  904. H-DMA: THE NUMBER OF BYTE TO BE TRANSFERED PER LINE
  905. AND WRITE METHOD DESIGNATION
  906. D2 D1 D0 | ADDRESS TO BE WRITTEN
  907. ---------------------------------
  908. 0 0 0 | 1-ADDRESS (1)
  909. 0 0 1 | 2-ADDRESS (VRAM ETC.) L,H (2)
  910. 0 1 0 | WRITE TWICE L,L (1)
  911. 0 1 1 | 2-ADDRESS/WRITE TWICE L,L,H,H(2)
  912. 1 0 0 | 4-ADDRESS L,H,L,H(4)
  913. ADDRESS : $43X1 (X: CHANNEL NUMBER 0-7)
  914. NAME : BBADX
  915. CONTENTS : B-BUS ADDRESS FOR DMA
  916. D7-D0 B-ADDRESS
  917. THIS IS A REGISTER, WHICH CAN SET THE ADDRESS OF B-BUS.
  918. WHETHER THIS IS THE ADDRESS OF THE "TRANSFER DESTINATION" OR
  919. THE ADDRESS OF THE "TRANSFER ORIGINATION" CAN BE DETERMINED BY
  920. D7 (TRANSFER ORIGINATION) OF REGISTER <4300H>.
  921. * WHEN THE H-DMA IS PERFORMED, IT WILL BE ADDRESS OF "TRANSFER
  922. DESTINATION".
  923. ADDRESS : $43X2/$43X3/$43X4 (X: CHANNEL NUMBER 0-7)
  924. NAME : A1TXL/A1TXH/A1BX
  925. CONTENTS : TABLE ADDRESS OF A-BUS FOR DMA <A1 TABLE ADDRESS>
  926. D7-D0 A1 TABLE ADDRESS (LOW) 43X2H
  927. D7-D0 A1 TABLE ADDRESS (HIGH) 43X3H
  928. D7-D0 A1 TABLE BANK 43X4H
  929. THIS IS A REGISTER, WHICH CAN SET THE ADDRESS OF A-BUS
  930. WHETHER THIS IS THE ADDRESS OF THE "TRANSFER DESTINATION" OR
  931. THE ADDRESS OF THE "TRANSFER ORIGINATION" CAN BE DETERMINED BY
  932. D7 (TRANSFER ORIGINATION) OF REGISTER <4300H>.
  933. "0" SHOULD BE WRITTEN TO D7 EXCEPT A SPECIAL CASE.
  934. IN THE H-DMA MODE, THE ADDRESS OF THE TRANSFER ORIGINATION IS
  935. DESIGNATED BY THIS ADDRESS, THE DATA (APPENDIX-2) MUST BE
  936. SET BY THE ABSOLUTE ADDRESSING MODE OR THE INDIRECT ADDRESSING
  937. MODE.
  938. THIS ADDRESS BECOMES THE BASIC ADDRESS ON THE A-BUS DURING DMA
  939. TRANSFER PERIOD, AND THE ADDRESS WILL BE INCREASED OR DECREASED
  940. BASED ON THIS ADDRESS. (WHEN THE GENERAL PURPOSE DMA IS PERFORMED
  941. IT WILL BE DECREASED.)
  942. ADDRESS : $43X5/$43X6/$43X7 (X: CHANNEL NUMBER 0-7)
  943. NAME : DASXL/DASXH/DASBX
  944. CONTENTS : DATA ADDRESS STORE BY H-DMA & NUMBER OF BYTE TO BE TRANSFERED
  945. SETTINGS BY GENERAL PURPOSE DMA
  946. D7-D0 DATA ADDRESS (LOW) H-DMA 43X5H
  947. NUMBER OF BYTES TO BE TRANSFERED (LOW) GP-DMA
  948. D7-D0 DATA ADDRESS (HIGH) H-DMA 43X6H
  949. NUMBER OF BYTES TO BE TRANSFERED (HIGH) GP-DMA
  950. D7-D0 DATA BANK 43X7H
  951. IN CASE OF H-DMA
  952. THIS IS A REGISTER WHICH THE INDIRECT ADDRESS WILL BE
  953. STORED AUTOMATICALLY IN THE INDIRECT ADDRESSING MODE.
  954. THE INDIRECT ADDRESS MEANS THE DATA ADDRESS DESCRIBED
  955. ON APPENDIX-2. IT IS NOT NECESSARY TO READ OR WRITE
  956. DIRECTLY BY THE CPU EXCEPT IN SPECIAL CASES.
  957. IN CASE OF GENERAL PURPOSE DMA
  958. THIS IS THE REGISTER, WHICH CAN SET THE NUMBER OF BYTE
  959. TO TRANSFER OR TO BE TRANSFERED. HOWEVER, THE NUMBER OF
  960. BYTE "0000H" MEANS "10000H".
  961. ADDRESS : $43X8/$43X9 (X: CHANNEL NUMBER 0-7)
  962. NAME : A2AXL/A2AXH
  963. CONTENTS : TABLE ADDRESS OF A-BUS BY DMA < A2 TABLE ADDRESS
  964. D7-D0 A2 TABLE ADDRESS (LOW) 43X8H
  965. D7-D0 A2 TABLE ADDRESS (HIGH) 43X9H
  966. THESE ARE THE ADDRESSES, WHICH ARE USED TO ACCESS THE CPU & RAM,
  967. AND IT WILL BE INCREASED AUTOMATICALLY. (SEE APPENDIX-2)
  968. THE DATA OF THESE REGISTERS ARE USED AS THE BASIC ADDRESS WHICH
  969. IS THE ADDRESSS SET BY THE "A1 TABLE ADDRESS". AFTERWARDS,
  970. BECAUSE IT WILL BE INCREASED OR DECREASED AUTOMATICALLY, IT IS
  971. NECESSARY TO SET THE ADDRESS INTO THIS REGISTER BY THE CPU
  972. DIRECTLY.
  973. FOLLOWING APPLY TO H-DMA ONLY:
  974. HOWEVER, IF THE DATA WHICH IS TRANSFERED NEED TO BE CHANGED
  975. BY FORCE, IT CAN BE DONE BY SETTING THE CPU MEMORY ADDRESS
  976. TO THIS REGISTER. AND ALSO, THE ADDRESS OF THE CPU WHICH IS
  977. ACCESSED CURRENTLY WILL BE CHANGED BY READING THIS REGISTER.
  978. ADDRESS : $43XA (X: CHANNEL NUMBER 0-7)
  979. NAME : NTRLX
  980. CONTENTS : THE NUMBER OF LINES TO BE TRANSFERED BY H-DMA›0;31;40m
  981. D7 CONTINUE
  982. D6-D0 NUMBER OF LINES TO BE TRANSFERED
  983. THIS IS A REGISTER WHICH SHOWS NUMBER OF LINES FOR H-DMA TRANSFER
  984. (SEE APPENDIX-2)
  985. THE NUMBER OF LINES WRITTEN TO THE CPU MEMORY WILL BE THE BASIC
  986. NUMBER OF LINE, IT IS NOT NECESSARY TO SET THE ADDRESS INTO
  987. THIS REGISTER DIRECTLY.