funcdesc.txt 19 KB

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  1. Functional Description
  2. The G65SC802 offers the design engineer the opportunity to utilize both
  3. existing software programs and hardware configurations, while also
  4. achieving the added advantages of increased register lengths and faster
  5. execution times. The G65SC802's "ease of use" design and implementation
  6. features provide the designer with increased flexibility and reduced
  7. implementation costs In the Emulation mode, the G65SC802 not only offers
  8. software compatibility, but is also hardware (pin-to-pin) compatible with
  9. 6502 designs plus it provides the advantages of 16-bit internal operation
  10. in 6502-compatible applications. The G65SC802 is an excellent direct
  11. replacement microprocessor for 6502 designs.
  12. The G65SC816 provides the design engineer with upward mobility and software
  13. compatibility in applications where a 16-bit system configuration is desired.
  14. The G65SC816's 16-bit hardware configuration, coupled with current software
  15. allows a wide selection of system applications. In the Emulation mode, the
  16. G65SC816 ofters many advantages, including full software compatibility with
  17. 6502 coding. In addition, the G65SC816's powerful instruction set and
  18. addressing modes make it an excellent choice for new 16-bit designs.
  19. Internal organization of the G65SC802 and G65SC816 can be divided into two
  20. parts: 1) The Register Section, and 2) The Control Section Instructions
  21. (or opcodes) obtained from program memory are executed by implementing a
  22. series of data transfers within the Register Section.
  23. Signals that cause data transfers to be executed are generated within the
  24. Control Section. Both the G65SC802 and the G65SC816 have a 16-bit internal
  25. architecture with an 8-bit external data bus.
  26. Instructlon Register and Decode
  27. An opcode enters the processor on the Data Bus, and is latched into the
  28. Instruction Register during the instruction fetch cycle. This instruction is
  29. then decoded, along with timing and interrupt signals, to generate the
  30. various Instruction Register control signals.
  31. Timing Control Unit (TCU)
  32. The Timing Control Unit keeps track of each instruction cycle as it is
  33. executed. The TCU is set to zero each time an instruction fetch is executed,
  34. and is advanced at the beginning of each cycle for as many cycles as is
  35. required to complete the instruction Each data transfer between registers
  36. depends upon decoding the contents of both the Instruction Register and
  37. the Timing Control Unit.
  38. Arithmetic and Logic Unit (ALU)
  39. All arithmetic and logic operations take place within the 16-bit ALU. In
  40. addition to data operations, the ALU also calculates the effective address
  41. for relative and indexed addressing modes. The result of a data operation
  42. is stored in either memory or an internal register. Carry, Negative, Over-
  43. flow and Zero flags may be updated following the ALU data operation.
  44. Internal Registers (Refer to Figure 2, Programming Model)
  45. Accumulator (A)
  46. The Accumulator is a general purpose register which stores one of the
  47. operands, or the result of most arithmetic and logical operations. In the
  48. Native mode (E=0), when the Accumulator Select Bit (M) equals zero, the
  49. Accumulator is established as 16 bits wide. When the Accumulator Select
  50. Bit (M) equals one, the Accumulator is 8 bits wide. In this case, the upper
  51. 8 bits (AH) may be used for temporary storage in conjunction with the
  52. Exchange AH and AL instruction.
  53. Data Bank (DB)
  54. During the Native mode (E=0), the 8-bit Data Bank Register holds the default
  55. bank address for memory transfers. The 24-bit address is composed of the
  56. 16-bit instruction effective address and the 8-bit Data Bank address. The
  57. register value is multiplexed with the data value and is present on the
  58. Data/Address lines during the first half of a data transfer memory cycle for
  59. the G65SC816. The Data Bank Register is initialized to zero during Reset.
  60. Direct (D)
  61. The 16-bit Direct Register provides an address offset for all instructions
  62. using direct addressing. The effective bank zero address is formed by adding
  63. the 8-bit instruction operand address to the Direct Register. The Direct
  64. Register is initialized to zero during Reset.
  65. Index (X and Y)
  66. There are two Index Registers (X and Y) which may be used as general purpose
  67. registers or to provide an index value for calculation of the effective
  68. address. When executing an instruction with indexed addressing, the
  69. microprocessor fetches the opcode and the base address, and then modifies the
  70. address by adding the Index Register contents to the address prior to
  71. performing the desired operation.
  72. Pre-indexing or postindexing of Indirect addresses may be selected. In the
  73. Native mode (E=0), both Index Registers are 16 bits wide (providing the Index
  74. Select Bit (X) equals zero). If the Index Select Bit (X) equals one, both
  75. registers will be 8 bits wide.
  76. Processor Status (P)
  77. The 8-bit Processor Status Register contains status flags and mode select bits.
  78. The Carry (C), Negative (N). Overflow (V), and Zero (Z) status flags serve to
  79. report the status ot most ALU operations. These status flags are tested by use
  80. of Conditional Branch instructions. The Decimal (D), IRQ Disable (I), Memory,
  81. Accumuiator (M), and Index (X) bits are used as mode select flags. These flags
  82. are set by the program to change microprocessor operations.
  83. The Emulation (E) select and the Break (B) flags are accessible only through
  84. the Processor Status Register. The Emulation mode select flag is selected by
  85. the Exchange Carry and Emulation Bits (XCE) instruction.
  86. Table 2, G65SC802 and G65SC816 Mode Comparison, illustrates the features of
  87. the Native (E=0) and Emulation (E=1) modes. The M and X flags are always equal
  88. to one in the Emulation mode. When an interrupt occurs during the Emulation
  89. mode, the Break flag is written to stack memory as bit 4 of the Processor
  90. Status Register.
  91. Program Bank (PB)
  92. The 8-bit Program Bank Register holds the bank address for all instruction
  93. fetches. The 24-bit address consists of the 16-bit instruction effective
  94. address and the 8-bit Program Bank address. The register value is multiplexed
  95. with the data value and presented on the Data/Address lines during the first
  96. half of a program memory read cycle. The Program Bank Register is initialized
  97. to zero during Reset.
  98. Program Counter (PC)
  99. The 16-bit Program Counter Register provides the addresses which are used to
  100. step the microprocessor through sequential program instructions. The register
  101. is incremented each time an instruction or operand is fetched from program
  102. memory.
  103. Stack Pointer (S)
  104. The Stack Pointer is a 16-bit register which is used to indicate the next
  105. available location in the stack memory area. It serves as the effective address
  106. in stack addressing modes as well as subroutine and interrupt processing. The
  107. Stack Pointer allows simple implementation of nested subroutines and multiple-
  108. level interrupts. During the Emulation mode, the Stack Pointer high-order byte
  109. (SH) is always equal to 01. The Bank Address is 00 for all Stack operations.
  110. Signal Description
  111. The following Signal Description applies to both the G65SC802 and the
  112. SSC816 except as otherwise noted.
  113. Abort (/ABORT) -- G65SC816
  114. The Abort input prevents modification of any internal registers during
  115. execution of the current instruction. Upon completion of this instruction,
  116. an interrupt sequence is initiated. The location of the aborted opcode is
  117. stored as the return address in Stack memory. The Abort vector address is
  118. 00FFF8, 9 (Emulation mode) or 00FFE8, 9 (Native mode). Abort is asserted
  119. whenever there is a low level on the Abort input. and the Phi2 clock is high.
  120. The Abort internal latch is cleared during the second cycle of the interrupt
  121. sequence. This signal may be used to handle out-of-bounds memory references
  122. in virtual memory systems.
  123. Address Bus (A0-A15)
  124. These sixteen output lines form the Address Bus for memory and I/O exchange on
  125. the Data Bus. When using the G65SC816, the address lines may be set to the
  126. high impedance state by the Bus Enable (BE) signal.
  127. Bus Enable (BE)
  128. The Bus Enable input signal allows external control of the Address and Data
  129. Buffers, as well as the R/W signal With Bus Enable high, the R/W and Address
  130. Buffers are active. The Data/Address Buffers are active during the first half
  131. of every cycle and the second half of a write cycle. When BE is low, these
  132. buffers are disabled. Bus Enable is an asynchronous signal.
  133. Data Bus (D0-D7) -- G65SC802
  134. The eight Data Bus lines provide an 8-bit bidirectional Data Bus for use
  135. during data exchanges between the microprocessor and external memory or
  136. peripherals. Two memory cycles are required for the transfer of 16-bit values.
  137. Data/Address Bus (D0/BA0-D7/BA7) -- G65SC816
  138. These eight lines multiplex bits BAO-BA7 with the data value. The Bank Address
  139. is present during the first half of a memory cycle, and the data value is read
  140. or written during the second half of the memory cycle.
  141. The Bank address external transparent latch should be latched when the Phi2
  142. clock is high or RDY is low. Two memory cycles are required to transfer 16-bit
  143. values. These lines may be set to the high impedance state by the Bus Enable
  144. (BE) signal.
  145. Emulation Status (E) -- G65SC816 (Also Applies to G65SC802, 44-Pin Version)
  146. The Emulation Status output reflects the state of the Emulation (E) mode flag
  147. in the Processor Status (P) Register. This signal may be thought of an opcode
  148. extension and used for memory and system management.
  149. Interrupt Request (/IRQ)
  150. The Interrupt Request input signal is used to request that an interrupt
  151. sequence be initiated. When the IRQ Disable (I) flag is cleared, a low input
  152. logic level initiates an interrupt sequence after the current instruction is
  153. completed. The Wait for Interrupt (WAI) instruction may be executed to ensure
  154. the interrupt will be recognized immediately. The Interrupt Request vector
  155. address is 00FFFE,F (Emulation mode) or 00FFEE,F (Native mode). Since IRQ is a
  156. level-sensitive input, an interrupt will occur if the interrupt source was not
  157. cleared since the last interrupt.
  158. Also, no interrupt will occur if the interrupt source is cleared prior to
  159. interrupt recognition.
  160. Memory Lock (/ML) -- G65SC816 (Also Applies to G65SC802, 44-Pin Version)
  161. The Memory Lock output may be used to ensure the integrity of Read-Modify-Write
  162. instructions in a multiprocessor system. Memory Lock indicates the need to
  163. defer arbitration of the next bus cycle. Memory Lock is low during the last
  164. three or five cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory
  165. referencing instructions, depending the state of the M flag.
  166. Memory/Index Select Status (M/X) -- G65SC816
  167. This multiplexed output reflects the state ot the Accumulator (M) and index (X)
  168. select flags (bits 5 and 4 of the Processor Status (P) Register).
  169. Flag M is valid during the Phi2 clock positive transition. Instructions PLP,
  170. REP, RTI and SEP may change the state of these bits. Note that the M/X output
  171. may be invalid in the cycle following a change in the M or X bits. These bits
  172. may be thought of as opcode extensions and may be used for memory and system
  173. management.
  174. Non-Maskable Interrupt (/NMI)
  175. A high-to-low transition initiates an intenupt sequence after the current
  176. instruction is completed. The Wait for Interrupt (WAI) instruction may be
  177. executed to ensure that the interrupt will be recognized immediately. The
  178. Non-Maskable Interrupt vector address is 00FFFA,B (Emulation mode) or 00FFEA,B
  179. (Native mode). Since NMI is an edge-sensitive Input, an interrupt will occur
  180. if there is a negative transition while servicing a previous interrupt. Also,
  181. no interrupt will occur if NMI remains low.
  182. Phase 1 Out (Phi1 (OUT)) -- G65SC802
  183. This inverted clock output signal provides timing for external read and write
  184. operations. Executing the Stop (STP) instruction holds this clock in the low
  185. state.
  186. Phase 2 In (Phi2 (IN))
  187. This is the system clock input to the microprocessor internal clock generator
  188. (equivalent to Phi0 (IN) on the 6502). During the low power Standby Mode, Phi2
  189. (IN) should be held in the high state to preserve the contents of internal
  190. registers.
  191. Phase 2 Out (Phi2 (OUT)) -- G65SC802
  192. This clock output signal provides timing for external read and write
  193. operations. Addresses are valid (after the Address Setup Time (TADS))
  194. following the negative transition of Phase 2 Out. Executing the Stop (STP)
  195. instruction holds Phase 2 Out in the High state.
  196. Read/Write (R/W)
  197. When the R/W output signal is in the high state, the microprocessor is reading
  198. data from memory or I/O. When in the low state, the Data Bus contains valid
  199. data from the microprocessor which is to be stored at the addressed memory
  200. location. When using the G65SC816, the R/W signal may be set to the high
  201. impedance state by Bus Enable (BE).
  202. Ready (RDY)
  203. This bidirectional signal indicates that a Wait for Interrupt (WAI) instruction
  204. has been executed allowing the user to halt operation of the microprocessor.
  205. A low input logic level will halt the microprocessor in its current state (note
  206. that when in the Emulation mode, the G65SC802 stops only during a read cycle).
  207. Returning RDY to the active high state allows the microprocessor to continue
  208. following the next Phase 2 In Clock negative transition. The RDY signal is
  209. internally pulled low following the execution of a Wait for Interrupt (WAI)
  210. instruction, and then returned to the high state when a /RES, /ABORT, /NMI, or
  211. /IRQ external interrupt is provided. This feature may be used to eliminate
  212. interrupt latency by placing the WAI instruction at the beginning of the IRQ
  213. servicing routine. If the IRQ Disable flag has been set, the next instruction
  214. will be executed when the IRQ occurs. The processor will not stop after a WAI
  215. instruction if RDY has been forced to a high state. The Stop (STP) instruction
  216. has no effect on RDY.
  217. Reset (/RES)
  218. The Reset input is used to initialize the microprocessor and start program
  219. execution. The Reset input buffer has hysteresis such that a simple R-C timing
  220. circuit may be used with the internal pullup device. The /RES signal must be
  221. held low for at least two clock cycles after VDD reaches operating voltage.
  222. Ready (RDY) has no effect while RES is being held low. During this Reset
  223. conditioning period, the following processor initialization takes place:
  224. Registers
  225. D = 0000 SH = 01
  226. DB = 00 XH = 00
  227. PB = 00 YH = 00
  228. N V M X D I Z C/E
  229. P = * * 1 1 0 1 * */1
  230. * = Not Initialized
  231. STP and WAI instructions are cleared.
  232. Signals
  233. E = 1 VDA = 0
  234. M/X = 1 /VP = 1
  235. R/W = 1 VPA = 0
  236. SYNC = 0
  237. When Reset is brought high, an interrupt sequence is initiated:
  238. * R/W remains in the high state during the stack address cycles.
  239. * The Reset vector address is 00FFFC,D.
  240. Set Overtlow (/SO) -- G65SC802
  241. A negative transition on this input sets the Overflow (V) flag, bit 6 of the
  242. Processor Status (P) Register.
  243. Synchronlze (SYNC) -- G65SC802
  244. The SYNC output is provided to identify those cycles during which the
  245. microprocessor is fetching an opcode. The SYNC signal is high during an opcode
  246. fetch cycle, and when combined with Ready (RDY), can be used for single
  247. instruction execution.
  248. Valid Data Address (VDA) and
  249. Valid Program Address (VPA) -- G65SC816
  250. These two output signals indicate the type of memory being accessed by
  251. the address bus. The following coding applies:
  252. VDA VPA
  253. 0 0 Internal Operation -- Address and Data Bus available. Address
  254. outputs may be invalid due to low byte additions only.
  255. 0 1 Valid program address -- may be used for program cache control.
  256. 1 0 Valid data address -- may be used for data cache control.
  257. 1 1 Opcode fetch -- may be used for program cache control
  258. and single step control.
  259. VDD and Vss
  260. VDD Vss the positive supply voltage and Vss is system ground. When
  261. using only one ground on the G65SC802 DIP package, pin 21 preferred.
  262. Vector Pull (VP) -- G65SC816 (Also Applies to G65SC802 44-Pin Version)
  263. The Vector Pull output indicates that a vector location is being addressed
  264. during an interrupt sequence. /VP is low during the last two interrupt sequence
  265. cycles, during which time the processor reads the interrupt vector. The /VP
  266. signal may be used to select and prioritize interrupts from several sources by
  267. modifying the vector addresses.
  268. --------------------------------------------------------------------------
  269. 8 bits 8 bits 8 bits
  270. DB DB Data Bank Register
  271. XH XL Index Register (X)
  272. YH YL Index Register (Y)
  273. 00 SH SL Stack Pointer (S)
  274. AH AL Accumulator (A)
  275. PB PCH PCL Program Counter (PC)
  276. Program Bank Register (PB)
  277. 00 DH DL Direct Register (D)
  278. L = Low, H = High
  279. Processor Status Register (P)
  280. ____________________________
  281. | 1 B E |
  282. |__________________________|
  283. | N V M X D I Z C |
  284. |__________________________|
  285. 1 Always 1 if E=1
  286. B Break 0 on Stack after interupt if E=1
  287. E Emulation Bit 0= Native mode, 1= 6502 emulation
  288. N Negative 1= Negative
  289. V Overflow 1= True
  290. M Memory/Acc. Select 1= 8 bit, 0= 16 bit
  291. X Index Register Select 1= 8 bit, 0= 16 bit
  292. D Decimal mode 1= Decimal Mode
  293. I IRQ Disable 1= Disable
  294. Z Zero 1= Result Zero
  295. C Carry 1= True
  296. Figure 2. Programming model
  297. --------------------------------------------------------------------------
  298. Table 1. G65SC802 and G65SC816 Compability
  299. Function G65SC802/816 G65SC02 NMOS 6502
  300. Emulation
  301. Decimal Mode:
  302. * After Interrupts 0 -> D 0 -> D Not initialized
  303. * N, Z Flags Valid Valid Undefined
  304. * ADC, SBC No added cycle Add 1 cycle No added cycle
  305. Read-Modify-Write:
  306. * Absolute Indexed, No Page Crossing
  307. 7 cycles 6 cycles 7 cycles
  308. * Write Last 2 cycles Last cycle Last 2 cycles
  309. * Memory Lock Last 3 cycles Last 2 cycles Not available
  310. Jump Indirect:
  311. * Cycles 5 cycles 6 cycles 5 cycles
  312. * Jump Address, operand = xxFF Correct Correct Invalid
  313. Branch or Index Across Page Boundary
  314. Read last Read last Read invalid
  315. program byte program byte address
  316. 0 -> RDY During Write G65SC802: Ignored Processor Ignored until
  317. until read stops read
  318. G65SC816: Processor
  319. stops
  320. Write During Reset No Yes No
  321. Unused Opcodes No operation No operation Undefined
  322. Phi1 (OUT), Phi2 (OUT), /SO, SYNC Signals
  323. Available with Available Available
  324. G65SC802 only
  325. RDY Signal Bidirectional Input Input
  326. --------------------------------------------------------------------------
  327. Table 2. G65SC802 and G65SC816 Mode Comparison
  328. Function Emulation (E = 1) Native (E = 0)
  329. Stack Pointer (S) 8 bits in page 1 16 bits
  330. Direct Index Address Wrap within page Crosses page boundary
  331. Processor Status (P):
  332. * Bit 4 Always one, except zero X flag (8/16-bit Index)
  333. in stack after hardware
  334. interrupt
  335. * Bit 5 Always one M flag (8/16-bit Accumulator)
  336. Branch Across Page Boundary
  337. 4 cycles 3 cycles
  338. Vector Locations:
  339. ABORT 00FFF8,9 00FFF8,9
  340. BRK 00FFFE,F 00FFF6,7
  341. COP 00FFF4,5 00FFF4,5
  342. IRQ 00FFFE,F 00FFFE,F
  343. NMI 00FFFA,B 00FFFA,B
  344. RES 00FFFC,D 00FFFC,D (1 -> E)
  345. Program Bank (PB) During Interrupt, RTI
  346. Not pushed, pulled Pushed and pulled
  347. 0 -> RDY During Write
  348. G65SC802: Ignored until read Processor stops
  349. G65SC816: Processor stops
  350. Write During Read-Modify-Write
  351. Last 2 cycles Last 1 or 2 cycles depending
  352. on M flag