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- Functional Description
- The G65SC802 offers the design engineer the opportunity to utilize both
- existing software programs and hardware configurations, while also
- achieving the added advantages of increased register lengths and faster
- execution times. The G65SC802's "ease of use" design and implementation
- features provide the designer with increased flexibility and reduced
- implementation costs In the Emulation mode, the G65SC802 not only offers
- software compatibility, but is also hardware (pin-to-pin) compatible with
- 6502 designs plus it provides the advantages of 16-bit internal operation
- in 6502-compatible applications. The G65SC802 is an excellent direct
- replacement microprocessor for 6502 designs.
- The G65SC816 provides the design engineer with upward mobility and software
- compatibility in applications where a 16-bit system configuration is desired.
- The G65SC816's 16-bit hardware configuration, coupled with current software
- allows a wide selection of system applications. In the Emulation mode, the
- G65SC816 ofters many advantages, including full software compatibility with
- 6502 coding. In addition, the G65SC816's powerful instruction set and
- addressing modes make it an excellent choice for new 16-bit designs.
- Internal organization of the G65SC802 and G65SC816 can be divided into two
- parts: 1) The Register Section, and 2) The Control Section Instructions
- (or opcodes) obtained from program memory are executed by implementing a
- series of data transfers within the Register Section.
- Signals that cause data transfers to be executed are generated within the
- Control Section. Both the G65SC802 and the G65SC816 have a 16-bit internal
- architecture with an 8-bit external data bus.
- Instructlon Register and Decode
- An opcode enters the processor on the Data Bus, and is latched into the
- Instruction Register during the instruction fetch cycle. This instruction is
- then decoded, along with timing and interrupt signals, to generate the
- various Instruction Register control signals.
- Timing Control Unit (TCU)
- The Timing Control Unit keeps track of each instruction cycle as it is
- executed. The TCU is set to zero each time an instruction fetch is executed,
- and is advanced at the beginning of each cycle for as many cycles as is
- required to complete the instruction Each data transfer between registers
- depends upon decoding the contents of both the Instruction Register and
- the Timing Control Unit.
- Arithmetic and Logic Unit (ALU)
- All arithmetic and logic operations take place within the 16-bit ALU. In
- addition to data operations, the ALU also calculates the effective address
- for relative and indexed addressing modes. The result of a data operation
- is stored in either memory or an internal register. Carry, Negative, Over-
- flow and Zero flags may be updated following the ALU data operation.
- Internal Registers (Refer to Figure 2, Programming Model)
- Accumulator (A)
- The Accumulator is a general purpose register which stores one of the
- operands, or the result of most arithmetic and logical operations. In the
- Native mode (E=0), when the Accumulator Select Bit (M) equals zero, the
- Accumulator is established as 16 bits wide. When the Accumulator Select
- Bit (M) equals one, the Accumulator is 8 bits wide. In this case, the upper
- 8 bits (AH) may be used for temporary storage in conjunction with the
- Exchange AH and AL instruction.
- Data Bank (DB)
- During the Native mode (E=0), the 8-bit Data Bank Register holds the default
- bank address for memory transfers. The 24-bit address is composed of the
- 16-bit instruction effective address and the 8-bit Data Bank address. The
- register value is multiplexed with the data value and is present on the
- Data/Address lines during the first half of a data transfer memory cycle for
- the G65SC816. The Data Bank Register is initialized to zero during Reset.
- Direct (D)
- The 16-bit Direct Register provides an address offset for all instructions
- using direct addressing. The effective bank zero address is formed by adding
- the 8-bit instruction operand address to the Direct Register. The Direct
- Register is initialized to zero during Reset.
- Index (X and Y)
- There are two Index Registers (X and Y) which may be used as general purpose
- registers or to provide an index value for calculation of the effective
- address. When executing an instruction with indexed addressing, the
- microprocessor fetches the opcode and the base address, and then modifies the
- address by adding the Index Register contents to the address prior to
- performing the desired operation.
- Pre-indexing or postindexing of Indirect addresses may be selected. In the
- Native mode (E=0), both Index Registers are 16 bits wide (providing the Index
- Select Bit (X) equals zero). If the Index Select Bit (X) equals one, both
- registers will be 8 bits wide.
- Processor Status (P)
- The 8-bit Processor Status Register contains status flags and mode select bits.
- The Carry (C), Negative (N). Overflow (V), and Zero (Z) status flags serve to
- report the status ot most ALU operations. These status flags are tested by use
- of Conditional Branch instructions. The Decimal (D), IRQ Disable (I), Memory,
- Accumuiator (M), and Index (X) bits are used as mode select flags. These flags
- are set by the program to change microprocessor operations.
- The Emulation (E) select and the Break (B) flags are accessible only through
- the Processor Status Register. The Emulation mode select flag is selected by
- the Exchange Carry and Emulation Bits (XCE) instruction.
- Table 2, G65SC802 and G65SC816 Mode Comparison, illustrates the features of
- the Native (E=0) and Emulation (E=1) modes. The M and X flags are always equal
- to one in the Emulation mode. When an interrupt occurs during the Emulation
- mode, the Break flag is written to stack memory as bit 4 of the Processor
- Status Register.
- Program Bank (PB)
- The 8-bit Program Bank Register holds the bank address for all instruction
- fetches. The 24-bit address consists of the 16-bit instruction effective
- address and the 8-bit Program Bank address. The register value is multiplexed
- with the data value and presented on the Data/Address lines during the first
- half of a program memory read cycle. The Program Bank Register is initialized
- to zero during Reset.
- Program Counter (PC)
- The 16-bit Program Counter Register provides the addresses which are used to
- step the microprocessor through sequential program instructions. The register
- is incremented each time an instruction or operand is fetched from program
- memory.
- Stack Pointer (S)
- The Stack Pointer is a 16-bit register which is used to indicate the next
- available location in the stack memory area. It serves as the effective address
- in stack addressing modes as well as subroutine and interrupt processing. The
- Stack Pointer allows simple implementation of nested subroutines and multiple-
- level interrupts. During the Emulation mode, the Stack Pointer high-order byte
- (SH) is always equal to 01. The Bank Address is 00 for all Stack operations.
- Signal Description
- The following Signal Description applies to both the G65SC802 and the
- SSC816 except as otherwise noted.
- Abort (/ABORT) -- G65SC816
- The Abort input prevents modification of any internal registers during
- execution of the current instruction. Upon completion of this instruction,
- an interrupt sequence is initiated. The location of the aborted opcode is
- stored as the return address in Stack memory. The Abort vector address is
- 00FFF8, 9 (Emulation mode) or 00FFE8, 9 (Native mode). Abort is asserted
- whenever there is a low level on the Abort input. and the Phi2 clock is high.
- The Abort internal latch is cleared during the second cycle of the interrupt
- sequence. This signal may be used to handle out-of-bounds memory references
- in virtual memory systems.
- Address Bus (A0-A15)
- These sixteen output lines form the Address Bus for memory and I/O exchange on
- the Data Bus. When using the G65SC816, the address lines may be set to the
- high impedance state by the Bus Enable (BE) signal.
- Bus Enable (BE)
- The Bus Enable input signal allows external control of the Address and Data
- Buffers, as well as the R/W signal With Bus Enable high, the R/W and Address
- Buffers are active. The Data/Address Buffers are active during the first half
- of every cycle and the second half of a write cycle. When BE is low, these
- buffers are disabled. Bus Enable is an asynchronous signal.
- Data Bus (D0-D7) -- G65SC802
- The eight Data Bus lines provide an 8-bit bidirectional Data Bus for use
- during data exchanges between the microprocessor and external memory or
- peripherals. Two memory cycles are required for the transfer of 16-bit values.
- Data/Address Bus (D0/BA0-D7/BA7) -- G65SC816
- These eight lines multiplex bits BAO-BA7 with the data value. The Bank Address
- is present during the first half of a memory cycle, and the data value is read
- or written during the second half of the memory cycle.
- The Bank address external transparent latch should be latched when the Phi2
- clock is high or RDY is low. Two memory cycles are required to transfer 16-bit
- values. These lines may be set to the high impedance state by the Bus Enable
- (BE) signal.
- Emulation Status (E) -- G65SC816 (Also Applies to G65SC802, 44-Pin Version)
- The Emulation Status output reflects the state of the Emulation (E) mode flag
- in the Processor Status (P) Register. This signal may be thought of an opcode
- extension and used for memory and system management.
- Interrupt Request (/IRQ)
- The Interrupt Request input signal is used to request that an interrupt
- sequence be initiated. When the IRQ Disable (I) flag is cleared, a low input
- logic level initiates an interrupt sequence after the current instruction is
- completed. The Wait for Interrupt (WAI) instruction may be executed to ensure
- the interrupt will be recognized immediately. The Interrupt Request vector
- address is 00FFFE,F (Emulation mode) or 00FFEE,F (Native mode). Since IRQ is a
- level-sensitive input, an interrupt will occur if the interrupt source was not
- cleared since the last interrupt.
- Also, no interrupt will occur if the interrupt source is cleared prior to
- interrupt recognition.
- Memory Lock (/ML) -- G65SC816 (Also Applies to G65SC802, 44-Pin Version)
- The Memory Lock output may be used to ensure the integrity of Read-Modify-Write
- instructions in a multiprocessor system. Memory Lock indicates the need to
- defer arbitration of the next bus cycle. Memory Lock is low during the last
- three or five cycles of ASL, DEC, INC, LSR, ROL, ROR, TRB, and TSB memory
- referencing instructions, depending the state of the M flag.
- Memory/Index Select Status (M/X) -- G65SC816
- This multiplexed output reflects the state ot the Accumulator (M) and index (X)
- select flags (bits 5 and 4 of the Processor Status (P) Register).
- Flag M is valid during the Phi2 clock positive transition. Instructions PLP,
- REP, RTI and SEP may change the state of these bits. Note that the M/X output
- may be invalid in the cycle following a change in the M or X bits. These bits
- may be thought of as opcode extensions and may be used for memory and system
- management.
- Non-Maskable Interrupt (/NMI)
- A high-to-low transition initiates an intenupt sequence after the current
- instruction is completed. The Wait for Interrupt (WAI) instruction may be
- executed to ensure that the interrupt will be recognized immediately. The
- Non-Maskable Interrupt vector address is 00FFFA,B (Emulation mode) or 00FFEA,B
- (Native mode). Since NMI is an edge-sensitive Input, an interrupt will occur
- if there is a negative transition while servicing a previous interrupt. Also,
- no interrupt will occur if NMI remains low.
- Phase 1 Out (Phi1 (OUT)) -- G65SC802
- This inverted clock output signal provides timing for external read and write
- operations. Executing the Stop (STP) instruction holds this clock in the low
- state.
- Phase 2 In (Phi2 (IN))
- This is the system clock input to the microprocessor internal clock generator
- (equivalent to Phi0 (IN) on the 6502). During the low power Standby Mode, Phi2
- (IN) should be held in the high state to preserve the contents of internal
- registers.
- Phase 2 Out (Phi2 (OUT)) -- G65SC802
- This clock output signal provides timing for external read and write
- operations. Addresses are valid (after the Address Setup Time (TADS))
- following the negative transition of Phase 2 Out. Executing the Stop (STP)
- instruction holds Phase 2 Out in the High state.
- Read/Write (R/W)
- When the R/W output signal is in the high state, the microprocessor is reading
- data from memory or I/O. When in the low state, the Data Bus contains valid
- data from the microprocessor which is to be stored at the addressed memory
- location. When using the G65SC816, the R/W signal may be set to the high
- impedance state by Bus Enable (BE).
- Ready (RDY)
- This bidirectional signal indicates that a Wait for Interrupt (WAI) instruction
- has been executed allowing the user to halt operation of the microprocessor.
- A low input logic level will halt the microprocessor in its current state (note
- that when in the Emulation mode, the G65SC802 stops only during a read cycle).
- Returning RDY to the active high state allows the microprocessor to continue
- following the next Phase 2 In Clock negative transition. The RDY signal is
- internally pulled low following the execution of a Wait for Interrupt (WAI)
- instruction, and then returned to the high state when a /RES, /ABORT, /NMI, or
- /IRQ external interrupt is provided. This feature may be used to eliminate
- interrupt latency by placing the WAI instruction at the beginning of the IRQ
- servicing routine. If the IRQ Disable flag has been set, the next instruction
- will be executed when the IRQ occurs. The processor will not stop after a WAI
- instruction if RDY has been forced to a high state. The Stop (STP) instruction
- has no effect on RDY.
- Reset (/RES)
- The Reset input is used to initialize the microprocessor and start program
- execution. The Reset input buffer has hysteresis such that a simple R-C timing
- circuit may be used with the internal pullup device. The /RES signal must be
- held low for at least two clock cycles after VDD reaches operating voltage.
- Ready (RDY) has no effect while RES is being held low. During this Reset
- conditioning period, the following processor initialization takes place:
- Registers
- D = 0000 SH = 01
- DB = 00 XH = 00
- PB = 00 YH = 00
- N V M X D I Z C/E
- P = * * 1 1 0 1 * */1
- * = Not Initialized
- STP and WAI instructions are cleared.
- Signals
- E = 1 VDA = 0
- M/X = 1 /VP = 1
- R/W = 1 VPA = 0
- SYNC = 0
- When Reset is brought high, an interrupt sequence is initiated:
- * R/W remains in the high state during the stack address cycles.
- * The Reset vector address is 00FFFC,D.
- Set Overtlow (/SO) -- G65SC802
- A negative transition on this input sets the Overflow (V) flag, bit 6 of the
- Processor Status (P) Register.
- Synchronlze (SYNC) -- G65SC802
- The SYNC output is provided to identify those cycles during which the
- microprocessor is fetching an opcode. The SYNC signal is high during an opcode
- fetch cycle, and when combined with Ready (RDY), can be used for single
- instruction execution.
- Valid Data Address (VDA) and
- Valid Program Address (VPA) -- G65SC816
- These two output signals indicate the type of memory being accessed by
- the address bus. The following coding applies:
- VDA VPA
- 0 0 Internal Operation -- Address and Data Bus available. Address
- outputs may be invalid due to low byte additions only.
- 0 1 Valid program address -- may be used for program cache control.
- 1 0 Valid data address -- may be used for data cache control.
- 1 1 Opcode fetch -- may be used for program cache control
- and single step control.
- VDD and Vss
- VDD Vss the positive supply voltage and Vss is system ground. When
- using only one ground on the G65SC802 DIP package, pin 21 preferred.
- Vector Pull (VP) -- G65SC816 (Also Applies to G65SC802 44-Pin Version)
- The Vector Pull output indicates that a vector location is being addressed
- during an interrupt sequence. /VP is low during the last two interrupt sequence
- cycles, during which time the processor reads the interrupt vector. The /VP
- signal may be used to select and prioritize interrupts from several sources by
- modifying the vector addresses.
- --------------------------------------------------------------------------
- 8 bits 8 bits 8 bits
- DB DB Data Bank Register
- XH XL Index Register (X)
- YH YL Index Register (Y)
- 00 SH SL Stack Pointer (S)
- AH AL Accumulator (A)
- PB PCH PCL Program Counter (PC)
- Program Bank Register (PB)
- 00 DH DL Direct Register (D)
- L = Low, H = High
- Processor Status Register (P)
- ____________________________
- | 1 B E |
- |__________________________|
- | N V M X D I Z C |
- |__________________________|
- 1 Always 1 if E=1
- B Break 0 on Stack after interupt if E=1
- E Emulation Bit 0= Native mode, 1= 6502 emulation
- N Negative 1= Negative
- V Overflow 1= True
- M Memory/Acc. Select 1= 8 bit, 0= 16 bit
- X Index Register Select 1= 8 bit, 0= 16 bit
- D Decimal mode 1= Decimal Mode
- I IRQ Disable 1= Disable
- Z Zero 1= Result Zero
- C Carry 1= True
- Figure 2. Programming model
- --------------------------------------------------------------------------
- Table 1. G65SC802 and G65SC816 Compability
- Function G65SC802/816 G65SC02 NMOS 6502
- Emulation
- Decimal Mode:
- * After Interrupts 0 -> D 0 -> D Not initialized
- * N, Z Flags Valid Valid Undefined
- * ADC, SBC No added cycle Add 1 cycle No added cycle
- Read-Modify-Write:
- * Absolute Indexed, No Page Crossing
- 7 cycles 6 cycles 7 cycles
- * Write Last 2 cycles Last cycle Last 2 cycles
- * Memory Lock Last 3 cycles Last 2 cycles Not available
- Jump Indirect:
- * Cycles 5 cycles 6 cycles 5 cycles
- * Jump Address, operand = xxFF Correct Correct Invalid
- Branch or Index Across Page Boundary
- Read last Read last Read invalid
- program byte program byte address
- 0 -> RDY During Write G65SC802: Ignored Processor Ignored until
- until read stops read
- G65SC816: Processor
- stops
- Write During Reset No Yes No
- Unused Opcodes No operation No operation Undefined
- Phi1 (OUT), Phi2 (OUT), /SO, SYNC Signals
- Available with Available Available
- G65SC802 only
- RDY Signal Bidirectional Input Input
- --------------------------------------------------------------------------
- Table 2. G65SC802 and G65SC816 Mode Comparison
- Function Emulation (E = 1) Native (E = 0)
- Stack Pointer (S) 8 bits in page 1 16 bits
- Direct Index Address Wrap within page Crosses page boundary
- Processor Status (P):
- * Bit 4 Always one, except zero X flag (8/16-bit Index)
- in stack after hardware
- interrupt
- * Bit 5 Always one M flag (8/16-bit Accumulator)
- Branch Across Page Boundary
- 4 cycles 3 cycles
- Vector Locations:
- ABORT 00FFF8,9 00FFF8,9
- BRK 00FFFE,F 00FFF6,7
- COP 00FFF4,5 00FFF4,5
- IRQ 00FFFE,F 00FFFE,F
- NMI 00FFFA,B 00FFFA,B
- RES 00FFFC,D 00FFFC,D (1 -> E)
- Program Bank (PB) During Interrupt, RTI
- Not pushed, pulled Pushed and pulled
- 0 -> RDY During Write
- G65SC802: Ignored until read Processor stops
- G65SC816: Processor stops
- Write During Read-Modify-Write
- Last 2 cycles Last 1 or 2 cycles depending
- on M flag
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