detailop.txt 19 KB

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  1. Table 9. Detailed Instruction Operation
  2. ADDRESS MODE
  3. CYCLE /VP /ML VDA VPA ADDRESS BUS DATA BUS R/W
  4. 1 Immediate -- #
  5. (LDY,CPY,CPX,LDX,ORA,AND,EOR,ADC,BIT,LDA,CMP,SBC,REP,SEP)
  6. (14 Op Codes)
  7. (2 and 3 bytes)
  8. (2 and 3 cycles)
  9. 1 1 1 1 1 PBR,PC Op Code 1
  10. 2 1 1 0 1 PBR,PC+1 IDL 1
  11. 2a 1 1 0 1 PBR,PC+2 IDH 1
  12. 2a Absolute -- a
  13. (BIT,STY,STZ,LDY,CPY,CPX,STX,LDX,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  14. (16 Op Codes)
  15. (3 bytes)
  16. (4 and 5 cycles)
  17. 1 1 1 1 1 PBR,PC Op Code 1
  18. 2 1 1 0 1 PBR,PC+1 AAL 1
  19. 3 1 1 0 1 PBR,PC+2 AAH 1
  20. 4 1 1 1 0 DBR,AA Data Low 1/0
  21. (1) 4a 1 1 1 0 DBR,AA+1 Data High 1/0
  22. 2b Absolute (R-M-W) -- a
  23. (ASL,ROL,LSR,ROR,DEC,INC,TSB,TRB)
  24. (8 Op Codes)
  25. (3 bytes)
  26. (6 and 8 cycles)
  27. 1 1 1 1 1 PBA,PC Op Code 1
  28. 2 1 1 0 1 PBR,PC+1 AAL 1
  29. 3 1 1 0 1 PBR,PC+2 AAH 1
  30. 4 1 0 1 0 DBR,AA Data Low 1
  31. (1) 4a 1 0 1 0 DBR,AA+1 Data High 1
  32. (3) 5 1 0 0 0 DBR,AA+2 IO 1
  33. (1) 6a 1 0 1 0 DBR,AA+3 Data Hiqh 0
  34. 6 1 0 1 0 DBR,AA Data Low 0
  35. 2c Absolute(JUMP) -- a
  36. (JMP)(4C)
  37. (1 Op Code)
  38. (3 bytes)
  39. (3 cycles)
  40. 1 1 1 1 1 PBR,PC Op Code 1
  41. 2 1 1 0 1 PBR,PC+1 NEW PCL 1
  42. 3 1 1 0 1 PBR,PC+2 NEW PCH 1
  43. 1 1 1 1 1 PBR,NEWPC New Op Code 1
  44. 2d Absolute (Jump to subroutine) -- a
  45. (JSR)
  46. (1 Op Code)
  47. (3 bytes)
  48. (6 cycles)
  49. (different order from N6502)
  50. 1 1 1 1 1 PBR,PC Op Code 1
  51. 2 1 1 0 1 PBA,PC+1 NEW FCC 1
  52. 3 1 1 0 1 PBR,PC+2 NEW PCH 1
  53. 4 1 1 0 0 PBR,PC+2 IO 1
  54. 5 1 1 1 0 0,S PCH 0
  55. 6 1 1 1 0 0,S-1 PCL 0
  56. 1 1 1 1 1 PBA,NEWPC New Op Code 1
  57. 3a Absolute Long -- al
  58. (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  59. (8 Op Codes)
  60. (4 bytes)
  61. (5 and 6 cycles)
  62. 1 1 1 1 1 PBR,PC Op Code 1
  63. 2 1 1 0 1 PBR,PC+1 AAL 1
  64. 3 1 1 0 1 PBR,PC+2 AAH 1
  65. 4 1 1 0 1 PBR,PC+3 AAB 1
  66. 5 1 1 1 0 AAB,AA Data Low 1/0
  67. (1) 5a 1 1 1 0 AAB,AA+1 Data High 1/0
  68. 3b Absolute Long (JUMP) -- al
  69. (JMP)
  70. (1 Op Code)
  71. (4 bytes)
  72. (4 cycles)
  73. 1 1 1 1 1 PBR,PC Op Code 1
  74. 2 1 1 0 1 PBR,PC+1 NEW PCL 1
  75. 3 1 1 0 1 PBR,PC+2 NEW PCH 1
  76. 4 1 1 0 1 PBR,PC+3 NEW BR 1
  77. 1 1 1 1 1 NEW PBR,PC New Op Code 1
  78. 3c Absolute Long (Jump to Subroutine Long) -- al
  79. (JSL)
  80. (1 Op Code)
  81. (4 bytes)
  82. (7 cycles)
  83. 1 1 1 1 1 PBR,PC Op Code 1
  84. 2 1 1 0 1 PBR,PC+1 NEW PCL 1
  85. 3 1 1 0 1 PBR,PC+2 NEW PCH 1
  86. 4 1 1 1 0 0,S PBR 0
  87. 5 1 1 0 0 0,S IO 1
  88. 6 1 1 0 1 PBR,PC+3 NEW PBR 1
  89. 7 1 1 1 0 0,S-1 PCH 0
  90. 8 1 1 1 0 0,S-2 FCL 0
  91. 1 1 1 1 1 NEW PBR,PC New Op Code 1
  92. 4a Direct -- d
  93. (BIT,STZ,STY,LDY,CPY,CPX,STX,LDX,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  94. (16 Op Codes)
  95. (2 bytes)
  96. (3,4 and 5 cycles)
  97. 1 1 1 1 1 PBR,PC Op Code 1
  98. 2 1 1 0 1 PBR,PC+1 DO 1
  99. (2) 2a 1 1 0 0 PBR,PC+2 IO 1
  100. 3 1 1 1 0 0,D+DO Data Low 1/0
  101. (1) 3a 1 1 1 0 0,D+DO+1 Data High 1/0
  102. 4b Direct (R-M-W) -- d
  103. (ASL,ROL,LSR,ROR,DEC,INC,TSB,TRB)
  104. (8 Op Codes)
  105. (2 bytes)
  106. (5,6,7 and 8 cycles)
  107. 1 1 1 1 1 PBR,PC Op Code 1
  108. 2 1 1 0 1 PBR,PC+1 DO 1
  109. (2) 3a 1 1 0 0 PBR,PC+1 IO 1
  110. 3 1 0 1 0 0,D+DO Data Low 1
  111. (1) 3a 1 0 1 0 0,D+DO+1 Data High 1
  112. (3) 4 1 0 0 0 0,D+DO+1 IO 1
  113. (1) 5a 1 0 1 0 0,D+D0+1 Data High 0
  114. 5 1 0 1 0 0,D+DO Data Low 0
  115. 5 Accumurator -- A
  116. (ASL,INC,ROL,DEC,LSR,ROR)
  117. (6 Op Codes)
  118. (1 byte)
  119. (2 cycles)
  120. 1 1 1 1 1 PBR,PC Op COde 1
  121. 2 1 1 0 0 PBR,PC+1 IO 1
  122. 6a Implied -- i
  123. (DEY,INY,INX,DEX,NOP,XCE,TYA,TAY,TXA,TXS,TAX,TSX,TCS,TSC,TCD,TDC,
  124. TXY,TYX,CLC,SEC,CLI,SEI,CLV,CLD,SED)
  125. (25 Op Codes)
  126. (1 byte)
  127. (2 cycles)
  128. 1 1 1 1 1 PBR,PC Op Code 1
  129. 2 1 1 0 0 PBR,PC+1 IO 1
  130. *6b Implied -- i
  131. (XBA)
  132. (1 Op Code)
  133. (1 byte)
  134. (3 cycles)
  135. 1 1 1 1 1 PBR,PC Op Code 1
  136. 2 1 1 0 0 PBR,PC+1 IO 1
  137. 3 1 1 0 0 PBR,PC+1 IO 1
  138. ADDRESS MODE
  139. CYCLE /VP /ML VDA VPA RDY ADDRESS BUS DATA BUS R/W
  140. 6c Wait for Interrupt
  141. (WAI)
  142. (1 Op Code)
  143. (1 byte)
  144. (3 cycles)
  145. 1 1 1 1 1 1 PBR,PC Op Code 1
  146. (9) 2 1 1 0 0 1 PBR,PC+1 IO 1
  147. 3 1 1 0 0 0 PBR,PC+1 IO 1
  148. IRQ,NMI 1 1 1 1 1 1 PBR,PC+1 IRO(BRK) 1
  149. 6d Stop-The-Clock
  150. (STP)
  151. (1 Op Code)
  152. (1 byte)
  153. (3 cycles)
  154. 1 1 1 1 1 1 PBR,PC Op Code 1
  155. 2 1 1 0 0 1 PBR,PC+1 IO 1
  156. RES=1 3 1 1 0 0 1 PBR,PC+1 IO 1
  157. RES=0 1c 1 1 0 0 1 PBR,PC+1 RES(BRK) 1
  158. RES=0 1b 1 1 0 0 1 PBR,PC+1 RES(BRK) 1
  159. RES=1 1a 1 1 0 0 1 PBR,PC+1 RES(BRK) 1
  160. 1 1 1 1 1 1 PBR,PC+1 BEGIN 1
  161. See 21a Stack (Hardware interrupt)
  162. ADDRESS MODE
  163. CYCLE /VP /ML VDA VPA ADDRESS BUS DATA BUS R/W
  164. 7 Direct Indirect Indexed -- (d),y
  165. (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  166. (8 Op Codes)
  167. (2 bytes)
  168. (5,6,7 and 8 cycles)
  169. 1 1 1 1 1 PBR,PC Op Code 1
  170. 2 1 1 0 1 PBR,PC+1 DO 1
  171. (2) 2a 1 1 0 0 PBR,PC+1 IO 1
  172. 3 1 1 1 0 0,D+DO AAL 1
  173. 4 1 1 1 0 0,D+DO+1 AAH 1
  174. (4) 4a 1 1 0 0 DBR,AAH,AAL+YL IO 1
  175. 5 1 1 1 0 DBR,AA+Y Data Low 1/0
  176. (1) 5a 1 1 1 1 DBR,AA+Y+1 Data High 1/0
  177. 8 Direct Indirect Indexed Long -- [d],y
  178. (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  179. (8 Op Codes)
  180. (2 bytes)
  181. (6,7 and 8 cycles)
  182. 1 1 1 1 1 PBR,PC Op Code 1
  183. 2 1 1 0 1 PBR,PC+1 DO 1
  184. (2) 2a 1 1 0 0 PBR,PC+1 IO 1
  185. 3 1 1 1 0 0,D+DO AAL 1
  186. 4 1 1 1 0 0,D+DO+1 AAH 1
  187. 5 1 1 1 0 0,D+DO+2 AAB 1
  188. 6 1 1 1 0 AAB,AA+Y Data Low 1/0
  189. (1) 6a 1 1 1 0 AAB,AA+Y+1 Data High 1/0
  190. 9 Direct Indexed Indirect -- (d,x)
  191. (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  192. (8 Op Codes)
  193. (2 bytes)
  194. (6,7 and 8 cycles)
  195. 1 1 1 1 1 PBR,PC Op Code 1
  196. 2 1 1 0 1 PBR,PC+1 DO 1
  197. (2) 2a 1 1 0 0 PBR,PC+1 IO 1
  198. 3 1 1 0 0 PBR,PC+1 IO 1
  199. a 1 1 1 0 0,D+DO+X AAL 1
  200. 5 1 1 1 0 0,D+DO+X+1 AAH 1
  201. 6 1 1 1 0 DBR,AA Data Low 1/0
  202. (1) 6a 1 1 1 0 DBR,AA+1 Data High 1/0
  203. 10a Direct,X -- d,x
  204. (BIT,STZ,STY,LDY,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  205. (12 Op Codes)
  206. (2 bytes)
  207. (4,5 and 6 cycles)
  208. 1 1 1 1 1 PBR,PC Op Code 1
  209. 2 1 1 0 1 PBR,PC+1 DO 1
  210. (2) 2a 1 1 0 0 PBR,PC+1 IO 1
  211. 3 1 1 0 0 PBR,PC+1 IO 1
  212. 4 1 1 1 0 0,D+DO+X Data Low 1/0
  213. (1) 4a 1 1 1 0 0,D+DO+X+1 Data High 1/0
  214. 10b Direct,X (R-M-W) -- d,x
  215. (ASL,ROL,LSR,ROR,DEC,INC)
  216. (6 Op Codes)
  217. (2 bytes)
  218. (6,7,8 and 9 cycles)
  219. 1 1 1 1 1 PBR,PC Op Code 1
  220. 2 1 1 0 1 PBR,PC+1 DO 1
  221. (2) 2a 1 1 0 0 PBR,PC+1 IO 1
  222. 3 1 1 0 0 PBR,PC+1 IO 1
  223. 4 1 0 1 0 0,D+DO+X Data Low 1
  224. (1) 4a 1 0 1 0 0,D+DO+X+1 Data High 1
  225. (3) 5 1 0 0 0 0,D+DO+X+1 IO 1
  226. (1) 6a 1 0 1 0 0,D+DO+X+1 Data High 0
  227. 6 1 0 1 0 0,D+DO+X Data Low 0
  228. 11 Direct,Y -- d,y
  229. (STX,LDX)
  230. (2 Op Codes)
  231. (2 bytes)
  232. (4,5 and 6 cycles)
  233. 1 1 1 1 1 PBR,PC Op Code 1
  234. 2 1 1 0 1 PBR,PC+1 DO 1
  235. (2) 2a 1 1 0 0 PBR,PC+1 IO 1
  236. 3 1 1 0 0 PBR,PC+1 IO 1
  237. 4 1 1 1 0 0,D+DO+Y Data Low 1/0
  238. (1) 4a 1 1 1 0 0,D+DO+Y+1 Data High 1/0
  239. 12a Absolute,X -- a,x
  240. (BlT,LDY,STZ,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  241. (11 Op Codes)
  242. (3 bytes)
  243. (4,5 and 6 cycles)
  244. 1 1 1 1 1 PBR,PC Op code 1
  245. 2 1 1 0 1 PBR,PC+1 AAL 1
  246. 3 1 1 0 1 PBR,PC+2 AAH 1
  247. (4) 3a 1 1 0 0 DBR,AAH,AAL+XL IO 1
  248. 4 1 1 1 0 DBR,AA+X Data Low 1/0
  249. (1) 4a 1 1 1 0 DBR,AA+X+1 Data High 1/0
  250. 12b Absolute,X (R-M-W) -- a,x
  251. (ASC,ROL,LSR,ROR,DEC,INC)
  252. (6 Op Codes)
  253. (3 bytes)
  254. (7 and 9 cycles)
  255. 1 1 1 1 1 PBR,PC Op Code 1
  256. 2 1 1 0 1 PBR,PC+1 AAL 1
  257. 3 1 1 0 1 PBR,PC+2 AAH 1
  258. 4 1 1 0 0 DBR,AAH,AAL+XL IO 1
  259. 5 1 0 1 0 DBR,AA+X Data Low 1
  260. (1) 5a 1 0 1 0 DBR,AA+X+1 Data High 1
  261. (3) 6 1 0 0 0 DBR,AA+X+1 lO 1
  262. (1) 7a 1 0 1 0 DBR,AA+X+1 Data High 0
  263. 7 1 0 1 0 DBR,AA+X Data Low 0
  264. *13 Absolute Long,X -- al,x
  265. (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  266. (8 Op Codes)
  267. (4 bytes)
  268. (5 and 6 cycles)
  269. 1 1 1 1 1 PBR,PC Op Code 1
  270. 2 1 1 0 1 PBR,PC+1 AAL 1
  271. 3 1 1 0 1 PBR,PC+7 AAH 1
  272. 4 1 1 0 1 PBA,PC+3 AAB 1
  273. 5 1 1 1 0 AAB,AA+X Data Low 1/0
  274. (1) 5a 1 1 1 0 AAB,AA+X+1 Data High 1/0
  275. 14 Absolute,Y -- a,y
  276. (LDX,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  277. (9 Op Codes)
  278. (3 bytes)
  279. (4,5 and 6 cycles)
  280. 1 1 1 1 1 PBR,PC Op Code 1
  281. 2 1 1 0 1 PBR,PC+1 AAL 1
  282. 3 1 1 0 1 PBR,PC+2 AAH 1
  283. (4) 3a 1 1 0 0 DBR,AAH,AAL+YL IO 1
  284. 4 1 1 1 0 DBR,AA+Y Data Low 1/0
  285. (1) 4a 1 1 1 0 DBR,AA+Y+1 Data High 1/0
  286. 15 Relative -- r
  287. (BPL,BMI,BVC,BVS,BCC,BCS,BNE,BEQ,BRA)
  288. (9 Op Codes)
  289. (2 bytes)
  290. (2,3 and 1 cycles)
  291. 1 1 1 1 1 PBR,PC Op Code 1
  292. 2 1 1 0 1 PBR,PC+1 Offset 1
  293. (5) 2a 1 1 0 0 PBR,PC+2 IO 1
  294. (61 2b 1 1 0 0 PBR,PC+2+OFF IO 1
  295. 1 1 1 1 1 PBR,NewPC New Op Code 1
  296. *16 Relative Long -- rl
  297. (BRL)
  298. (1 Op Code)
  299. (3 bytes)
  300. (4 cycles)
  301. 1 1 1 1 1 PBR,PC Op Code 1
  302. 2 1 1 0 1 PBR,PC+1 Offset Low 1
  303. 3 1 1 0 1 PBR,PC+2 Offset High 1
  304. 4 1 1 0 0 PBR,PC+2 IO 1
  305. 1 1 1 1 1 PBR,NewPC New Op Code 1
  306. 17a Absolute Indirect -- (a)
  307. (JMP)
  308. (1 Op Code)
  309. (3 bytes)
  310. (5 cycles)
  311. 1 1 1 1 1 PBR,PC Op Code 1
  312. 2 1 1 0 1 PBR,PC+1 AAL 1
  313. 3 1 1 0 1 PBR,PC+2 AAH 1
  314. 4 1 1 1 0 0,AA NEW PCL 1
  315. 5 1 1 1 0 0,AA+1 NEW PCH 1
  316. 1 1 1 1 1 PBR,NewPC New Op Code 1
  317. *17b Absolute Indirect -- (a)
  318. (JML)
  319. (1 Op Code)
  320. (3 bytes)
  321. (6 cycles)
  322. 1 1 1 1 1 PBR,PC Op Code 1
  323. 2 1 1 0 1 PBR,PC+1 AAL 1
  324. 3 1 1 0 1 PBR,PC+1 AAH 1
  325. 4 1 1 1 0 0,AA NEW PCL 1
  326. 5 1 1 1 0 0,AA+1 NEW PCH 1
  327. 6 1 1 1 0 0,AA+2 NEW PBR 1
  328. 1 1 1 1 1 NEW PBR,PC New Op Code 1
  329. **18 Direct Indirect -- (d)
  330. (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  331. (8 Op Codes)
  332. (2 bytes)
  333. (5,6 and 7 cycles)
  334. 1 1 1 1 1 PBR,PC Op Code 1
  335. 2 1 1 0 1 PBR,PC+1 DO 1
  336. (2) 2a 1 1 0 0 PBR,PC+1 IO 1
  337. 3 1 1 1 0 0,D+DO AAL 1
  338. 1 1 1 1 0 0,D+DO+1 AAH 1
  339. 5 1 1 1 0 DBR,AA Data Low 1/0
  340. (1) 5a 1 1 1 0 DBR,AA+1 Data Low 1/0
  341. *19 Direct Indirect Long -- [d]
  342. (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  343. (8 Op Codes)
  344. (2 bytes)
  345. (6,7 and 8 cycles)
  346. 1 1 1 1 1 PBR,PC Op Code 1
  347. 2 1 1 0 1 PBR,PC+1 DO 1
  348. (2) 2a 1 1 0 0 PBR,PC+1 IO 1
  349. 3 1 1 1 0 0,D+DO AAL 1
  350. 4 1 1 1 0 0,D+DO+1 AAH 1
  351. 5 1 1 1 0 0,D+DO+2 AAB 1
  352. 6 1 1 1 0 AAB,AA Data Low 1/0
  353. (1) 6a 1 1 1 0 AAB,AA+1 Data High 1/0
  354. 20a Absolute Indexed Indirect -- (a,x)
  355. (JMP)
  356. (1 Op Code)
  357. (3 bytes)
  358. (6 cycles)
  359. 1 1 1 1 1 PBR,PC Op Code 1
  360. 2 1 1 0 1 PBR,PC+1 AAL 1
  361. 3 1 1 0 1 PBR,PC+2 AAH 1
  362. 4 1 1 0 0 PBR,PC+2 IO 1
  363. 5 1 1 0 1 PBR,AA+X NEW PCL 1
  364. 6 1 1 0 1 PBR,AA+X+1 NEW PCH 1
  365. 1 1 1 1 1 PBR,NEWPC New Op Code 1
  366. *20b Absolute Indered Indirect (Jump to Subroutine Indexed Indirect) -- (a,x)
  367. (JSR)
  368. (1 Op Code)
  369. (3 bytes)
  370. (8 cycles)
  371. 1 1 1 1 1 PBR,PC Op Code 1
  372. 2 1 1 0 1 PBR,PC+1 AAL 1
  373. 3 1 1 1 0 0,S PCH 0
  374. 4 1 1 1 0 0,S-1 PCL 0
  375. 5 1 1 0 1 PBR,PC+2 AAH 1
  376. 6 1 1 0 0 PBR,PC+2 IO 1
  377. 7 1 1 0 1 PBR,AA+X NEW PCL 1
  378. 8 1 1 0 1 PBR,AA+X+1 NEW PCH 1
  379. 1 1 1 1 1 PBR,NEWPC New Op Code 1
  380. 21a Stack (Hardware Interrupts) -- s
  381. (IRQ,NMI,ABORT,RES)
  382. (4 hardware Interrupts)
  383. (0 bytes)
  384. (7 and 8 cycles)
  385. 1 1 1 1 1 PBR,PC IO 1
  386. (3) 2 1 1 0 0 PBR,PC IO 1
  387. (7) 3 1 1 1 0 0,S PBR 0
  388. (10) 4 1 1 1 0 0,S-1 PCH 0
  389. (10) 5 1 1 1 0 0,S-2 PCL 0
  390. (10,11) 6 1 1 1 0 0,S-3 P 0
  391. 7 0 1 1 0 0,VA AAVL 1
  392. 8 0 1 1 0 0,VA+1 AAVH 1
  393. 1 1 1 1 1 0,AAV New Op Code 1
  394. 21b Stack (Software Interrupts) -- s
  395. (BRK,COP)
  396. (2 Op Codes)
  397. (2 bytes)
  398. (7 and 8 cycles)
  399. 1 1 1 1 1 PBR,PC Op Code 1
  400. (3) 2 1 1 0 1 PBR,PC+1 Signature 1
  401. (7) 3 1 1 1 0 0,S PBR 0
  402. 4 1 1 1 0 0,S-1 PCH 0
  403. 5 1 1 1 0 0,S-2 PCL 0
  404. 6 1 1 1 0 0,S-3 (COP Latches) P 0
  405. 7 0 1 1 0 0,VA AAVL 1
  406. 8 0 1 1 0 0,VA+1 AAVH 1
  407. 1 1 1 1 1 0,AAV New Op Code 1
  408. 21c Stack (Return from Interrupt) -- s
  409. (RTI)
  410. (1 Op Code)
  411. (1 byte)
  412. (6 and 7 cycles)
  413. (different order from N6502)
  414. 1 1 1 1 1 PBR,PC Op Code 1
  415. 2 1 1 0 0 PBR,PC+1 IO 1
  416. (3) 3 1 1 0 0 PBR,PC+1 IO 1
  417. 4 1 1 1 0 0,S+1 P 1
  418. 5 1 1 1 0 0,S+2 New PCL 1
  419. 6 1 1 1 0 0,S+3 New PCH 1
  420. (7) 7 1 1 1 0 0,S+4 PBR 1
  421. 1 1 1 1 1 PBR,NewPC New Op Code 1
  422. 21d Stack (Return from Subroutine) -- s
  423. (RTS)
  424. (1 Op Code)
  425. (1 byte)
  426. (6 cycles)
  427. 1 1 1 1 1 PBR,PC Op Code 1
  428. 2 1 1 0 0 PBR,PC+1 IO 1
  429. 3 1 1 0 0 PBR,PC+1 IO 1
  430. 4 1 1 1 0 0,S+1 New PCL-1 1
  431. 5 1 1 1 0 0,S+2 New PCH 1
  432. 6 1 1 0 0 0,S+2 IO 1
  433. 1 1 1 1 1 PBR,NewPC New Op Code 1
  434. *21e Stack (Return from Subroutine Long) -- s
  435. (RTL)
  436. (1 Op Code)
  437. (1 byte)
  438. (6 cycles)
  439. 1 1 1 1 1 PBR,PC Op Code 1
  440. 2 1 1 0 0 PBR,PC+1 IO 1
  441. 3 1 1 0 0 PBR,PC+1 IO 1
  442. 4 1 1 1 0 0,S+1 NEW PCL 1
  443. 5 1 1 1 0 0,S+2 NEW PCH 1
  444. 6 1 1 1 0 0,S+3 NEW PBR 1
  445. 1 1 1 1 1 NEWPBR,PC New Op Code 1
  446. 21f Stack (Push) -- s
  447. (PHP,PHA,PHY,PHX,PHD,PHK,PHB)
  448. (7 Op Codes)
  449. (1 byte)
  450. (3 and 4 cycles)
  451. 1 1 1 1 1 PBR,PC Op Code 1
  452. 2 1 1 0 0 PBR,PC+1 IO 1
  453. 3a 1 1 1 0 0,S Register High 0
  454. 3 1 1 1 0 0,S-1 Register Low 0
  455. 21g Stack (Pull) -- s
  456. (PLP,PLA,PLY,PLX,PLD,PLB)
  457. (Different than N6502)
  458. (6 Op Codes)
  459. (1 byte)
  460. (4 and 5 cycles)
  461. 1 1 1 1 1 PBR,PC Op Code 1
  462. 2 1 1 0 0 PBR,PC+1 IO 1
  463. 3 1 1 0 0 PBR,PC+1 IO 1
  464. 4 1 1 1 0 0,S+1 Register Low 1
  465. (1) 4a 1 1 1 0 0,S+2 Register High 1
  466. *21h Stack (Push Effective Indirect Address) -- s
  467. (PEI)
  468. (1 Op Code)
  469. (2 bytes)
  470. (6 and 7 cycles)
  471. 1 1 1 1 1 PBR,PC Op Code 1
  472. 2 1 1 0 1 PBR,PC+1 DO 1
  473. (2) 2a 1 1 0 0 PBR,PC+1 IO 1
  474. 3 1 1 1 0 0,D+DO AAL 1
  475. d 1 1 1 0 0,D+DO+1 AAH 1
  476. 5 1 1 1 0 0,S AAH 0
  477. 6 1 1 1 0 0,S-1 AAL 0
  478. *21i Stack (Push Effective Absolute Address) -- s
  479. (PEA)
  480. (1 Op Code)
  481. (3 bytes)
  482. (5 cycles)
  483. 1 1 1 1 1 PBR,PC Op Code 1
  484. 2 1 1 0 1 PBR,PC+1 AAL 1
  485. 3 1 1 0 1 PBR,PC+2 AAH 1
  486. 4 1 1 1 0 0,S AAH 0
  487. 5 1 1 1 0 0,S-1 AAL 0
  488. *21j Stack (Push Effective Program Counter Relative Address) -- s
  489. (PER)
  490. (1 Op Code)
  491. (3 bytes)
  492. (6 cycles)
  493. 1 1 1 1 1 PBR,PC Op Code 1
  494. 2 1 1 0 1 PBR,PC+1 Offset Low 1
  495. 3 1 1 0 1 PBR,PC+2 Offset High 1
  496. 4 1 1 0 0 PBR,PC+2 IO 1
  497. 5 1 1 1 0 0,S PCH+Offset+CARRY 0
  498. 6 1 1 1 0 0,S-1 PCL + Offset 0
  499. *22 Stace Relative -- d,s
  500. (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
  501. (8 Op Codes)
  502. (2 bytes)
  503. (4 and 5 cycles)
  504. 1 1 1 1 1 PBR,PC Op Code 1
  505. 2 1 1 0 1 PBR,PC+1 SO 1
  506. 3 1 1 0 0 PBR,PC+1 IO 1
  507. 4 1 1 1 0 0,S+SO Data Low 1/0
  508. (1) 4a 1 1 1 0 0,S+SO+1 Data High 1/0
  509. *23 Stack Relative Indirect Indexed -- (d,s),y
  510. (8 Op Codes)
  511. (2 bytes)
  512. (7 and 8 cycles)
  513. 1 1 1 1 1 PBR,PC Op Code 1
  514. 2 1 1 0 1 PBR,PC+1 SO 1
  515. 3 1 1 0 0 PBR,PC+1 IO 1
  516. 4 1 1 1 0 0,S+SO AAL 1
  517. 5 1 1 1 0 0,S+SO+1 AAH 1
  518. 6 1 1 0 0 0,S+SO+1 IO 1
  519. 7 1 1 1 0 DBR,AA+Y Data Low 1/0
  520. (1) 7a 1 1 1 0 DBR,AA+Y+1 Data High 1/0
  521. *24a Block Move Positive (forward) -- xyc
  522. (MVP)
  523. (1 Op Code)
  524. (3 bytes)
  525. (7 cycles)
  526. +- 1 1 1 1 1 PBR,PC Op Code 1
  527. | 2 1 1 0 1 PBR,PC+1 DBA 1
  528. | 3 1 1 0 1 PBR,PC+2 SBA 1
  529. N-2 | 4 1 1 1 0 SBA,X Source Data 1
  530. Byte | 5 1 1 1 0 DBA,Y Dest Data 0
  531. C=2 | 6 1 1 0 0 DBA,Y IO 1
  532. +- 7 1 1 0 0 DBA,Y IO 1
  533. +- 1 1 1 1 1 PBR,PC Op Code 1
  534. | 2 1 1 0 1 PBR,PC+1 DBA 1
  535. N-1 | 3 1 1 0 1 PBR,PC+2 SBA 1
  536. Byte | 4 1 1 1 0 SBA,X-1 Source Data 1
  537. C=1 | 5 1 1 1 0 DBA,Y-1 Dest Data 0
  538. | 6 1 1 0 0 DBA,Y-1 IO 1
  539. +- 7 1 1 0 0 DBA,Y-1 IO 1
  540. +- 1 1 1 1 1 PBR,PC Op Code 1
  541. | 2 1 1 0 1 PBR,PC+1 DBA 1
  542. N Byte | 3 1 1 0 1 PBR,PC+2 SBA 1
  543. Last | 4 1 1 1 0 SBA,X-2 Source Data 1
  544. C=0 | 5 1 1 1 0 DBA,Y-2 Dest Data 0
  545. | 6 1 1 0 0 DBA,Y-2 IO 1
  546. | 7 1 1 0 0 DBA,Y-2 IO 1
  547. +- 1 1 1 1 1 PBR,PC+3 New Op Code 1
  548. x = Source Address
  549. y = Destination
  550. c = Number of Bytes to move -1
  551. x,y Decrement
  552. MVP is used when the destination start address is higher (more positive)
  553. than the source start address.
  554. FFFFFF
  555. ^ Dest Start
  556. | Source Start
  557. | Dest End
  558. | Source End
  559. 000000
  560. *24b, Block Move Negative (backward) -- xyc
  561. (MVN)
  562. (1 Op Code)
  563. (3 bytes)
  564. (7 cycles)
  565. +- 1 1 1 1 1 PBR,PC Op Code 1
  566. | 2 1 1 0 1 PBR,PC+1 DBA 1
  567. | 3 1 1 0 1 PBR,PC+2 SBA 1
  568. N-2 | 4 1 1 1 0 SBA,X Source Data 1
  569. Byte | 5 1 1 1 0 DBA,Y Dest Data 0
  570. C=2 | 6 1 1 0 0 DBA,Y IO 1
  571. +- 7 1 1 0 0 DBA,Y IO 1
  572. +- 1 1 1 1 1 PBR,PC Op Code 1
  573. | 2 1 1 0 1 PBR,PC+1 DBA 1
  574. N-1 | 3 1 1 0 1 PBR,PC+2 SBA 1
  575. Byte | 4 1 1 1 0 SBA,X+1 Source Data 1
  576. C=1 | 5 1 1 1 0 DBA,Y+1 Dest Data 0
  577. | 6 1 1 0 0 DBA,Y+1 IO 1
  578. +- 7 1 1 0 0 DBA,Y+1 IO 1
  579. +- 1 1 1 1 1 PBR,PC Op Code 1
  580. | 2 1 1 0 1 PBR,PC+1 DBA 1
  581. N Byte | 3 1 1 0 1 PBR,PC+2 SBA 1
  582. Last | 4 1 1 1 0 SBA,X+2 Source Data 1
  583. C=0 | 5 1 1 1 0 DBA,Y+2 Dest Data 0
  584. | 6 1 1 0 0 DBA,Y+2 IO 1
  585. | 7 1 1 0 0 DBA,Y+2 IO 1
  586. +- 1 1 1 1 1 PBR,PC+3 New Op Code 1
  587. x = Source Address
  588. y = Destination
  589. c = Number of Bytes to move -1
  590. x,y Increment
  591. MVN is used when the destination start address is lower (more negative)
  592. than the source start address.
  593. FFFFFF
  594. | Source End
  595. | Dest End
  596. | Source Start
  597. v Dest Start
  598. 000000
  599. Notes
  600. (1) Add 1 byte (for immediate only) for M=O or X=O (i.e. 16 bit data),
  601. add 1 cycle for M=O or X=0.
  602. (2) Add 1 cycle for direct register low (DL) not equal 0.
  603. (3) Special case for aborting instruction. This is the last cycle which
  604. may be aborted or the Status, PBR or DBR registers will be updated.
  605. (4) Add 1 cycle for indexing across page boundaries, or write, or X=0.
  606. When X=1 or in the emulation mode, this cycle contains invalid
  607. addresses.
  608. (5) Add 1 cycle if branch is taken.
  609. (6) Add 1 cycle if branch is taken across page boundaries in 6502 emutation
  610. mode (E=1).
  611. (7) Subtract 1 cycle for 6502 emulation mode (E=1).
  612. (8) Add 1 cycle lor REP, SEP.
  613. (9) Wait at cycle 2 for 2 cycles after /NMI or /IRQ active input.
  614. (10) R/W remains high during Reset.
  615. (11) BRK bit 4 equals "0" in Emulation mode.
  616. Abbreviations
  617. AAB Absolute Address Bank
  618. AAH Absolute Address High
  619. AAL Absolute Address Low
  620. AAVH Absolute Address Vector High
  621. AAVL Absolute Address Vector Low
  622. C Accumulator
  623. D Direct Register
  624. DBA Destination Bank Address
  625. DBR Data Bank Register
  626. DO Direct Offset
  627. IDH Immediate Data High
  628. IDL Immediate Data Low
  629. IO Internal Operation
  630. P Status Register
  631. PBR Program Bank Register
  632. PC Program Counter
  633. R-M-W Read-Modify-Write
  634. S Stack Address
  635. SBA Source Bank Address
  636. SO Stack Offset
  637. VA Vector Address
  638. x, y Index Registers
  639. * New G65SC816/802 Addressing Modes
  640. ** New G65SC02 Addressing Modes
  641. Blank NMOS 6502 Addressing Modes