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- Table 9. Detailed Instruction Operation
- ADDRESS MODE
- CYCLE /VP /ML VDA VPA ADDRESS BUS DATA BUS R/W
- 1 Immediate -- #
- (LDY,CPY,CPX,LDX,ORA,AND,EOR,ADC,BIT,LDA,CMP,SBC,REP,SEP)
- (14 Op Codes)
- (2 and 3 bytes)
- (2 and 3 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 IDL 1
- 2a 1 1 0 1 PBR,PC+2 IDH 1
- 2a Absolute -- a
- (BIT,STY,STZ,LDY,CPY,CPX,STX,LDX,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (16 Op Codes)
- (3 bytes)
- (4 and 5 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+2 AAH 1
- 4 1 1 1 0 DBR,AA Data Low 1/0
- (1) 4a 1 1 1 0 DBR,AA+1 Data High 1/0
- 2b Absolute (R-M-W) -- a
- (ASL,ROL,LSR,ROR,DEC,INC,TSB,TRB)
- (8 Op Codes)
- (3 bytes)
- (6 and 8 cycles)
- 1 1 1 1 1 PBA,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+2 AAH 1
- 4 1 0 1 0 DBR,AA Data Low 1
- (1) 4a 1 0 1 0 DBR,AA+1 Data High 1
- (3) 5 1 0 0 0 DBR,AA+2 IO 1
- (1) 6a 1 0 1 0 DBR,AA+3 Data Hiqh 0
- 6 1 0 1 0 DBR,AA Data Low 0
-
- 2c Absolute(JUMP) -- a
- (JMP)(4C)
- (1 Op Code)
- (3 bytes)
- (3 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 NEW PCL 1
- 3 1 1 0 1 PBR,PC+2 NEW PCH 1
- 1 1 1 1 1 PBR,NEWPC New Op Code 1
- 2d Absolute (Jump to subroutine) -- a
- (JSR)
- (1 Op Code)
- (3 bytes)
- (6 cycles)
- (different order from N6502)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBA,PC+1 NEW FCC 1
- 3 1 1 0 1 PBR,PC+2 NEW PCH 1
- 4 1 1 0 0 PBR,PC+2 IO 1
- 5 1 1 1 0 0,S PCH 0
- 6 1 1 1 0 0,S-1 PCL 0
- 1 1 1 1 1 PBA,NEWPC New Op Code 1
- 3a Absolute Long -- al
- (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (8 Op Codes)
- (4 bytes)
- (5 and 6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+2 AAH 1
- 4 1 1 0 1 PBR,PC+3 AAB 1
- 5 1 1 1 0 AAB,AA Data Low 1/0
- (1) 5a 1 1 1 0 AAB,AA+1 Data High 1/0
- 3b Absolute Long (JUMP) -- al
- (JMP)
- (1 Op Code)
- (4 bytes)
- (4 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 NEW PCL 1
- 3 1 1 0 1 PBR,PC+2 NEW PCH 1
- 4 1 1 0 1 PBR,PC+3 NEW BR 1
- 1 1 1 1 1 NEW PBR,PC New Op Code 1
- 3c Absolute Long (Jump to Subroutine Long) -- al
- (JSL)
- (1 Op Code)
- (4 bytes)
- (7 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 NEW PCL 1
- 3 1 1 0 1 PBR,PC+2 NEW PCH 1
- 4 1 1 1 0 0,S PBR 0
- 5 1 1 0 0 0,S IO 1
- 6 1 1 0 1 PBR,PC+3 NEW PBR 1
- 7 1 1 1 0 0,S-1 PCH 0
- 8 1 1 1 0 0,S-2 FCL 0
- 1 1 1 1 1 NEW PBR,PC New Op Code 1
- 4a Direct -- d
- (BIT,STZ,STY,LDY,CPY,CPX,STX,LDX,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (16 Op Codes)
- (2 bytes)
- (3,4 and 5 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+2 IO 1
- 3 1 1 1 0 0,D+DO Data Low 1/0
- (1) 3a 1 1 1 0 0,D+DO+1 Data High 1/0
- 4b Direct (R-M-W) -- d
- (ASL,ROL,LSR,ROR,DEC,INC,TSB,TRB)
- (8 Op Codes)
- (2 bytes)
- (5,6,7 and 8 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 3a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 0 1 0 0,D+DO Data Low 1
- (1) 3a 1 0 1 0 0,D+DO+1 Data High 1
- (3) 4 1 0 0 0 0,D+DO+1 IO 1
- (1) 5a 1 0 1 0 0,D+D0+1 Data High 0
- 5 1 0 1 0 0,D+DO Data Low 0
- 5 Accumurator -- A
- (ASL,INC,ROL,DEC,LSR,ROR)
- (6 Op Codes)
- (1 byte)
- (2 cycles)
- 1 1 1 1 1 PBR,PC Op COde 1
- 2 1 1 0 0 PBR,PC+1 IO 1
-
- 6a Implied -- i
- (DEY,INY,INX,DEX,NOP,XCE,TYA,TAY,TXA,TXS,TAX,TSX,TCS,TSC,TCD,TDC,
- TXY,TYX,CLC,SEC,CLI,SEI,CLV,CLD,SED)
- (25 Op Codes)
- (1 byte)
- (2 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 0 PBR,PC+1 IO 1
- *6b Implied -- i
- (XBA)
- (1 Op Code)
- (1 byte)
- (3 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- ADDRESS MODE
- CYCLE /VP /ML VDA VPA RDY ADDRESS BUS DATA BUS R/W
- 6c Wait for Interrupt
- (WAI)
- (1 Op Code)
- (1 byte)
- (3 cycles)
- 1 1 1 1 1 1 PBR,PC Op Code 1
- (9) 2 1 1 0 0 1 PBR,PC+1 IO 1
- 3 1 1 0 0 0 PBR,PC+1 IO 1
- IRQ,NMI 1 1 1 1 1 1 PBR,PC+1 IRO(BRK) 1
- 6d Stop-The-Clock
- (STP)
- (1 Op Code)
- (1 byte)
- (3 cycles)
- 1 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 0 1 PBR,PC+1 IO 1
- RES=1 3 1 1 0 0 1 PBR,PC+1 IO 1
- RES=0 1c 1 1 0 0 1 PBR,PC+1 RES(BRK) 1
- RES=0 1b 1 1 0 0 1 PBR,PC+1 RES(BRK) 1
- RES=1 1a 1 1 0 0 1 PBR,PC+1 RES(BRK) 1
- 1 1 1 1 1 1 PBR,PC+1 BEGIN 1
- See 21a Stack (Hardware interrupt)
- ADDRESS MODE
- CYCLE /VP /ML VDA VPA ADDRESS BUS DATA BUS R/W
- 7 Direct Indirect Indexed -- (d),y
- (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (8 Op Codes)
- (2 bytes)
- (5,6,7 and 8 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 1 0 0,D+DO AAL 1
- 4 1 1 1 0 0,D+DO+1 AAH 1
- (4) 4a 1 1 0 0 DBR,AAH,AAL+YL IO 1
- 5 1 1 1 0 DBR,AA+Y Data Low 1/0
- (1) 5a 1 1 1 1 DBR,AA+Y+1 Data High 1/0
- 8 Direct Indirect Indexed Long -- [d],y
- (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (8 Op Codes)
- (2 bytes)
- (6,7 and 8 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 1 0 0,D+DO AAL 1
- 4 1 1 1 0 0,D+DO+1 AAH 1
- 5 1 1 1 0 0,D+DO+2 AAB 1
- 6 1 1 1 0 AAB,AA+Y Data Low 1/0
- (1) 6a 1 1 1 0 AAB,AA+Y+1 Data High 1/0
- 9 Direct Indexed Indirect -- (d,x)
- (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (8 Op Codes)
- (2 bytes)
- (6,7 and 8 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- a 1 1 1 0 0,D+DO+X AAL 1
- 5 1 1 1 0 0,D+DO+X+1 AAH 1
- 6 1 1 1 0 DBR,AA Data Low 1/0
- (1) 6a 1 1 1 0 DBR,AA+1 Data High 1/0
- 10a Direct,X -- d,x
- (BIT,STZ,STY,LDY,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (12 Op Codes)
- (2 bytes)
- (4,5 and 6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- 4 1 1 1 0 0,D+DO+X Data Low 1/0
- (1) 4a 1 1 1 0 0,D+DO+X+1 Data High 1/0
- 10b Direct,X (R-M-W) -- d,x
- (ASL,ROL,LSR,ROR,DEC,INC)
- (6 Op Codes)
- (2 bytes)
- (6,7,8 and 9 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- 4 1 0 1 0 0,D+DO+X Data Low 1
- (1) 4a 1 0 1 0 0,D+DO+X+1 Data High 1
- (3) 5 1 0 0 0 0,D+DO+X+1 IO 1
- (1) 6a 1 0 1 0 0,D+DO+X+1 Data High 0
- 6 1 0 1 0 0,D+DO+X Data Low 0
- 11 Direct,Y -- d,y
- (STX,LDX)
- (2 Op Codes)
- (2 bytes)
- (4,5 and 6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- 4 1 1 1 0 0,D+DO+Y Data Low 1/0
- (1) 4a 1 1 1 0 0,D+DO+Y+1 Data High 1/0
- 12a Absolute,X -- a,x
- (BlT,LDY,STZ,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (11 Op Codes)
- (3 bytes)
- (4,5 and 6 cycles)
- 1 1 1 1 1 PBR,PC Op code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+2 AAH 1
- (4) 3a 1 1 0 0 DBR,AAH,AAL+XL IO 1
- 4 1 1 1 0 DBR,AA+X Data Low 1/0
- (1) 4a 1 1 1 0 DBR,AA+X+1 Data High 1/0
- 12b Absolute,X (R-M-W) -- a,x
- (ASC,ROL,LSR,ROR,DEC,INC)
- (6 Op Codes)
- (3 bytes)
- (7 and 9 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+2 AAH 1
- 4 1 1 0 0 DBR,AAH,AAL+XL IO 1
- 5 1 0 1 0 DBR,AA+X Data Low 1
- (1) 5a 1 0 1 0 DBR,AA+X+1 Data High 1
- (3) 6 1 0 0 0 DBR,AA+X+1 lO 1
- (1) 7a 1 0 1 0 DBR,AA+X+1 Data High 0
- 7 1 0 1 0 DBR,AA+X Data Low 0
- *13 Absolute Long,X -- al,x
- (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (8 Op Codes)
- (4 bytes)
- (5 and 6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+7 AAH 1
- 4 1 1 0 1 PBA,PC+3 AAB 1
- 5 1 1 1 0 AAB,AA+X Data Low 1/0
- (1) 5a 1 1 1 0 AAB,AA+X+1 Data High 1/0
- 14 Absolute,Y -- a,y
- (LDX,ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (9 Op Codes)
- (3 bytes)
- (4,5 and 6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+2 AAH 1
- (4) 3a 1 1 0 0 DBR,AAH,AAL+YL IO 1
- 4 1 1 1 0 DBR,AA+Y Data Low 1/0
- (1) 4a 1 1 1 0 DBR,AA+Y+1 Data High 1/0
- 15 Relative -- r
- (BPL,BMI,BVC,BVS,BCC,BCS,BNE,BEQ,BRA)
- (9 Op Codes)
- (2 bytes)
- (2,3 and 1 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 Offset 1
- (5) 2a 1 1 0 0 PBR,PC+2 IO 1
- (61 2b 1 1 0 0 PBR,PC+2+OFF IO 1
- 1 1 1 1 1 PBR,NewPC New Op Code 1
- *16 Relative Long -- rl
- (BRL)
- (1 Op Code)
- (3 bytes)
- (4 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 Offset Low 1
- 3 1 1 0 1 PBR,PC+2 Offset High 1
- 4 1 1 0 0 PBR,PC+2 IO 1
- 1 1 1 1 1 PBR,NewPC New Op Code 1
- 17a Absolute Indirect -- (a)
- (JMP)
- (1 Op Code)
- (3 bytes)
- (5 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+2 AAH 1
- 4 1 1 1 0 0,AA NEW PCL 1
- 5 1 1 1 0 0,AA+1 NEW PCH 1
- 1 1 1 1 1 PBR,NewPC New Op Code 1
- *17b Absolute Indirect -- (a)
- (JML)
- (1 Op Code)
- (3 bytes)
- (6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+1 AAH 1
- 4 1 1 1 0 0,AA NEW PCL 1
- 5 1 1 1 0 0,AA+1 NEW PCH 1
- 6 1 1 1 0 0,AA+2 NEW PBR 1
- 1 1 1 1 1 NEW PBR,PC New Op Code 1
- **18 Direct Indirect -- (d)
- (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (8 Op Codes)
- (2 bytes)
- (5,6 and 7 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 1 0 0,D+DO AAL 1
- 1 1 1 1 0 0,D+DO+1 AAH 1
- 5 1 1 1 0 DBR,AA Data Low 1/0
- (1) 5a 1 1 1 0 DBR,AA+1 Data Low 1/0
- *19 Direct Indirect Long -- [d]
- (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (8 Op Codes)
- (2 bytes)
- (6,7 and 8 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 1 0 0,D+DO AAL 1
- 4 1 1 1 0 0,D+DO+1 AAH 1
- 5 1 1 1 0 0,D+DO+2 AAB 1
- 6 1 1 1 0 AAB,AA Data Low 1/0
- (1) 6a 1 1 1 0 AAB,AA+1 Data High 1/0
- 20a Absolute Indexed Indirect -- (a,x)
- (JMP)
- (1 Op Code)
- (3 bytes)
- (6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+2 AAH 1
- 4 1 1 0 0 PBR,PC+2 IO 1
- 5 1 1 0 1 PBR,AA+X NEW PCL 1
- 6 1 1 0 1 PBR,AA+X+1 NEW PCH 1
- 1 1 1 1 1 PBR,NEWPC New Op Code 1
- *20b Absolute Indered Indirect (Jump to Subroutine Indexed Indirect) -- (a,x)
- (JSR)
- (1 Op Code)
- (3 bytes)
- (8 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 1 0 0,S PCH 0
- 4 1 1 1 0 0,S-1 PCL 0
- 5 1 1 0 1 PBR,PC+2 AAH 1
- 6 1 1 0 0 PBR,PC+2 IO 1
- 7 1 1 0 1 PBR,AA+X NEW PCL 1
- 8 1 1 0 1 PBR,AA+X+1 NEW PCH 1
- 1 1 1 1 1 PBR,NEWPC New Op Code 1
- 21a Stack (Hardware Interrupts) -- s
- (IRQ,NMI,ABORT,RES)
- (4 hardware Interrupts)
- (0 bytes)
- (7 and 8 cycles)
- 1 1 1 1 1 PBR,PC IO 1
- (3) 2 1 1 0 0 PBR,PC IO 1
- (7) 3 1 1 1 0 0,S PBR 0
- (10) 4 1 1 1 0 0,S-1 PCH 0
- (10) 5 1 1 1 0 0,S-2 PCL 0
- (10,11) 6 1 1 1 0 0,S-3 P 0
- 7 0 1 1 0 0,VA AAVL 1
- 8 0 1 1 0 0,VA+1 AAVH 1
- 1 1 1 1 1 0,AAV New Op Code 1
- 21b Stack (Software Interrupts) -- s
- (BRK,COP)
- (2 Op Codes)
- (2 bytes)
- (7 and 8 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- (3) 2 1 1 0 1 PBR,PC+1 Signature 1
- (7) 3 1 1 1 0 0,S PBR 0
- 4 1 1 1 0 0,S-1 PCH 0
- 5 1 1 1 0 0,S-2 PCL 0
- 6 1 1 1 0 0,S-3 (COP Latches) P 0
- 7 0 1 1 0 0,VA AAVL 1
- 8 0 1 1 0 0,VA+1 AAVH 1
- 1 1 1 1 1 0,AAV New Op Code 1
- 21c Stack (Return from Interrupt) -- s
- (RTI)
- (1 Op Code)
- (1 byte)
- (6 and 7 cycles)
- (different order from N6502)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 0 PBR,PC+1 IO 1
- (3) 3 1 1 0 0 PBR,PC+1 IO 1
- 4 1 1 1 0 0,S+1 P 1
- 5 1 1 1 0 0,S+2 New PCL 1
- 6 1 1 1 0 0,S+3 New PCH 1
- (7) 7 1 1 1 0 0,S+4 PBR 1
- 1 1 1 1 1 PBR,NewPC New Op Code 1
- 21d Stack (Return from Subroutine) -- s
- (RTS)
- (1 Op Code)
- (1 byte)
- (6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- 4 1 1 1 0 0,S+1 New PCL-1 1
- 5 1 1 1 0 0,S+2 New PCH 1
- 6 1 1 0 0 0,S+2 IO 1
- 1 1 1 1 1 PBR,NewPC New Op Code 1
- *21e Stack (Return from Subroutine Long) -- s
- (RTL)
- (1 Op Code)
- (1 byte)
- (6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- 4 1 1 1 0 0,S+1 NEW PCL 1
- 5 1 1 1 0 0,S+2 NEW PCH 1
- 6 1 1 1 0 0,S+3 NEW PBR 1
- 1 1 1 1 1 NEWPBR,PC New Op Code 1
- 21f Stack (Push) -- s
- (PHP,PHA,PHY,PHX,PHD,PHK,PHB)
- (7 Op Codes)
- (1 byte)
- (3 and 4 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 0 PBR,PC+1 IO 1
- 3a 1 1 1 0 0,S Register High 0
- 3 1 1 1 0 0,S-1 Register Low 0
- 21g Stack (Pull) -- s
- (PLP,PLA,PLY,PLX,PLD,PLB)
- (Different than N6502)
- (6 Op Codes)
- (1 byte)
- (4 and 5 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- 4 1 1 1 0 0,S+1 Register Low 1
- (1) 4a 1 1 1 0 0,S+2 Register High 1
- *21h Stack (Push Effective Indirect Address) -- s
- (PEI)
- (1 Op Code)
- (2 bytes)
- (6 and 7 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 DO 1
- (2) 2a 1 1 0 0 PBR,PC+1 IO 1
- 3 1 1 1 0 0,D+DO AAL 1
- d 1 1 1 0 0,D+DO+1 AAH 1
- 5 1 1 1 0 0,S AAH 0
- 6 1 1 1 0 0,S-1 AAL 0
- *21i Stack (Push Effective Absolute Address) -- s
- (PEA)
- (1 Op Code)
- (3 bytes)
- (5 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 AAL 1
- 3 1 1 0 1 PBR,PC+2 AAH 1
- 4 1 1 1 0 0,S AAH 0
- 5 1 1 1 0 0,S-1 AAL 0
-
- *21j Stack (Push Effective Program Counter Relative Address) -- s
- (PER)
- (1 Op Code)
- (3 bytes)
- (6 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 Offset Low 1
- 3 1 1 0 1 PBR,PC+2 Offset High 1
- 4 1 1 0 0 PBR,PC+2 IO 1
- 5 1 1 1 0 0,S PCH+Offset+CARRY 0
- 6 1 1 1 0 0,S-1 PCL + Offset 0
- *22 Stace Relative -- d,s
- (ORA,AND,EOR,ADC,STA,LDA,CMP,SBC)
- (8 Op Codes)
- (2 bytes)
- (4 and 5 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 SO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- 4 1 1 1 0 0,S+SO Data Low 1/0
- (1) 4a 1 1 1 0 0,S+SO+1 Data High 1/0
-
- *23 Stack Relative Indirect Indexed -- (d,s),y
- (8 Op Codes)
- (2 bytes)
- (7 and 8 cycles)
- 1 1 1 1 1 PBR,PC Op Code 1
- 2 1 1 0 1 PBR,PC+1 SO 1
- 3 1 1 0 0 PBR,PC+1 IO 1
- 4 1 1 1 0 0,S+SO AAL 1
- 5 1 1 1 0 0,S+SO+1 AAH 1
- 6 1 1 0 0 0,S+SO+1 IO 1
- 7 1 1 1 0 DBR,AA+Y Data Low 1/0
- (1) 7a 1 1 1 0 DBR,AA+Y+1 Data High 1/0
- *24a Block Move Positive (forward) -- xyc
- (MVP)
- (1 Op Code)
- (3 bytes)
- (7 cycles)
- +- 1 1 1 1 1 PBR,PC Op Code 1
- | 2 1 1 0 1 PBR,PC+1 DBA 1
- | 3 1 1 0 1 PBR,PC+2 SBA 1
- N-2 | 4 1 1 1 0 SBA,X Source Data 1
- Byte | 5 1 1 1 0 DBA,Y Dest Data 0
- C=2 | 6 1 1 0 0 DBA,Y IO 1
- +- 7 1 1 0 0 DBA,Y IO 1
- +- 1 1 1 1 1 PBR,PC Op Code 1
- | 2 1 1 0 1 PBR,PC+1 DBA 1
- N-1 | 3 1 1 0 1 PBR,PC+2 SBA 1
- Byte | 4 1 1 1 0 SBA,X-1 Source Data 1
- C=1 | 5 1 1 1 0 DBA,Y-1 Dest Data 0
- | 6 1 1 0 0 DBA,Y-1 IO 1
- +- 7 1 1 0 0 DBA,Y-1 IO 1
- +- 1 1 1 1 1 PBR,PC Op Code 1
- | 2 1 1 0 1 PBR,PC+1 DBA 1
- N Byte | 3 1 1 0 1 PBR,PC+2 SBA 1
- Last | 4 1 1 1 0 SBA,X-2 Source Data 1
- C=0 | 5 1 1 1 0 DBA,Y-2 Dest Data 0
- | 6 1 1 0 0 DBA,Y-2 IO 1
- | 7 1 1 0 0 DBA,Y-2 IO 1
- +- 1 1 1 1 1 PBR,PC+3 New Op Code 1
- x = Source Address
- y = Destination
- c = Number of Bytes to move -1
- x,y Decrement
- MVP is used when the destination start address is higher (more positive)
- than the source start address.
- FFFFFF
- ^ Dest Start
- | Source Start
- | Dest End
- | Source End
- 000000
- *24b, Block Move Negative (backward) -- xyc
- (MVN)
- (1 Op Code)
- (3 bytes)
- (7 cycles)
- +- 1 1 1 1 1 PBR,PC Op Code 1
- | 2 1 1 0 1 PBR,PC+1 DBA 1
- | 3 1 1 0 1 PBR,PC+2 SBA 1
- N-2 | 4 1 1 1 0 SBA,X Source Data 1
- Byte | 5 1 1 1 0 DBA,Y Dest Data 0
- C=2 | 6 1 1 0 0 DBA,Y IO 1
- +- 7 1 1 0 0 DBA,Y IO 1
- +- 1 1 1 1 1 PBR,PC Op Code 1
- | 2 1 1 0 1 PBR,PC+1 DBA 1
- N-1 | 3 1 1 0 1 PBR,PC+2 SBA 1
- Byte | 4 1 1 1 0 SBA,X+1 Source Data 1
- C=1 | 5 1 1 1 0 DBA,Y+1 Dest Data 0
- | 6 1 1 0 0 DBA,Y+1 IO 1
- +- 7 1 1 0 0 DBA,Y+1 IO 1
- +- 1 1 1 1 1 PBR,PC Op Code 1
- | 2 1 1 0 1 PBR,PC+1 DBA 1
- N Byte | 3 1 1 0 1 PBR,PC+2 SBA 1
- Last | 4 1 1 1 0 SBA,X+2 Source Data 1
- C=0 | 5 1 1 1 0 DBA,Y+2 Dest Data 0
- | 6 1 1 0 0 DBA,Y+2 IO 1
- | 7 1 1 0 0 DBA,Y+2 IO 1
- +- 1 1 1 1 1 PBR,PC+3 New Op Code 1
- x = Source Address
- y = Destination
- c = Number of Bytes to move -1
- x,y Increment
- MVN is used when the destination start address is lower (more negative)
- than the source start address.
- FFFFFF
- | Source End
- | Dest End
- | Source Start
- v Dest Start
- 000000
- Notes
- (1) Add 1 byte (for immediate only) for M=O or X=O (i.e. 16 bit data),
- add 1 cycle for M=O or X=0.
- (2) Add 1 cycle for direct register low (DL) not equal 0.
- (3) Special case for aborting instruction. This is the last cycle which
- may be aborted or the Status, PBR or DBR registers will be updated.
- (4) Add 1 cycle for indexing across page boundaries, or write, or X=0.
- When X=1 or in the emulation mode, this cycle contains invalid
- addresses.
- (5) Add 1 cycle if branch is taken.
- (6) Add 1 cycle if branch is taken across page boundaries in 6502 emutation
- mode (E=1).
- (7) Subtract 1 cycle for 6502 emulation mode (E=1).
- (8) Add 1 cycle lor REP, SEP.
- (9) Wait at cycle 2 for 2 cycles after /NMI or /IRQ active input.
- (10) R/W remains high during Reset.
- (11) BRK bit 4 equals "0" in Emulation mode.
- Abbreviations
- AAB Absolute Address Bank
- AAH Absolute Address High
- AAL Absolute Address Low
- AAVH Absolute Address Vector High
- AAVL Absolute Address Vector Low
- C Accumulator
- D Direct Register
- DBA Destination Bank Address
- DBR Data Bank Register
- DO Direct Offset
- IDH Immediate Data High
- IDL Immediate Data Low
- IO Internal Operation
- P Status Register
- PBR Program Bank Register
- PC Program Counter
- R-M-W Read-Modify-Write
- S Stack Address
- SBA Source Bank Address
- SO Stack Offset
- VA Vector Address
- x, y Index Registers
- * New G65SC816/802 Addressing Modes
- ** New G65SC02 Addressing Modes
- Blank NMOS 6502 Addressing Modes
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