dma.txt 5.4 KB

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  1. From: LAY@uk.tele.nokia.fi
  2. To: "Super Famicom Development Group" <famidev@busop.cit.wayne.edu>
  3. Subject: RE: Assorted questions...
  4. >> 2) I asked a question before about HDMA, and I got replies saying that
  5. >> it has something to do with the horizontal interrupt or horizontal
  6. >> blank time (I forget which). Later on I saw people talking about
  7. >> HDMA "channels". Could someone please tell me what the "channels"
  8. >> are used for, or are they another name for a register or a memory
  9. >> storage location?
  10. It's probably best to start by explaning "normal" DMA. The SNES
  11. supports 8 DMA channels which allow data to be copied to VRAM
  12. extremely quickly, bypassing the 65c816 processor. Each channel
  13. consists of the following registers.
  14. Byte $43?0 DMA channel ? control register
  15. Byte $43?1 DMA channel ? destination
  16. Word $43?2 DMA channel ? source address offset
  17. Byte $43?4 DMA channel ? source address bank
  18. Word $43?5 DMA channel ? transfer bytes
  19. where ? is 0..7
  20. A value of $01 written to the DMA channel control register at
  21. $43?0 indicates that we're using "normal" DMA. The graphics
  22. register destination is formed by using $21 as the high byte
  23. of the address and using the byte specified at $43?1 as the
  24. low byte. Hence you can DMA to any of the graphics registers
  25. between $2100..$21FF.
  26. There is also a DMA control register.
  27. Byte $420B DMA control register
  28. Here bit 0 enables channel 0, bit 1 enables channel 1 etc...
  29. For example, suppose I wanted to copy a 32 x 32 character
  30. screen map (ie. $800 bytes) from location $18000 in ROM into
  31. location $0000 of VRAM. I could do this using DMA channel 0
  32. with the following code (A is 8-bits, X & Y are 16-bits).
  33. ldx.w #$0000 ; set VRAM pointer to $0000
  34. stx $2116
  35. lda #$01 ; control value for "normal" DMA
  36. sta $4300
  37. lda #$18 ; dma to $2118
  38. sta $4301
  39. ldx.w #$8000 ; source offset
  40. stx $4302
  41. lda #$01 ; source bank
  42. sta $4304
  43. ldx.w #$0800 ; number of bytes
  44. stx $4305
  45. lda #$01 ; enable DMA channel 0
  46. sta $420B
  47. And that's all there is to it. After completion of the last
  48. instruction "sta $420B" the $800 bytes at $18000 will have
  49. been copied into VRAM at location $0000.
  50. HDMA allows you to use any combination of these DMA channels
  51. to modify graphics registers just before the start of every
  52. horizontal scan line.
  53. To use HDMA you have to write a value of $00 or $02 to the
  54. DMA channel control register at $43?0 to indicate "horizontal"
  55. DMA. Writing $00 indicates a byte is to be DMA'd each scan
  56. line, writing $02 indicates a word. The DMA channel destination
  57. at $43?1 works just as before with "normal" DMA. The source
  58. address offset and bank registers at $43?2 & $43?4 will point
  59. to a HDMA table. The transfer bytes register at $43?5 is not
  60. used.
  61. The format of the HDMA table depends on the value you have
  62. written to the DMA channel control register. If you have
  63. written $00 then a byte will be written to the selected
  64. graphics register each scan line. The table should have the
  65. following format.
  66. hdma_table
  67. Byte n ; number of bytes that follow (7-bit value 0..127)
  68. Byte value_1, value_2, value_3 ... value_n
  69. Byte n ; number of bytes that follow (7-bit value 0..127)
  70. Byte value_1, value_2, value_3 ... value_n
  71. .
  72. etc
  73. .
  74. Byte 0 ; ends list
  75. The table is made up of a number of entries. The first byte
  76. in each entry is a count on the number of bytes that follow.
  77. The table is terminated by a 0 entry.
  78. If you have written $02 to the DMA channel control register
  79. then a word will be written to the selected graphics register
  80. each scan line. The table should have the following format.
  81. hdma_table
  82. Byte n ; # times to repeat next word (7-bit value 0..127)
  83. Word value
  84. Byte n ; # times to repeat next word (7-bit value 0..127)
  85. Word value
  86. .
  87. etc
  88. .
  89. Byte 0 ; ends list
  90. The table is made up of a number of entries. The first byte of
  91. each entry indicates the number of times the following word is
  92. to be repeated. The table is terminated by a 0 entry.
  93. The only other thing you'll need to know is that there is a
  94. HDMA control register.
  95. Byte $420C HDMA control register
  96. This is the same format as the DMA control register at $420B,
  97. ie. bit 0 enables HDMA channel 0, bit 1 enables channel 1 etc...
  98. For example, suppose halfway down the screen I want to scroll
  99. graphics plane 0 left by 128 pixels.
  100. lda #$02 ; word format HDMA (count, word)
  101. sta $4300
  102. lda #$0D ; plane 0 x-scroll at $210D
  103. sta $4301
  104. ldx.w #hdma_table&$FFFF ; hdma table offset
  105. stx $4302
  106. lda #hdma_table/$10000 ; hdma table bank
  107. sta $4304
  108. lda #$01 ; enable HDMA channel 0
  109. sta $420c
  110. .
  111. .
  112. .
  113. hdma_table
  114. dc.b 112 ; for first 112 scan lines
  115. dc.w 0 ; set plane 0 x-scroll to 0
  116. dc.b 1 ; on next scan line
  117. dc.w 128 ; set plane 0 x-scroll to 128
  118. dc.b 0
  119. You can use HDMA channels in combination, ie. you could use HDMA
  120. channel 0 to select a colour register and HDMA channel 1 to write
  121. the RGB data for that colour register.
  122. I don't have access to any of the official Nintendo documentation
  123. so I may not have entirely understood everything about HDMA but
  124. this is a much as I've been able to work out. Maybe there are other
  125. (H)DMA modes too?
  126. I'll should have put a simple HDMA demo with source code on the
  127. busop.cit.wayne.edu ftp site (in pub/famidev/incoming/hdmademo.zip).
  128. Hope that helps.
  129. Paul.