addrmode.txt 16 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515
  1. G65SC802 and G65SC816
  2. Microprocessor Addressing modes
  3. The G65SC816 is capable of directly addressing 16 MBytes of memory.
  4. This address space has special significance within certain addressing
  5. modes, as follows:
  6. Reset and Interrupt Vectors
  7. The Reset and Interrupt vectors use the majority of the fixed addresses
  8. between 00FFE0 and 00FFFF.
  9. Stack
  10. The Native mode Stack address will always be within the range 000000 to
  11. 00FFFF. In the Emulation mode, the Stack address range is 000100 to 0001FF.
  12. The following opcodes and addressing modes can increment or decrement beyond
  13. this range when accessing two or three bytes:
  14. JSL; JSR (a,x); PEA; PEI; PER; PHD; PLD; RTL; d,s; (d,s),y.
  15. Direct
  16. The Direct addressing modes are often used to access memory registers and
  17. pointers. The contents of the Direct Register (D) is added to the offset
  18. contained in the instruction operand to produce an address in the range 000000
  19. to 00FFFF. Note that in the Emulation mode, [Direct] and [Direct],y addressing
  20. modes and the PEI instruction will increment from 0000FE or 0000FF into the
  21. Stack area, even if D=0.
  22. Program Address Space
  23. The Program Bank register is not affected by the Relative, Relative Long,
  24. Absolute, Absolute Indirect, and Absolute Indexed Indirect addressing modes
  25. or by incrementing the Program Counter from FFFF. The only instructions that
  26. affect the Program Bank register are: RTI, RTL, JML, JSL, and JMP Absolute
  27. Long. Program code may exceed 64K bytes altough code segments may not span
  28. bank boundaries.
  29. Data Address Space
  30. The data address space is contiguous throughout the 16 MByte address space.
  31. Words, arrays, records, or any data structures may span 64K byte bank
  32. boundaries with no compromise in code efficiency. As a result, indexing from
  33. page FF in the G65SC802 may result in data accessed in page zero. The
  34. following addressing modes generate 24-bit effective addresses.
  35. * Direct Indexed Indirect (d,x)
  36. * Direct Indirect Indexed (d),y
  37. * Direct Indirect (d)
  38. * Direct Indirect Long [d]
  39. * Direct Indirect Indexed Long [d],y
  40. * Absolute
  41. * Absolute,x
  42. * Absolute,y
  43. * Absolute long
  44. * Absolute long indexed
  45. * Stack Relative Indirect Indexed (d,s),y
  46. The following addressing mode descriptions provide additional detail as
  47. to how effective addresses are calculated.
  48. Twenty-four addressing modes are available for use with the G65SC802
  49. and G65SC816 microprocessors. The "long" addressing modes may be
  50. used with the G65SC802; however, the high byte of the address is not
  51. available to the hardware. Detailed descriptions of the 24 addressing
  52. modes are as follows:
  53. 1. Immediate Addressing -- #
  54. The operand is the second byte (second and third bytes when in the 16-bit
  55. mode) of the instruction.
  56. 2. Absolute -- a
  57. With Absolute addressing the second and third bytes of the instruction form
  58. the low-order 16 bits of the effective address. The Data Bank Register
  59. contains the high-order 8 bits of the operand address.
  60. __________________________
  61. Instruction: | opcode | addrl | addrh |
  62. ~~~~~~~~~~~~~~~~~~~~~~~~~~
  63. Operand
  64. Address: | DB | addrh | addrl |
  65. 3. Absolute Long -- al
  66. The second, third, and fourth byte of the instruction form the 24-bit
  67. effective address.
  68. __________________________________
  69. Instruction: | opcode | addrl | addrh | baddr |
  70. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  71. Operand
  72. Address: | baddr | addrh | addrl |
  73. 4. Direct -- d
  74. The second byte of the instruction is added to the Direct Register
  75. (D) to form the effective address. An additional cycle is required
  76. when the Direct Register is not page aligned (DL not equal 0). The
  77. Bank register is always 0.
  78. ___________________
  79. Instruction: | opcode | offset |
  80. ~~~~~~~~~~~~~~~~~~~
  81. | Direct Register |
  82. + | offset |
  83. ---------------------
  84. Operand
  85. Address: | 00 | effective address |
  86. 5. Accumulator -- A
  87. This form of addressing always uses a single byte instruction. The
  88. operand is the Accumulator.
  89. 6. Implied -- i
  90. Implied addressing uses a single byte instruction. The operand is implicitly
  91. defined by the instruction.
  92. 7. Direct Indirect Indexed -- (d),y
  93. This address mode is often referred to as Indirect,Y. The second byte of the
  94. instruction is added to the Direct Register (D). The 16-bit contents of this
  95. memory location is then combined with the Data Bank register to form a 24-bit
  96. base address. The Y Index Register is added to the base address to form the
  97. effective address.
  98. ___________________
  99. Instruction: | opcode | offset |
  100. ~~~~~~~~~~~~~~~~~~~
  101. | Direct Register |
  102. + | offset |
  103. ---------------------
  104. | 00 | direct address |
  105. then:
  106. | 00 | (direct address) |
  107. + | DB |
  108. -------------------------------
  109. | base address |
  110. + | | Y Reg |
  111. ------------------------------
  112. Operand
  113. Address: | effective address |
  114. 8. Direct Indirect Indexed Long -- [d],y
  115. With this addressing mode the 24-bit base address is pointed to by
  116. the sum of the second byte of the instruction and the Direct
  117. Register The effective address is this 24-bit base address plus the Y
  118. Index Register
  119. ___________________
  120. Instruction: | opcode | offset |
  121. ~~~~~~~~~~~~~~~~~~~
  122. | Direct Register |
  123. + | offset |
  124. ---------------------
  125. | 00 | direct address |
  126. then:
  127. | (direct address) |
  128. + | | Y Reg |
  129. ------------------------------
  130. Operand
  131. Address: | effective address |
  132. 9. Direct Indexed Indirect -- (d,x)
  133. This address mode is often referred to as Indirect X The second
  134. byte of the Instruction is added to the sum of the Direct Register
  135. and the X Index Register. The result points to the low-order 16 bits
  136. of the effective address. The Data Bank Register contains the high-
  137. order 8 bits of the effective address.
  138. ___________________
  139. Instruction: | opcode | offset |
  140. ~~~~~~~~~~~~~~~~~~~
  141. | Direct Register |
  142. + | offset |
  143. ---------------------
  144. | direct address |
  145. + | | X Reg |
  146. ---------------------
  147. | 00 | address |
  148. then:
  149. | 00 | (address) |
  150. + | DB |
  151. -------------------------------
  152. Operand
  153. Address: | effective address |
  154. 10. Direct Indexed With X -- d,x
  155. The second byte of the instruction is added to the sum of the Direct Register
  156. and the X Index Register to form the 16-bit effective address. The operand is
  157. always in Bank 0.
  158. ___________________
  159. Instruction: | opcode | offset |
  160. ~~~~~~~~~~~~~~~~~~~
  161. | Direct Register |
  162. + | offset |
  163. ---------------------
  164. | direct address |
  165. + | | X Reg |
  166. -------------------------------
  167. Operand
  168. Address: | 00 | effective address |
  169. 11. Direct Indexed With Y -- d,y
  170. The second byte of the instruction is added to the sum of the Direct Register
  171. and the Y Index Register to form the 16-bit effective address. The operand is
  172. always in Bank 0.
  173. ___________________
  174. Instruction: | opcode | offset |
  175. ~~~~~~~~~~~~~~~~~~~
  176. | Direct Register |
  177. + | offset |
  178. ---------------------
  179. | direct address |
  180. + | | Y Reg |
  181. -------------------------------
  182. Operand
  183. Address: | 00 | effective address |
  184. 12. Absolute Indexed With X -- a,x
  185. The second and third bytes of the instruction are added to the
  186. X Index Register to form the low-order 16 bits of the ef~ective ad-
  187. dress The Data Bank Register contains the high-order 8 bits of the
  188. effective address
  189. ____________________________
  190. Instruction: | opcode | addrl | addrh |
  191. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  192. | DB | addrrh | addrl |
  193. + | | X Reg |
  194. -------------------------------
  195. Operand
  196. Address: | effective address |
  197. 13. Absolute Indexed With Y -- a,y
  198. The second and third bytes of the instruction are added to the
  199. Y Index Register to form the low-order 16 bits of the eftective ad-
  200. dress The Data Bank Register contains the high-order 8 bits of tne
  201. effective address.
  202. ____________________________
  203. Instruction: | opcode | addrl | addrh |
  204. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  205. | DB | addrrh | addrl |
  206. + | | Y Reg |
  207. -------------------------------
  208. Operand
  209. Address: | effective address |
  210. 14. Absolute Long Indexed With X -- al,x
  211. The second third and fourth bytes ot the instruction form a 24-bit base
  212. address. The effective address is the sum of this 24-bit address and the
  213. X Index Register.
  214. ____________________________________
  215. Instruction: | opcode | addrl | addrh | baddr |
  216. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  217. | baddr | addrrh | addrl |
  218. + | | X Reg |
  219. -------------------------------
  220. Operand
  221. Address: | effective address |
  222. 15. Program Counter Relative -- r
  223. This address mode referred to as Relative Addressing is used only with the
  224. Branch instructions. If the conditlon being tested is met, the second byte
  225. of the instruction is added to the Program Counter, which has been updated
  226. to point to the opcode of the next instruction. The offset is a signed 8-bit
  227. quantity in the range from -128 to 127 The Program Bank Register is not
  228. affected.
  229. 16. Program Counter Relative Long -- rl
  230. This address mode referred to as Relative Long Addressing is used only with
  231. the Unconditional Branch Long instruction (BRL) and the Push Effective
  232. Relative instruction (PER). The second and third 2 bytes of the instruction
  233. are added to the Program Counter which has been updated to point to the opcode
  234. of the next instruction. With the branch instruction the Program Counter is
  235. loaded with the result With the Push Effective Relative instruction the result
  236. is stored on the stack. The offset and result are both an unsigned 16-bit
  237. quantity in the range 0 to 65535.
  238. 17. Absolute Indirect -- (a)
  239. The second and third bytes of the instruction form an address to a pointer
  240. in Bank 0. The Program Counter is loaded with the first and second bytes at
  241. this pointer With the Jump Long (JML) instruction the Program Bank Register
  242. is loaded with the third byte of the pointer
  243. ____________________________
  244. Instruction: | opcode | addrl | addrh |
  245. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  246. | baddr | addrrh | addrl |
  247. Indirect Address = | 00 | addrh | addrl |
  248. New PC = (indirect address)
  249. with JML:
  250. New PC = (indirect address)
  251. New PB = (indirect address +2)
  252. 18. Direct Indirect -- (d)
  253. The second byte of the instruction is added to the Direct Register to form
  254. a pointer to the low-order 16 bits of the effective address. The Data Bank
  255. Register contains the high-order 8 bits of the effective address.
  256. ___________________
  257. Instruction: | opcode | offset |
  258. ~~~~~~~~~~~~~~~~~~~
  259. | Direct Register |
  260. + | offset |
  261. ---------------------
  262. | 00 | direct address |
  263. then:
  264. | 00 | (direct address) |
  265. + | DB |
  266. -------------------------------
  267. Operand
  268. Address: | effective address |
  269. 19. Direct Indirect Long -- [d]
  270. The second byte of the instruction is added to the Direct Register to form
  271. a pointer to the 24-bit effective address.
  272. ___________________
  273. Instruction: | opcode | offset |
  274. ~~~~~~~~~~~~~~~~~~~
  275. | Direct Register |
  276. + | offset |
  277. ---------------------
  278. | 00 | direct address |
  279. then:
  280. -------------------------------
  281. Operand
  282. Address: | (direct address) |
  283. 20. Absolute Indexed Indirect -- (a,x)
  284. The second and third bytes of the instruction are added to the X Index
  285. Register to form a 16-bit pointer in Bank 0. The contents of this pointer
  286. are loaded in the Program Counter. The Program Bank Register is not changed.
  287. ____________________________
  288. Instruction: | opcode | addrl | addrh |
  289. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  290. | addrrh | addrl |
  291. + | | X Reg |
  292. -------------------------------
  293. | 00 | address |
  294. then:
  295. PC = (address)
  296. 21. Stack -- s
  297. Stack addressing refers to all instructions that push or pull data from the
  298. stack such as Push, Pull, Jump to Subroutine, Return from Subroutine,
  299. Interrupts, and Return from Interrupt. The bank address is always 0.
  300. Interrupt Vectors are always fetched from Bank 0.
  301. 22. Stack Relative -- d,s
  302. The low-order 16 bits of the effective address is formed from the sum of the
  303. second byte of the instruction and the Stack Pointer. The high-order 8 bits
  304. of the effective address is always zero. The relative offset is an unsigned
  305. 8-bit quantity in the range of 0 to 255.
  306. ___________________
  307. Instruction: | opcode | offset |
  308. ~~~~~~~~~~~~~~~~~~~
  309. | Stack Pointer |
  310. + | offset |
  311. ---------------------
  312. | 00 | effective address |
  313. 23. Stack Relative Indirect Indexed -- (d,s),y
  314. The second byte of the instruction is added to the Stack Pointer to form
  315. a pointer to the low-order 16-bit base address in Bank 0. The Data Bank
  316. Register contains the high-order 8 bits of the base address. The effective
  317. address is the sum of the 24-bit base address and the Y Index Register.
  318. ___________________
  319. Instruction: | opcode | offset |
  320. ~~~~~~~~~~~~~~~~~~~
  321. | Stack Pointer |
  322. + | offset |
  323. ---------------------
  324. | 00 | S + offset |
  325. then:
  326. | S + offset |
  327. + | DB |
  328. -------------------------------
  329. | base address |
  330. + | | Y Reg |
  331. ------------------------------
  332. Operand
  333. Address: | effective address |
  334. 24. Block Source Bank, Destination Bank -- xyc
  335. This addressing mode is used by the Block Move instructions.
  336. The second byte of the instruction contains the high-order 8 bits of the
  337. destination address.
  338. The Y Index Register contains the low-order 16 bits of the destination
  339. address. The third byte of the instruction contains the high-order 8 bits
  340. of the source address.
  341. The X Index Register contains the low-order 16 bits of the source address.
  342. The Accumulator contains one less than the number of bytes to move.
  343. The second byte of the block move instructions is also loaded into the Data
  344. Bank Register.
  345. ____________________________
  346. Instruction: | opcode | dstbnk | srcbnk |
  347. ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
  348. dstbnk -> DB
  349. Source Address: | scrbnk | X reg |
  350. Destination Address: | DB | Y reg |
  351. Increment (MVN) or decrement (MVP) X and Y.
  352. Decrement A (if greaterthan zero) then PC-3 -> PC.