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- G65SC802 and G65SC816
- Microprocessor Addressing modes
- The G65SC816 is capable of directly addressing 16 MBytes of memory.
- This address space has special significance within certain addressing
- modes, as follows:
- Reset and Interrupt Vectors
- The Reset and Interrupt vectors use the majority of the fixed addresses
- between 00FFE0 and 00FFFF.
- Stack
- The Native mode Stack address will always be within the range 000000 to
- 00FFFF. In the Emulation mode, the Stack address range is 000100 to 0001FF.
- The following opcodes and addressing modes can increment or decrement beyond
- this range when accessing two or three bytes:
- JSL; JSR (a,x); PEA; PEI; PER; PHD; PLD; RTL; d,s; (d,s),y.
- Direct
- The Direct addressing modes are often used to access memory registers and
- pointers. The contents of the Direct Register (D) is added to the offset
- contained in the instruction operand to produce an address in the range 000000
- to 00FFFF. Note that in the Emulation mode, [Direct] and [Direct],y addressing
- modes and the PEI instruction will increment from 0000FE or 0000FF into the
- Stack area, even if D=0.
- Program Address Space
- The Program Bank register is not affected by the Relative, Relative Long,
- Absolute, Absolute Indirect, and Absolute Indexed Indirect addressing modes
- or by incrementing the Program Counter from FFFF. The only instructions that
- affect the Program Bank register are: RTI, RTL, JML, JSL, and JMP Absolute
- Long. Program code may exceed 64K bytes altough code segments may not span
- bank boundaries.
- Data Address Space
- The data address space is contiguous throughout the 16 MByte address space.
- Words, arrays, records, or any data structures may span 64K byte bank
- boundaries with no compromise in code efficiency. As a result, indexing from
- page FF in the G65SC802 may result in data accessed in page zero. The
- following addressing modes generate 24-bit effective addresses.
- * Direct Indexed Indirect (d,x)
- * Direct Indirect Indexed (d),y
- * Direct Indirect (d)
- * Direct Indirect Long [d]
- * Direct Indirect Indexed Long [d],y
- * Absolute
- * Absolute,x
- * Absolute,y
- * Absolute long
- * Absolute long indexed
- * Stack Relative Indirect Indexed (d,s),y
- The following addressing mode descriptions provide additional detail as
- to how effective addresses are calculated.
- Twenty-four addressing modes are available for use with the G65SC802
- and G65SC816 microprocessors. The "long" addressing modes may be
- used with the G65SC802; however, the high byte of the address is not
- available to the hardware. Detailed descriptions of the 24 addressing
- modes are as follows:
- 1. Immediate Addressing -- #
- The operand is the second byte (second and third bytes when in the 16-bit
- mode) of the instruction.
- 2. Absolute -- a
- With Absolute addressing the second and third bytes of the instruction form
- the low-order 16 bits of the effective address. The Data Bank Register
- contains the high-order 8 bits of the operand address.
- __________________________
- Instruction: | opcode | addrl | addrh |
- ~~~~~~~~~~~~~~~~~~~~~~~~~~
- Operand
- Address: | DB | addrh | addrl |
- 3. Absolute Long -- al
- The second, third, and fourth byte of the instruction form the 24-bit
- effective address.
- __________________________________
- Instruction: | opcode | addrl | addrh | baddr |
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- Operand
- Address: | baddr | addrh | addrl |
- 4. Direct -- d
- The second byte of the instruction is added to the Direct Register
- (D) to form the effective address. An additional cycle is required
- when the Direct Register is not page aligned (DL not equal 0). The
- Bank register is always 0.
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Direct Register |
- + | offset |
- ---------------------
- Operand
- Address: | 00 | effective address |
- 5. Accumulator -- A
- This form of addressing always uses a single byte instruction. The
- operand is the Accumulator.
- 6. Implied -- i
- Implied addressing uses a single byte instruction. The operand is implicitly
- defined by the instruction.
- 7. Direct Indirect Indexed -- (d),y
- This address mode is often referred to as Indirect,Y. The second byte of the
- instruction is added to the Direct Register (D). The 16-bit contents of this
- memory location is then combined with the Data Bank register to form a 24-bit
- base address. The Y Index Register is added to the base address to form the
- effective address.
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Direct Register |
- + | offset |
- ---------------------
- | 00 | direct address |
- then:
- | 00 | (direct address) |
- + | DB |
- -------------------------------
- | base address |
- + | | Y Reg |
- ------------------------------
- Operand
- Address: | effective address |
- 8. Direct Indirect Indexed Long -- [d],y
- With this addressing mode the 24-bit base address is pointed to by
- the sum of the second byte of the instruction and the Direct
- Register The effective address is this 24-bit base address plus the Y
- Index Register
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Direct Register |
- + | offset |
- ---------------------
- | 00 | direct address |
- then:
- | (direct address) |
- + | | Y Reg |
- ------------------------------
- Operand
- Address: | effective address |
- 9. Direct Indexed Indirect -- (d,x)
- This address mode is often referred to as Indirect X The second
- byte of the Instruction is added to the sum of the Direct Register
- and the X Index Register. The result points to the low-order 16 bits
- of the effective address. The Data Bank Register contains the high-
- order 8 bits of the effective address.
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Direct Register |
- + | offset |
- ---------------------
- | direct address |
- + | | X Reg |
- ---------------------
- | 00 | address |
- then:
- | 00 | (address) |
- + | DB |
- -------------------------------
- Operand
- Address: | effective address |
- 10. Direct Indexed With X -- d,x
- The second byte of the instruction is added to the sum of the Direct Register
- and the X Index Register to form the 16-bit effective address. The operand is
- always in Bank 0.
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Direct Register |
- + | offset |
- ---------------------
- | direct address |
- + | | X Reg |
- -------------------------------
- Operand
- Address: | 00 | effective address |
- 11. Direct Indexed With Y -- d,y
- The second byte of the instruction is added to the sum of the Direct Register
- and the Y Index Register to form the 16-bit effective address. The operand is
- always in Bank 0.
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Direct Register |
- + | offset |
- ---------------------
- | direct address |
- + | | Y Reg |
- -------------------------------
- Operand
- Address: | 00 | effective address |
- 12. Absolute Indexed With X -- a,x
- The second and third bytes of the instruction are added to the
- X Index Register to form the low-order 16 bits of the ef~ective ad-
- dress The Data Bank Register contains the high-order 8 bits of the
- effective address
- ____________________________
- Instruction: | opcode | addrl | addrh |
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- | DB | addrrh | addrl |
- + | | X Reg |
- -------------------------------
- Operand
- Address: | effective address |
- 13. Absolute Indexed With Y -- a,y
- The second and third bytes of the instruction are added to the
- Y Index Register to form the low-order 16 bits of the eftective ad-
- dress The Data Bank Register contains the high-order 8 bits of tne
- effective address.
- ____________________________
- Instruction: | opcode | addrl | addrh |
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- | DB | addrrh | addrl |
- + | | Y Reg |
- -------------------------------
- Operand
- Address: | effective address |
- 14. Absolute Long Indexed With X -- al,x
- The second third and fourth bytes ot the instruction form a 24-bit base
- address. The effective address is the sum of this 24-bit address and the
- X Index Register.
- ____________________________________
- Instruction: | opcode | addrl | addrh | baddr |
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- | baddr | addrrh | addrl |
- + | | X Reg |
- -------------------------------
- Operand
- Address: | effective address |
- 15. Program Counter Relative -- r
- This address mode referred to as Relative Addressing is used only with the
- Branch instructions. If the conditlon being tested is met, the second byte
- of the instruction is added to the Program Counter, which has been updated
- to point to the opcode of the next instruction. The offset is a signed 8-bit
- quantity in the range from -128 to 127 The Program Bank Register is not
- affected.
- 16. Program Counter Relative Long -- rl
- This address mode referred to as Relative Long Addressing is used only with
- the Unconditional Branch Long instruction (BRL) and the Push Effective
- Relative instruction (PER). The second and third 2 bytes of the instruction
- are added to the Program Counter which has been updated to point to the opcode
- of the next instruction. With the branch instruction the Program Counter is
- loaded with the result With the Push Effective Relative instruction the result
- is stored on the stack. The offset and result are both an unsigned 16-bit
- quantity in the range 0 to 65535.
- 17. Absolute Indirect -- (a)
- The second and third bytes of the instruction form an address to a pointer
- in Bank 0. The Program Counter is loaded with the first and second bytes at
- this pointer With the Jump Long (JML) instruction the Program Bank Register
- is loaded with the third byte of the pointer
- ____________________________
- Instruction: | opcode | addrl | addrh |
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- | baddr | addrrh | addrl |
- Indirect Address = | 00 | addrh | addrl |
- New PC = (indirect address)
- with JML:
- New PC = (indirect address)
- New PB = (indirect address +2)
- 18. Direct Indirect -- (d)
- The second byte of the instruction is added to the Direct Register to form
- a pointer to the low-order 16 bits of the effective address. The Data Bank
- Register contains the high-order 8 bits of the effective address.
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Direct Register |
- + | offset |
- ---------------------
- | 00 | direct address |
- then:
- | 00 | (direct address) |
- + | DB |
- -------------------------------
- Operand
- Address: | effective address |
- 19. Direct Indirect Long -- [d]
- The second byte of the instruction is added to the Direct Register to form
- a pointer to the 24-bit effective address.
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Direct Register |
- + | offset |
- ---------------------
- | 00 | direct address |
- then:
- -------------------------------
- Operand
- Address: | (direct address) |
- 20. Absolute Indexed Indirect -- (a,x)
- The second and third bytes of the instruction are added to the X Index
- Register to form a 16-bit pointer in Bank 0. The contents of this pointer
- are loaded in the Program Counter. The Program Bank Register is not changed.
- ____________________________
- Instruction: | opcode | addrl | addrh |
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- | addrrh | addrl |
- + | | X Reg |
- -------------------------------
- | 00 | address |
- then:
- PC = (address)
- 21. Stack -- s
- Stack addressing refers to all instructions that push or pull data from the
- stack such as Push, Pull, Jump to Subroutine, Return from Subroutine,
- Interrupts, and Return from Interrupt. The bank address is always 0.
- Interrupt Vectors are always fetched from Bank 0.
- 22. Stack Relative -- d,s
- The low-order 16 bits of the effective address is formed from the sum of the
- second byte of the instruction and the Stack Pointer. The high-order 8 bits
- of the effective address is always zero. The relative offset is an unsigned
- 8-bit quantity in the range of 0 to 255.
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Stack Pointer |
- + | offset |
- ---------------------
- | 00 | effective address |
- 23. Stack Relative Indirect Indexed -- (d,s),y
- The second byte of the instruction is added to the Stack Pointer to form
- a pointer to the low-order 16-bit base address in Bank 0. The Data Bank
- Register contains the high-order 8 bits of the base address. The effective
- address is the sum of the 24-bit base address and the Y Index Register.
- ___________________
- Instruction: | opcode | offset |
- ~~~~~~~~~~~~~~~~~~~
- | Stack Pointer |
- + | offset |
- ---------------------
- | 00 | S + offset |
- then:
- | S + offset |
- + | DB |
- -------------------------------
- | base address |
- + | | Y Reg |
- ------------------------------
- Operand
- Address: | effective address |
- 24. Block Source Bank, Destination Bank -- xyc
- This addressing mode is used by the Block Move instructions.
- The second byte of the instruction contains the high-order 8 bits of the
- destination address.
- The Y Index Register contains the low-order 16 bits of the destination
- address. The third byte of the instruction contains the high-order 8 bits
- of the source address.
- The X Index Register contains the low-order 16 bits of the source address.
- The Accumulator contains one less than the number of bytes to move.
- The second byte of the block move instructions is also loaded into the Data
- Bank Register.
- ____________________________
- Instruction: | opcode | dstbnk | srcbnk |
- ~~~~~~~~~~~~~~~~~~~~~~~~~~~~
- dstbnk -> DB
- Source Address: | scrbnk | X reg |
- Destination Address: | DB | Y reg |
- Increment (MVN) or decrement (MVP) X and Y.
- Decrement A (if greaterthan zero) then PC-3 -> PC.
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