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@@ -20,6 +20,13 @@
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#include "renesas-cpg-mssr.h"
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#include "rcar-gen3-cpg.h"
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+#define CPG_SD0CKCR 0x0074
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+
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+enum r8a77970_clk_types {
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+ CLK_TYPE_R8A77970_SD0H = CLK_TYPE_GEN3_SOC_BASE,
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+ CLK_TYPE_R8A77970_SD0,
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+};
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+
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enum clk_ids {
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/* Core Clock Outputs exported to DT */
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LAST_DT_CORE_CLK = R8A77970_CLK_OSC,
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@@ -32,24 +39,9 @@ enum clk_ids {
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CLK_MAIN,
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CLK_PLL0,
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CLK_PLL1,
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- CLK_PLL2,
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CLK_PLL3,
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- CLK_PLL4,
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CLK_PLL1_DIV2,
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CLK_PLL1_DIV4,
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- CLK_PLL0D2,
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- CLK_PLL0D3,
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- CLK_PLL0D5,
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- CLK_PLL1D2,
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- CLK_PE,
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- CLK_S0,
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- CLK_S1,
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- CLK_S2,
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- CLK_S3,
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- CLK_SDSRC,
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- CLK_RPCSRC,
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- CLK_SSPSRC,
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- CLK_RINT,
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/* Module Clocks */
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MOD_CLK_BASE
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@@ -57,67 +49,80 @@ enum clk_ids {
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static const struct cpg_core_clk r8a77970_core_clks[] = {
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/* External Clock Inputs */
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- DEF_INPUT("extal", CLK_EXTAL),
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- DEF_INPUT("extalr", CLK_EXTALR),
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+ DEF_INPUT("extal", CLK_EXTAL),
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+ DEF_INPUT("extalr", CLK_EXTALR),
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/* Internal Core Clocks */
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- DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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- DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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- DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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- DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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+ DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
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+ DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
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+ DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
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+ DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
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- DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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- DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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- DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 4, 1),
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- DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 6, 1),
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- DEF_FIXED(".rpcsrc", CLK_RPCSRC, CLK_PLL1, 2, 1),
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+ DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
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+ DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
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/* Core Clock Outputs */
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- DEF_BASE("z2", R8A77970_CLK_Z2, CLK_TYPE_GEN3_Z2, CLK_PLL1_DIV4),
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- DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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- DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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- DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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- DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
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- DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_S1, 1, 1),
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- DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_S1, 2, 1),
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- DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_S1, 4, 1),
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- DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_S2, 1, 1),
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- DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_S2, 2, 1),
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- DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_S2, 4, 1),
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-
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- DEF_GEN3_SD("sd0", R8A77970_CLK_SD0, CLK_PLL1_DIV4, 0x0074),
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-
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- DEF_GEN3_RPC("rpc", R8A77970_CLK_RPC, CLK_RPCSRC, 0x238),
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-
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- DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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- DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
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-
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- /* NOTE: HDMI, CSI, CAN etc. clock are missing */
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-
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- DEF_BASE("r", R8A77970_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
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+ DEF_FIXED("ztr", R8A77970_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
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+ DEF_FIXED("ztrd2", R8A77970_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
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+ DEF_FIXED("zt", R8A77970_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
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+ DEF_FIXED("zx", R8A77970_CLK_ZX, CLK_PLL1_DIV2, 3, 1),
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+ DEF_FIXED("s1d1", R8A77970_CLK_S1D1, CLK_PLL1_DIV2, 4, 1),
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+ DEF_FIXED("s1d2", R8A77970_CLK_S1D2, CLK_PLL1_DIV2, 8, 1),
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+ DEF_FIXED("s1d4", R8A77970_CLK_S1D4, CLK_PLL1_DIV2, 16, 1),
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+ DEF_FIXED("s2d1", R8A77970_CLK_S2D1, CLK_PLL1_DIV2, 6, 1),
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+ DEF_FIXED("s2d2", R8A77970_CLK_S2D2, CLK_PLL1_DIV2, 12, 1),
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+ DEF_FIXED("s2d4", R8A77970_CLK_S2D4, CLK_PLL1_DIV2, 24, 1),
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+
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+ DEF_BASE("sd0h", R8A77970_CLK_SD0H, CLK_TYPE_R8A77970_SD0H,
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+ CLK_PLL1_DIV2),
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+ DEF_BASE("sd0", R8A77970_CLK_SD0, CLK_TYPE_R8A77970_SD0, CLK_PLL1_DIV2),
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+
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+ DEF_FIXED("rpc", R8A77970_CLK_RPC, CLK_PLL1_DIV2, 5, 1),
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+ DEF_FIXED("rpcd2", R8A77970_CLK_RPCD2, CLK_PLL1_DIV2, 10, 1),
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+
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+ DEF_FIXED("cl", R8A77970_CLK_CL, CLK_PLL1_DIV2, 48, 1),
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+ DEF_FIXED("cp", R8A77970_CLK_CP, CLK_EXTAL, 2, 1),
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+ DEF_FIXED("cpex", R8A77970_CLK_CPEX, CLK_EXTAL, 2, 1),
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+
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+ DEF_DIV6P1("canfd", R8A77970_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
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+ DEF_DIV6P1("mso", R8A77970_CLK_MSO, CLK_PLL1_DIV4, 0x014),
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+ DEF_DIV6P1("csi0", R8A77970_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
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+
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+ DEF_FIXED("osc", R8A77970_CLK_OSC, CLK_PLL1_DIV2, 12*1024, 1),
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+ DEF_FIXED("r", R8A77970_CLK_R, CLK_EXTALR, 1, 1),
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};
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static const struct mssr_mod_clk r8a77970_mod_clks[] = {
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+ DEF_MOD("tmu4", 121, R8A77970_CLK_S2D2),
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+ DEF_MOD("tmu3", 122, R8A77970_CLK_S2D2),
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+ DEF_MOD("tmu2", 123, R8A77970_CLK_S2D2),
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+ DEF_MOD("tmu1", 124, R8A77970_CLK_S2D2),
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+ DEF_MOD("tmu0", 125, R8A77970_CLK_CP),
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DEF_MOD("ivcp1e", 127, R8A77970_CLK_S2D1),
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- DEF_MOD("scif4", 203, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
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- DEF_MOD("scif3", 204, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
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- DEF_MOD("scif1", 206, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
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- DEF_MOD("scif0", 207, R8A77970_CLK_S2D4), /* @@ H3=S3D4 */
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+ DEF_MOD("scif4", 203, R8A77970_CLK_S2D4),
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+ DEF_MOD("scif3", 204, R8A77970_CLK_S2D4),
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+ DEF_MOD("scif1", 206, R8A77970_CLK_S2D4),
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+ DEF_MOD("scif0", 207, R8A77970_CLK_S2D4),
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DEF_MOD("msiof3", 208, R8A77970_CLK_MSO),
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DEF_MOD("msiof2", 209, R8A77970_CLK_MSO),
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DEF_MOD("msiof1", 210, R8A77970_CLK_MSO),
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DEF_MOD("msiof0", 211, R8A77970_CLK_MSO),
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- DEF_MOD("mfis", 213, R8A77970_CLK_S2D2), /* @@ H3=S3D2 */
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- DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
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- DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
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- DEF_MOD("sdif", 314, R8A77970_CLK_SD0),
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- DEF_MOD("rwdt0", 402, R8A77970_CLK_R),
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+ DEF_MOD("mfis", 213, R8A77970_CLK_S2D2),
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+ DEF_MOD("sys-dmac2", 217, R8A77970_CLK_S2D1),
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+ DEF_MOD("sys-dmac1", 218, R8A77970_CLK_S2D1),
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+ DEF_MOD("cmt3", 300, R8A77970_CLK_R),
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+ DEF_MOD("cmt2", 301, R8A77970_CLK_R),
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+ DEF_MOD("cmt1", 302, R8A77970_CLK_R),
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+ DEF_MOD("cmt0", 303, R8A77970_CLK_R),
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+ DEF_MOD("tpu0", 304, R8A77970_CLK_S2D4),
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+ DEF_MOD("sd-if", 314, R8A77970_CLK_SD0),
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+ DEF_MOD("rwdt", 402, R8A77970_CLK_R),
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DEF_MOD("intc-ex", 407, R8A77970_CLK_CP),
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- DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
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- DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
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- DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
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- DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
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- DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1), /* @@ H3=S3D1 */
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+ DEF_MOD("intc-ap", 408, R8A77970_CLK_S2D1),
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+ DEF_MOD("hscif3", 517, R8A77970_CLK_S2D1),
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+ DEF_MOD("hscif2", 518, R8A77970_CLK_S2D1),
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+ DEF_MOD("hscif1", 519, R8A77970_CLK_S2D1),
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+ DEF_MOD("hscif0", 520, R8A77970_CLK_S2D1),
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DEF_MOD("thermal", 522, R8A77970_CLK_CP),
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DEF_MOD("pwm", 523, R8A77970_CLK_S2D4),
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DEF_MOD("fcpvd0", 603, R8A77970_CLK_S2D1),
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@@ -130,7 +135,6 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
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DEF_MOD("vin1", 810, R8A77970_CLK_S2D1),
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DEF_MOD("vin0", 811, R8A77970_CLK_S2D1),
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DEF_MOD("etheravb", 812, R8A77970_CLK_S2D2),
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- DEF_MOD("isp", 817, R8A77970_CLK_S2D1),
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DEF_MOD("gpio5", 907, R8A77970_CLK_CP),
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DEF_MOD("gpio4", 908, R8A77970_CLK_CP),
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DEF_MOD("gpio3", 909, R8A77970_CLK_CP),
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@@ -138,7 +142,7 @@ static const struct mssr_mod_clk r8a77970_mod_clks[] = {
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DEF_MOD("gpio1", 911, R8A77970_CLK_CP),
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DEF_MOD("gpio0", 912, R8A77970_CLK_CP),
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DEF_MOD("can-fd", 914, R8A77970_CLK_S2D2),
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- DEF_MOD("rpc", 917, R8A77970_CLK_RPC),
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+ DEF_MOD("rpc-if", 917, R8A77970_CLK_RPC),
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DEF_MOD("i2c4", 927, R8A77970_CLK_S2D2),
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DEF_MOD("i2c3", 928, R8A77970_CLK_S2D2),
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DEF_MOD("i2c2", 929, R8A77970_CLK_S2D2),
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@@ -207,6 +211,7 @@ static const struct cpg_mssr_info r8a77970_cpg_mssr_info = {
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.mstp_table = r8a77970_mstp_table,
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.mstp_table_size = ARRAY_SIZE(r8a77970_mstp_table),
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.reset_node = "renesas,r8a77970-rst",
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+ .reset_modemr_offset = CPG_RST_MODEMR,
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.extalr_node = "extalr",
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.mod_clk_base = MOD_CLK_BASE,
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.clk_extal_id = CLK_EXTAL,
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