r8a7792-cpg-mssr.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a7792 Clock Pulse Generator / Module Standby and Software Reset
  4. *
  5. * Copyright (C) 2017 Glider bvba
  6. *
  7. * Based on clk-rcar-gen2.c
  8. *
  9. * Copyright (C) 2013 Ideas On Board SPRL
  10. */
  11. #include <common.h>
  12. #include <clk-uclass.h>
  13. #include <dm.h>
  14. #include <linux/bitops.h>
  15. #include <dt-bindings/clock/r8a7792-cpg-mssr.h>
  16. #include "renesas-cpg-mssr.h"
  17. #include "rcar-gen2-cpg.h"
  18. enum clk_ids {
  19. /* Core Clock Outputs exported to DT */
  20. LAST_DT_CORE_CLK = R8A7792_CLK_OSC,
  21. /* External Input Clocks */
  22. CLK_EXTAL,
  23. /* Internal Core Clocks */
  24. CLK_MAIN,
  25. CLK_PLL0,
  26. CLK_PLL1,
  27. CLK_PLL3,
  28. CLK_PLL1_DIV2,
  29. /* Module Clocks */
  30. MOD_CLK_BASE
  31. };
  32. static const struct cpg_core_clk r8a7792_core_clks[] = {
  33. /* External Clock Inputs */
  34. DEF_INPUT("extal", CLK_EXTAL),
  35. /* Internal Core Clocks */
  36. DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN2_MAIN, CLK_EXTAL),
  37. DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN2_PLL0, CLK_MAIN),
  38. DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN2_PLL1, CLK_MAIN),
  39. DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN2_PLL3, CLK_MAIN),
  40. DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
  41. /* Core Clock Outputs */
  42. DEF_BASE("qspi", R8A7792_CLK_QSPI, CLK_TYPE_GEN2_QSPI, CLK_PLL1_DIV2),
  43. DEF_FIXED("z", R8A7792_CLK_Z, CLK_PLL0, 1, 1),
  44. DEF_FIXED("zg", R8A7792_CLK_ZG, CLK_PLL1, 5, 1),
  45. DEF_FIXED("zx", R8A7792_CLK_ZX, CLK_PLL1, 3, 1),
  46. DEF_FIXED("zs", R8A7792_CLK_ZS, CLK_PLL1, 6, 1),
  47. DEF_FIXED("hp", R8A7792_CLK_HP, CLK_PLL1, 12, 1),
  48. DEF_FIXED("i", R8A7792_CLK_I, CLK_PLL1, 3, 1),
  49. DEF_FIXED("b", R8A7792_CLK_B, CLK_PLL1, 12, 1),
  50. DEF_FIXED("lb", R8A7792_CLK_LB, CLK_PLL1, 24, 1),
  51. DEF_FIXED("p", R8A7792_CLK_P, CLK_PLL1, 24, 1),
  52. DEF_FIXED("cl", R8A7792_CLK_CL, CLK_PLL1, 48, 1),
  53. DEF_FIXED("m2", R8A7792_CLK_M2, CLK_PLL1, 8, 1),
  54. DEF_FIXED("imp", R8A7792_CLK_IMP, CLK_PLL1, 4, 1),
  55. DEF_FIXED("zb3", R8A7792_CLK_ZB3, CLK_PLL3, 4, 1),
  56. DEF_FIXED("zb3d2", R8A7792_CLK_ZB3D2, CLK_PLL3, 8, 1),
  57. DEF_FIXED("ddr", R8A7792_CLK_DDR, CLK_PLL3, 8, 1),
  58. DEF_FIXED("sd", R8A7792_CLK_SD, CLK_PLL1_DIV2, 8, 1),
  59. DEF_FIXED("mp", R8A7792_CLK_MP, CLK_PLL1_DIV2, 15, 1),
  60. DEF_FIXED("cp", R8A7792_CLK_CP, CLK_PLL1, 48, 1),
  61. DEF_FIXED("cpex", R8A7792_CLK_CPEX, CLK_EXTAL, 2, 1),
  62. DEF_FIXED("rcan", R8A7792_CLK_RCAN, CLK_PLL1_DIV2, 49, 1),
  63. DEF_FIXED("r", R8A7792_CLK_R, CLK_PLL1, 49152, 1),
  64. DEF_FIXED("osc", R8A7792_CLK_OSC, CLK_PLL1, 12288, 1),
  65. };
  66. static const struct mssr_mod_clk r8a7792_mod_clks[] = {
  67. DEF_MOD("msiof0", 0, R8A7792_CLK_MP),
  68. DEF_MOD("jpu", 106, R8A7792_CLK_M2),
  69. DEF_MOD("tmu1", 111, R8A7792_CLK_P),
  70. DEF_MOD("3dg", 112, R8A7792_CLK_ZG),
  71. DEF_MOD("2d-dmac", 115, R8A7792_CLK_ZS),
  72. DEF_MOD("tmu3", 121, R8A7792_CLK_P),
  73. DEF_MOD("tmu2", 122, R8A7792_CLK_P),
  74. DEF_MOD("cmt0", 124, R8A7792_CLK_R),
  75. DEF_MOD("tmu0", 125, R8A7792_CLK_CP),
  76. DEF_MOD("vsp1du1", 127, R8A7792_CLK_ZS),
  77. DEF_MOD("vsp1du0", 128, R8A7792_CLK_ZS),
  78. DEF_MOD("vsps", 131, R8A7792_CLK_ZS),
  79. DEF_MOD("msiof1", 208, R8A7792_CLK_MP),
  80. DEF_MOD("sys-dmac1", 218, R8A7792_CLK_ZS),
  81. DEF_MOD("sys-dmac0", 219, R8A7792_CLK_ZS),
  82. DEF_MOD("tpu0", 304, R8A7792_CLK_CP),
  83. DEF_MOD("sdhi0", 314, R8A7792_CLK_SD),
  84. DEF_MOD("cmt1", 329, R8A7792_CLK_R),
  85. DEF_MOD("rwdt", 402, R8A7792_CLK_R),
  86. DEF_MOD("irqc", 407, R8A7792_CLK_CP),
  87. DEF_MOD("intc-sys", 408, R8A7792_CLK_ZS),
  88. DEF_MOD("audio-dmac0", 502, R8A7792_CLK_HP),
  89. DEF_MOD("thermal", 522, CLK_EXTAL),
  90. DEF_MOD("pwm", 523, R8A7792_CLK_P),
  91. DEF_MOD("hscif1", 716, R8A7792_CLK_ZS),
  92. DEF_MOD("hscif0", 717, R8A7792_CLK_ZS),
  93. DEF_MOD("scif3", 718, R8A7792_CLK_P),
  94. DEF_MOD("scif2", 719, R8A7792_CLK_P),
  95. DEF_MOD("scif1", 720, R8A7792_CLK_P),
  96. DEF_MOD("scif0", 721, R8A7792_CLK_P),
  97. DEF_MOD("du1", 723, R8A7792_CLK_ZX),
  98. DEF_MOD("du0", 724, R8A7792_CLK_ZX),
  99. DEF_MOD("vin5", 804, R8A7792_CLK_ZG),
  100. DEF_MOD("vin4", 805, R8A7792_CLK_ZG),
  101. DEF_MOD("vin3", 808, R8A7792_CLK_ZG),
  102. DEF_MOD("vin2", 809, R8A7792_CLK_ZG),
  103. DEF_MOD("vin1", 810, R8A7792_CLK_ZG),
  104. DEF_MOD("vin0", 811, R8A7792_CLK_ZG),
  105. DEF_MOD("etheravb", 812, R8A7792_CLK_HP),
  106. DEF_MOD("imr-lx3", 821, R8A7792_CLK_ZG),
  107. DEF_MOD("imr-lsx3-1", 822, R8A7792_CLK_ZG),
  108. DEF_MOD("imr-lsx3-0", 823, R8A7792_CLK_ZG),
  109. DEF_MOD("imr-lsx3-5", 825, R8A7792_CLK_ZG),
  110. DEF_MOD("imr-lsx3-4", 826, R8A7792_CLK_ZG),
  111. DEF_MOD("imr-lsx3-3", 827, R8A7792_CLK_ZG),
  112. DEF_MOD("imr-lsx3-2", 828, R8A7792_CLK_ZG),
  113. DEF_MOD("gyro-adc", 901, R8A7792_CLK_P),
  114. DEF_MOD("gpio7", 904, R8A7792_CLK_CP),
  115. DEF_MOD("gpio6", 905, R8A7792_CLK_CP),
  116. DEF_MOD("gpio5", 907, R8A7792_CLK_CP),
  117. DEF_MOD("gpio4", 908, R8A7792_CLK_CP),
  118. DEF_MOD("gpio3", 909, R8A7792_CLK_CP),
  119. DEF_MOD("gpio2", 910, R8A7792_CLK_CP),
  120. DEF_MOD("gpio1", 911, R8A7792_CLK_CP),
  121. DEF_MOD("gpio0", 912, R8A7792_CLK_CP),
  122. DEF_MOD("gpio11", 913, R8A7792_CLK_CP),
  123. DEF_MOD("gpio10", 914, R8A7792_CLK_CP),
  124. DEF_MOD("can1", 915, R8A7792_CLK_P),
  125. DEF_MOD("can0", 916, R8A7792_CLK_P),
  126. DEF_MOD("qspi_mod", 917, R8A7792_CLK_QSPI),
  127. DEF_MOD("gpio9", 919, R8A7792_CLK_CP),
  128. DEF_MOD("gpio8", 921, R8A7792_CLK_CP),
  129. DEF_MOD("i2c5", 925, R8A7792_CLK_HP),
  130. DEF_MOD("iicdvfs", 926, R8A7792_CLK_CP),
  131. DEF_MOD("i2c4", 927, R8A7792_CLK_HP),
  132. DEF_MOD("i2c3", 928, R8A7792_CLK_HP),
  133. DEF_MOD("i2c2", 929, R8A7792_CLK_HP),
  134. DEF_MOD("i2c1", 930, R8A7792_CLK_HP),
  135. DEF_MOD("i2c0", 931, R8A7792_CLK_HP),
  136. DEF_MOD("ssi-all", 1005, R8A7792_CLK_P),
  137. DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
  138. DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
  139. };
  140. /*
  141. * CPG Clock Data
  142. */
  143. /*
  144. * MD EXTAL PLL0 PLL1 PLL3
  145. * 14 13 19 (MHz) *1 *2
  146. *---------------------------------------------------
  147. * 0 0 0 15 x200/3 x208/2 x106
  148. * 0 0 1 15 x200/3 x208/2 x88
  149. * 0 1 0 20 x150/3 x156/2 x80
  150. * 0 1 1 20 x150/3 x156/2 x66
  151. * 1 0 0 26 / 2 x230/3 x240/2 x122
  152. * 1 0 1 26 / 2 x230/3 x240/2 x102
  153. * 1 1 0 30 / 2 x200/3 x208/2 x106
  154. * 1 1 1 30 / 2 x200/3 x208/2 x88
  155. *
  156. * *1 : Table 7.5b indicates VCO output (PLL0 = VCO/3)
  157. * *2 : Table 7.5b indicates VCO output (PLL1 = VCO/2)
  158. */
  159. #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 12) | \
  160. (((md) & BIT(13)) >> 12) | \
  161. (((md) & BIT(19)) >> 19))
  162. static const struct rcar_gen2_cpg_pll_config cpg_pll_configs[8] = {
  163. { 1, 208, 106, 200 },
  164. { 1, 208, 88, 200 },
  165. { 1, 156, 80, 150 },
  166. { 1, 156, 66, 150 },
  167. { 2, 240, 122, 230 },
  168. { 2, 240, 102, 230 },
  169. { 2, 208, 106, 200 },
  170. { 2, 208, 88, 200 },
  171. };
  172. static const struct mstp_stop_table r8a7792_mstp_table[] = {
  173. { 0x00400801, 0x400000, 0x00400801, 0x0 },
  174. { 0x9B6F987F, 0x0, 0x9B6F987F, 0x0 },
  175. { 0x108CE100, 0x0, 0x108CE100, 0x80000 },
  176. { 0x20004010, 0x4000, 0x20004010, 0x0 },
  177. { 0x80000184, 0x180, 0x80000184, 0x0 },
  178. { 0x44C00004, 0x0, 0x44C00004, 0x0 },
  179. { 0x0, 0x0, 0x0, 0x0 }, /* SMSTP6 is not present on Gen2 */
  180. { 0x01BF0000, 0x200000, 0x01BF0000, 0x0 },
  181. { 0x1FE01FB0, 0x0, 0x1FE01FB0, 0x0 },
  182. { 0xFE2BFFB2, 0x20000, 0xFE2BFFB2, 0x0 },
  183. { 0x00001820, 0x0, 0x00001820, 0x0 },
  184. { 0x00000008, 0x0, 0x00000008, 0x0 },
  185. };
  186. static const void *r8a7792_get_pll_config(const u32 cpg_mode)
  187. {
  188. return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
  189. }
  190. static const struct cpg_mssr_info r8a7792_cpg_mssr_info = {
  191. .core_clk = r8a7792_core_clks,
  192. .core_clk_size = ARRAY_SIZE(r8a7792_core_clks),
  193. .mod_clk = r8a7792_mod_clks,
  194. .mod_clk_size = ARRAY_SIZE(r8a7792_mod_clks),
  195. .mstp_table = r8a7792_mstp_table,
  196. .mstp_table_size = ARRAY_SIZE(r8a7792_mstp_table),
  197. .reset_node = "renesas,r8a7792-rst",
  198. .reset_modemr_offset = CPG_RST_MODEMR,
  199. .mod_clk_base = MOD_CLK_BASE,
  200. .clk_extal_id = CLK_EXTAL,
  201. .pll0_div = 2,
  202. .get_pll_config = r8a7792_get_pll_config,
  203. };
  204. static const struct udevice_id r8a7792_clk_ids[] = {
  205. {
  206. .compatible = "renesas,r8a7792-cpg-mssr",
  207. .data = (ulong)&r8a7792_cpg_mssr_info
  208. },
  209. {
  210. .compatible = "renesas,r8a7793-cpg-mssr",
  211. .data = (ulong)&r8a7792_cpg_mssr_info
  212. },
  213. { }
  214. };
  215. U_BOOT_DRIVER(clk_r8a7792) = {
  216. .name = "clk_r8a7792",
  217. .id = UCLASS_CLK,
  218. .of_match = r8a7792_clk_ids,
  219. .priv_auto = sizeof(struct gen2_clk_priv),
  220. .ops = &gen2_clk_ops,
  221. .probe = gen2_clk_probe,
  222. .remove = gen2_clk_remove,
  223. };