rcar-gen3-cpg.h 2.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0 */
  2. /*
  3. * R-Car Gen3 Clock Pulse Generator
  4. *
  5. * Copyright (C) 2015-2018 Glider bvba
  6. * Copyright (C) 2018 Renesas Electronics Corp.
  7. *
  8. */
  9. #ifndef __CLK_RENESAS_RCAR_GEN3_CPG_H__
  10. #define __CLK_RENESAS_RCAR_GEN3_CPG_H__
  11. enum rcar_gen3_clk_types {
  12. CLK_TYPE_GEN3_MAIN = CLK_TYPE_CUSTOM,
  13. CLK_TYPE_GEN3_PLL0,
  14. CLK_TYPE_GEN3_PLL1,
  15. CLK_TYPE_GEN3_PLL2,
  16. CLK_TYPE_GEN3_PLL3,
  17. CLK_TYPE_GEN3_PLL4,
  18. CLK_TYPE_GEN3_SD,
  19. CLK_TYPE_GEN3_R,
  20. CLK_TYPE_GEN3_MDSEL, /* Select parent/divider using mode pin */
  21. CLK_TYPE_GEN3_Z,
  22. CLK_TYPE_GEN3_OSC, /* OSC EXTAL predivider and fixed divider */
  23. CLK_TYPE_GEN3_RCKSEL, /* Select parent/divider using RCKCR.CKSEL */
  24. CLK_TYPE_GEN3_RPCSRC,
  25. CLK_TYPE_GEN3_E3_RPCSRC,
  26. CLK_TYPE_GEN3_RPC,
  27. CLK_TYPE_GEN3_RPCD2,
  28. /* SoC specific definitions start here */
  29. CLK_TYPE_GEN3_SOC_BASE,
  30. };
  31. #define DEF_GEN3_SD(_name, _id, _parent, _offset) \
  32. DEF_BASE(_name, _id, CLK_TYPE_GEN3_SD, _parent, .offset = _offset)
  33. #define DEF_GEN3_RPCD2(_name, _id, _parent, _offset) \
  34. DEF_BASE(_name, _id, CLK_TYPE_GEN3_RPCD2, _parent, .offset = _offset)
  35. #define DEF_GEN3_MDSEL(_name, _id, _md, _parent0, _div0, _parent1, _div1) \
  36. DEF_BASE(_name, _id, CLK_TYPE_GEN3_MDSEL, \
  37. (_parent0) << 16 | (_parent1), \
  38. .div = (_div0) << 16 | (_div1), .offset = _md)
  39. #define DEF_GEN3_PE(_name, _id, _parent_sscg, _div_sscg, _parent_clean, \
  40. _div_clean) \
  41. DEF_GEN3_MDSEL(_name, _id, 12, _parent_sscg, _div_sscg, \
  42. _parent_clean, _div_clean)
  43. #define DEF_GEN3_OSC(_name, _id, _parent, _div) \
  44. DEF_BASE(_name, _id, CLK_TYPE_GEN3_OSC, _parent, .div = _div)
  45. #define DEF_GEN3_RCKSEL(_name, _id, _parent0, _div0, _parent1, _div1) \
  46. DEF_BASE(_name, _id, CLK_TYPE_GEN3_RCKSEL, \
  47. (_parent0) << 16 | (_parent1), .div = (_div0) << 16 | (_div1))
  48. #define DEF_GEN3_Z(_name, _id, _type, _parent, _div, _offset) \
  49. DEF_BASE(_name, _id, _type, _parent, .div = _div, .offset = _offset)
  50. #define DEF_FIXED_RPCSRC_E3(_name, _id, _parent0, _parent1) \
  51. DEF_BASE(_name, _id, CLK_TYPE_GEN3_E3_RPCSRC, \
  52. (_parent0) << 16 | (_parent1), .div = 8)
  53. struct rcar_gen3_cpg_pll_config {
  54. u8 extal_div;
  55. u8 pll1_mult;
  56. u8 pll1_div;
  57. u8 pll3_mult;
  58. u8 pll3_div;
  59. u8 osc_prediv;
  60. };
  61. #define CPG_RST_MODEMR 0x060
  62. #define CPG_RPCCKCR 0x238
  63. #define CPG_RCKCR 0x240
  64. struct gen3_clk_priv {
  65. void __iomem *base;
  66. struct cpg_mssr_info *info;
  67. struct clk clk_extal;
  68. struct clk clk_extalr;
  69. bool sscg;
  70. const struct rcar_gen3_cpg_pll_config *cpg_pll_config;
  71. };
  72. int gen3_clk_probe(struct udevice *dev);
  73. int gen3_clk_remove(struct udevice *dev);
  74. extern const struct clk_ops gen3_clk_ops;
  75. #endif