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@@ -490,9 +490,6 @@ do { \
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#define MVPP22_SMI_MISC_CFG_REG (MVPP22_SMI + 0x04)
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#define MVPP22_SMI_POLLING_EN BIT(10)
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-#define MVPP22_SMI_PHY_ADDR_REG(port) (MVPP22_SMI + 0x04 + \
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- (0x4 * (port)))
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-
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#define MVPP2_CAUSE_TXQ_SENT_DESC_ALL_MASK 0xff
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/* Descriptor ring Macros */
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@@ -520,8 +517,9 @@ do { \
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/* Net Complex */
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enum mv_netc_topology {
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MV_NETC_GE_MAC2_SGMII = BIT(0),
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- MV_NETC_GE_MAC3_SGMII = BIT(1),
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- MV_NETC_GE_MAC3_RGMII = BIT(2),
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+ MV_NETC_GE_MAC2_RGMII = BIT(1),
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+ MV_NETC_GE_MAC3_SGMII = BIT(2),
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+ MV_NETC_GE_MAC3_RGMII = BIT(3),
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};
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enum mv_netc_phase {
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@@ -978,8 +976,6 @@ struct mvpp2_port {
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unsigned int duplex;
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unsigned int speed;
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- unsigned int phy_speed; /* SGMII 1Gbps vs 2.5Gbps */
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-
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struct mvpp2_bm_pool *pool_long;
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struct mvpp2_bm_pool *pool_short;
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@@ -2877,8 +2873,13 @@ static void mvpp2_port_mii_set(struct mvpp2_port *port)
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switch (port->phy_interface) {
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case PHY_INTERFACE_MODE_SGMII:
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+ case PHY_INTERFACE_MODE_SGMII_2500:
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val |= MVPP2_GMAC_INBAND_AN_MASK;
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break;
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+ case PHY_INTERFACE_MODE_1000BASEX:
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ val &= ~MVPP2_GMAC_INBAND_AN_MASK;
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+ break;
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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val |= MVPP2_GMAC_PORT_RGMII_MASK;
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@@ -2939,7 +2940,10 @@ static void mvpp2_port_loopback_set(struct mvpp2_port *port)
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else
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val &= ~MVPP2_GMAC_GMII_LB_EN_MASK;
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- if (port->phy_interface == PHY_INTERFACE_MODE_SGMII)
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+ if (port->phy_interface == PHY_INTERFACE_MODE_SGMII ||
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+ port->phy_interface == PHY_INTERFACE_MODE_SGMII_2500 ||
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+ port->phy_interface == PHY_INTERFACE_MODE_1000BASEX ||
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+ port->phy_interface == PHY_INTERFACE_MODE_2500BASEX)
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val |= MVPP2_GMAC_PCS_LB_EN_MASK;
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else
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val &= ~MVPP2_GMAC_PCS_LB_EN_MASK;
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@@ -3050,10 +3054,10 @@ static void gop_gmac_sgmii2_5_cfg(struct mvpp2_port *port)
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val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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/*
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- * Configure GIG MAC to 1000Base-X mode connected to a fiber
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+ * Configure GIG MAC to SGMII mode connected to a fiber
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* transceiver
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*/
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- val |= MVPP2_GMAC_PORT_TYPE_MASK;
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+ val &= ~MVPP2_GMAC_PORT_TYPE_MASK;
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writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
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/* configure AN 0x9268 */
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@@ -3105,6 +3109,91 @@ static void gop_gmac_sgmii_cfg(struct mvpp2_port *port)
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writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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}
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+static void gop_gmac_2500basex_cfg(struct mvpp2_port *port)
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+{
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+ u32 val, thresh;
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+
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+ /*
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+ * Configure minimal level of the Tx FIFO before the lower part
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+ * starts to read a packet
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+ */
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+ thresh = MVPP2_SGMII2_5_TX_FIFO_MIN_TH;
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+ val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
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+ val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
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+ val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
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+ writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
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+
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+ /* Disable bypass of sync module */
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+ val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
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+ val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
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+ /* configure DP clock select according to mode */
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+ val |= MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
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+ /* configure QSGMII bypass according to mode */
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+ val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
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+ writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
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+
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+ val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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+ /*
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+ * Configure GIG MAC to 2500Base-X mode connected to a fiber
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+ * transceiver
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+ */
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+ val |= MVPP2_GMAC_PORT_TYPE_MASK;
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+ writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
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+
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+ /* In 2500BaseX mode, we can't negotiate speed
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+ * and we do not want InBand autoneg
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+ * bypass enabled (link interrupt storm risk
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+ * otherwise).
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+ */
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+ val = MVPP2_GMAC_AN_BYPASS_EN |
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+ MVPP2_GMAC_EN_PCS_AN |
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+ MVPP2_GMAC_CONFIG_GMII_SPEED |
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+ MVPP2_GMAC_CONFIG_FULL_DUPLEX |
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+ MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
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+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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+}
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+
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+static void gop_gmac_1000basex_cfg(struct mvpp2_port *port)
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+{
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+ u32 val, thresh;
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+
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+ /*
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+ * Configure minimal level of the Tx FIFO before the lower part
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+ * starts to read a packet
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+ */
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+ thresh = MVPP2_SGMII_TX_FIFO_MIN_TH;
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+ val = readl(port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
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+ val &= ~MVPP2_GMAC_TX_FIFO_MIN_TH_ALL_MASK;
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+ val |= MVPP2_GMAC_TX_FIFO_MIN_TH_MASK(thresh);
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+ writel(val, port->base + MVPP2_GMAC_PORT_FIFO_CFG_1_REG);
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+
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+ /* Disable bypass of sync module */
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+ val = readl(port->base + MVPP2_GMAC_CTRL_4_REG);
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+ val |= MVPP2_GMAC_CTRL4_SYNC_BYPASS_MASK;
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+ /* configure DP clock select according to mode */
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+ val &= ~MVPP2_GMAC_CTRL4_DP_CLK_SEL_MASK;
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+ /* configure QSGMII bypass according to mode */
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+ val |= MVPP2_GMAC_CTRL4_QSGMII_BYPASS_ACTIVE_MASK;
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+ writel(val, port->base + MVPP2_GMAC_CTRL_4_REG);
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+
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+ val = readl(port->base + MVPP2_GMAC_CTRL_0_REG);
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+ /* configure GIG MAC to 1000BASEX mode */
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+ val |= MVPP2_GMAC_PORT_TYPE_MASK;
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+ writel(val, port->base + MVPP2_GMAC_CTRL_0_REG);
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+
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+ /* In 1000BaseX mode, we can't negotiate speed (it's
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+ * only 1000), and we do not want InBand autoneg
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+ * bypass enabled (link interrupt storm risk
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+ * otherwise).
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+ */
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+ val = MVPP2_GMAC_AN_BYPASS_EN |
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+ MVPP2_GMAC_EN_PCS_AN |
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+ MVPP2_GMAC_CONFIG_GMII_SPEED |
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+ MVPP2_GMAC_CONFIG_FULL_DUPLEX |
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+ MVPP2_GMAC_CHOOSE_SAMPLE_TX_CONFIG;
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+ writel(val, port->base + MVPP2_GMAC_AUTONEG_CONFIG);
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+}
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+
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static void gop_gmac_rgmii_cfg(struct mvpp2_port *port)
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{
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u32 val, thresh;
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@@ -3150,10 +3239,17 @@ static int gop_gmac_mode_cfg(struct mvpp2_port *port)
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/* Set TX FIFO thresholds */
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switch (port->phy_interface) {
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case PHY_INTERFACE_MODE_SGMII:
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- if (port->phy_speed == 2500)
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- gop_gmac_sgmii2_5_cfg(port);
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- else
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- gop_gmac_sgmii_cfg(port);
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+ gop_gmac_sgmii_cfg(port);
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+ break;
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+ case PHY_INTERFACE_MODE_SGMII_2500:
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+ gop_gmac_sgmii2_5_cfg(port);
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+ break;
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+ case PHY_INTERFACE_MODE_1000BASEX:
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+ gop_gmac_1000basex_cfg(port);
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+ break;
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+
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+ case PHY_INTERFACE_MODE_2500BASEX:
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+ gop_gmac_2500basex_cfg(port);
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break;
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case PHY_INTERFACE_MODE_RGMII:
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@@ -3208,56 +3304,31 @@ static int gop_gpcs_reset(struct mvpp2_port *port, int reset)
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return 0;
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}
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-/* Set the internal mux's to the required PCS in the PI */
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-static int gop_xpcs_mode(struct mvpp2_port *port, int num_of_lanes)
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-{
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- u32 val;
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- int lane;
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-
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- switch (num_of_lanes) {
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- case 1:
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- lane = 0;
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- break;
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- case 2:
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- lane = 1;
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- break;
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- case 4:
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- lane = 2;
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- break;
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- default:
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- return -1;
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- }
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-
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- /* configure XG MAC mode */
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- val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
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- val &= ~MVPP22_XPCS_PCSMODE_MASK;
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- val &= ~MVPP22_XPCS_LANEACTIVE_MASK;
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- val |= (2 * lane) << MVPP22_XPCS_LANEACTIVE_OFFS;
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- writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
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-
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- return 0;
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-}
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-
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static int gop_mpcs_mode(struct mvpp2_port *port)
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{
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u32 val;
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/* configure PCS40G COMMON CONTROL */
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- val = readl(port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
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+ val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
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+ PCS40G_COMMON_CONTROL);
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val &= ~FORWARD_ERROR_CORRECTION_MASK;
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- writel(val, port->priv->mpcs_base + PCS40G_COMMON_CONTROL);
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+ writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
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+ PCS40G_COMMON_CONTROL);
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/* configure PCS CLOCK RESET */
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- val = readl(port->priv->mpcs_base + PCS_CLOCK_RESET);
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+ val = readl(port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
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+ PCS_CLOCK_RESET);
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val &= ~CLK_DIVISION_RATIO_MASK;
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val |= 1 << CLK_DIVISION_RATIO_OFFS;
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- writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
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+ writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
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+ PCS_CLOCK_RESET);
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val &= ~CLK_DIV_PHASE_SET_MASK;
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val |= MAC_CLK_RESET_MASK;
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val |= RX_SD_CLK_RESET_MASK;
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val |= TX_SD_CLK_RESET_MASK;
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- writel(val, port->priv->mpcs_base + PCS_CLOCK_RESET);
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+ writel(val, port->priv->mpcs_base + port->gop_id * MVPP22_PORT_OFFSET +
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+ PCS_CLOCK_RESET);
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return 0;
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}
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@@ -3300,22 +3371,6 @@ static int gop_xlg_mac_mode_cfg(struct mvpp2_port *port, int num_of_act_lanes)
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return 0;
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}
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-/* Set PCS to reset or exit from reset */
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-static int gop_xpcs_reset(struct mvpp2_port *port, int reset)
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-{
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- u32 val;
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-
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- /* read - modify - write */
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- val = readl(port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
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- if (reset)
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- val &= ~MVPP22_XPCS_PCSRESET;
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- else
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- val |= MVPP22_XPCS_PCSRESET;
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- writel(val, port->priv->xpcs_base + MVPP22_XPCS_GLOBAL_CFG_0_REG);
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-
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- return 0;
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-}
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-
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/* Set the MAC to reset or exit from reset */
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static int gop_xlg_mac_reset(struct mvpp2_port *port, int reset)
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{
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@@ -3369,6 +3424,9 @@ static int gop_port_init(struct mvpp2_port *port)
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break;
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case PHY_INTERFACE_MODE_SGMII:
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+ case PHY_INTERFACE_MODE_SGMII_2500:
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+ case PHY_INTERFACE_MODE_1000BASEX:
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+ case PHY_INTERFACE_MODE_2500BASEX:
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/* configure PCS */
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gop_gpcs_mode_cfg(port, 1);
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@@ -3387,14 +3445,10 @@ static int gop_port_init(struct mvpp2_port *port)
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num_of_act_lanes = 2;
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mac_num = 0;
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/* configure PCS */
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- gop_xpcs_mode(port, num_of_act_lanes);
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gop_mpcs_mode(port);
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/* configure MAC */
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gop_xlg_mac_mode_cfg(port, num_of_act_lanes);
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- /* pcs unreset */
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- gop_xpcs_reset(port, 0);
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-
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/* mac unreset */
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gop_xlg_mac_reset(port, 0);
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break;
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@@ -3430,6 +3484,9 @@ static void gop_port_enable(struct mvpp2_port *port, int enable)
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_SGMII:
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+ case PHY_INTERFACE_MODE_SGMII_2500:
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+ case PHY_INTERFACE_MODE_1000BASEX:
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+ case PHY_INTERFACE_MODE_2500BASEX:
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if (enable)
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mvpp2_port_enable(port);
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else
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@@ -3463,12 +3520,21 @@ static u32 mvpp2_netc_cfg_create(int gop_id, phy_interface_t phy_type)
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u32 val = 0;
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if (gop_id == 2) {
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- if (phy_type == PHY_INTERFACE_MODE_SGMII)
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+ if (phy_type == PHY_INTERFACE_MODE_SGMII ||
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+ phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
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+ phy_type == PHY_INTERFACE_MODE_1000BASEX ||
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+ phy_type == PHY_INTERFACE_MODE_2500BASEX)
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val |= MV_NETC_GE_MAC2_SGMII;
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+ else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
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+ phy_type == PHY_INTERFACE_MODE_RGMII_ID)
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+ val |= MV_NETC_GE_MAC2_RGMII;
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}
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if (gop_id == 3) {
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- if (phy_type == PHY_INTERFACE_MODE_SGMII)
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+ if (phy_type == PHY_INTERFACE_MODE_SGMII ||
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+ phy_type == PHY_INTERFACE_MODE_SGMII_2500 ||
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+ phy_type == PHY_INTERFACE_MODE_1000BASEX ||
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+ phy_type == PHY_INTERFACE_MODE_2500BASEX)
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val |= MV_NETC_GE_MAC3_SGMII;
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else if (phy_type == PHY_INTERFACE_MODE_RGMII ||
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phy_type == PHY_INTERFACE_MODE_RGMII_ID)
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@@ -3656,7 +3722,7 @@ static int gop_netc_init(struct mvpp2 *priv, enum mv_netc_phase phase)
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if (c & MV_NETC_GE_MAC2_SGMII)
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gop_netc_mac_to_sgmii(priv, 2, phase);
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- else
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+ else if (c & MV_NETC_GE_MAC2_RGMII)
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gop_netc_mac_to_xgmii(priv, 2, phase);
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if (c & MV_NETC_GE_MAC3_SGMII) {
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@@ -4383,7 +4449,8 @@ static void mvpp2_link_event(struct mvpp2_port *port)
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if (phydev->duplex)
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val |= MVPP2_GMAC_CONFIG_FULL_DUPLEX;
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- if (phydev->speed == SPEED_1000)
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+ if (phydev->speed == SPEED_1000 ||
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+ phydev->speed == 2500)
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val |= MVPP2_GMAC_CONFIG_GMII_SPEED;
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else if (phydev->speed == SPEED_100)
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val |= MVPP2_GMAC_CONFIG_MII_SPEED;
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@@ -4464,6 +4531,9 @@ static void mvpp2_start_dev(struct mvpp2_port *port)
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_SGMII:
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+ case PHY_INTERFACE_MODE_SGMII_2500:
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+ case PHY_INTERFACE_MODE_1000BASEX:
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+ case PHY_INTERFACE_MODE_2500BASEX:
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mvpp2_gmac_max_rx_size_set(port);
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default:
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break;
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@@ -4721,16 +4791,25 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
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u32 id;
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u32 phyaddr = 0;
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int phy_mode = -1;
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+ int fixed_link = 0;
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int ret;
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phy_node = fdtdec_lookup_phandle(gd->fdt_blob, port_node, "phy");
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+ fixed_link = fdt_subnode_offset(gd->fdt_blob, port_node, "fixed-link");
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if (phy_node > 0) {
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int parent;
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- phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node, "reg", 0);
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- if (phyaddr < 0) {
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- dev_err(dev, "could not find phy address\n");
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- return -1;
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+
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+ if (fixed_link != -FDT_ERR_NOTFOUND) {
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+ /* phy_addr is set to invalid value for fixed links */
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+ phyaddr = PHY_MAX_ADDR;
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+ } else {
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+ phyaddr = fdtdec_get_int(gd->fdt_blob, phy_node,
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+ "reg", 0);
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+ if (phyaddr < 0) {
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+ dev_err(dev, "could not find phy address\n");
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+ return -1;
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+ }
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}
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parent = fdt_parent_offset(gd->fdt_blob, phy_node);
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ret = uclass_get_device_by_of_offset(UCLASS_MDIO, parent,
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@@ -4763,15 +4842,6 @@ static int phy_info_parse(struct udevice *dev, struct mvpp2_port *port)
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&port->phy_tx_disable_gpio, GPIOD_IS_OUT);
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#endif
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- /*
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- * ToDo:
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- * Not sure if this DT property "phy-speed" will get accepted, so
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- * this might change later
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- */
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- /* Get phy-speed for SGMII 2.5Gbps vs 1Gbps setup */
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- port->phy_speed = fdtdec_get_int(gd->fdt_blob, port_node,
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- "phy-speed", 1000);
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-
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port->id = id;
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if (port->priv->hw_version == MVPP21)
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port->first_rxq = port->id * rxq_number;
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@@ -5200,6 +5270,9 @@ static int mvpp2_start(struct udevice *dev)
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case PHY_INTERFACE_MODE_RGMII:
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case PHY_INTERFACE_MODE_RGMII_ID:
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case PHY_INTERFACE_MODE_SGMII:
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+ case PHY_INTERFACE_MODE_SGMII_2500:
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+ case PHY_INTERFACE_MODE_1000BASEX:
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+ case PHY_INTERFACE_MODE_2500BASEX:
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mvpp2_port_power_up(port);
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default:
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break;
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@@ -5226,14 +5299,6 @@ static int mvpp2_write_hwaddr(struct udevice *dev)
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return mvpp2_prs_update_mac_da(port, port->dev_addr);
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}
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-static int mvpp22_smi_phy_addr_cfg(struct mvpp2_port *port)
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-{
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- writel(port->phyaddr, port->priv->iface_base +
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- MVPP22_SMI_PHY_ADDR_REG(port->gop_id));
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-
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- return 0;
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-}
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-
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static int mvpp2_base_probe(struct udevice *dev)
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{
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struct mvpp2 *priv = dev_get_priv(dev);
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@@ -5356,10 +5421,6 @@ static int mvpp2_probe(struct udevice *dev)
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port->base = priv->iface_base + MVPP22_PORT_BASE +
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port->gop_id * MVPP22_PORT_OFFSET;
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- /* Set phy address of the port */
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- if (port->phyaddr < PHY_MAX_ADDR)
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- mvpp22_smi_phy_addr_cfg(port);
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-
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/* GoP Init */
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gop_port_init(port);
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}
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