renesas-cpg-mssr.h 4.8 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Renesas RCar Gen3 CPG MSSR driver
  4. *
  5. * Copyright (C) 2017-2018 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Based on the following driver from Linux kernel:
  8. * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
  9. *
  10. * Copyright (C) 2016 Glider bvba
  11. */
  12. #ifndef __DRIVERS_CLK_RENESAS_CPG_MSSR__
  13. #define __DRIVERS_CLK_RENESAS_CPG_MSSR__
  14. #include <linux/bitops.h>
  15. enum clk_reg_layout {
  16. CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3 = 0,
  17. };
  18. struct cpg_mssr_info {
  19. const struct cpg_core_clk *core_clk;
  20. unsigned int core_clk_size;
  21. enum clk_reg_layout reg_layout;
  22. const struct mssr_mod_clk *mod_clk;
  23. unsigned int mod_clk_size;
  24. const struct mstp_stop_table *mstp_table;
  25. unsigned int mstp_table_size;
  26. const char *reset_node;
  27. unsigned int reset_modemr_offset;
  28. const char *extalr_node;
  29. const char *extal_usb_node;
  30. unsigned int mod_clk_base;
  31. unsigned int clk_extal_id;
  32. unsigned int clk_extalr_id;
  33. unsigned int clk_extal_usb_id;
  34. unsigned int pll0_div;
  35. const void *(*get_pll_config)(const u32 cpg_mode);
  36. const u16 *status_regs;
  37. const u16 *control_regs;
  38. const u16 *reset_regs;
  39. const u16 *reset_clear_regs;
  40. };
  41. /*
  42. * Definitions of CPG Core Clocks
  43. *
  44. * These include:
  45. * - Clock outputs exported to DT
  46. * - External input clocks
  47. * - Internal CPG clocks
  48. */
  49. struct cpg_core_clk {
  50. /* Common */
  51. const char *name;
  52. unsigned int id;
  53. unsigned int type;
  54. /* Depending on type */
  55. unsigned int parent; /* Core Clocks only */
  56. unsigned int div;
  57. unsigned int mult;
  58. unsigned int offset;
  59. };
  60. enum clk_types {
  61. /* Generic */
  62. CLK_TYPE_IN, /* External Clock Input */
  63. CLK_TYPE_FF, /* Fixed Factor Clock */
  64. CLK_TYPE_DIV6P1, /* DIV6 Clock with 1 parent clock */
  65. CLK_TYPE_DIV6_RO, /* DIV6 Clock read only with extra divisor */
  66. CLK_TYPE_FR, /* Fixed Rate Clock */
  67. /* Custom definitions start here */
  68. CLK_TYPE_CUSTOM,
  69. };
  70. #define DEF_TYPE(_name, _id, _type...) \
  71. { .name = _name, .id = _id, .type = _type }
  72. #define DEF_BASE(_name, _id, _type, _parent...) \
  73. DEF_TYPE(_name, _id, _type, .parent = _parent)
  74. #define DEF_INPUT(_name, _id) \
  75. DEF_TYPE(_name, _id, CLK_TYPE_IN)
  76. #define DEF_FIXED(_name, _id, _parent, _div, _mult) \
  77. DEF_BASE(_name, _id, CLK_TYPE_FF, _parent, .div = _div, .mult = _mult)
  78. #define DEF_DIV6P1(_name, _id, _parent, _offset) \
  79. DEF_BASE(_name, _id, CLK_TYPE_DIV6P1, _parent, .offset = _offset)
  80. #define DEF_DIV6_RO(_name, _id, _parent, _offset, _div) \
  81. DEF_BASE(_name, _id, CLK_TYPE_DIV6_RO, _parent, .offset = _offset, .div = _div, .mult = 1)
  82. #define DEF_RATE(_name, _id, _rate) \
  83. DEF_TYPE(_name, _id, CLK_TYPE_FR, .mult = _rate)
  84. /*
  85. * Definitions of Module Clocks
  86. */
  87. struct mssr_mod_clk {
  88. const char *name;
  89. unsigned int id;
  90. unsigned int parent; /* Add MOD_CLK_BASE for Module Clocks */
  91. };
  92. /* Convert from sparse base-100 to packed index space */
  93. #define MOD_CLK_PACK(x) ((x) - ((x) / 100) * (100 - 32))
  94. #define MOD_CLK_ID(x) (MOD_CLK_BASE + MOD_CLK_PACK(x))
  95. #define DEF_MOD(_name, _mod, _parent...) \
  96. { .name = _name, .id = MOD_CLK_ID(_mod), .parent = _parent }
  97. struct mstp_stop_table {
  98. u32 sdis;
  99. u32 sen;
  100. u32 rdis;
  101. u32 ren;
  102. };
  103. #define TSTR0 0x04
  104. #define TSTR0_STR0 BIT(0)
  105. bool renesas_clk_is_mod(struct clk *clk);
  106. int renesas_clk_get_mod(struct clk *clk, struct cpg_mssr_info *info,
  107. const struct mssr_mod_clk **mssr);
  108. int renesas_clk_get_core(struct clk *clk, struct cpg_mssr_info *info,
  109. const struct cpg_core_clk **core);
  110. int renesas_clk_get_parent(struct clk *clk, struct cpg_mssr_info *info,
  111. struct clk *parent);
  112. int renesas_clk_endisable(struct clk *clk, void __iomem *base,
  113. struct cpg_mssr_info *info, bool enable);
  114. int renesas_clk_remove(void __iomem *base, struct cpg_mssr_info *info);
  115. /*
  116. * Module Standby and Software Reset register offets.
  117. *
  118. * If the registers exist, these are valid for SH-Mobile, R-Mobile,
  119. * R-Car Gen2, R-Car Gen3, and RZ/G1.
  120. * These are NOT valid for R-Car Gen1 and RZ/A1!
  121. */
  122. /*
  123. * Module Stop Status Register offsets
  124. */
  125. static const u16 mstpsr[] = {
  126. 0x030, 0x038, 0x040, 0x048, 0x04C, 0x03C, 0x1C0, 0x1C4,
  127. 0x9A0, 0x9A4, 0x9A8, 0x9AC,
  128. };
  129. /*
  130. * System Module Stop Control Register offsets
  131. */
  132. static const u16 smstpcr[] = {
  133. 0x130, 0x134, 0x138, 0x13C, 0x140, 0x144, 0x148, 0x14C,
  134. 0x990, 0x994, 0x998, 0x99C,
  135. };
  136. /*
  137. * Software Reset Register offsets
  138. */
  139. static const u16 srcr[] = {
  140. 0x0A0, 0x0A8, 0x0B0, 0x0B8, 0x0BC, 0x0C4, 0x1C8, 0x1CC,
  141. 0x920, 0x924, 0x928, 0x92C,
  142. };
  143. /* Realtime Module Stop Control Register offsets */
  144. #define RMSTPCR(i) ((i) < 8 ? smstpcr[i] - 0x20 : smstpcr[i] - 0x10)
  145. /* Modem Module Stop Control Register offsets (r8a73a4) */
  146. #define MMSTPCR(i) (smstpcr[i] + 0x20)
  147. /* Software Reset Clearing Register offsets */
  148. static const u16 srstclr[] = {
  149. 0x940, 0x944, 0x948, 0x94C, 0x950, 0x954, 0x958, 0x95C,
  150. 0x960, 0x964, 0x968, 0x96C,
  151. };
  152. #endif /* __DRIVERS_CLK_RENESAS_CPG_MSSR__ */