r8a77995-cpg-mssr.c 9.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a77995 Clock Pulse Generator / Module Standby and Software Reset
  4. *
  5. * Copyright (C) 2017 Glider bvba
  6. *
  7. * Based on r8a7795-cpg-mssr.c
  8. *
  9. * Copyright (C) 2015 Glider bvba
  10. * Copyright (C) 2015 Renesas Electronics Corp.
  11. */
  12. #include <common.h>
  13. #include <clk-uclass.h>
  14. #include <dm.h>
  15. #include <linux/bitops.h>
  16. #include <dt-bindings/clock/r8a77995-cpg-mssr.h>
  17. #include "renesas-cpg-mssr.h"
  18. #include "rcar-gen3-cpg.h"
  19. enum clk_ids {
  20. /* Core Clock Outputs exported to DT */
  21. LAST_DT_CORE_CLK = R8A77995_CLK_CPEX,
  22. /* External Input Clocks */
  23. CLK_EXTAL,
  24. /* Internal Core Clocks */
  25. CLK_MAIN,
  26. CLK_PLL0,
  27. CLK_PLL1,
  28. CLK_PLL3,
  29. CLK_PLL0D2,
  30. CLK_PLL0D3,
  31. CLK_PLL0D5,
  32. CLK_PLL1D2,
  33. CLK_PE,
  34. CLK_S0,
  35. CLK_S1,
  36. CLK_S2,
  37. CLK_S3,
  38. CLK_SDSRC,
  39. CLK_RPCSRC,
  40. CLK_RINT,
  41. CLK_OCO,
  42. /* Module Clocks */
  43. MOD_CLK_BASE
  44. };
  45. static const struct cpg_core_clk r8a77995_core_clks[] = {
  46. /* External Clock Inputs */
  47. DEF_INPUT("extal", CLK_EXTAL),
  48. /* Internal Core Clocks */
  49. DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  50. DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  51. DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  52. DEF_FIXED(".pll0", CLK_PLL0, CLK_MAIN, 4, 250),
  53. DEF_FIXED(".pll0d2", CLK_PLL0D2, CLK_PLL0, 2, 1),
  54. DEF_FIXED(".pll0d3", CLK_PLL0D3, CLK_PLL0, 3, 1),
  55. DEF_FIXED(".pll0d5", CLK_PLL0D5, CLK_PLL0, 5, 1),
  56. DEF_FIXED(".pll1d2", CLK_PLL1D2, CLK_PLL1, 2, 1),
  57. DEF_FIXED(".pe", CLK_PE, CLK_PLL0D3, 4, 1),
  58. DEF_FIXED(".s0", CLK_S0, CLK_PLL1, 2, 1),
  59. DEF_FIXED(".s1", CLK_S1, CLK_PLL1, 3, 1),
  60. DEF_FIXED(".s2", CLK_S2, CLK_PLL1, 4, 1),
  61. DEF_FIXED(".s3", CLK_S3, CLK_PLL1, 6, 1),
  62. DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1, 2, 1),
  63. DEF_FIXED_RPCSRC_E3(".rpcsrc", CLK_RPCSRC, CLK_PLL0, CLK_PLL1),
  64. DEF_BASE("rpc", R8A77995_CLK_RPC, CLK_TYPE_GEN3_RPC,
  65. CLK_RPCSRC),
  66. DEF_BASE("rpcd2", R8A77995_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
  67. R8A77995_CLK_RPC),
  68. DEF_DIV6_RO(".r", CLK_RINT, CLK_EXTAL, CPG_RCKCR, 32),
  69. DEF_RATE(".oco", CLK_OCO, 8 * 1000 * 1000),
  70. /* Core Clock Outputs */
  71. DEF_FIXED("z2", R8A77995_CLK_Z2, CLK_PLL0D3, 1, 1),
  72. DEF_FIXED("ztr", R8A77995_CLK_ZTR, CLK_PLL1, 6, 1),
  73. DEF_FIXED("zt", R8A77995_CLK_ZT, CLK_PLL1, 4, 1),
  74. DEF_FIXED("zx", R8A77995_CLK_ZX, CLK_PLL1, 3, 1),
  75. DEF_FIXED("s0d1", R8A77995_CLK_S0D1, CLK_S0, 1, 1),
  76. DEF_FIXED("s1d1", R8A77995_CLK_S1D1, CLK_S1, 1, 1),
  77. DEF_FIXED("s1d2", R8A77995_CLK_S1D2, CLK_S1, 2, 1),
  78. DEF_FIXED("s1d4", R8A77995_CLK_S1D4, CLK_S1, 4, 1),
  79. DEF_FIXED("s2d1", R8A77995_CLK_S2D1, CLK_S2, 1, 1),
  80. DEF_FIXED("s2d2", R8A77995_CLK_S2D2, CLK_S2, 2, 1),
  81. DEF_FIXED("s2d4", R8A77995_CLK_S2D4, CLK_S2, 4, 1),
  82. DEF_FIXED("s3d1", R8A77995_CLK_S3D1, CLK_S3, 1, 1),
  83. DEF_FIXED("s3d2", R8A77995_CLK_S3D2, CLK_S3, 2, 1),
  84. DEF_FIXED("s3d4", R8A77995_CLK_S3D4, CLK_S3, 4, 1),
  85. DEF_FIXED("cl", R8A77995_CLK_CL, CLK_PLL1, 48, 1),
  86. DEF_FIXED("cr", R8A77995_CLK_CR, CLK_PLL1D2, 2, 1),
  87. DEF_FIXED("cp", R8A77995_CLK_CP, CLK_EXTAL, 2, 1),
  88. DEF_FIXED("cpex", R8A77995_CLK_CPEX, CLK_EXTAL, 4, 1),
  89. DEF_DIV6_RO("osc", R8A77995_CLK_OSC, CLK_EXTAL, CPG_RCKCR, 8),
  90. DEF_GEN3_PE("s1d4c", R8A77995_CLK_S1D4C, CLK_S1, 4, CLK_PE, 2),
  91. DEF_GEN3_PE("s3d1c", R8A77995_CLK_S3D1C, CLK_S3, 1, CLK_PE, 1),
  92. DEF_GEN3_PE("s3d2c", R8A77995_CLK_S3D2C, CLK_S3, 2, CLK_PE, 2),
  93. DEF_GEN3_PE("s3d4c", R8A77995_CLK_S3D4C, CLK_S3, 4, CLK_PE, 4),
  94. DEF_GEN3_SD("sd0", R8A77995_CLK_SD0, CLK_SDSRC, 0x268),
  95. DEF_DIV6P1("canfd", R8A77995_CLK_CANFD, CLK_PLL0D3, 0x244),
  96. DEF_DIV6P1("mso", R8A77995_CLK_MSO, CLK_PLL1D2, 0x014),
  97. DEF_GEN3_RCKSEL("r", R8A77995_CLK_R, CLK_RINT, 1, CLK_OCO, 61 * 4),
  98. };
  99. static const struct mssr_mod_clk r8a77995_mod_clks[] = {
  100. DEF_MOD("tmu4", 121, R8A77995_CLK_S1D4C),
  101. DEF_MOD("tmu3", 122, R8A77995_CLK_S3D2C),
  102. DEF_MOD("tmu2", 123, R8A77995_CLK_S3D2C),
  103. DEF_MOD("tmu1", 124, R8A77995_CLK_S3D2C),
  104. DEF_MOD("tmu0", 125, R8A77995_CLK_CP),
  105. DEF_MOD("scif5", 202, R8A77995_CLK_S3D4C),
  106. DEF_MOD("scif4", 203, R8A77995_CLK_S3D4C),
  107. DEF_MOD("scif3", 204, R8A77995_CLK_S3D4C),
  108. DEF_MOD("scif1", 206, R8A77995_CLK_S3D4C),
  109. DEF_MOD("scif0", 207, R8A77995_CLK_S3D4C),
  110. DEF_MOD("msiof3", 208, R8A77995_CLK_MSO),
  111. DEF_MOD("msiof2", 209, R8A77995_CLK_MSO),
  112. DEF_MOD("msiof1", 210, R8A77995_CLK_MSO),
  113. DEF_MOD("msiof0", 211, R8A77995_CLK_MSO),
  114. DEF_MOD("sys-dmac2", 217, R8A77995_CLK_S3D1),
  115. DEF_MOD("sys-dmac1", 218, R8A77995_CLK_S3D1),
  116. DEF_MOD("sys-dmac0", 219, R8A77995_CLK_S3D1),
  117. DEF_MOD("sceg-pub", 229, R8A77995_CLK_CR),
  118. DEF_MOD("cmt3", 300, R8A77995_CLK_R),
  119. DEF_MOD("cmt2", 301, R8A77995_CLK_R),
  120. DEF_MOD("cmt1", 302, R8A77995_CLK_R),
  121. DEF_MOD("cmt0", 303, R8A77995_CLK_R),
  122. DEF_MOD("scif2", 310, R8A77995_CLK_S3D4C),
  123. DEF_MOD("emmc0", 312, R8A77995_CLK_SD0),
  124. DEF_MOD("usb-dmac0", 330, R8A77995_CLK_S3D1),
  125. DEF_MOD("usb-dmac1", 331, R8A77995_CLK_S3D1),
  126. DEF_MOD("rwdt", 402, R8A77995_CLK_R),
  127. DEF_MOD("intc-ex", 407, R8A77995_CLK_CP),
  128. DEF_MOD("intc-ap", 408, R8A77995_CLK_S1D2),
  129. DEF_MOD("audmac0", 502, R8A77995_CLK_S1D2),
  130. DEF_MOD("hscif3", 517, R8A77995_CLK_S3D1C),
  131. DEF_MOD("hscif0", 520, R8A77995_CLK_S3D1C),
  132. DEF_MOD("thermal", 522, R8A77995_CLK_CP),
  133. DEF_MOD("pwm", 523, R8A77995_CLK_S3D4C),
  134. DEF_MOD("fcpvd1", 602, R8A77995_CLK_S1D2),
  135. DEF_MOD("fcpvd0", 603, R8A77995_CLK_S1D2),
  136. DEF_MOD("fcpvbs", 607, R8A77995_CLK_S0D1),
  137. DEF_MOD("vspd1", 622, R8A77995_CLK_S1D2),
  138. DEF_MOD("vspd0", 623, R8A77995_CLK_S1D2),
  139. DEF_MOD("vspbs", 627, R8A77995_CLK_S0D1),
  140. DEF_MOD("ehci0", 703, R8A77995_CLK_S3D2),
  141. DEF_MOD("hsusb", 704, R8A77995_CLK_S3D2),
  142. DEF_MOD("cmm1", 710, R8A77995_CLK_S1D1),
  143. DEF_MOD("cmm0", 711, R8A77995_CLK_S1D1),
  144. DEF_MOD("du1", 723, R8A77995_CLK_S1D1),
  145. DEF_MOD("du0", 724, R8A77995_CLK_S1D1),
  146. DEF_MOD("lvds", 727, R8A77995_CLK_S2D1),
  147. DEF_MOD("vin4", 807, R8A77995_CLK_S1D2),
  148. DEF_MOD("etheravb", 812, R8A77995_CLK_S3D2),
  149. DEF_MOD("imr0", 823, R8A77995_CLK_S1D2),
  150. DEF_MOD("gpio6", 906, R8A77995_CLK_S3D4),
  151. DEF_MOD("gpio5", 907, R8A77995_CLK_S3D4),
  152. DEF_MOD("gpio4", 908, R8A77995_CLK_S3D4),
  153. DEF_MOD("gpio3", 909, R8A77995_CLK_S3D4),
  154. DEF_MOD("gpio2", 910, R8A77995_CLK_S3D4),
  155. DEF_MOD("gpio1", 911, R8A77995_CLK_S3D4),
  156. DEF_MOD("gpio0", 912, R8A77995_CLK_S3D4),
  157. DEF_MOD("can-fd", 914, R8A77995_CLK_S3D2),
  158. DEF_MOD("can-if1", 915, R8A77995_CLK_S3D4),
  159. DEF_MOD("can-if0", 916, R8A77995_CLK_S3D4),
  160. DEF_MOD("rpc", 917, R8A77995_CLK_RPC),
  161. DEF_MOD("i2c3", 928, R8A77995_CLK_S3D2),
  162. DEF_MOD("i2c2", 929, R8A77995_CLK_S3D2),
  163. DEF_MOD("i2c1", 930, R8A77995_CLK_S3D2),
  164. DEF_MOD("i2c0", 931, R8A77995_CLK_S3D2),
  165. DEF_MOD("ssi-all", 1005, R8A77995_CLK_S3D4),
  166. DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
  167. DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
  168. DEF_MOD("scu-all", 1017, R8A77995_CLK_S3D4),
  169. DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
  170. DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
  171. DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
  172. DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
  173. DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
  174. DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
  175. };
  176. /*
  177. * CPG Clock Data
  178. */
  179. /*
  180. * MD19 EXTAL (MHz) PLL0 PLL1 PLL3
  181. *--------------------------------------------------------------------
  182. * 0 48 x 1 x250/4 x100/3 x100/3
  183. * 1 48 x 1 x250/4 x100/3 x58/3
  184. */
  185. #define CPG_PLL_CONFIG_INDEX(md) (((md) & BIT(19)) >> 19)
  186. static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[2] = {
  187. /* EXTAL div PLL1 mult/div PLL3 mult/div */
  188. { 1, 100, 3, 100, 3, },
  189. { 1, 100, 3, 58, 3, },
  190. };
  191. static const struct mstp_stop_table r8a77995_mstp_table[] = {
  192. { 0x00210000, 0x0, 0x00210000, 0 },
  193. { 0x03e01000, 0x0, 0x03e01000, 0 },
  194. { 0x000e2fdc, 0x2000, 0x000e2fd8, 0 },
  195. { 0xc00014df, 0x400, 0xc00014df, 0 },
  196. { 0x80000004, 0x180, 0x80000004, 0 },
  197. { 0x40d20004, 0x0, 0x40d20004, 0 },
  198. { 0x08c0008c, 0x0, 0x08c0008c, 0 },
  199. { 0x09941c18, 0x0, 0x09941c18, 0 },
  200. { 0x00801087, 0x0, 0x00801087, 0 },
  201. { 0xf143dfc0, 0x0, 0xf143dfc0, 0 },
  202. { 0x063e1820, 0x0, 0x063e1820, 0 },
  203. { 0x00000000, 0x0, 0x00000000, 0 },
  204. };
  205. static const void *r8a77995_get_pll_config(const u32 cpg_mode)
  206. {
  207. return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
  208. }
  209. static const struct cpg_mssr_info r8a77995_cpg_mssr_info = {
  210. .core_clk = r8a77995_core_clks,
  211. .core_clk_size = ARRAY_SIZE(r8a77995_core_clks),
  212. .mod_clk = r8a77995_mod_clks,
  213. .mod_clk_size = ARRAY_SIZE(r8a77995_mod_clks),
  214. .mstp_table = r8a77995_mstp_table,
  215. .mstp_table_size = ARRAY_SIZE(r8a77995_mstp_table),
  216. .reset_node = "renesas,r8a77995-rst",
  217. .reset_modemr_offset = CPG_RST_MODEMR,
  218. .mod_clk_base = MOD_CLK_BASE,
  219. .clk_extal_id = CLK_EXTAL,
  220. .clk_extalr_id = ~0,
  221. .get_pll_config = r8a77995_get_pll_config,
  222. };
  223. static const struct udevice_id r8a77995_clk_ids[] = {
  224. {
  225. .compatible = "renesas,r8a77995-cpg-mssr",
  226. .data = (ulong)&r8a77995_cpg_mssr_info
  227. },
  228. { }
  229. };
  230. U_BOOT_DRIVER(clk_r8a77995) = {
  231. .name = "clk_r8a77995",
  232. .id = UCLASS_CLK,
  233. .of_match = r8a77995_clk_ids,
  234. .priv_auto = sizeof(struct gen3_clk_priv),
  235. .ops = &gen3_clk_ops,
  236. .probe = gen3_clk_probe,
  237. .remove = gen3_clk_remove,
  238. };