r8a774b1-cpg-mssr.c 13 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * r8a774b1 Clock Pulse Generator / Module Standby and Software Reset
  4. *
  5. * Copyright (C) 2020 Renesas Electronics Corp.
  6. *
  7. * Based on r8a7796-cpg-mssr.c
  8. *
  9. * Copyright (C) 2016 Glider bvba
  10. */
  11. #include <common.h>
  12. #include <clk-uclass.h>
  13. #include <dm.h>
  14. #include <dt-bindings/clock/r8a774b1-cpg-mssr.h>
  15. #include "renesas-cpg-mssr.h"
  16. #include "rcar-gen3-cpg.h"
  17. enum clk_ids {
  18. /* Core Clock Outputs exported to DT */
  19. LAST_DT_CORE_CLK = R8A774B1_CLK_CANFD,
  20. /* External Input Clocks */
  21. CLK_EXTAL,
  22. CLK_EXTALR,
  23. /* Internal Core Clocks */
  24. CLK_MAIN,
  25. CLK_PLL0,
  26. CLK_PLL1,
  27. CLK_PLL3,
  28. CLK_PLL4,
  29. CLK_PLL1_DIV2,
  30. CLK_PLL1_DIV4,
  31. CLK_S0,
  32. CLK_S1,
  33. CLK_S2,
  34. CLK_S3,
  35. CLK_SDSRC,
  36. CLK_RPCSRC,
  37. CLK_RINT,
  38. /* Module Clocks */
  39. MOD_CLK_BASE
  40. };
  41. static const struct cpg_core_clk r8a774b1_core_clks[] = {
  42. /* External Clock Inputs */
  43. DEF_INPUT("extal", CLK_EXTAL),
  44. DEF_INPUT("extalr", CLK_EXTALR),
  45. /* Internal Core Clocks */
  46. DEF_BASE(".main", CLK_MAIN, CLK_TYPE_GEN3_MAIN, CLK_EXTAL),
  47. DEF_BASE(".pll0", CLK_PLL0, CLK_TYPE_GEN3_PLL0, CLK_MAIN),
  48. DEF_BASE(".pll1", CLK_PLL1, CLK_TYPE_GEN3_PLL1, CLK_MAIN),
  49. DEF_BASE(".pll3", CLK_PLL3, CLK_TYPE_GEN3_PLL3, CLK_MAIN),
  50. DEF_BASE(".pll4", CLK_PLL4, CLK_TYPE_GEN3_PLL4, CLK_MAIN),
  51. DEF_FIXED(".pll1_div2", CLK_PLL1_DIV2, CLK_PLL1, 2, 1),
  52. DEF_FIXED(".pll1_div4", CLK_PLL1_DIV4, CLK_PLL1_DIV2, 2, 1),
  53. DEF_FIXED(".s0", CLK_S0, CLK_PLL1_DIV2, 2, 1),
  54. DEF_FIXED(".s1", CLK_S1, CLK_PLL1_DIV2, 3, 1),
  55. DEF_FIXED(".s2", CLK_S2, CLK_PLL1_DIV2, 4, 1),
  56. DEF_FIXED(".s3", CLK_S3, CLK_PLL1_DIV2, 6, 1),
  57. DEF_FIXED(".sdsrc", CLK_SDSRC, CLK_PLL1_DIV2, 2, 1),
  58. DEF_BASE(".rpcsrc", CLK_RPCSRC, CLK_TYPE_GEN3_RPCSRC, CLK_PLL1),
  59. DEF_BASE("rpc", R8A774B1_CLK_RPC, CLK_TYPE_GEN3_RPC,
  60. CLK_RPCSRC),
  61. DEF_BASE("rpcd2", R8A774B1_CLK_RPCD2, CLK_TYPE_GEN3_RPCD2,
  62. R8A774B1_CLK_RPC),
  63. DEF_GEN3_OSC(".r", CLK_RINT, CLK_EXTAL, 32),
  64. /* Core Clock Outputs */
  65. DEF_GEN3_Z("z", R8A774B1_CLK_Z, CLK_TYPE_GEN3_Z, CLK_PLL0, 2, 8),
  66. DEF_FIXED("ztr", R8A774B1_CLK_ZTR, CLK_PLL1_DIV2, 6, 1),
  67. DEF_FIXED("ztrd2", R8A774B1_CLK_ZTRD2, CLK_PLL1_DIV2, 12, 1),
  68. DEF_FIXED("zt", R8A774B1_CLK_ZT, CLK_PLL1_DIV2, 4, 1),
  69. DEF_FIXED("zx", R8A774B1_CLK_ZX, CLK_PLL1_DIV2, 2, 1),
  70. DEF_FIXED("s0d1", R8A774B1_CLK_S0D1, CLK_S0, 1, 1),
  71. DEF_FIXED("s0d2", R8A774B1_CLK_S0D2, CLK_S0, 2, 1),
  72. DEF_FIXED("s0d3", R8A774B1_CLK_S0D3, CLK_S0, 3, 1),
  73. DEF_FIXED("s0d4", R8A774B1_CLK_S0D4, CLK_S0, 4, 1),
  74. DEF_FIXED("s0d6", R8A774B1_CLK_S0D6, CLK_S0, 6, 1),
  75. DEF_FIXED("s0d8", R8A774B1_CLK_S0D8, CLK_S0, 8, 1),
  76. DEF_FIXED("s0d12", R8A774B1_CLK_S0D12, CLK_S0, 12, 1),
  77. DEF_FIXED("s1d2", R8A774B1_CLK_S1D2, CLK_S1, 2, 1),
  78. DEF_FIXED("s1d4", R8A774B1_CLK_S1D4, CLK_S1, 4, 1),
  79. DEF_FIXED("s2d1", R8A774B1_CLK_S2D1, CLK_S2, 1, 1),
  80. DEF_FIXED("s2d2", R8A774B1_CLK_S2D2, CLK_S2, 2, 1),
  81. DEF_FIXED("s2d4", R8A774B1_CLK_S2D4, CLK_S2, 4, 1),
  82. DEF_FIXED("s3d1", R8A774B1_CLK_S3D1, CLK_S3, 1, 1),
  83. DEF_FIXED("s3d2", R8A774B1_CLK_S3D2, CLK_S3, 2, 1),
  84. DEF_FIXED("s3d4", R8A774B1_CLK_S3D4, CLK_S3, 4, 1),
  85. DEF_GEN3_SD("sd0", R8A774B1_CLK_SD0, CLK_SDSRC, 0x074),
  86. DEF_GEN3_SD("sd1", R8A774B1_CLK_SD1, CLK_SDSRC, 0x078),
  87. DEF_GEN3_SD("sd2", R8A774B1_CLK_SD2, CLK_SDSRC, 0x268),
  88. DEF_GEN3_SD("sd3", R8A774B1_CLK_SD3, CLK_SDSRC, 0x26c),
  89. DEF_FIXED("cl", R8A774B1_CLK_CL, CLK_PLL1_DIV2, 48, 1),
  90. DEF_FIXED("cp", R8A774B1_CLK_CP, CLK_EXTAL, 2, 1),
  91. DEF_FIXED("cpex", R8A774B1_CLK_CPEX, CLK_EXTAL, 2, 1),
  92. DEF_DIV6P1("canfd", R8A774B1_CLK_CANFD, CLK_PLL1_DIV4, 0x244),
  93. DEF_DIV6P1("csi0", R8A774B1_CLK_CSI0, CLK_PLL1_DIV4, 0x00c),
  94. DEF_DIV6P1("mso", R8A774B1_CLK_MSO, CLK_PLL1_DIV4, 0x014),
  95. DEF_DIV6P1("hdmi", R8A774B1_CLK_HDMI, CLK_PLL1_DIV4, 0x250),
  96. DEF_GEN3_OSC("osc", R8A774B1_CLK_OSC, CLK_EXTAL, 8),
  97. DEF_BASE("r", R8A774B1_CLK_R, CLK_TYPE_GEN3_R, CLK_RINT),
  98. };
  99. static const struct mssr_mod_clk r8a774b1_mod_clks[] = {
  100. DEF_MOD("tmu4", 121, R8A774B1_CLK_S0D6),
  101. DEF_MOD("tmu3", 122, R8A774B1_CLK_S3D2),
  102. DEF_MOD("tmu2", 123, R8A774B1_CLK_S3D2),
  103. DEF_MOD("tmu1", 124, R8A774B1_CLK_S3D2),
  104. DEF_MOD("tmu0", 125, R8A774B1_CLK_CP),
  105. DEF_MOD("fdp1-0", 119, R8A774B1_CLK_S0D1),
  106. DEF_MOD("scif5", 202, R8A774B1_CLK_S3D4),
  107. DEF_MOD("scif4", 203, R8A774B1_CLK_S3D4),
  108. DEF_MOD("scif3", 204, R8A774B1_CLK_S3D4),
  109. DEF_MOD("scif1", 206, R8A774B1_CLK_S3D4),
  110. DEF_MOD("scif0", 207, R8A774B1_CLK_S3D4),
  111. DEF_MOD("msiof3", 208, R8A774B1_CLK_MSO),
  112. DEF_MOD("msiof2", 209, R8A774B1_CLK_MSO),
  113. DEF_MOD("msiof1", 210, R8A774B1_CLK_MSO),
  114. DEF_MOD("msiof0", 211, R8A774B1_CLK_MSO),
  115. DEF_MOD("sys-dmac2", 217, R8A774B1_CLK_S3D1),
  116. DEF_MOD("sys-dmac1", 218, R8A774B1_CLK_S3D1),
  117. DEF_MOD("sys-dmac0", 219, R8A774B1_CLK_S0D3),
  118. DEF_MOD("cmt3", 300, R8A774B1_CLK_R),
  119. DEF_MOD("cmt2", 301, R8A774B1_CLK_R),
  120. DEF_MOD("cmt1", 302, R8A774B1_CLK_R),
  121. DEF_MOD("cmt0", 303, R8A774B1_CLK_R),
  122. DEF_MOD("tpu0", 304, R8A774B1_CLK_S3D4),
  123. DEF_MOD("scif2", 310, R8A774B1_CLK_S3D4),
  124. DEF_MOD("sdif3", 311, R8A774B1_CLK_SD3),
  125. DEF_MOD("sdif2", 312, R8A774B1_CLK_SD2),
  126. DEF_MOD("sdif1", 313, R8A774B1_CLK_SD1),
  127. DEF_MOD("sdif0", 314, R8A774B1_CLK_SD0),
  128. DEF_MOD("pcie1", 318, R8A774B1_CLK_S3D1),
  129. DEF_MOD("pcie0", 319, R8A774B1_CLK_S3D1),
  130. DEF_MOD("usb3-if0", 328, R8A774B1_CLK_S3D1),
  131. DEF_MOD("usb-dmac0", 330, R8A774B1_CLK_S3D1),
  132. DEF_MOD("usb-dmac1", 331, R8A774B1_CLK_S3D1),
  133. DEF_MOD("rwdt", 402, R8A774B1_CLK_R),
  134. DEF_MOD("intc-ex", 407, R8A774B1_CLK_CP),
  135. DEF_MOD("intc-ap", 408, R8A774B1_CLK_S0D3),
  136. DEF_MOD("audmac1", 501, R8A774B1_CLK_S1D2),
  137. DEF_MOD("audmac0", 502, R8A774B1_CLK_S1D2),
  138. DEF_MOD("hscif4", 516, R8A774B1_CLK_S3D1),
  139. DEF_MOD("hscif3", 517, R8A774B1_CLK_S3D1),
  140. DEF_MOD("hscif2", 518, R8A774B1_CLK_S3D1),
  141. DEF_MOD("hscif1", 519, R8A774B1_CLK_S3D1),
  142. DEF_MOD("hscif0", 520, R8A774B1_CLK_S3D1),
  143. DEF_MOD("thermal", 522, R8A774B1_CLK_CP),
  144. DEF_MOD("pwm", 523, R8A774B1_CLK_S0D12),
  145. DEF_MOD("fcpvd1", 602, R8A774B1_CLK_S0D2),
  146. DEF_MOD("fcpvd0", 603, R8A774B1_CLK_S0D2),
  147. DEF_MOD("fcpvb0", 607, R8A774B1_CLK_S0D1),
  148. DEF_MOD("fcpvi0", 611, R8A774B1_CLK_S0D1),
  149. DEF_MOD("fcpf0", 615, R8A774B1_CLK_S0D1),
  150. DEF_MOD("fcpcs", 619, R8A774B1_CLK_S0D2),
  151. DEF_MOD("vspd1", 622, R8A774B1_CLK_S0D2),
  152. DEF_MOD("vspd0", 623, R8A774B1_CLK_S0D2),
  153. DEF_MOD("vspb", 626, R8A774B1_CLK_S0D1),
  154. DEF_MOD("vspi0", 631, R8A774B1_CLK_S0D1),
  155. DEF_MOD("ehci1", 702, R8A774B1_CLK_S3D2),
  156. DEF_MOD("ehci0", 703, R8A774B1_CLK_S3D2),
  157. DEF_MOD("hsusb", 704, R8A774B1_CLK_S3D2),
  158. DEF_MOD("csi20", 714, R8A774B1_CLK_CSI0),
  159. DEF_MOD("csi40", 716, R8A774B1_CLK_CSI0),
  160. DEF_MOD("du3", 721, R8A774B1_CLK_S2D1),
  161. DEF_MOD("du1", 723, R8A774B1_CLK_S2D1),
  162. DEF_MOD("du0", 724, R8A774B1_CLK_S2D1),
  163. DEF_MOD("lvds", 727, R8A774B1_CLK_S2D1),
  164. DEF_MOD("hdmi0", 729, R8A774B1_CLK_HDMI),
  165. DEF_MOD("vin7", 804, R8A774B1_CLK_S0D2),
  166. DEF_MOD("vin6", 805, R8A774B1_CLK_S0D2),
  167. DEF_MOD("vin5", 806, R8A774B1_CLK_S0D2),
  168. DEF_MOD("vin4", 807, R8A774B1_CLK_S0D2),
  169. DEF_MOD("vin3", 808, R8A774B1_CLK_S0D2),
  170. DEF_MOD("vin2", 809, R8A774B1_CLK_S0D2),
  171. DEF_MOD("vin1", 810, R8A774B1_CLK_S0D2),
  172. DEF_MOD("vin0", 811, R8A774B1_CLK_S0D2),
  173. DEF_MOD("etheravb", 812, R8A774B1_CLK_S0D6),
  174. DEF_MOD("sata0", 815, R8A774B1_CLK_S3D2),
  175. DEF_MOD("gpio7", 905, R8A774B1_CLK_S3D4),
  176. DEF_MOD("gpio6", 906, R8A774B1_CLK_S3D4),
  177. DEF_MOD("gpio5", 907, R8A774B1_CLK_S3D4),
  178. DEF_MOD("gpio4", 908, R8A774B1_CLK_S3D4),
  179. DEF_MOD("gpio3", 909, R8A774B1_CLK_S3D4),
  180. DEF_MOD("gpio2", 910, R8A774B1_CLK_S3D4),
  181. DEF_MOD("gpio1", 911, R8A774B1_CLK_S3D4),
  182. DEF_MOD("gpio0", 912, R8A774B1_CLK_S3D4),
  183. DEF_MOD("can-fd", 914, R8A774B1_CLK_S3D2),
  184. DEF_MOD("can-if1", 915, R8A774B1_CLK_S3D4),
  185. DEF_MOD("can-if0", 916, R8A774B1_CLK_S3D4),
  186. DEF_MOD("rpc-if", 917, R8A774B1_CLK_RPCD2),
  187. DEF_MOD("i2c6", 918, R8A774B1_CLK_S0D6),
  188. DEF_MOD("i2c5", 919, R8A774B1_CLK_S0D6),
  189. DEF_MOD("i2c-dvfs", 926, R8A774B1_CLK_CP),
  190. DEF_MOD("i2c4", 927, R8A774B1_CLK_S0D6),
  191. DEF_MOD("i2c3", 928, R8A774B1_CLK_S0D6),
  192. DEF_MOD("i2c2", 929, R8A774B1_CLK_S3D2),
  193. DEF_MOD("i2c1", 930, R8A774B1_CLK_S3D2),
  194. DEF_MOD("i2c0", 931, R8A774B1_CLK_S3D2),
  195. DEF_MOD("ssi-all", 1005, R8A774B1_CLK_S3D4),
  196. DEF_MOD("ssi9", 1006, MOD_CLK_ID(1005)),
  197. DEF_MOD("ssi8", 1007, MOD_CLK_ID(1005)),
  198. DEF_MOD("ssi7", 1008, MOD_CLK_ID(1005)),
  199. DEF_MOD("ssi6", 1009, MOD_CLK_ID(1005)),
  200. DEF_MOD("ssi5", 1010, MOD_CLK_ID(1005)),
  201. DEF_MOD("ssi4", 1011, MOD_CLK_ID(1005)),
  202. DEF_MOD("ssi3", 1012, MOD_CLK_ID(1005)),
  203. DEF_MOD("ssi2", 1013, MOD_CLK_ID(1005)),
  204. DEF_MOD("ssi1", 1014, MOD_CLK_ID(1005)),
  205. DEF_MOD("ssi0", 1015, MOD_CLK_ID(1005)),
  206. DEF_MOD("scu-all", 1017, R8A774B1_CLK_S3D4),
  207. DEF_MOD("scu-dvc1", 1018, MOD_CLK_ID(1017)),
  208. DEF_MOD("scu-dvc0", 1019, MOD_CLK_ID(1017)),
  209. DEF_MOD("scu-ctu1-mix1", 1020, MOD_CLK_ID(1017)),
  210. DEF_MOD("scu-ctu0-mix0", 1021, MOD_CLK_ID(1017)),
  211. DEF_MOD("scu-src9", 1022, MOD_CLK_ID(1017)),
  212. DEF_MOD("scu-src8", 1023, MOD_CLK_ID(1017)),
  213. DEF_MOD("scu-src7", 1024, MOD_CLK_ID(1017)),
  214. DEF_MOD("scu-src6", 1025, MOD_CLK_ID(1017)),
  215. DEF_MOD("scu-src5", 1026, MOD_CLK_ID(1017)),
  216. DEF_MOD("scu-src4", 1027, MOD_CLK_ID(1017)),
  217. DEF_MOD("scu-src3", 1028, MOD_CLK_ID(1017)),
  218. DEF_MOD("scu-src2", 1029, MOD_CLK_ID(1017)),
  219. DEF_MOD("scu-src1", 1030, MOD_CLK_ID(1017)),
  220. DEF_MOD("scu-src0", 1031, MOD_CLK_ID(1017)),
  221. };
  222. /*
  223. * CPG Clock Data
  224. */
  225. /*
  226. * MD EXTAL PLL0 PLL1 PLL3 PLL4 OSC
  227. * 14 13 19 17 (MHz)
  228. *-----------------------------------------------------------------
  229. * 0 0 0 0 16.66 x 1 x180 x192 x192 x144 /16
  230. * 0 0 0 1 16.66 x 1 x180 x192 x128 x144 /16
  231. * 0 0 1 0 Prohibited setting
  232. * 0 0 1 1 16.66 x 1 x180 x192 x192 x144 /16
  233. * 0 1 0 0 20 x 1 x150 x160 x160 x120 /19
  234. * 0 1 0 1 20 x 1 x150 x160 x106 x120 /19
  235. * 0 1 1 0 Prohibited setting
  236. * 0 1 1 1 20 x 1 x150 x160 x160 x120 /19
  237. * 1 0 0 0 25 x 1 x120 x128 x128 x96 /24
  238. * 1 0 0 1 25 x 1 x120 x128 x84 x96 /24
  239. * 1 0 1 0 Prohibited setting
  240. * 1 0 1 1 25 x 1 x120 x128 x128 x96 /24
  241. * 1 1 0 0 33.33 / 2 x180 x192 x192 x144 /32
  242. * 1 1 0 1 33.33 / 2 x180 x192 x128 x144 /32
  243. * 1 1 1 0 Prohibited setting
  244. * 1 1 1 1 33.33 / 2 x180 x192 x192 x144 /32
  245. */
  246. #define CPG_PLL_CONFIG_INDEX(md) ((((md) & BIT(14)) >> 11) | \
  247. (((md) & BIT(13)) >> 11) | \
  248. (((md) & BIT(19)) >> 18) | \
  249. (((md) & BIT(17)) >> 17))
  250. static const struct rcar_gen3_cpg_pll_config cpg_pll_configs[16] = {
  251. /* EXTAL div PLL1 mult/div PLL3 mult/div OSC prediv */
  252. { 1, 192, 1, 192, 1, 16, },
  253. { 1, 192, 1, 128, 1, 16, },
  254. { 0, /* Prohibited setting */ },
  255. { 1, 192, 1, 192, 1, 16, },
  256. { 1, 160, 1, 160, 1, 19, },
  257. { 1, 160, 1, 106, 1, 19, },
  258. { 0, /* Prohibited setting */ },
  259. { 1, 160, 1, 160, 1, 19, },
  260. { 1, 128, 1, 128, 1, 24, },
  261. { 1, 128, 1, 84, 1, 24, },
  262. { 0, /* Prohibited setting */ },
  263. { 1, 128, 1, 128, 1, 24, },
  264. { 2, 192, 1, 192, 1, 32, },
  265. { 2, 192, 1, 128, 1, 32, },
  266. { 0, /* Prohibited setting */ },
  267. { 2, 192, 1, 192, 1, 32, },
  268. };
  269. /* RMSTPCR[0-11] is not present on RZ/G2N */
  270. static const struct mstp_stop_table r8a774b1_mstp_table[] = {
  271. { 0x00200000, 0x0, 0x0, 0 },
  272. { 0xFFFFFFFF, 0x0, 0x0, 0 },
  273. { 0x340E2FDC, 0x2040, 0x0, 0 },
  274. { 0xFFFFFFDF, 0x400, 0x0, 0 },
  275. { 0x80000184, 0x180, 0x0, 0 },
  276. { 0xC3FFFFFF, 0x0, 0x0, 0 },
  277. { 0xFFFFFFFF, 0x0, 0x0, 0 },
  278. { 0xFFFFFFFF, 0x0, 0x0, 0 },
  279. { 0x01F1FFF7, 0x0, 0x0, 0 },
  280. { 0xFFFFFFFE, 0x0, 0x0, 0 },
  281. { 0xFFFEFFE0, 0x0, 0x0, 0 },
  282. { 0x000000B7, 0x0, 0x0, 0 },
  283. };
  284. static const void *r8a774b1_get_pll_config(const u32 cpg_mode)
  285. {
  286. return &cpg_pll_configs[CPG_PLL_CONFIG_INDEX(cpg_mode)];
  287. }
  288. static const struct cpg_mssr_info r8a774b1_cpg_mssr_info = {
  289. .core_clk = r8a774b1_core_clks,
  290. .core_clk_size = ARRAY_SIZE(r8a774b1_core_clks),
  291. .mod_clk = r8a774b1_mod_clks,
  292. .mod_clk_size = ARRAY_SIZE(r8a774b1_mod_clks),
  293. .mstp_table = r8a774b1_mstp_table,
  294. .mstp_table_size = ARRAY_SIZE(r8a774b1_mstp_table),
  295. .reset_node = "renesas,r8a774b1-rst",
  296. .reset_modemr_offset = CPG_RST_MODEMR,
  297. .extalr_node = "extalr",
  298. .mod_clk_base = MOD_CLK_BASE,
  299. .clk_extal_id = CLK_EXTAL,
  300. .clk_extalr_id = CLK_EXTALR,
  301. .get_pll_config = r8a774b1_get_pll_config,
  302. };
  303. static const struct udevice_id r8a774b1_clk_ids[] = {
  304. {
  305. .compatible = "renesas,r8a774b1-cpg-mssr",
  306. .data = (ulong)&r8a774b1_cpg_mssr_info,
  307. },
  308. { }
  309. };
  310. U_BOOT_DRIVER(clk_r8a774b1) = {
  311. .name = "clk_r8a774b1",
  312. .id = UCLASS_CLK,
  313. .of_match = r8a774b1_clk_ids,
  314. .priv_auto = sizeof(struct gen3_clk_priv),
  315. .ops = &gen3_clk_ops,
  316. .probe = gen3_clk_probe,
  317. .remove = gen3_clk_remove,
  318. };