sh_pfc.h 22 KB

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  1. /*
  2. * SuperH Pin Function Controller Support
  3. *
  4. * Copyright (c) 2008 Magnus Damm
  5. *
  6. * This file is subject to the terms and conditions of the GNU General Public
  7. * License. See the file "COPYING" in the main directory of this archive
  8. * for more details.
  9. */
  10. #ifndef __SH_PFC_H
  11. #define __SH_PFC_H
  12. #include <linux/stringify.h>
  13. enum {
  14. PINMUX_TYPE_NONE,
  15. PINMUX_TYPE_FUNCTION,
  16. PINMUX_TYPE_GPIO,
  17. PINMUX_TYPE_OUTPUT,
  18. PINMUX_TYPE_INPUT,
  19. };
  20. #define SH_PFC_PIN_CFG_INPUT (1 << 0)
  21. #define SH_PFC_PIN_CFG_OUTPUT (1 << 1)
  22. #define SH_PFC_PIN_CFG_PULL_UP (1 << 2)
  23. #define SH_PFC_PIN_CFG_PULL_DOWN (1 << 3)
  24. #define SH_PFC_PIN_CFG_IO_VOLTAGE (1 << 4)
  25. #define SH_PFC_PIN_CFG_DRIVE_STRENGTH (1 << 5)
  26. #define SH_PFC_PIN_CFG_NO_GPIO (1 << 31)
  27. struct sh_pfc_pin {
  28. u16 pin;
  29. u16 enum_id;
  30. const char *name;
  31. unsigned int configs;
  32. };
  33. #define SH_PFC_PIN_GROUP_ALIAS(alias, n) \
  34. { \
  35. .name = #alias, \
  36. .pins = n##_pins, \
  37. .mux = n##_mux, \
  38. .nr_pins = ARRAY_SIZE(n##_pins) + \
  39. BUILD_BUG_ON_ZERO(sizeof(n##_pins) != sizeof(n##_mux)), \
  40. }
  41. #define SH_PFC_PIN_GROUP(n) SH_PFC_PIN_GROUP_ALIAS(n, n)
  42. struct sh_pfc_pin_group {
  43. const char *name;
  44. const unsigned int *pins;
  45. const unsigned int *mux;
  46. unsigned int nr_pins;
  47. };
  48. /*
  49. * Using union vin_data{,12,16} saves memory occupied by the VIN data pins.
  50. * VIN_DATA_PIN_GROUP() is a macro used to describe the VIN pin groups
  51. * in this case. It accepts an optional 'version' argument used when the
  52. * same group can appear on a different set of pins.
  53. */
  54. #define VIN_DATA_PIN_GROUP(n, s, ...) \
  55. { \
  56. .name = #n#s#__VA_ARGS__, \
  57. .pins = n##__VA_ARGS__##_pins.data##s, \
  58. .mux = n##__VA_ARGS__##_mux.data##s, \
  59. .nr_pins = ARRAY_SIZE(n##__VA_ARGS__##_pins.data##s), \
  60. }
  61. union vin_data12 {
  62. unsigned int data12[12];
  63. unsigned int data10[10];
  64. unsigned int data8[8];
  65. };
  66. union vin_data16 {
  67. unsigned int data16[16];
  68. unsigned int data12[12];
  69. unsigned int data10[10];
  70. unsigned int data8[8];
  71. };
  72. union vin_data {
  73. unsigned int data24[24];
  74. unsigned int data20[20];
  75. unsigned int data16[16];
  76. unsigned int data12[12];
  77. unsigned int data10[10];
  78. unsigned int data8[8];
  79. unsigned int data4[4];
  80. };
  81. #define SH_PFC_FUNCTION(n) \
  82. { \
  83. .name = #n, \
  84. .groups = n##_groups, \
  85. .nr_groups = ARRAY_SIZE(n##_groups), \
  86. }
  87. struct sh_pfc_function {
  88. const char *name;
  89. const char * const *groups;
  90. unsigned int nr_groups;
  91. };
  92. struct pinmux_func {
  93. u16 enum_id;
  94. const char *name;
  95. };
  96. struct pinmux_cfg_reg {
  97. u32 reg;
  98. u8 reg_width, field_width;
  99. #ifdef DEBUG
  100. u16 nr_enum_ids; /* for variable width regs only */
  101. #define SET_NR_ENUM_IDS(n) .nr_enum_ids = n,
  102. #else
  103. #define SET_NR_ENUM_IDS(n)
  104. #endif
  105. const u16 *enum_ids;
  106. const u8 *var_field_width;
  107. };
  108. #define GROUP(...) __VA_ARGS__
  109. /*
  110. * Describe a config register consisting of several fields of the same width
  111. * - name: Register name (unused, for documentation purposes only)
  112. * - r: Physical register address
  113. * - r_width: Width of the register (in bits)
  114. * - f_width: Width of the fixed-width register fields (in bits)
  115. * - ids: For each register field (from left to right, i.e. MSB to LSB),
  116. * 2^f_width enum IDs must be specified, one for each possible
  117. * combination of the register field bit values, all wrapped using
  118. * the GROUP() macro.
  119. */
  120. #define PINMUX_CFG_REG(name, r, r_width, f_width, ids) \
  121. .reg = r, .reg_width = r_width, \
  122. .field_width = f_width + BUILD_BUG_ON_ZERO(r_width % f_width) + \
  123. BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
  124. (r_width / f_width) * (1 << f_width)), \
  125. .enum_ids = (const u16 [(r_width / f_width) * (1 << f_width)]) \
  126. { ids }
  127. /*
  128. * Describe a config register consisting of several fields of different widths
  129. * - name: Register name (unused, for documentation purposes only)
  130. * - r: Physical register address
  131. * - r_width: Width of the register (in bits)
  132. * - f_widths: List of widths of the register fields (in bits), from left
  133. * to right (i.e. MSB to LSB), wrapped using the GROUP() macro.
  134. * - ids: For each register field (from left to right, i.e. MSB to LSB),
  135. * 2^f_widths[i] enum IDs must be specified, one for each possible
  136. * combination of the register field bit values, all wrapped using
  137. * the GROUP() macro.
  138. */
  139. #define PINMUX_CFG_REG_VAR(name, r, r_width, f_widths, ids) \
  140. .reg = r, .reg_width = r_width, \
  141. .var_field_width = (const u8 []) { f_widths, 0 }, \
  142. SET_NR_ENUM_IDS(sizeof((const u16 []) { ids }) / sizeof(u16)) \
  143. .enum_ids = (const u16 []) { ids }
  144. struct pinmux_drive_reg_field {
  145. u16 pin;
  146. u8 offset;
  147. u8 size;
  148. };
  149. struct pinmux_drive_reg {
  150. u32 reg;
  151. const struct pinmux_drive_reg_field fields[8];
  152. };
  153. #define PINMUX_DRIVE_REG(name, r) \
  154. .reg = r, \
  155. .fields =
  156. struct pinmux_bias_reg {
  157. u32 puen; /* Pull-enable or pull-up control register */
  158. u32 pud; /* Pull-up/down control register (optional) */
  159. const u16 pins[32];
  160. };
  161. #define PINMUX_BIAS_REG(name1, r1, name2, r2) \
  162. .puen = r1, \
  163. .pud = r2, \
  164. .pins =
  165. struct pinmux_ioctrl_reg {
  166. u32 reg;
  167. };
  168. struct pinmux_data_reg {
  169. u32 reg;
  170. u8 reg_width;
  171. const u16 *enum_ids;
  172. };
  173. /*
  174. * Describe a data register
  175. * - name: Register name (unused, for documentation purposes only)
  176. * - r: Physical register address
  177. * - r_width: Width of the register (in bits)
  178. * - ids: For each register bit (from left to right, i.e. MSB to LSB), one
  179. * enum ID must be specified, all wrapped using the GROUP() macro.
  180. */
  181. #define PINMUX_DATA_REG(name, r, r_width, ids) \
  182. .reg = r, .reg_width = r_width + \
  183. BUILD_BUG_ON_ZERO(sizeof((const u16 []) { ids }) / sizeof(u16) != \
  184. r_width), \
  185. .enum_ids = (const u16 [r_width]) { ids }
  186. struct pinmux_irq {
  187. const short *gpios;
  188. };
  189. /*
  190. * Describe the mapping from GPIOs to a single IRQ
  191. * - ids...: List of GPIOs that are mapped to the same IRQ
  192. */
  193. #define PINMUX_IRQ(ids...) \
  194. { .gpios = (const short []) { ids, -1 } }
  195. struct pinmux_range {
  196. u16 begin;
  197. u16 end;
  198. u16 force;
  199. };
  200. struct sh_pfc_window {
  201. phys_addr_t phys;
  202. void __iomem *virt;
  203. unsigned long size;
  204. };
  205. struct sh_pfc_pin_range;
  206. struct sh_pfc {
  207. struct device *dev;
  208. const struct sh_pfc_soc_info *info;
  209. void *regs;
  210. struct sh_pfc_pin_range *ranges;
  211. unsigned int nr_ranges;
  212. unsigned int nr_gpio_pins;
  213. struct sh_pfc_chip *gpio;
  214. };
  215. struct sh_pfc_soc_operations {
  216. int (*init)(struct sh_pfc *pfc);
  217. unsigned int (*get_bias)(struct sh_pfc *pfc, unsigned int pin);
  218. void (*set_bias)(struct sh_pfc *pfc, unsigned int pin,
  219. unsigned int bias);
  220. int (*pin_to_pocctrl)(struct sh_pfc *pfc, unsigned int pin, u32 *pocctrl);
  221. };
  222. struct sh_pfc_soc_info {
  223. const char *name;
  224. const struct sh_pfc_soc_operations *ops;
  225. struct pinmux_range input;
  226. struct pinmux_range output;
  227. struct pinmux_range function;
  228. const struct sh_pfc_pin *pins;
  229. unsigned int nr_pins;
  230. const struct sh_pfc_pin_group *groups;
  231. unsigned int nr_groups;
  232. const struct sh_pfc_function *functions;
  233. unsigned int nr_functions;
  234. const struct pinmux_cfg_reg *cfg_regs;
  235. const struct pinmux_drive_reg *drive_regs;
  236. const struct pinmux_bias_reg *bias_regs;
  237. const struct pinmux_ioctrl_reg *ioctrl_regs;
  238. const struct pinmux_data_reg *data_regs;
  239. const u16 *pinmux_data;
  240. unsigned int pinmux_data_size;
  241. const struct pinmux_irq *gpio_irq;
  242. unsigned int gpio_irq_size;
  243. u32 unlock_reg; /* can be literal address or mask */
  244. };
  245. u32 sh_pfc_read(struct sh_pfc *pfc, u32 reg);
  246. void sh_pfc_write(struct sh_pfc *pfc, u32 reg, u32 data);
  247. const struct pinmux_bias_reg *
  248. sh_pfc_pin_to_bias_reg(const struct sh_pfc *pfc, unsigned int pin,
  249. unsigned int *bit);
  250. extern const struct sh_pfc_soc_info r8a774a1_pinmux_info;
  251. extern const struct sh_pfc_soc_info r8a774b1_pinmux_info;
  252. extern const struct sh_pfc_soc_info r8a774c0_pinmux_info;
  253. extern const struct sh_pfc_soc_info r8a774e1_pinmux_info;
  254. extern const struct sh_pfc_soc_info r8a7790_pinmux_info;
  255. extern const struct sh_pfc_soc_info r8a7791_pinmux_info;
  256. extern const struct sh_pfc_soc_info r8a7792_pinmux_info;
  257. extern const struct sh_pfc_soc_info r8a7793_pinmux_info;
  258. extern const struct sh_pfc_soc_info r8a7794_pinmux_info;
  259. extern const struct sh_pfc_soc_info r8a7795_pinmux_info;
  260. extern const struct sh_pfc_soc_info r8a7796_pinmux_info;
  261. extern const struct sh_pfc_soc_info r8a77965_pinmux_info;
  262. extern const struct sh_pfc_soc_info r8a77970_pinmux_info;
  263. extern const struct sh_pfc_soc_info r8a77980_pinmux_info;
  264. extern const struct sh_pfc_soc_info r8a77990_pinmux_info;
  265. extern const struct sh_pfc_soc_info r8a77995_pinmux_info;
  266. /* -----------------------------------------------------------------------------
  267. * Helper macros to create pin and port lists
  268. */
  269. /*
  270. * sh_pfc_soc_info pinmux_data array macros
  271. */
  272. /*
  273. * Describe generic pinmux data
  274. * - data_or_mark: *_DATA or *_MARK enum ID
  275. * - ids...: List of enum IDs to associate with data_or_mark
  276. */
  277. #define PINMUX_DATA(data_or_mark, ids...) data_or_mark, ids, 0
  278. /*
  279. * Describe a pinmux configuration without GPIO function that needs
  280. * configuration in a Peripheral Function Select Register (IPSR)
  281. * - ipsr: IPSR field (unused, for documentation purposes only)
  282. * - fn: Function name, referring to a field in the IPSR
  283. */
  284. #define PINMUX_IPSR_NOGP(ipsr, fn) \
  285. PINMUX_DATA(fn##_MARK, FN_##fn)
  286. /*
  287. * Describe a pinmux configuration with GPIO function that needs configuration
  288. * in both a Peripheral Function Select Register (IPSR) and in a
  289. * GPIO/Peripheral Function Select Register (GPSR)
  290. * - ipsr: IPSR field
  291. * - fn: Function name, also referring to the IPSR field
  292. */
  293. #define PINMUX_IPSR_GPSR(ipsr, fn) \
  294. PINMUX_DATA(fn##_MARK, FN_##fn, FN_##ipsr)
  295. /*
  296. * Describe a pinmux configuration without GPIO function that needs
  297. * configuration in a Peripheral Function Select Register (IPSR), and where the
  298. * pinmux function has a representation in a Module Select Register (MOD_SEL).
  299. * - ipsr: IPSR field (unused, for documentation purposes only)
  300. * - fn: Function name, also referring to the IPSR field
  301. * - msel: Module selector
  302. */
  303. #define PINMUX_IPSR_NOGM(ipsr, fn, msel) \
  304. PINMUX_DATA(fn##_MARK, FN_##fn, FN_##msel)
  305. /*
  306. * Describe a pinmux configuration with GPIO function where the pinmux function
  307. * has no representation in a Peripheral Function Select Register (IPSR), but
  308. * instead solely depends on a group selection.
  309. * - gpsr: GPSR field
  310. * - fn: Function name, also referring to the GPSR field
  311. * - gsel: Group selector
  312. */
  313. #define PINMUX_IPSR_NOFN(gpsr, fn, gsel) \
  314. PINMUX_DATA(fn##_MARK, FN_##gpsr, FN_##gsel)
  315. /*
  316. * Describe a pinmux configuration with GPIO function that needs configuration
  317. * in both a Peripheral Function Select Register (IPSR) and a GPIO/Peripheral
  318. * Function Select Register (GPSR), and where the pinmux function has a
  319. * representation in a Module Select Register (MOD_SEL).
  320. * - ipsr: IPSR field
  321. * - fn: Function name, also referring to the IPSR field
  322. * - msel: Module selector
  323. */
  324. #define PINMUX_IPSR_MSEL(ipsr, fn, msel) \
  325. PINMUX_DATA(fn##_MARK, FN_##msel, FN_##fn, FN_##ipsr)
  326. /*
  327. * Describe a pinmux configuration similar to PINMUX_IPSR_MSEL, but with
  328. * an additional select register that controls physical multiplexing
  329. * with another pin.
  330. * - ipsr: IPSR field
  331. * - fn: Function name, also referring to the IPSR field
  332. * - psel: Physical multiplexing selector
  333. * - msel: Module selector
  334. */
  335. #define PINMUX_IPSR_PHYS_MSEL(ipsr, fn, psel, msel) \
  336. PINMUX_DATA(fn##_MARK, FN_##psel, FN_##msel, FN_##fn, FN_##ipsr)
  337. /*
  338. * Describe a pinmux configuration in which a pin is physically multiplexed
  339. * with other pins.
  340. * - ipsr: IPSR field (unused, for documentation purposes only)
  341. * - fn: Function name
  342. * - psel: Physical multiplexing selector
  343. */
  344. #define PINMUX_IPSR_PHYS(ipsr, fn, psel) \
  345. PINMUX_DATA(fn##_MARK, FN_##psel)
  346. /*
  347. * Describe a pinmux configuration for a single-function pin with GPIO
  348. * capability.
  349. * - fn: Function name
  350. */
  351. #define PINMUX_SINGLE(fn) \
  352. PINMUX_DATA(fn##_MARK, FN_##fn)
  353. /*
  354. * GP port style (32 ports banks)
  355. */
  356. #define PORT_GP_CFG_1(bank, pin, fn, sfx, cfg) \
  357. fn(bank, pin, GP_##bank##_##pin, sfx, cfg)
  358. #define PORT_GP_1(bank, pin, fn, sfx) PORT_GP_CFG_1(bank, pin, fn, sfx, 0)
  359. #define PORT_GP_CFG_4(bank, fn, sfx, cfg) \
  360. PORT_GP_CFG_1(bank, 0, fn, sfx, cfg), \
  361. PORT_GP_CFG_1(bank, 1, fn, sfx, cfg), \
  362. PORT_GP_CFG_1(bank, 2, fn, sfx, cfg), \
  363. PORT_GP_CFG_1(bank, 3, fn, sfx, cfg)
  364. #define PORT_GP_4(bank, fn, sfx) PORT_GP_CFG_4(bank, fn, sfx, 0)
  365. #define PORT_GP_CFG_6(bank, fn, sfx, cfg) \
  366. PORT_GP_CFG_4(bank, fn, sfx, cfg), \
  367. PORT_GP_CFG_1(bank, 4, fn, sfx, cfg), \
  368. PORT_GP_CFG_1(bank, 5, fn, sfx, cfg)
  369. #define PORT_GP_6(bank, fn, sfx) PORT_GP_CFG_6(bank, fn, sfx, 0)
  370. #define PORT_GP_CFG_8(bank, fn, sfx, cfg) \
  371. PORT_GP_CFG_6(bank, fn, sfx, cfg), \
  372. PORT_GP_CFG_1(bank, 6, fn, sfx, cfg), \
  373. PORT_GP_CFG_1(bank, 7, fn, sfx, cfg)
  374. #define PORT_GP_8(bank, fn, sfx) PORT_GP_CFG_8(bank, fn, sfx, 0)
  375. #define PORT_GP_CFG_9(bank, fn, sfx, cfg) \
  376. PORT_GP_CFG_8(bank, fn, sfx, cfg), \
  377. PORT_GP_CFG_1(bank, 8, fn, sfx, cfg)
  378. #define PORT_GP_9(bank, fn, sfx) PORT_GP_CFG_9(bank, fn, sfx, 0)
  379. #define PORT_GP_CFG_10(bank, fn, sfx, cfg) \
  380. PORT_GP_CFG_9(bank, fn, sfx, cfg), \
  381. PORT_GP_CFG_1(bank, 9, fn, sfx, cfg)
  382. #define PORT_GP_10(bank, fn, sfx) PORT_GP_CFG_10(bank, fn, sfx, 0)
  383. #define PORT_GP_CFG_11(bank, fn, sfx, cfg) \
  384. PORT_GP_CFG_10(bank, fn, sfx, cfg), \
  385. PORT_GP_CFG_1(bank, 10, fn, sfx, cfg)
  386. #define PORT_GP_11(bank, fn, sfx) PORT_GP_CFG_11(bank, fn, sfx, 0)
  387. #define PORT_GP_CFG_12(bank, fn, sfx, cfg) \
  388. PORT_GP_CFG_11(bank, fn, sfx, cfg), \
  389. PORT_GP_CFG_1(bank, 11, fn, sfx, cfg)
  390. #define PORT_GP_12(bank, fn, sfx) PORT_GP_CFG_12(bank, fn, sfx, 0)
  391. #define PORT_GP_CFG_14(bank, fn, sfx, cfg) \
  392. PORT_GP_CFG_12(bank, fn, sfx, cfg), \
  393. PORT_GP_CFG_1(bank, 12, fn, sfx, cfg), \
  394. PORT_GP_CFG_1(bank, 13, fn, sfx, cfg)
  395. #define PORT_GP_14(bank, fn, sfx) PORT_GP_CFG_14(bank, fn, sfx, 0)
  396. #define PORT_GP_CFG_15(bank, fn, sfx, cfg) \
  397. PORT_GP_CFG_14(bank, fn, sfx, cfg), \
  398. PORT_GP_CFG_1(bank, 14, fn, sfx, cfg)
  399. #define PORT_GP_15(bank, fn, sfx) PORT_GP_CFG_15(bank, fn, sfx, 0)
  400. #define PORT_GP_CFG_16(bank, fn, sfx, cfg) \
  401. PORT_GP_CFG_15(bank, fn, sfx, cfg), \
  402. PORT_GP_CFG_1(bank, 15, fn, sfx, cfg)
  403. #define PORT_GP_16(bank, fn, sfx) PORT_GP_CFG_16(bank, fn, sfx, 0)
  404. #define PORT_GP_CFG_17(bank, fn, sfx, cfg) \
  405. PORT_GP_CFG_16(bank, fn, sfx, cfg), \
  406. PORT_GP_CFG_1(bank, 16, fn, sfx, cfg)
  407. #define PORT_GP_17(bank, fn, sfx) PORT_GP_CFG_17(bank, fn, sfx, 0)
  408. #define PORT_GP_CFG_18(bank, fn, sfx, cfg) \
  409. PORT_GP_CFG_17(bank, fn, sfx, cfg), \
  410. PORT_GP_CFG_1(bank, 17, fn, sfx, cfg)
  411. #define PORT_GP_18(bank, fn, sfx) PORT_GP_CFG_18(bank, fn, sfx, 0)
  412. #define PORT_GP_CFG_20(bank, fn, sfx, cfg) \
  413. PORT_GP_CFG_18(bank, fn, sfx, cfg), \
  414. PORT_GP_CFG_1(bank, 18, fn, sfx, cfg), \
  415. PORT_GP_CFG_1(bank, 19, fn, sfx, cfg)
  416. #define PORT_GP_20(bank, fn, sfx) PORT_GP_CFG_20(bank, fn, sfx, 0)
  417. #define PORT_GP_CFG_21(bank, fn, sfx, cfg) \
  418. PORT_GP_CFG_20(bank, fn, sfx, cfg), \
  419. PORT_GP_CFG_1(bank, 20, fn, sfx, cfg)
  420. #define PORT_GP_21(bank, fn, sfx) PORT_GP_CFG_21(bank, fn, sfx, 0)
  421. #define PORT_GP_CFG_22(bank, fn, sfx, cfg) \
  422. PORT_GP_CFG_21(bank, fn, sfx, cfg), \
  423. PORT_GP_CFG_1(bank, 21, fn, sfx, cfg)
  424. #define PORT_GP_22(bank, fn, sfx) PORT_GP_CFG_22(bank, fn, sfx, 0)
  425. #define PORT_GP_CFG_23(bank, fn, sfx, cfg) \
  426. PORT_GP_CFG_22(bank, fn, sfx, cfg), \
  427. PORT_GP_CFG_1(bank, 22, fn, sfx, cfg)
  428. #define PORT_GP_23(bank, fn, sfx) PORT_GP_CFG_23(bank, fn, sfx, 0)
  429. #define PORT_GP_CFG_24(bank, fn, sfx, cfg) \
  430. PORT_GP_CFG_23(bank, fn, sfx, cfg), \
  431. PORT_GP_CFG_1(bank, 23, fn, sfx, cfg)
  432. #define PORT_GP_24(bank, fn, sfx) PORT_GP_CFG_24(bank, fn, sfx, 0)
  433. #define PORT_GP_CFG_25(bank, fn, sfx, cfg) \
  434. PORT_GP_CFG_24(bank, fn, sfx, cfg), \
  435. PORT_GP_CFG_1(bank, 24, fn, sfx, cfg)
  436. #define PORT_GP_25(bank, fn, sfx) PORT_GP_CFG_25(bank, fn, sfx, 0)
  437. #define PORT_GP_CFG_26(bank, fn, sfx, cfg) \
  438. PORT_GP_CFG_25(bank, fn, sfx, cfg), \
  439. PORT_GP_CFG_1(bank, 25, fn, sfx, cfg)
  440. #define PORT_GP_26(bank, fn, sfx) PORT_GP_CFG_26(bank, fn, sfx, 0)
  441. #define PORT_GP_CFG_28(bank, fn, sfx, cfg) \
  442. PORT_GP_CFG_26(bank, fn, sfx, cfg), \
  443. PORT_GP_CFG_1(bank, 26, fn, sfx, cfg), \
  444. PORT_GP_CFG_1(bank, 27, fn, sfx, cfg)
  445. #define PORT_GP_28(bank, fn, sfx) PORT_GP_CFG_28(bank, fn, sfx, 0)
  446. #define PORT_GP_CFG_29(bank, fn, sfx, cfg) \
  447. PORT_GP_CFG_28(bank, fn, sfx, cfg), \
  448. PORT_GP_CFG_1(bank, 28, fn, sfx, cfg)
  449. #define PORT_GP_29(bank, fn, sfx) PORT_GP_CFG_29(bank, fn, sfx, 0)
  450. #define PORT_GP_CFG_30(bank, fn, sfx, cfg) \
  451. PORT_GP_CFG_29(bank, fn, sfx, cfg), \
  452. PORT_GP_CFG_1(bank, 29, fn, sfx, cfg)
  453. #define PORT_GP_30(bank, fn, sfx) PORT_GP_CFG_30(bank, fn, sfx, 0)
  454. #define PORT_GP_CFG_32(bank, fn, sfx, cfg) \
  455. PORT_GP_CFG_30(bank, fn, sfx, cfg), \
  456. PORT_GP_CFG_1(bank, 30, fn, sfx, cfg), \
  457. PORT_GP_CFG_1(bank, 31, fn, sfx, cfg)
  458. #define PORT_GP_32(bank, fn, sfx) PORT_GP_CFG_32(bank, fn, sfx, 0)
  459. #define PORT_GP_32_REV(bank, fn, sfx) \
  460. PORT_GP_1(bank, 31, fn, sfx), PORT_GP_1(bank, 30, fn, sfx), \
  461. PORT_GP_1(bank, 29, fn, sfx), PORT_GP_1(bank, 28, fn, sfx), \
  462. PORT_GP_1(bank, 27, fn, sfx), PORT_GP_1(bank, 26, fn, sfx), \
  463. PORT_GP_1(bank, 25, fn, sfx), PORT_GP_1(bank, 24, fn, sfx), \
  464. PORT_GP_1(bank, 23, fn, sfx), PORT_GP_1(bank, 22, fn, sfx), \
  465. PORT_GP_1(bank, 21, fn, sfx), PORT_GP_1(bank, 20, fn, sfx), \
  466. PORT_GP_1(bank, 19, fn, sfx), PORT_GP_1(bank, 18, fn, sfx), \
  467. PORT_GP_1(bank, 17, fn, sfx), PORT_GP_1(bank, 16, fn, sfx), \
  468. PORT_GP_1(bank, 15, fn, sfx), PORT_GP_1(bank, 14, fn, sfx), \
  469. PORT_GP_1(bank, 13, fn, sfx), PORT_GP_1(bank, 12, fn, sfx), \
  470. PORT_GP_1(bank, 11, fn, sfx), PORT_GP_1(bank, 10, fn, sfx), \
  471. PORT_GP_1(bank, 9, fn, sfx), PORT_GP_1(bank, 8, fn, sfx), \
  472. PORT_GP_1(bank, 7, fn, sfx), PORT_GP_1(bank, 6, fn, sfx), \
  473. PORT_GP_1(bank, 5, fn, sfx), PORT_GP_1(bank, 4, fn, sfx), \
  474. PORT_GP_1(bank, 3, fn, sfx), PORT_GP_1(bank, 2, fn, sfx), \
  475. PORT_GP_1(bank, 1, fn, sfx), PORT_GP_1(bank, 0, fn, sfx)
  476. /* GP_ALL(suffix) - Expand to a list of GP_#_#_suffix */
  477. #define _GP_ALL(bank, pin, name, sfx, cfg) name##_##sfx
  478. #define GP_ALL(str) CPU_ALL_PORT(_GP_ALL, str)
  479. /* PINMUX_GPIO_GP_ALL - Expand to a list of sh_pfc_pin entries */
  480. #define _GP_GPIO(bank, _pin, _name, sfx, cfg) \
  481. { \
  482. .pin = (bank * 32) + _pin, \
  483. .name = __stringify(_name), \
  484. .enum_id = _name##_DATA, \
  485. .configs = cfg, \
  486. }
  487. #define PINMUX_GPIO_GP_ALL() CPU_ALL_PORT(_GP_GPIO, unused)
  488. /* PINMUX_DATA_GP_ALL - Expand to a list of name_DATA, name_FN marks */
  489. #define _GP_DATA(bank, pin, name, sfx, cfg) PINMUX_DATA(name##_DATA, name##_FN)
  490. #define PINMUX_DATA_GP_ALL() CPU_ALL_PORT(_GP_DATA, unused)
  491. /*
  492. * PORT style (linear pin space)
  493. */
  494. #define PORT_1(pn, fn, pfx, sfx) fn(pn, pfx, sfx)
  495. #define PORT_10(pn, fn, pfx, sfx) \
  496. PORT_1(pn, fn, pfx##0, sfx), PORT_1(pn+1, fn, pfx##1, sfx), \
  497. PORT_1(pn+2, fn, pfx##2, sfx), PORT_1(pn+3, fn, pfx##3, sfx), \
  498. PORT_1(pn+4, fn, pfx##4, sfx), PORT_1(pn+5, fn, pfx##5, sfx), \
  499. PORT_1(pn+6, fn, pfx##6, sfx), PORT_1(pn+7, fn, pfx##7, sfx), \
  500. PORT_1(pn+8, fn, pfx##8, sfx), PORT_1(pn+9, fn, pfx##9, sfx)
  501. #define PORT_90(pn, fn, pfx, sfx) \
  502. PORT_10(pn+10, fn, pfx##1, sfx), PORT_10(pn+20, fn, pfx##2, sfx), \
  503. PORT_10(pn+30, fn, pfx##3, sfx), PORT_10(pn+40, fn, pfx##4, sfx), \
  504. PORT_10(pn+50, fn, pfx##5, sfx), PORT_10(pn+60, fn, pfx##6, sfx), \
  505. PORT_10(pn+70, fn, pfx##7, sfx), PORT_10(pn+80, fn, pfx##8, sfx), \
  506. PORT_10(pn+90, fn, pfx##9, sfx)
  507. /* PORT_ALL(suffix) - Expand to a list of PORT_#_suffix */
  508. #define _PORT_ALL(pn, pfx, sfx) pfx##_##sfx
  509. #define PORT_ALL(str) CPU_ALL_PORT(_PORT_ALL, PORT, str)
  510. /* PINMUX_GPIO - Expand to a sh_pfc_pin entry */
  511. #define PINMUX_GPIO(_pin) \
  512. [GPIO_##_pin] = { \
  513. .pin = (u16)-1, \
  514. .name = __stringify(GPIO_##_pin), \
  515. .enum_id = _pin##_DATA, \
  516. }
  517. /* SH_PFC_PIN_CFG - Expand to a sh_pfc_pin entry (named PORT#) with config */
  518. #define SH_PFC_PIN_CFG(_pin, cfgs) \
  519. { \
  520. .pin = _pin, \
  521. .name = __stringify(PORT##_pin), \
  522. .enum_id = PORT##_pin##_DATA, \
  523. .configs = cfgs, \
  524. }
  525. /* SH_PFC_PIN_NAMED - Expand to a sh_pfc_pin entry with the given name */
  526. #define SH_PFC_PIN_NAMED(row, col, _name) \
  527. { \
  528. .pin = PIN_NUMBER(row, col), \
  529. .name = __stringify(PIN_##_name), \
  530. .configs = SH_PFC_PIN_CFG_NO_GPIO, \
  531. }
  532. /* SH_PFC_PIN_NAMED_CFG - Expand to a sh_pfc_pin entry with the given name */
  533. #define SH_PFC_PIN_NAMED_CFG(row, col, _name, cfgs) \
  534. { \
  535. .pin = PIN_NUMBER(row, col), \
  536. .name = __stringify(PIN_##_name), \
  537. .configs = SH_PFC_PIN_CFG_NO_GPIO | cfgs, \
  538. }
  539. /* PINMUX_DATA_ALL - Expand to a list of PORT_name_DATA, PORT_name_FN0,
  540. * PORT_name_OUT, PORT_name_IN marks
  541. */
  542. #define _PORT_DATA(pn, pfx, sfx) \
  543. PINMUX_DATA(PORT##pfx##_DATA, PORT##pfx##_FN0, \
  544. PORT##pfx##_OUT, PORT##pfx##_IN)
  545. #define PINMUX_DATA_ALL() CPU_ALL_PORT(_PORT_DATA, , unused)
  546. /* GPIO_FN(name) - Expand to a sh_pfc_pin entry for a function GPIO */
  547. #define PINMUX_GPIO_FN(gpio, base, data_or_mark) \
  548. [gpio - (base)] = { \
  549. .name = __stringify(gpio), \
  550. .enum_id = data_or_mark, \
  551. }
  552. #define GPIO_FN(str) \
  553. PINMUX_GPIO_FN(GPIO_FN_##str, PINMUX_FN_BASE, str##_MARK)
  554. /*
  555. * PORTnCR helper macro for SH-Mobile/R-Mobile
  556. */
  557. #define PORTCR(nr, reg) \
  558. { \
  559. PINMUX_CFG_REG_VAR("PORT" nr "CR", reg, 8, \
  560. GROUP(2, 2, 1, 3), \
  561. GROUP( \
  562. /* PULMD[1:0], handled by .set_bias() */ \
  563. 0, 0, 0, 0, \
  564. /* IE and OE */ \
  565. 0, PORT##nr##_OUT, PORT##nr##_IN, 0, \
  566. /* SEC, not supported */ \
  567. 0, 0, \
  568. /* PTMD[2:0] */ \
  569. PORT##nr##_FN0, PORT##nr##_FN1, \
  570. PORT##nr##_FN2, PORT##nr##_FN3, \
  571. PORT##nr##_FN4, PORT##nr##_FN5, \
  572. PORT##nr##_FN6, PORT##nr##_FN7 \
  573. )) \
  574. }
  575. /*
  576. * GPIO number helper macro for R-Car
  577. */
  578. #define RCAR_GP_PIN(bank, pin) (((bank) * 32) + (pin))
  579. #include <linux/bug.h>
  580. #endif /* __SH_PFC_H */