clk-rcar-gen3.c 11 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Renesas RCar Gen3 CPG MSSR driver
  4. *
  5. * Copyright (C) 2017 Marek Vasut <marek.vasut@gmail.com>
  6. *
  7. * Based on the following driver from Linux kernel:
  8. * r8a7796 Clock Pulse Generator / Module Standby and Software Reset
  9. *
  10. * Copyright (C) 2016 Glider bvba
  11. */
  12. #include <common.h>
  13. #include <clk-uclass.h>
  14. #include <dm.h>
  15. #include <errno.h>
  16. #include <log.h>
  17. #include <wait_bit.h>
  18. #include <asm/global_data.h>
  19. #include <asm/io.h>
  20. #include <linux/bitops.h>
  21. #include <dt-bindings/clock/renesas-cpg-mssr.h>
  22. #include "renesas-cpg-mssr.h"
  23. #include "rcar-gen3-cpg.h"
  24. #define CPG_PLL0CR 0x00d8
  25. #define CPG_PLL2CR 0x002c
  26. #define CPG_PLL4CR 0x01f4
  27. #define CPG_RPC_PREDIV_MASK 0x3
  28. #define CPG_RPC_PREDIV_OFFSET 3
  29. #define CPG_RPC_POSTDIV_MASK 0x7
  30. #define CPG_RPC_POSTDIV_OFFSET 0
  31. /*
  32. * SDn Clock
  33. */
  34. #define CPG_SD_STP_HCK BIT(9)
  35. #define CPG_SD_STP_CK BIT(8)
  36. #define CPG_SD_STP_MASK (CPG_SD_STP_HCK | CPG_SD_STP_CK)
  37. #define CPG_SD_FC_MASK (0x7 << 2 | 0x3 << 0)
  38. #define CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) \
  39. { \
  40. .val = ((stp_hck) ? CPG_SD_STP_HCK : 0) | \
  41. ((stp_ck) ? CPG_SD_STP_CK : 0) | \
  42. ((sd_srcfc) << 2) | \
  43. ((sd_fc) << 0), \
  44. .div = (sd_div), \
  45. }
  46. struct sd_div_table {
  47. u32 val;
  48. unsigned int div;
  49. };
  50. /* SDn divider
  51. * sd_srcfc sd_fc div
  52. * stp_hck stp_ck (div) (div) = sd_srcfc x sd_fc
  53. *-------------------------------------------------------------------
  54. * 0 0 0 (1) 1 (4) 4
  55. * 0 0 1 (2) 1 (4) 8
  56. * 1 0 2 (4) 1 (4) 16
  57. * 1 0 3 (8) 1 (4) 32
  58. * 1 0 4 (16) 1 (4) 64
  59. * 0 0 0 (1) 0 (2) 2
  60. * 0 0 1 (2) 0 (2) 4
  61. * 1 0 2 (4) 0 (2) 8
  62. * 1 0 3 (8) 0 (2) 16
  63. * 1 0 4 (16) 0 (2) 32
  64. */
  65. static const struct sd_div_table cpg_sd_div_table[] = {
  66. /* CPG_SD_DIV_TABLE_DATA(stp_hck, stp_ck, sd_srcfc, sd_fc, sd_div) */
  67. CPG_SD_DIV_TABLE_DATA(0, 0, 0, 1, 4),
  68. CPG_SD_DIV_TABLE_DATA(0, 0, 1, 1, 8),
  69. CPG_SD_DIV_TABLE_DATA(1, 0, 2, 1, 16),
  70. CPG_SD_DIV_TABLE_DATA(1, 0, 3, 1, 32),
  71. CPG_SD_DIV_TABLE_DATA(1, 0, 4, 1, 64),
  72. CPG_SD_DIV_TABLE_DATA(0, 0, 0, 0, 2),
  73. CPG_SD_DIV_TABLE_DATA(0, 0, 1, 0, 4),
  74. CPG_SD_DIV_TABLE_DATA(1, 0, 2, 0, 8),
  75. CPG_SD_DIV_TABLE_DATA(1, 0, 3, 0, 16),
  76. CPG_SD_DIV_TABLE_DATA(1, 0, 4, 0, 32),
  77. };
  78. static int gen3_clk_get_parent(struct gen3_clk_priv *priv, struct clk *clk,
  79. struct cpg_mssr_info *info, struct clk *parent)
  80. {
  81. const struct cpg_core_clk *core;
  82. int ret;
  83. if (!renesas_clk_is_mod(clk)) {
  84. ret = renesas_clk_get_core(clk, info, &core);
  85. if (ret)
  86. return ret;
  87. if (core->type == CLK_TYPE_GEN3_MDSEL) {
  88. parent->dev = clk->dev;
  89. parent->id = core->parent >> (priv->sscg ? 16 : 0);
  90. parent->id &= 0xffff;
  91. return 0;
  92. }
  93. }
  94. return renesas_clk_get_parent(clk, info, parent);
  95. }
  96. static int gen3_clk_setup_sdif_div(struct clk *clk, ulong rate)
  97. {
  98. struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
  99. struct cpg_mssr_info *info = priv->info;
  100. const struct cpg_core_clk *core;
  101. struct clk parent;
  102. int ret;
  103. ret = gen3_clk_get_parent(priv, clk, info, &parent);
  104. if (ret) {
  105. printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
  106. return ret;
  107. }
  108. if (renesas_clk_is_mod(&parent))
  109. return 0;
  110. ret = renesas_clk_get_core(&parent, info, &core);
  111. if (ret)
  112. return ret;
  113. if (core->type != CLK_TYPE_GEN3_SD)
  114. return 0;
  115. debug("%s[%i] SDIF offset=%x\n", __func__, __LINE__, core->offset);
  116. writel((rate == 400000000) ? 0x4 : 0x1, priv->base + core->offset);
  117. return 0;
  118. }
  119. static int gen3_clk_enable(struct clk *clk)
  120. {
  121. struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
  122. return renesas_clk_endisable(clk, priv->base, priv->info, true);
  123. }
  124. static int gen3_clk_disable(struct clk *clk)
  125. {
  126. struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
  127. return renesas_clk_endisable(clk, priv->base, priv->info, false);
  128. }
  129. static u64 gen3_clk_get_rate64(struct clk *clk);
  130. static u64 gen3_clk_get_rate64_pll_mul_reg(struct gen3_clk_priv *priv,
  131. struct clk *parent,
  132. const struct cpg_core_clk *core,
  133. u32 mul_reg, u32 mult, u32 div,
  134. char *name)
  135. {
  136. u32 value;
  137. u64 rate;
  138. if (mul_reg) {
  139. value = readl(priv->base + mul_reg);
  140. mult = (((value >> 24) & 0x7f) + 1) * 2;
  141. div = 1;
  142. }
  143. rate = (gen3_clk_get_rate64(parent) * mult) / div;
  144. debug("%s[%i] %s clk: parent=%i mult=%u div=%u => rate=%llu\n",
  145. __func__, __LINE__, name, core->parent, mult, div, rate);
  146. return rate;
  147. }
  148. static u64 gen3_clk_get_rate64(struct clk *clk)
  149. {
  150. struct gen3_clk_priv *priv = dev_get_priv(clk->dev);
  151. struct cpg_mssr_info *info = priv->info;
  152. struct clk parent;
  153. const struct cpg_core_clk *core;
  154. const struct rcar_gen3_cpg_pll_config *pll_config =
  155. priv->cpg_pll_config;
  156. u32 value, div, prediv, postdiv;
  157. u64 rate = 0;
  158. int i, ret;
  159. debug("%s[%i] Clock: id=%lu\n", __func__, __LINE__, clk->id);
  160. ret = gen3_clk_get_parent(priv, clk, info, &parent);
  161. if (ret) {
  162. printf("%s[%i] parent fail, ret=%i\n", __func__, __LINE__, ret);
  163. return ret;
  164. }
  165. if (renesas_clk_is_mod(clk)) {
  166. rate = gen3_clk_get_rate64(&parent);
  167. debug("%s[%i] MOD clk: parent=%lu => rate=%llu\n",
  168. __func__, __LINE__, parent.id, rate);
  169. return rate;
  170. }
  171. ret = renesas_clk_get_core(clk, info, &core);
  172. if (ret)
  173. return ret;
  174. switch (core->type) {
  175. case CLK_TYPE_IN:
  176. if (core->id == info->clk_extal_id) {
  177. rate = clk_get_rate(&priv->clk_extal);
  178. debug("%s[%i] EXTAL clk: rate=%llu\n",
  179. __func__, __LINE__, rate);
  180. return rate;
  181. }
  182. if (core->id == info->clk_extalr_id) {
  183. rate = clk_get_rate(&priv->clk_extalr);
  184. debug("%s[%i] EXTALR clk: rate=%llu\n",
  185. __func__, __LINE__, rate);
  186. return rate;
  187. }
  188. return -EINVAL;
  189. case CLK_TYPE_GEN3_MAIN:
  190. return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
  191. 0, 1, pll_config->extal_div,
  192. "MAIN");
  193. case CLK_TYPE_GEN3_PLL0:
  194. return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
  195. CPG_PLL0CR, 0, 0, "PLL0");
  196. case CLK_TYPE_GEN3_PLL1:
  197. return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
  198. 0, pll_config->pll1_mult,
  199. pll_config->pll1_div, "PLL1");
  200. case CLK_TYPE_GEN3_PLL2:
  201. return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
  202. CPG_PLL2CR, 0, 0, "PLL2");
  203. case CLK_TYPE_GEN3_PLL3:
  204. return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
  205. 0, pll_config->pll3_mult,
  206. pll_config->pll3_div, "PLL3");
  207. case CLK_TYPE_GEN3_PLL4:
  208. return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
  209. CPG_PLL4CR, 0, 0, "PLL4");
  210. case CLK_TYPE_FF:
  211. return gen3_clk_get_rate64_pll_mul_reg(priv, &parent, core,
  212. 0, core->mult, core->div,
  213. "FIXED");
  214. case CLK_TYPE_GEN3_MDSEL:
  215. div = (core->div >> (priv->sscg ? 16 : 0)) & 0xffff;
  216. rate = gen3_clk_get_rate64(&parent) / div;
  217. debug("%s[%i] PE clk: parent=%i div=%u => rate=%llu\n",
  218. __func__, __LINE__,
  219. (core->parent >> (priv->sscg ? 16 : 0)) & 0xffff,
  220. div, rate);
  221. return rate;
  222. case CLK_TYPE_GEN3_SD: /* FIXME */
  223. value = readl(priv->base + core->offset);
  224. value &= CPG_SD_STP_MASK | CPG_SD_FC_MASK;
  225. for (i = 0; i < ARRAY_SIZE(cpg_sd_div_table); i++) {
  226. if (cpg_sd_div_table[i].val != value)
  227. continue;
  228. rate = gen3_clk_get_rate64(&parent) /
  229. cpg_sd_div_table[i].div;
  230. debug("%s[%i] SD clk: parent=%i div=%i => rate=%llu\n",
  231. __func__, __LINE__,
  232. core->parent, cpg_sd_div_table[i].div, rate);
  233. return rate;
  234. }
  235. return -EINVAL;
  236. case CLK_TYPE_GEN3_RPC:
  237. case CLK_TYPE_GEN3_RPCD2:
  238. rate = gen3_clk_get_rate64(&parent);
  239. value = readl(priv->base + core->offset);
  240. prediv = (value >> CPG_RPC_PREDIV_OFFSET) &
  241. CPG_RPC_PREDIV_MASK;
  242. if (prediv == 2)
  243. rate /= 5;
  244. else if (prediv == 3)
  245. rate /= 6;
  246. else
  247. return -EINVAL;
  248. postdiv = (value >> CPG_RPC_POSTDIV_OFFSET) &
  249. CPG_RPC_POSTDIV_MASK;
  250. if (postdiv % 2 != 0) {
  251. rate /= postdiv + 1;
  252. if (core->type == CLK_TYPE_GEN3_RPCD2)
  253. rate /= 2;
  254. debug("%s[%i] RPC clk: parent=%i prediv=%i postdiv=%i => rate=%llu\n",
  255. __func__, __LINE__,
  256. core->parent, prediv, postdiv, rate);
  257. return rate;
  258. }
  259. return -EINVAL;
  260. }
  261. printf("%s[%i] unknown fail\n", __func__, __LINE__);
  262. return -ENOENT;
  263. }
  264. static ulong gen3_clk_get_rate(struct clk *clk)
  265. {
  266. return gen3_clk_get_rate64(clk);
  267. }
  268. static ulong gen3_clk_set_rate(struct clk *clk, ulong rate)
  269. {
  270. /* Force correct SD-IF divider configuration if applicable */
  271. gen3_clk_setup_sdif_div(clk, rate);
  272. return gen3_clk_get_rate64(clk);
  273. }
  274. static int gen3_clk_of_xlate(struct clk *clk, struct ofnode_phandle_args *args)
  275. {
  276. if (args->args_count != 2) {
  277. debug("Invaild args_count: %d\n", args->args_count);
  278. return -EINVAL;
  279. }
  280. clk->id = (args->args[0] << 16) | args->args[1];
  281. return 0;
  282. }
  283. const struct clk_ops gen3_clk_ops = {
  284. .enable = gen3_clk_enable,
  285. .disable = gen3_clk_disable,
  286. .get_rate = gen3_clk_get_rate,
  287. .set_rate = gen3_clk_set_rate,
  288. .of_xlate = gen3_clk_of_xlate,
  289. };
  290. int gen3_clk_probe(struct udevice *dev)
  291. {
  292. struct gen3_clk_priv *priv = dev_get_priv(dev);
  293. struct cpg_mssr_info *info =
  294. (struct cpg_mssr_info *)dev_get_driver_data(dev);
  295. fdt_addr_t rst_base;
  296. u32 cpg_mode;
  297. int ret;
  298. priv->base = dev_read_addr_ptr(dev);
  299. if (!priv->base)
  300. return -EINVAL;
  301. priv->info = info;
  302. ret = fdt_node_offset_by_compatible(gd->fdt_blob, -1, info->reset_node);
  303. if (ret < 0)
  304. return ret;
  305. rst_base = fdtdec_get_addr(gd->fdt_blob, ret, "reg");
  306. if (rst_base == FDT_ADDR_T_NONE)
  307. return -EINVAL;
  308. cpg_mode = readl(rst_base + info->reset_modemr_offset);
  309. priv->cpg_pll_config =
  310. (struct rcar_gen3_cpg_pll_config *)info->get_pll_config(cpg_mode);
  311. if (!priv->cpg_pll_config->extal_div)
  312. return -EINVAL;
  313. priv->sscg = !(cpg_mode & BIT(12));
  314. if (info->reg_layout == CLK_REG_LAYOUT_RCAR_GEN2_AND_GEN3) {
  315. priv->info->status_regs = mstpsr;
  316. priv->info->control_regs = smstpcr;
  317. priv->info->reset_regs = srcr;
  318. priv->info->reset_clear_regs = srstclr;
  319. } else {
  320. return -EINVAL;
  321. }
  322. ret = clk_get_by_name(dev, "extal", &priv->clk_extal);
  323. if (ret < 0)
  324. return ret;
  325. if (info->extalr_node) {
  326. ret = clk_get_by_name(dev, info->extalr_node, &priv->clk_extalr);
  327. if (ret < 0)
  328. return ret;
  329. }
  330. return 0;
  331. }
  332. int gen3_clk_remove(struct udevice *dev)
  333. {
  334. struct gen3_clk_priv *priv = dev_get_priv(dev);
  335. return renesas_clk_remove(priv->base, priv->info);
  336. }