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@@ -162,9 +162,9 @@
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"", "", "", "", "", /* 65 - 69 */
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"", "", "", "", "", /* 70 - 74 */
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"", "ETH_MDC", "ETH_MDIO", /* 75 - 77, MIO end and EMIO start */
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- "", "", /* 78 - 79 */
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- "", "", "", "", "", /* 80 - 84 */
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- "", "", "", "", "", /* 85 -89 */
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+ "SYSCTLR_VERSAL_MODE0", "SYSCTLR_VERSAL_MODE1", /* 78 - 79 */
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+ "SYSCTLR_VERSAL_MODE2", "SYSCTLR_VERSAL_MODE3", "SYSCTLR_POR_B_LS", "", "", /* 80 - 84 */
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+ "", "", "", "", "", /* 85 - 89 */
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"", "", "", "", "", /* 90 - 94 */
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"", "", "", "", "", /* 95 - 99 */
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"", "", "", "", "", /* 100 - 104 */
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@@ -198,9 +198,6 @@
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#size-cells = <0>;
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reg = <0>;
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/* u152 IR35215 0x16/0x46 vcc_soc */
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- /* u160 IRPS5401 0x17/0x47 */
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- /* u167 IRPS5401 0x1c/0x4c */
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- /* u175 IRPS5401 0x1d/0x4d */
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/* u179 ir38164 0x19/0x49 vcco_500 */
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/* u181 ir38164 0x1a/0x4a vcco_501 */
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/* u183 ir38164 0x1b/0x4b vcco_502 */
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@@ -209,6 +206,19 @@
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/* u189 ir38164 0x20/0x50 mgtyavtt */
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/* u194 ir38164 0x13/0x43 vdd1_1v8_lp4 */
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/* u195 ir38164 0x14/0x44 vdd2_1v8_lp4 */
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+
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+ irps5401_47: irps5401@47 { /* IRPS5401 - u160 */
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+ compatible = "infineon,irps5401";
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+ reg = <0x47>; /* pmbus / i2c 0x17 */
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+ };
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+ irps5401_4c: irps5401@4c { /* IRPS5401 - u167 */
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+ compatible = "infineon,irps5401";
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+ reg = <0x4c>; /* pmbus / i2c 0x1c */
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+ };
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+ irps5401_4d: irps5401@4d { /* IRPS5401 - u175 */
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+ compatible = "infineon,irps5401";
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+ reg = <0x4d>; /* pmbus / i2c 0x1d */
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+ };
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};
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i2c@1 { /* PMBUS1_INA226 */
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#address-cells = <1>;
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