zynq_nand.c 36 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2016 Xilinx, Inc.
  4. *
  5. * Xilinx Zynq NAND Flash Controller Driver
  6. * This driver is based on plat_nand.c and mxc_nand.c drivers
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <asm/io.h>
  11. #include <linux/errno.h>
  12. #include <nand.h>
  13. #include <linux/ioport.h>
  14. #include <linux/mtd/mtd.h>
  15. #include <linux/mtd/rawnand.h>
  16. #include <linux/mtd/partitions.h>
  17. #include <linux/mtd/nand_ecc.h>
  18. #include <asm/arch/hardware.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <dm.h>
  21. /* The NAND flash driver defines */
  22. #define ZYNQ_NAND_CMD_PHASE 1
  23. #define ZYNQ_NAND_DATA_PHASE 2
  24. #define ZYNQ_NAND_ECC_SIZE 512
  25. #define ZYNQ_NAND_SET_OPMODE_8BIT (0 << 0)
  26. #define ZYNQ_NAND_SET_OPMODE_16BIT (1 << 0)
  27. #define ZYNQ_NAND_ECC_STATUS (1 << 6)
  28. #define ZYNQ_MEMC_CLRCR_INT_CLR1 (1 << 4)
  29. #define ZYNQ_MEMC_SR_RAW_INT_ST1 (1 << 6)
  30. #define ZYNQ_MEMC_SR_INT_ST1 (1 << 4)
  31. #define ZYNQ_MEMC_NAND_ECC_MODE_MASK 0xC
  32. /* Flash memory controller operating parameters */
  33. #define ZYNQ_NAND_CLR_CONFIG ((0x1 << 1) | /* Disable interrupt */ \
  34. (0x1 << 4) | /* Clear interrupt */ \
  35. (0x1 << 6)) /* Disable ECC interrupt */
  36. #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  37. /* Assuming 50MHz clock (20ns cycle time) and 3V operation */
  38. #define ZYNQ_NAND_SET_CYCLES ((0x2 << 20) | /* t_rr from nand_cycles */ \
  39. (0x2 << 17) | /* t_ar from nand_cycles */ \
  40. (0x1 << 14) | /* t_clr from nand_cycles */ \
  41. (0x3 << 11) | /* t_wp from nand_cycles */ \
  42. (0x2 << 8) | /* t_rea from nand_cycles */ \
  43. (0x5 << 4) | /* t_wc from nand_cycles */ \
  44. (0x5 << 0)) /* t_rc from nand_cycles */
  45. #endif
  46. #define ZYNQ_NAND_DIRECT_CMD ((0x4 << 23) | /* Chip 0 from interface 1 */ \
  47. (0x2 << 21)) /* UpdateRegs operation */
  48. #define ZYNQ_NAND_ECC_CONFIG ((0x1 << 2) | /* ECC available on APB */ \
  49. (0x1 << 4) | /* ECC read at end of page */ \
  50. (0x0 << 5)) /* No Jumping */
  51. #define ZYNQ_NAND_ECC_CMD1 ((0x80) | /* Write command */ \
  52. (0x00 << 8) | /* Read command */ \
  53. (0x30 << 16) | /* Read End command */ \
  54. (0x1 << 24)) /* Read End command calid */
  55. #define ZYNQ_NAND_ECC_CMD2 ((0x85) | /* Write col change cmd */ \
  56. (0x05 << 8) | /* Read col change cmd */ \
  57. (0xE0 << 16) | /* Read col change end cmd */ \
  58. (0x1 << 24)) /* Read col change
  59. end cmd valid */
  60. /* AXI Address definitions */
  61. #define START_CMD_SHIFT 3
  62. #define END_CMD_SHIFT 11
  63. #define END_CMD_VALID_SHIFT 20
  64. #define ADDR_CYCLES_SHIFT 21
  65. #define CLEAR_CS_SHIFT 21
  66. #define ECC_LAST_SHIFT 10
  67. #define COMMAND_PHASE (0 << 19)
  68. #define DATA_PHASE (1 << 19)
  69. #define ONDIE_ECC_FEATURE_ADDR 0x90
  70. #define ONDIE_ECC_FEATURE_ENABLE 0x08
  71. #define ZYNQ_NAND_ECC_LAST (1 << ECC_LAST_SHIFT) /* Set ECC_Last */
  72. #define ZYNQ_NAND_CLEAR_CS (1 << CLEAR_CS_SHIFT) /* Clear chip select */
  73. /* ECC block registers bit position and bit mask */
  74. #define ZYNQ_NAND_ECC_BUSY (1 << 6) /* ECC block is busy */
  75. #define ZYNQ_NAND_ECC_MASK 0x00FFFFFF /* ECC value mask */
  76. #define ZYNQ_NAND_ROW_ADDR_CYCL_MASK 0x0F
  77. #define ZYNQ_NAND_COL_ADDR_CYCL_MASK 0xF0
  78. #define ZYNQ_NAND_MIO_NUM_NAND_8BIT 13
  79. #define ZYNQ_NAND_MIO_NUM_NAND_16BIT 8
  80. enum zynq_nand_bus_width {
  81. NAND_BW_UNKNOWN = -1,
  82. NAND_BW_8BIT,
  83. NAND_BW_16BIT,
  84. };
  85. #ifndef NAND_CMD_LOCK_TIGHT
  86. #define NAND_CMD_LOCK_TIGHT 0x2c
  87. #endif
  88. #ifndef NAND_CMD_LOCK_STATUS
  89. #define NAND_CMD_LOCK_STATUS 0x7a
  90. #endif
  91. /* SMC register set */
  92. struct zynq_nand_smc_regs {
  93. u32 csr; /* 0x00 */
  94. u32 reserved0[2];
  95. u32 cfr; /* 0x0C */
  96. u32 dcr; /* 0x10 */
  97. u32 scr; /* 0x14 */
  98. u32 sor; /* 0x18 */
  99. u32 reserved1[249];
  100. u32 esr; /* 0x400 */
  101. u32 emcr; /* 0x404 */
  102. u32 emcmd1r; /* 0x408 */
  103. u32 emcmd2r; /* 0x40C */
  104. u32 reserved2[2];
  105. u32 eval0r; /* 0x418 */
  106. };
  107. /*
  108. * struct nand_config - Defines the NAND flash driver instance
  109. * @parts: Pointer to the mtd_partition structure
  110. * @nand_base: Virtual address of the NAND flash device
  111. * @end_cmd_pending: End command is pending
  112. * @end_cmd: End command
  113. */
  114. struct nand_config {
  115. void __iomem *nand_base;
  116. u8 end_cmd_pending;
  117. u8 end_cmd;
  118. };
  119. struct nand_drv {
  120. struct zynq_nand_smc_regs *reg;
  121. struct nand_config config;
  122. };
  123. struct zynq_nand_info {
  124. struct udevice *dev;
  125. struct nand_drv nand_ctrl;
  126. struct nand_chip nand_chip;
  127. };
  128. /*
  129. * struct zynq_nand_command_format - Defines NAND flash command format
  130. * @start_cmd: First cycle command (Start command)
  131. * @end_cmd: Second cycle command (Last command)
  132. * @addr_cycles: Number of address cycles required to send the address
  133. * @end_cmd_valid: The second cycle command is valid for cmd or data phase
  134. */
  135. struct zynq_nand_command_format {
  136. u8 start_cmd;
  137. u8 end_cmd;
  138. u8 addr_cycles;
  139. u8 end_cmd_valid;
  140. };
  141. /* The NAND flash operations command format */
  142. static const struct zynq_nand_command_format zynq_nand_commands[] = {
  143. {NAND_CMD_READ0, NAND_CMD_READSTART, 5, ZYNQ_NAND_CMD_PHASE},
  144. {NAND_CMD_RNDOUT, NAND_CMD_RNDOUTSTART, 2, ZYNQ_NAND_CMD_PHASE},
  145. {NAND_CMD_READID, NAND_CMD_NONE, 1, 0},
  146. {NAND_CMD_STATUS, NAND_CMD_NONE, 0, 0},
  147. {NAND_CMD_SEQIN, NAND_CMD_PAGEPROG, 5, ZYNQ_NAND_DATA_PHASE},
  148. {NAND_CMD_RNDIN, NAND_CMD_NONE, 2, 0},
  149. {NAND_CMD_ERASE1, NAND_CMD_ERASE2, 3, ZYNQ_NAND_CMD_PHASE},
  150. {NAND_CMD_RESET, NAND_CMD_NONE, 0, 0},
  151. {NAND_CMD_PARAM, NAND_CMD_NONE, 1, 0},
  152. {NAND_CMD_GET_FEATURES, NAND_CMD_NONE, 1, 0},
  153. {NAND_CMD_SET_FEATURES, NAND_CMD_NONE, 1, 0},
  154. {NAND_CMD_LOCK, NAND_CMD_NONE, 0, 0},
  155. {NAND_CMD_LOCK_TIGHT, NAND_CMD_NONE, 0, 0},
  156. {NAND_CMD_UNLOCK1, NAND_CMD_NONE, 3, 0},
  157. {NAND_CMD_UNLOCK2, NAND_CMD_NONE, 3, 0},
  158. {NAND_CMD_LOCK_STATUS, NAND_CMD_NONE, 3, 0},
  159. {NAND_CMD_NONE, NAND_CMD_NONE, 0, 0},
  160. /* Add all the flash commands supported by the flash device */
  161. };
  162. /* Define default oob placement schemes for large and small page devices */
  163. static struct nand_ecclayout nand_oob_16 = {
  164. .eccbytes = 3,
  165. .eccpos = {0, 1, 2},
  166. .oobfree = {
  167. { .offset = 8, .length = 8 }
  168. }
  169. };
  170. static struct nand_ecclayout nand_oob_64 = {
  171. .eccbytes = 12,
  172. .eccpos = {
  173. 52, 53, 54, 55, 56, 57,
  174. 58, 59, 60, 61, 62, 63},
  175. .oobfree = {
  176. { .offset = 2, .length = 50 }
  177. }
  178. };
  179. static struct nand_ecclayout ondie_nand_oob_64 = {
  180. .eccbytes = 32,
  181. .eccpos = {
  182. 8, 9, 10, 11, 12, 13, 14, 15,
  183. 24, 25, 26, 27, 28, 29, 30, 31,
  184. 40, 41, 42, 43, 44, 45, 46, 47,
  185. 56, 57, 58, 59, 60, 61, 62, 63
  186. },
  187. .oobfree = {
  188. { .offset = 4, .length = 4 },
  189. { .offset = 20, .length = 4 },
  190. { .offset = 36, .length = 4 },
  191. { .offset = 52, .length = 4 }
  192. }
  193. };
  194. /* bbt decriptors for chips with on-die ECC and
  195. chips with 64-byte OOB */
  196. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  197. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  198. static struct nand_bbt_descr bbt_main_descr = {
  199. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  200. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  201. .offs = 4,
  202. .len = 4,
  203. .veroffs = 20,
  204. .maxblocks = 4,
  205. .pattern = bbt_pattern
  206. };
  207. static struct nand_bbt_descr bbt_mirror_descr = {
  208. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  209. NAND_BBT_2BIT | NAND_BBT_VERSION | NAND_BBT_PERCHIP,
  210. .offs = 4,
  211. .len = 4,
  212. .veroffs = 20,
  213. .maxblocks = 4,
  214. .pattern = mirror_pattern
  215. };
  216. /*
  217. * zynq_nand_waitfor_ecc_completion - Wait for ECC completion
  218. *
  219. * returns: status for command completion, -1 for Timeout
  220. */
  221. static int zynq_nand_waitfor_ecc_completion(struct mtd_info *mtd)
  222. {
  223. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  224. struct nand_drv *smc = nand_get_controller_data(nand_chip);
  225. unsigned long timeout;
  226. u32 status;
  227. /* Wait max 10us */
  228. timeout = 10;
  229. status = readl(&smc->reg->esr);
  230. while (status & ZYNQ_NAND_ECC_BUSY) {
  231. status = readl(&smc->reg->esr);
  232. if (timeout == 0)
  233. return -1;
  234. timeout--;
  235. udelay(1);
  236. }
  237. return status;
  238. }
  239. /*
  240. * zynq_nand_init_nand_flash - Initialize NAND controller
  241. * @option: Device property flags
  242. *
  243. * This function initializes the NAND flash interface on the NAND controller.
  244. *
  245. * returns: 0 on success or error value on failure
  246. */
  247. static int zynq_nand_init_nand_flash(struct mtd_info *mtd, int option)
  248. {
  249. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  250. struct nand_drv *smc = nand_get_controller_data(nand_chip);
  251. u32 status;
  252. /* disable interrupts */
  253. writel(ZYNQ_NAND_CLR_CONFIG, &smc->reg->cfr);
  254. #ifndef CONFIG_NAND_ZYNQ_USE_BOOTLOADER1_TIMINGS
  255. /* Initialize the NAND interface by setting cycles and operation mode */
  256. writel(ZYNQ_NAND_SET_CYCLES, &smc->reg->scr);
  257. #endif
  258. if (option & NAND_BUSWIDTH_16)
  259. writel(ZYNQ_NAND_SET_OPMODE_16BIT, &smc->reg->sor);
  260. else
  261. writel(ZYNQ_NAND_SET_OPMODE_8BIT, &smc->reg->sor);
  262. writel(ZYNQ_NAND_DIRECT_CMD, &smc->reg->dcr);
  263. /* Wait till the ECC operation is complete */
  264. status = zynq_nand_waitfor_ecc_completion(mtd);
  265. if (status < 0) {
  266. printf("%s: Timeout\n", __func__);
  267. return status;
  268. }
  269. /* Set the command1 and command2 register */
  270. writel(ZYNQ_NAND_ECC_CMD1, &smc->reg->emcmd1r);
  271. writel(ZYNQ_NAND_ECC_CMD2, &smc->reg->emcmd2r);
  272. return 0;
  273. }
  274. /*
  275. * zynq_nand_calculate_hwecc - Calculate Hardware ECC
  276. * @mtd: Pointer to the mtd_info structure
  277. * @data: Pointer to the page data
  278. * @ecc_code: Pointer to the ECC buffer where ECC data needs to be stored
  279. *
  280. * This function retrieves the Hardware ECC data from the controller and returns
  281. * ECC data back to the MTD subsystem.
  282. *
  283. * returns: 0 on success or error value on failure
  284. */
  285. static int zynq_nand_calculate_hwecc(struct mtd_info *mtd, const u8 *data,
  286. u8 *ecc_code)
  287. {
  288. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  289. struct nand_drv *smc = nand_get_controller_data(nand_chip);
  290. u32 ecc_value = 0;
  291. u8 ecc_reg, ecc_byte;
  292. u32 ecc_status;
  293. /* Wait till the ECC operation is complete */
  294. ecc_status = zynq_nand_waitfor_ecc_completion(mtd);
  295. if (ecc_status < 0) {
  296. printf("%s: Timeout\n", __func__);
  297. return ecc_status;
  298. }
  299. for (ecc_reg = 0; ecc_reg < 4; ecc_reg++) {
  300. /* Read ECC value for each block */
  301. ecc_value = readl(&smc->reg->eval0r + ecc_reg);
  302. /* Get the ecc status from ecc read value */
  303. ecc_status = (ecc_value >> 24) & 0xFF;
  304. /* ECC value valid */
  305. if (ecc_status & ZYNQ_NAND_ECC_STATUS) {
  306. for (ecc_byte = 0; ecc_byte < 3; ecc_byte++) {
  307. /* Copy ECC bytes to MTD buffer */
  308. *ecc_code = ecc_value & 0xFF;
  309. ecc_value = ecc_value >> 8;
  310. ecc_code++;
  311. }
  312. } else {
  313. debug("%s: ecc status failed\n", __func__);
  314. }
  315. }
  316. return 0;
  317. }
  318. /*
  319. * onehot - onehot function
  320. * @value: value to check for onehot
  321. *
  322. * This function checks whether a value is onehot or not.
  323. * onehot is if and only if one bit is set.
  324. *
  325. * FIXME: Try to move this in common.h
  326. */
  327. static bool onehot(unsigned short value)
  328. {
  329. bool onehot;
  330. onehot = value && !(value & (value - 1));
  331. return onehot;
  332. }
  333. /*
  334. * zynq_nand_correct_data - ECC correction function
  335. * @mtd: Pointer to the mtd_info structure
  336. * @buf: Pointer to the page data
  337. * @read_ecc: Pointer to the ECC value read from spare data area
  338. * @calc_ecc: Pointer to the calculated ECC value
  339. *
  340. * This function corrects the ECC single bit errors & detects 2-bit errors.
  341. *
  342. * returns: 0 if no ECC errors found
  343. * 1 if single bit error found and corrected.
  344. * -1 if multiple ECC errors found.
  345. */
  346. static int zynq_nand_correct_data(struct mtd_info *mtd, unsigned char *buf,
  347. unsigned char *read_ecc, unsigned char *calc_ecc)
  348. {
  349. unsigned char bit_addr;
  350. unsigned int byte_addr;
  351. unsigned short ecc_odd, ecc_even;
  352. unsigned short read_ecc_lower, read_ecc_upper;
  353. unsigned short calc_ecc_lower, calc_ecc_upper;
  354. read_ecc_lower = (read_ecc[0] | (read_ecc[1] << 8)) & 0xfff;
  355. read_ecc_upper = ((read_ecc[1] >> 4) | (read_ecc[2] << 4)) & 0xfff;
  356. calc_ecc_lower = (calc_ecc[0] | (calc_ecc[1] << 8)) & 0xfff;
  357. calc_ecc_upper = ((calc_ecc[1] >> 4) | (calc_ecc[2] << 4)) & 0xfff;
  358. ecc_odd = read_ecc_lower ^ calc_ecc_lower;
  359. ecc_even = read_ecc_upper ^ calc_ecc_upper;
  360. if ((ecc_odd == 0) && (ecc_even == 0))
  361. return 0; /* no error */
  362. if (ecc_odd == (~ecc_even & 0xfff)) {
  363. /* bits [11:3] of error code is byte offset */
  364. byte_addr = (ecc_odd >> 3) & 0x1ff;
  365. /* bits [2:0] of error code is bit offset */
  366. bit_addr = ecc_odd & 0x7;
  367. /* Toggling error bit */
  368. buf[byte_addr] ^= (1 << bit_addr);
  369. return 1;
  370. }
  371. if (onehot(ecc_odd | ecc_even))
  372. return 1; /* one error in parity */
  373. return -1; /* Uncorrectable error */
  374. }
  375. /*
  376. * zynq_nand_read_oob - [REPLACABLE] the most common OOB data read function
  377. * @mtd: mtd info structure
  378. * @chip: nand chip info structure
  379. * @page: page number to read
  380. * @sndcmd: flag whether to issue read command or not
  381. */
  382. static int zynq_nand_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  383. int page)
  384. {
  385. unsigned long data_phase_addr = 0;
  386. int data_width = 4;
  387. u8 *p;
  388. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  389. p = chip->oob_poi;
  390. chip->read_buf(mtd, p, (mtd->oobsize - data_width));
  391. p += mtd->oobsize - data_width;
  392. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  393. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  394. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  395. chip->read_buf(mtd, p, data_width);
  396. return 0;
  397. }
  398. /*
  399. * zynq_nand_write_oob - [REPLACABLE] the most common OOB data write function
  400. * @mtd: mtd info structure
  401. * @chip: nand chip info structure
  402. * @page: page number to write
  403. */
  404. static int zynq_nand_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  405. int page)
  406. {
  407. int status = 0, data_width = 4;
  408. const u8 *buf = chip->oob_poi;
  409. unsigned long data_phase_addr = 0;
  410. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  411. chip->write_buf(mtd, buf, (mtd->oobsize - data_width));
  412. buf += mtd->oobsize - data_width;
  413. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  414. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  415. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  416. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  417. chip->write_buf(mtd, buf, data_width);
  418. /* Send command to program the OOB data */
  419. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  420. status = chip->waitfunc(mtd, chip);
  421. return status & NAND_STATUS_FAIL ? -EIO : 0;
  422. }
  423. /*
  424. * zynq_nand_read_page_raw - [Intern] read raw page data without ecc
  425. * @mtd: mtd info structure
  426. * @chip: nand chip info structure
  427. * @buf: buffer to store read data
  428. * @oob_required: must write chip->oob_poi to OOB
  429. * @page: page number to read
  430. */
  431. static int zynq_nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  432. u8 *buf, int oob_required, int page)
  433. {
  434. unsigned long data_width = 4;
  435. unsigned long data_phase_addr = 0;
  436. u8 *p;
  437. chip->read_buf(mtd, buf, mtd->writesize);
  438. p = chip->oob_poi;
  439. chip->read_buf(mtd, p, (mtd->oobsize - data_width));
  440. p += (mtd->oobsize - data_width);
  441. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  442. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  443. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  444. chip->read_buf(mtd, p, data_width);
  445. return 0;
  446. }
  447. static int zynq_nand_read_page_raw_nooob(struct mtd_info *mtd,
  448. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  449. {
  450. chip->read_buf(mtd, buf, mtd->writesize);
  451. return 0;
  452. }
  453. static int zynq_nand_read_subpage_raw(struct mtd_info *mtd,
  454. struct nand_chip *chip, u32 data_offs,
  455. u32 readlen, u8 *buf, int page)
  456. {
  457. if (data_offs != 0) {
  458. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_offs, -1);
  459. buf += data_offs;
  460. }
  461. chip->read_buf(mtd, buf, readlen);
  462. return 0;
  463. }
  464. /*
  465. * zynq_nand_write_page_raw - [Intern] raw page write function
  466. * @mtd: mtd info structure
  467. * @chip: nand chip info structure
  468. * @buf: data buffer
  469. * @oob_required: must write chip->oob_poi to OOB
  470. */
  471. static int zynq_nand_write_page_raw(struct mtd_info *mtd,
  472. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  473. {
  474. unsigned long data_width = 4;
  475. unsigned long data_phase_addr = 0;
  476. u8 *p;
  477. chip->write_buf(mtd, buf, mtd->writesize);
  478. p = chip->oob_poi;
  479. chip->write_buf(mtd, p, (mtd->oobsize - data_width));
  480. p += (mtd->oobsize - data_width);
  481. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  482. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  483. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  484. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  485. chip->write_buf(mtd, p, data_width);
  486. return 0;
  487. }
  488. /*
  489. * nand_write_page_hwecc - Hardware ECC based page write function
  490. * @mtd: Pointer to the mtd info structure
  491. * @chip: Pointer to the NAND chip info structure
  492. * @buf: Pointer to the data buffer
  493. * @oob_required: must write chip->oob_poi to OOB
  494. *
  495. * This functions writes data and hardware generated ECC values in to the page.
  496. */
  497. static int zynq_nand_write_page_hwecc(struct mtd_info *mtd,
  498. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  499. {
  500. int i, eccsteps, eccsize = chip->ecc.size;
  501. u8 *ecc_calc = chip->buffers->ecccalc;
  502. const u8 *p = buf;
  503. u32 *eccpos = chip->ecc.layout->eccpos;
  504. unsigned long data_phase_addr = 0;
  505. unsigned long data_width = 4;
  506. u8 *oob_ptr;
  507. for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
  508. chip->write_buf(mtd, p, eccsize);
  509. p += eccsize;
  510. }
  511. chip->write_buf(mtd, p, (eccsize - data_width));
  512. p += eccsize - data_width;
  513. /* Set ECC Last bit to 1 */
  514. data_phase_addr = (unsigned long) chip->IO_ADDR_W;
  515. data_phase_addr |= ZYNQ_NAND_ECC_LAST;
  516. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  517. chip->write_buf(mtd, p, data_width);
  518. /* Wait for ECC to be calculated and read the error values */
  519. p = buf;
  520. chip->ecc.calculate(mtd, p, &ecc_calc[0]);
  521. for (i = 0; i < chip->ecc.total; i++)
  522. chip->oob_poi[eccpos[i]] = ~(ecc_calc[i]);
  523. /* Clear ECC last bit */
  524. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  525. data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
  526. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  527. /* Write the spare area with ECC bytes */
  528. oob_ptr = chip->oob_poi;
  529. chip->write_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
  530. data_phase_addr = (unsigned long)chip->IO_ADDR_W;
  531. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  532. data_phase_addr |= (1 << END_CMD_VALID_SHIFT);
  533. chip->IO_ADDR_W = (void __iomem *)data_phase_addr;
  534. oob_ptr += (mtd->oobsize - data_width);
  535. chip->write_buf(mtd, oob_ptr, data_width);
  536. return 0;
  537. }
  538. /*
  539. * zynq_nand_write_page_swecc - [REPLACABLE] software ecc based page
  540. * write function
  541. * @mtd: mtd info structure
  542. * @chip: nand chip info structure
  543. * @buf: data buffer
  544. * @oob_required: must write chip->oob_poi to OOB
  545. */
  546. static int zynq_nand_write_page_swecc(struct mtd_info *mtd,
  547. struct nand_chip *chip, const u8 *buf, int oob_required, int page)
  548. {
  549. int i, eccsize = chip->ecc.size;
  550. int eccbytes = chip->ecc.bytes;
  551. int eccsteps = chip->ecc.steps;
  552. u8 *ecc_calc = chip->buffers->ecccalc;
  553. const u8 *p = buf;
  554. u32 *eccpos = chip->ecc.layout->eccpos;
  555. /* Software ecc calculation */
  556. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  557. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  558. for (i = 0; i < chip->ecc.total; i++)
  559. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  560. return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
  561. }
  562. /*
  563. * nand_read_page_hwecc - Hardware ECC based page read function
  564. * @mtd: Pointer to the mtd info structure
  565. * @chip: Pointer to the NAND chip info structure
  566. * @buf: Pointer to the buffer to store read data
  567. * @oob_required: must write chip->oob_poi to OOB
  568. * @page: page number to read
  569. *
  570. * This functions reads data and checks the data integrity by comparing hardware
  571. * generated ECC values and read ECC values from spare area.
  572. *
  573. * returns: 0 always and updates ECC operation status in to MTD structure
  574. */
  575. static int zynq_nand_read_page_hwecc(struct mtd_info *mtd,
  576. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  577. {
  578. int i, stat, eccsteps, eccsize = chip->ecc.size;
  579. int eccbytes = chip->ecc.bytes;
  580. u8 *p = buf;
  581. u8 *ecc_calc = chip->buffers->ecccalc;
  582. u8 *ecc_code = chip->buffers->ecccode;
  583. u32 *eccpos = chip->ecc.layout->eccpos;
  584. unsigned long data_phase_addr = 0;
  585. unsigned long data_width = 4;
  586. u8 *oob_ptr;
  587. for (eccsteps = chip->ecc.steps; (eccsteps - 1); eccsteps--) {
  588. chip->read_buf(mtd, p, eccsize);
  589. p += eccsize;
  590. }
  591. chip->read_buf(mtd, p, (eccsize - data_width));
  592. p += eccsize - data_width;
  593. /* Set ECC Last bit to 1 */
  594. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  595. data_phase_addr |= ZYNQ_NAND_ECC_LAST;
  596. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  597. chip->read_buf(mtd, p, data_width);
  598. /* Read the calculated ECC value */
  599. p = buf;
  600. chip->ecc.calculate(mtd, p, &ecc_calc[0]);
  601. /* Clear ECC last bit */
  602. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  603. data_phase_addr &= ~ZYNQ_NAND_ECC_LAST;
  604. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  605. /* Read the stored ECC value */
  606. oob_ptr = chip->oob_poi;
  607. chip->read_buf(mtd, oob_ptr, (mtd->oobsize - data_width));
  608. /* de-assert chip select */
  609. data_phase_addr = (unsigned long)chip->IO_ADDR_R;
  610. data_phase_addr |= ZYNQ_NAND_CLEAR_CS;
  611. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  612. oob_ptr += (mtd->oobsize - data_width);
  613. chip->read_buf(mtd, oob_ptr, data_width);
  614. for (i = 0; i < chip->ecc.total; i++)
  615. ecc_code[i] = ~(chip->oob_poi[eccpos[i]]);
  616. eccsteps = chip->ecc.steps;
  617. p = buf;
  618. /* Check ECC error for all blocks and correct if it is correctable */
  619. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  620. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  621. if (stat < 0)
  622. mtd->ecc_stats.failed++;
  623. else
  624. mtd->ecc_stats.corrected += stat;
  625. }
  626. return 0;
  627. }
  628. /*
  629. * zynq_nand_read_page_swecc - [REPLACABLE] software ecc based page
  630. * read function
  631. * @mtd: mtd info structure
  632. * @chip: nand chip info structure
  633. * @buf: buffer to store read data
  634. * @page: page number to read
  635. */
  636. static int zynq_nand_read_page_swecc(struct mtd_info *mtd,
  637. struct nand_chip *chip, u8 *buf, int oob_required, int page)
  638. {
  639. int i, eccsize = chip->ecc.size;
  640. int eccbytes = chip->ecc.bytes;
  641. int eccsteps = chip->ecc.steps;
  642. u8 *p = buf;
  643. u8 *ecc_calc = chip->buffers->ecccalc;
  644. u8 *ecc_code = chip->buffers->ecccode;
  645. u32 *eccpos = chip->ecc.layout->eccpos;
  646. chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
  647. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  648. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  649. for (i = 0; i < chip->ecc.total; i++)
  650. ecc_code[i] = chip->oob_poi[eccpos[i]];
  651. eccsteps = chip->ecc.steps;
  652. p = buf;
  653. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  654. int stat;
  655. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  656. if (stat < 0)
  657. mtd->ecc_stats.failed++;
  658. else
  659. mtd->ecc_stats.corrected += stat;
  660. }
  661. return 0;
  662. }
  663. /*
  664. * zynq_nand_select_chip - Select the flash device
  665. * @mtd: Pointer to the mtd_info structure
  666. * @chip: Chip number to be selected
  667. *
  668. * This function is empty as the NAND controller handles chip select line
  669. * internally based on the chip address passed in command and data phase.
  670. */
  671. static void zynq_nand_select_chip(struct mtd_info *mtd, int chip)
  672. {
  673. /* Not support multiple chips yet */
  674. }
  675. /*
  676. * zynq_nand_cmd_function - Send command to NAND device
  677. * @mtd: Pointer to the mtd_info structure
  678. * @command: The command to be sent to the flash device
  679. * @column: The column address for this command, -1 if none
  680. * @page_addr: The page address for this command, -1 if none
  681. */
  682. static void zynq_nand_cmd_function(struct mtd_info *mtd, unsigned int command,
  683. int column, int page_addr)
  684. {
  685. struct nand_chip *chip = mtd_to_nand(mtd);
  686. struct nand_drv *smc = nand_get_controller_data(chip);
  687. const struct zynq_nand_command_format *curr_cmd = NULL;
  688. u8 addr_cycles = 0;
  689. struct nand_config *xnand = &smc->config;
  690. void *cmd_addr;
  691. unsigned long cmd_data = 0;
  692. unsigned long cmd_phase_addr = 0;
  693. unsigned long data_phase_addr = 0;
  694. u8 end_cmd = 0;
  695. u8 end_cmd_valid = 0;
  696. u32 index;
  697. if (xnand->end_cmd_pending) {
  698. /* Check for end command if this command request is same as the
  699. * pending command then return
  700. */
  701. if (xnand->end_cmd == command) {
  702. xnand->end_cmd = 0;
  703. xnand->end_cmd_pending = 0;
  704. return;
  705. }
  706. }
  707. /* Emulate NAND_CMD_READOOB for large page device */
  708. if ((mtd->writesize > ZYNQ_NAND_ECC_SIZE) &&
  709. (command == NAND_CMD_READOOB)) {
  710. column += mtd->writesize;
  711. command = NAND_CMD_READ0;
  712. }
  713. /* Get the command format */
  714. for (index = 0; index < ARRAY_SIZE(zynq_nand_commands); index++)
  715. if (command == zynq_nand_commands[index].start_cmd)
  716. break;
  717. if (index == ARRAY_SIZE(zynq_nand_commands)) {
  718. printf("%s: Unsupported start cmd %02x\n", __func__, command);
  719. return;
  720. }
  721. curr_cmd = &zynq_nand_commands[index];
  722. /* Clear interrupt */
  723. writel(ZYNQ_MEMC_CLRCR_INT_CLR1, &smc->reg->cfr);
  724. /* Get the command phase address */
  725. if (curr_cmd->end_cmd_valid == ZYNQ_NAND_CMD_PHASE)
  726. end_cmd_valid = 1;
  727. if (curr_cmd->end_cmd == (u8)NAND_CMD_NONE)
  728. end_cmd = 0x0;
  729. else
  730. end_cmd = curr_cmd->end_cmd;
  731. if (command == NAND_CMD_READ0 ||
  732. command == NAND_CMD_SEQIN) {
  733. addr_cycles = chip->onfi_params.addr_cycles &
  734. ZYNQ_NAND_ROW_ADDR_CYCL_MASK;
  735. addr_cycles += ((chip->onfi_params.addr_cycles &
  736. ZYNQ_NAND_COL_ADDR_CYCL_MASK) >> 4);
  737. } else {
  738. addr_cycles = curr_cmd->addr_cycles;
  739. }
  740. cmd_phase_addr = (unsigned long)xnand->nand_base |
  741. (addr_cycles << ADDR_CYCLES_SHIFT) |
  742. (end_cmd_valid << END_CMD_VALID_SHIFT) |
  743. (COMMAND_PHASE) |
  744. (end_cmd << END_CMD_SHIFT) |
  745. (curr_cmd->start_cmd << START_CMD_SHIFT);
  746. cmd_addr = (void __iomem *)cmd_phase_addr;
  747. /* Get the data phase address */
  748. end_cmd_valid = 0;
  749. data_phase_addr = (unsigned long)xnand->nand_base |
  750. (0x0 << CLEAR_CS_SHIFT) |
  751. (end_cmd_valid << END_CMD_VALID_SHIFT) |
  752. (DATA_PHASE) |
  753. (end_cmd << END_CMD_SHIFT) |
  754. (0x0 << ECC_LAST_SHIFT);
  755. chip->IO_ADDR_R = (void __iomem *)data_phase_addr;
  756. chip->IO_ADDR_W = chip->IO_ADDR_R;
  757. /* Command phase AXI Read & Write */
  758. if (column != -1 && page_addr != -1) {
  759. /* Adjust columns for 16 bit bus width */
  760. if (chip->options & NAND_BUSWIDTH_16)
  761. column >>= 1;
  762. cmd_data = column;
  763. if (mtd->writesize > ZYNQ_NAND_ECC_SIZE) {
  764. cmd_data |= page_addr << 16;
  765. /* Another address cycle for devices > 128MiB */
  766. if (chip->chipsize > (128 << 20)) {
  767. writel(cmd_data, cmd_addr);
  768. cmd_data = (page_addr >> 16);
  769. }
  770. } else {
  771. cmd_data |= page_addr << 8;
  772. }
  773. } else if (page_addr != -1) { /* Erase */
  774. cmd_data = page_addr;
  775. } else if (column != -1) { /* Change read/write column, read id etc */
  776. /* Adjust columns for 16 bit bus width */
  777. if ((chip->options & NAND_BUSWIDTH_16) &&
  778. ((command == NAND_CMD_READ0) ||
  779. (command == NAND_CMD_SEQIN) ||
  780. (command == NAND_CMD_RNDOUT) ||
  781. (command == NAND_CMD_RNDIN)))
  782. column >>= 1;
  783. cmd_data = column;
  784. }
  785. writel(cmd_data, cmd_addr);
  786. if (curr_cmd->end_cmd_valid) {
  787. xnand->end_cmd = curr_cmd->end_cmd;
  788. xnand->end_cmd_pending = 1;
  789. }
  790. ndelay(100);
  791. if ((command == NAND_CMD_READ0) ||
  792. (command == NAND_CMD_RESET) ||
  793. (command == NAND_CMD_PARAM) ||
  794. (command == NAND_CMD_GET_FEATURES))
  795. /* wait until command is processed */
  796. nand_wait_ready(mtd);
  797. }
  798. /*
  799. * zynq_nand_read_buf - read chip data into buffer
  800. * @mtd: MTD device structure
  801. * @buf: buffer to store date
  802. * @len: number of bytes to read
  803. */
  804. static void zynq_nand_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  805. {
  806. struct nand_chip *chip = mtd_to_nand(mtd);
  807. /* Make sure that buf is 32 bit aligned */
  808. if (((unsigned long)buf & 0x3) != 0) {
  809. if (((unsigned long)buf & 0x1) != 0) {
  810. if (len) {
  811. *buf = readb(chip->IO_ADDR_R);
  812. buf += 1;
  813. len--;
  814. }
  815. }
  816. if (((unsigned long)buf & 0x3) != 0) {
  817. if (len >= 2) {
  818. *(u16 *)buf = readw(chip->IO_ADDR_R);
  819. buf += 2;
  820. len -= 2;
  821. }
  822. }
  823. }
  824. /* copy aligned data */
  825. while (len >= 4) {
  826. *(u32 *)buf = readl(chip->IO_ADDR_R);
  827. buf += 4;
  828. len -= 4;
  829. }
  830. /* mop up any remaining bytes */
  831. if (len) {
  832. if (len >= 2) {
  833. *(u16 *)buf = readw(chip->IO_ADDR_R);
  834. buf += 2;
  835. len -= 2;
  836. }
  837. if (len)
  838. *buf = readb(chip->IO_ADDR_R);
  839. }
  840. }
  841. /*
  842. * zynq_nand_write_buf - write buffer to chip
  843. * @mtd: MTD device structure
  844. * @buf: data buffer
  845. * @len: number of bytes to write
  846. */
  847. static void zynq_nand_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  848. {
  849. struct nand_chip *chip = mtd_to_nand(mtd);
  850. const u32 *nand = chip->IO_ADDR_W;
  851. /* Make sure that buf is 32 bit aligned */
  852. if (((unsigned long)buf & 0x3) != 0) {
  853. if (((unsigned long)buf & 0x1) != 0) {
  854. if (len) {
  855. writeb(*buf, nand);
  856. buf += 1;
  857. len--;
  858. }
  859. }
  860. if (((unsigned long)buf & 0x3) != 0) {
  861. if (len >= 2) {
  862. writew(*(u16 *)buf, nand);
  863. buf += 2;
  864. len -= 2;
  865. }
  866. }
  867. }
  868. /* copy aligned data */
  869. while (len >= 4) {
  870. writel(*(u32 *)buf, nand);
  871. buf += 4;
  872. len -= 4;
  873. }
  874. /* mop up any remaining bytes */
  875. if (len) {
  876. if (len >= 2) {
  877. writew(*(u16 *)buf, nand);
  878. buf += 2;
  879. len -= 2;
  880. }
  881. if (len)
  882. writeb(*buf, nand);
  883. }
  884. }
  885. /*
  886. * zynq_nand_device_ready - Check device ready/busy line
  887. * @mtd: Pointer to the mtd_info structure
  888. *
  889. * returns: 0 on busy or 1 on ready state
  890. */
  891. static int zynq_nand_device_ready(struct mtd_info *mtd)
  892. {
  893. struct nand_chip *nand_chip = mtd_to_nand(mtd);
  894. struct nand_drv *smc = nand_get_controller_data(nand_chip);
  895. u32 csr_val;
  896. csr_val = readl(&smc->reg->csr);
  897. /* Check the raw_int_status1 bit */
  898. if (csr_val & ZYNQ_MEMC_SR_RAW_INT_ST1) {
  899. /* Clear the interrupt condition */
  900. writel(ZYNQ_MEMC_SR_INT_ST1, &smc->reg->cfr);
  901. return 1;
  902. }
  903. return 0;
  904. }
  905. static int zynq_nand_check_is_16bit_bw_flash(void)
  906. {
  907. int is_16bit_bw = NAND_BW_UNKNOWN;
  908. int mio_num_8bit = 0, mio_num_16bit = 0;
  909. mio_num_8bit = zynq_slcr_get_mio_pin_status("nand8");
  910. if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT)
  911. is_16bit_bw = NAND_BW_8BIT;
  912. mio_num_16bit = zynq_slcr_get_mio_pin_status("nand16");
  913. if (mio_num_8bit == ZYNQ_NAND_MIO_NUM_NAND_8BIT &&
  914. mio_num_16bit == ZYNQ_NAND_MIO_NUM_NAND_16BIT)
  915. is_16bit_bw = NAND_BW_16BIT;
  916. return is_16bit_bw;
  917. }
  918. static int zynq_nand_probe(struct udevice *dev)
  919. {
  920. struct zynq_nand_info *zynq = dev_get_priv(dev);
  921. struct nand_chip *nand_chip = &zynq->nand_chip;
  922. struct nand_drv *smc = &zynq->nand_ctrl;
  923. struct nand_config *xnand = &smc->config;
  924. struct mtd_info *mtd;
  925. struct resource res;
  926. ofnode of_nand;
  927. unsigned long ecc_page_size;
  928. u8 maf_id, dev_id, i;
  929. u8 get_feature[4];
  930. u8 set_feature[4] = {ONDIE_ECC_FEATURE_ENABLE, 0x00, 0x00, 0x00};
  931. unsigned long ecc_cfg;
  932. int ondie_ecc_enabled = 0;
  933. int is_16bit_bw;
  934. smc->reg = (struct zynq_nand_smc_regs *)dev_read_addr(dev);
  935. of_nand = dev_read_subnode(dev, "flash@e1000000");
  936. if (!ofnode_valid(of_nand)) {
  937. printf("Failed to find nand node in dt\n");
  938. return -ENODEV;
  939. }
  940. if (!ofnode_is_available(of_nand)) {
  941. debug("Nand node in dt disabled\n");
  942. return dm_scan_fdt_dev(dev);
  943. }
  944. if (ofnode_read_resource(of_nand, 0, &res)) {
  945. printf("Failed to get nand resource\n");
  946. return -ENODEV;
  947. }
  948. xnand->nand_base = (void __iomem *)res.start;
  949. mtd = nand_to_mtd(nand_chip);
  950. nand_set_controller_data(nand_chip, &zynq->nand_ctrl);
  951. /* Set address of NAND IO lines */
  952. nand_chip->IO_ADDR_R = xnand->nand_base;
  953. nand_chip->IO_ADDR_W = xnand->nand_base;
  954. /* Set the driver entry points for MTD */
  955. nand_chip->cmdfunc = zynq_nand_cmd_function;
  956. nand_chip->dev_ready = zynq_nand_device_ready;
  957. nand_chip->select_chip = zynq_nand_select_chip;
  958. /* If we don't set this delay driver sets 20us by default */
  959. nand_chip->chip_delay = 30;
  960. /* Buffer read/write routines */
  961. nand_chip->read_buf = zynq_nand_read_buf;
  962. nand_chip->write_buf = zynq_nand_write_buf;
  963. is_16bit_bw = zynq_nand_check_is_16bit_bw_flash();
  964. if (is_16bit_bw == NAND_BW_UNKNOWN) {
  965. printf("%s: Unable detect NAND based on MIO settings\n",
  966. __func__);
  967. return -EINVAL;
  968. }
  969. if (is_16bit_bw == NAND_BW_16BIT)
  970. nand_chip->options = NAND_BUSWIDTH_16;
  971. nand_chip->bbt_options = NAND_BBT_USE_FLASH;
  972. /* Initialize the NAND flash interface on NAND controller */
  973. if (zynq_nand_init_nand_flash(mtd, nand_chip->options) < 0) {
  974. printf("%s: nand flash init failed\n", __func__);
  975. return -EINVAL;
  976. }
  977. /* first scan to find the device and get the page size */
  978. if (nand_scan_ident(mtd, 1, NULL)) {
  979. printf("%s: nand_scan_ident failed\n", __func__);
  980. return -EINVAL;
  981. }
  982. /* Send the command for reading device ID */
  983. nand_chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  984. nand_chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  985. /* Read manufacturer and device IDs */
  986. maf_id = nand_chip->read_byte(mtd);
  987. dev_id = nand_chip->read_byte(mtd);
  988. if ((maf_id == 0x2c) && ((dev_id == 0xf1) ||
  989. (dev_id == 0xa1) || (dev_id == 0xb1) ||
  990. (dev_id == 0xaa) || (dev_id == 0xba) ||
  991. (dev_id == 0xda) || (dev_id == 0xca) ||
  992. (dev_id == 0xac) || (dev_id == 0xbc) ||
  993. (dev_id == 0xdc) || (dev_id == 0xcc) ||
  994. (dev_id == 0xa3) || (dev_id == 0xb3) ||
  995. (dev_id == 0xd3) || (dev_id == 0xc3))) {
  996. nand_chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES,
  997. ONDIE_ECC_FEATURE_ADDR, -1);
  998. for (i = 0; i < 4; i++)
  999. writeb(set_feature[i], nand_chip->IO_ADDR_W);
  1000. /* Wait for 1us after writing data with SET_FEATURES command */
  1001. ndelay(1000);
  1002. nand_chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES,
  1003. ONDIE_ECC_FEATURE_ADDR, -1);
  1004. nand_chip->read_buf(mtd, get_feature, 4);
  1005. if (get_feature[0] & ONDIE_ECC_FEATURE_ENABLE) {
  1006. debug("%s: OnDie ECC flash\n", __func__);
  1007. ondie_ecc_enabled = 1;
  1008. } else {
  1009. printf("%s: Unable to detect OnDie ECC\n", __func__);
  1010. }
  1011. }
  1012. if (ondie_ecc_enabled) {
  1013. /* Bypass the controller ECC block */
  1014. ecc_cfg = readl(&smc->reg->emcr);
  1015. ecc_cfg &= ~ZYNQ_MEMC_NAND_ECC_MODE_MASK;
  1016. writel(ecc_cfg, &smc->reg->emcr);
  1017. /* The software ECC routines won't work
  1018. * with the SMC controller
  1019. */
  1020. nand_chip->ecc.mode = NAND_ECC_HW;
  1021. nand_chip->ecc.strength = 1;
  1022. nand_chip->ecc.read_page = zynq_nand_read_page_raw_nooob;
  1023. nand_chip->ecc.read_subpage = zynq_nand_read_subpage_raw;
  1024. nand_chip->ecc.write_page = zynq_nand_write_page_raw;
  1025. nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
  1026. nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
  1027. nand_chip->ecc.read_oob = zynq_nand_read_oob;
  1028. nand_chip->ecc.write_oob = zynq_nand_write_oob;
  1029. nand_chip->ecc.size = mtd->writesize;
  1030. nand_chip->ecc.bytes = 0;
  1031. /* NAND with on-die ECC supports subpage reads */
  1032. nand_chip->options |= NAND_SUBPAGE_READ;
  1033. /* On-Die ECC spare bytes offset 8 is used for ECC codes */
  1034. if (ondie_ecc_enabled) {
  1035. nand_chip->ecc.layout = &ondie_nand_oob_64;
  1036. /* Use the BBT pattern descriptors */
  1037. nand_chip->bbt_td = &bbt_main_descr;
  1038. nand_chip->bbt_md = &bbt_mirror_descr;
  1039. }
  1040. } else {
  1041. /* Hardware ECC generates 3 bytes ECC code for each 512 bytes */
  1042. nand_chip->ecc.mode = NAND_ECC_HW;
  1043. nand_chip->ecc.strength = 1;
  1044. nand_chip->ecc.size = ZYNQ_NAND_ECC_SIZE;
  1045. nand_chip->ecc.bytes = 3;
  1046. nand_chip->ecc.calculate = zynq_nand_calculate_hwecc;
  1047. nand_chip->ecc.correct = zynq_nand_correct_data;
  1048. nand_chip->ecc.hwctl = NULL;
  1049. nand_chip->ecc.read_page = zynq_nand_read_page_hwecc;
  1050. nand_chip->ecc.write_page = zynq_nand_write_page_hwecc;
  1051. nand_chip->ecc.read_page_raw = zynq_nand_read_page_raw;
  1052. nand_chip->ecc.write_page_raw = zynq_nand_write_page_raw;
  1053. nand_chip->ecc.read_oob = zynq_nand_read_oob;
  1054. nand_chip->ecc.write_oob = zynq_nand_write_oob;
  1055. switch (mtd->writesize) {
  1056. case 512:
  1057. ecc_page_size = 0x1;
  1058. /* Set the ECC memory config register */
  1059. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1060. &smc->reg->emcr);
  1061. break;
  1062. case 1024:
  1063. ecc_page_size = 0x2;
  1064. /* Set the ECC memory config register */
  1065. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1066. &smc->reg->emcr);
  1067. break;
  1068. case 2048:
  1069. ecc_page_size = 0x3;
  1070. /* Set the ECC memory config register */
  1071. writel((ZYNQ_NAND_ECC_CONFIG | ecc_page_size),
  1072. &smc->reg->emcr);
  1073. break;
  1074. default:
  1075. nand_chip->ecc.mode = NAND_ECC_SOFT;
  1076. nand_chip->ecc.calculate = nand_calculate_ecc;
  1077. nand_chip->ecc.correct = nand_correct_data;
  1078. nand_chip->ecc.read_page = zynq_nand_read_page_swecc;
  1079. nand_chip->ecc.write_page = zynq_nand_write_page_swecc;
  1080. nand_chip->ecc.size = 256;
  1081. break;
  1082. }
  1083. if (mtd->oobsize == 16)
  1084. nand_chip->ecc.layout = &nand_oob_16;
  1085. else if (mtd->oobsize == 64)
  1086. nand_chip->ecc.layout = &nand_oob_64;
  1087. else
  1088. printf("%s: No oob layout found\n", __func__);
  1089. }
  1090. /* Second phase scan */
  1091. if (nand_scan_tail(mtd)) {
  1092. printf("%s: nand_scan_tail failed\n", __func__);
  1093. return -EINVAL;
  1094. }
  1095. if (nand_register(0, mtd))
  1096. return -EINVAL;
  1097. return 0;
  1098. }
  1099. static const struct udevice_id zynq_nand_dt_ids[] = {
  1100. {.compatible = "arm,pl353-smc-r2p1",},
  1101. { /* sentinel */ }
  1102. };
  1103. U_BOOT_DRIVER(zynq_nand) = {
  1104. .name = "zynq-nand",
  1105. .id = UCLASS_MTD,
  1106. .of_match = zynq_nand_dt_ids,
  1107. .probe = zynq_nand_probe,
  1108. .priv_auto_alloc_size = sizeof(struct zynq_nand_info),
  1109. };
  1110. void board_nand_init(void)
  1111. {
  1112. struct udevice *dev;
  1113. int ret;
  1114. ret = uclass_get_device_by_driver(UCLASS_MTD,
  1115. DM_GET_DRIVER(zynq_nand), &dev);
  1116. if (ret && ret != -ENODEV)
  1117. pr_err("Failed to initialize %s. (error %d)\n", dev->name, ret);
  1118. }