clk_versal.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2019 Xilinx, Inc.
  4. * Siva Durga Prasad Paladugu <siva.durga.paladugu@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <dm/device_compat.h>
  8. #include <linux/bitops.h>
  9. #include <linux/bitfield.h>
  10. #include <malloc.h>
  11. #include <clk-uclass.h>
  12. #include <clk.h>
  13. #include <dm.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <zynqmp_firmware.h>
  16. #include <linux/err.h>
  17. #define MAX_PARENT 100
  18. #define MAX_NODES 6
  19. #define MAX_NAME_LEN 50
  20. #define CLK_TYPE_SHIFT 2
  21. #define PM_API_PAYLOAD_LEN 3
  22. #define NA_PARENT 0xFFFFFFFF
  23. #define DUMMY_PARENT 0xFFFFFFFE
  24. #define CLK_TYPE_FIELD_LEN 4
  25. #define CLK_TOPOLOGY_NODE_OFFSET 16
  26. #define NODES_PER_RESP 3
  27. #define CLK_TYPE_FIELD_MASK 0xF
  28. #define CLK_FLAG_FIELD_MASK GENMASK(21, 8)
  29. #define CLK_TYPE_FLAG_FIELD_MASK GENMASK(31, 24)
  30. #define CLK_TYPE_FLAG2_FIELD_MASK GENMASK(7, 4)
  31. #define CLK_TYPE_FLAG_BITS 8
  32. #define CLK_PARENTS_ID_LEN 16
  33. #define CLK_PARENTS_ID_MASK 0xFFFF
  34. #define END_OF_TOPOLOGY_NODE 1
  35. #define END_OF_PARENTS 1
  36. #define CLK_VALID_MASK 0x1
  37. #define NODE_CLASS_SHIFT 26U
  38. #define NODE_SUBCLASS_SHIFT 20U
  39. #define NODE_TYPE_SHIFT 14U
  40. #define NODE_INDEX_SHIFT 0U
  41. #define CLK_GET_NAME_RESP_LEN 16
  42. #define CLK_GET_TOPOLOGY_RESP_WORDS 3
  43. #define CLK_GET_PARENTS_RESP_WORDS 3
  44. #define CLK_GET_ATTR_RESP_WORDS 1
  45. #define NODE_SUBCLASS_CLOCK_PLL 1
  46. #define NODE_SUBCLASS_CLOCK_OUT 2
  47. #define NODE_SUBCLASS_CLOCK_REF 3
  48. #define NODE_CLASS_CLOCK 2
  49. #define NODE_CLASS_MASK 0x3F
  50. #define CLOCK_NODE_TYPE_MUX 1
  51. #define CLOCK_NODE_TYPE_DIV 4
  52. #define CLOCK_NODE_TYPE_GATE 6
  53. enum pm_query_id {
  54. PM_QID_INVALID,
  55. PM_QID_CLOCK_GET_NAME,
  56. PM_QID_CLOCK_GET_TOPOLOGY,
  57. PM_QID_CLOCK_GET_FIXEDFACTOR_PARAMS,
  58. PM_QID_CLOCK_GET_PARENTS,
  59. PM_QID_CLOCK_GET_ATTRIBUTES,
  60. PM_QID_PINCTRL_GET_NUM_PINS,
  61. PM_QID_PINCTRL_GET_NUM_FUNCTIONS,
  62. PM_QID_PINCTRL_GET_NUM_FUNCTION_GROUPS,
  63. PM_QID_PINCTRL_GET_FUNCTION_NAME,
  64. PM_QID_PINCTRL_GET_FUNCTION_GROUPS,
  65. PM_QID_PINCTRL_GET_PIN_GROUPS,
  66. PM_QID_CLOCK_GET_NUM_CLOCKS,
  67. PM_QID_CLOCK_GET_MAX_DIVISOR,
  68. };
  69. enum clk_type {
  70. CLK_TYPE_OUTPUT,
  71. CLK_TYPE_EXTERNAL,
  72. };
  73. struct clock_parent {
  74. char name[MAX_NAME_LEN];
  75. int id;
  76. u32 flag;
  77. };
  78. struct clock_topology {
  79. u32 type;
  80. u32 flag;
  81. u32 type_flag;
  82. };
  83. struct versal_clock {
  84. char clk_name[MAX_NAME_LEN];
  85. u32 valid;
  86. enum clk_type type;
  87. struct clock_topology node[MAX_NODES];
  88. u32 num_nodes;
  89. struct clock_parent parent[MAX_PARENT];
  90. u32 num_parents;
  91. u32 clk_id;
  92. };
  93. struct versal_clk_priv {
  94. struct versal_clock *clk;
  95. };
  96. static ulong alt_ref_clk;
  97. static ulong pl_alt_ref_clk;
  98. static ulong ref_clk;
  99. struct versal_pm_query_data {
  100. u32 qid;
  101. u32 arg1;
  102. u32 arg2;
  103. u32 arg3;
  104. };
  105. static struct versal_clock *clock;
  106. static unsigned int clock_max_idx;
  107. #define PM_QUERY_DATA 35
  108. static int versal_pm_query(struct versal_pm_query_data qdata, u32 *ret_payload)
  109. {
  110. struct pt_regs regs;
  111. regs.regs[0] = PM_SIP_SVC | PM_QUERY_DATA;
  112. regs.regs[1] = ((u64)qdata.arg1 << 32) | qdata.qid;
  113. regs.regs[2] = ((u64)qdata.arg3 << 32) | qdata.arg2;
  114. smc_call(&regs);
  115. if (ret_payload) {
  116. ret_payload[0] = (u32)regs.regs[0];
  117. ret_payload[1] = upper_32_bits(regs.regs[0]);
  118. ret_payload[2] = (u32)regs.regs[1];
  119. ret_payload[3] = upper_32_bits(regs.regs[1]);
  120. ret_payload[4] = (u32)regs.regs[2];
  121. }
  122. return qdata.qid == PM_QID_CLOCK_GET_NAME ? 0 : regs.regs[0];
  123. }
  124. static inline int versal_is_valid_clock(u32 clk_id)
  125. {
  126. if (clk_id >= clock_max_idx)
  127. return -ENODEV;
  128. return clock[clk_id].valid;
  129. }
  130. static int versal_get_clock_name(u32 clk_id, char *clk_name)
  131. {
  132. int ret;
  133. ret = versal_is_valid_clock(clk_id);
  134. if (ret == 1) {
  135. strncpy(clk_name, clock[clk_id].clk_name, MAX_NAME_LEN);
  136. return 0;
  137. }
  138. return ret == 0 ? -EINVAL : ret;
  139. }
  140. static int versal_get_clock_type(u32 clk_id, u32 *type)
  141. {
  142. int ret;
  143. ret = versal_is_valid_clock(clk_id);
  144. if (ret == 1) {
  145. *type = clock[clk_id].type;
  146. return 0;
  147. }
  148. return ret == 0 ? -EINVAL : ret;
  149. }
  150. static int versal_pm_clock_get_num_clocks(u32 *nclocks)
  151. {
  152. struct versal_pm_query_data qdata = {0};
  153. u32 ret_payload[PAYLOAD_ARG_CNT];
  154. int ret;
  155. qdata.qid = PM_QID_CLOCK_GET_NUM_CLOCKS;
  156. ret = versal_pm_query(qdata, ret_payload);
  157. *nclocks = ret_payload[1];
  158. return ret;
  159. }
  160. static int versal_pm_clock_get_name(u32 clock_id, char *name)
  161. {
  162. struct versal_pm_query_data qdata = {0};
  163. u32 ret_payload[PAYLOAD_ARG_CNT];
  164. int ret;
  165. qdata.qid = PM_QID_CLOCK_GET_NAME;
  166. qdata.arg1 = clock_id;
  167. ret = versal_pm_query(qdata, ret_payload);
  168. if (ret)
  169. return ret;
  170. memcpy(name, ret_payload, CLK_GET_NAME_RESP_LEN);
  171. return 0;
  172. }
  173. static int versal_pm_clock_get_topology(u32 clock_id, u32 index, u32 *topology)
  174. {
  175. struct versal_pm_query_data qdata = {0};
  176. u32 ret_payload[PAYLOAD_ARG_CNT];
  177. int ret;
  178. qdata.qid = PM_QID_CLOCK_GET_TOPOLOGY;
  179. qdata.arg1 = clock_id;
  180. qdata.arg2 = index;
  181. ret = versal_pm_query(qdata, ret_payload);
  182. memcpy(topology, &ret_payload[1], CLK_GET_TOPOLOGY_RESP_WORDS * 4);
  183. return ret;
  184. }
  185. static int versal_pm_clock_get_parents(u32 clock_id, u32 index, u32 *parents)
  186. {
  187. struct versal_pm_query_data qdata = {0};
  188. u32 ret_payload[PAYLOAD_ARG_CNT];
  189. int ret;
  190. qdata.qid = PM_QID_CLOCK_GET_PARENTS;
  191. qdata.arg1 = clock_id;
  192. qdata.arg2 = index;
  193. ret = versal_pm_query(qdata, ret_payload);
  194. memcpy(parents, &ret_payload[1], CLK_GET_PARENTS_RESP_WORDS * 4);
  195. return ret;
  196. }
  197. static int versal_pm_clock_get_attributes(u32 clock_id, u32 *attr)
  198. {
  199. struct versal_pm_query_data qdata = {0};
  200. u32 ret_payload[PAYLOAD_ARG_CNT];
  201. int ret;
  202. qdata.qid = PM_QID_CLOCK_GET_ATTRIBUTES;
  203. qdata.arg1 = clock_id;
  204. ret = versal_pm_query(qdata, ret_payload);
  205. memcpy(attr, &ret_payload[1], CLK_GET_ATTR_RESP_WORDS * 4);
  206. return ret;
  207. }
  208. static int __versal_clock_get_topology(struct clock_topology *topology,
  209. u32 *data, u32 *nnodes)
  210. {
  211. int i;
  212. for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
  213. if (!(data[i] & CLK_TYPE_FIELD_MASK))
  214. return END_OF_TOPOLOGY_NODE;
  215. topology[*nnodes].type = data[i] & CLK_TYPE_FIELD_MASK;
  216. topology[*nnodes].flag = FIELD_GET(CLK_FLAG_FIELD_MASK,
  217. data[i]);
  218. topology[*nnodes].type_flag =
  219. FIELD_GET(CLK_TYPE_FLAG_FIELD_MASK, data[i]);
  220. topology[*nnodes].type_flag |=
  221. FIELD_GET(CLK_TYPE_FLAG2_FIELD_MASK, data[i]) <<
  222. CLK_TYPE_FLAG_BITS;
  223. debug("topology type:0x%x, flag:0x%x, type_flag:0x%x\n",
  224. topology[*nnodes].type, topology[*nnodes].flag,
  225. topology[*nnodes].type_flag);
  226. (*nnodes)++;
  227. }
  228. return 0;
  229. }
  230. static int versal_clock_get_topology(u32 clk_id,
  231. struct clock_topology *topology,
  232. u32 *num_nodes)
  233. {
  234. int j, ret;
  235. u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
  236. *num_nodes = 0;
  237. for (j = 0; j <= MAX_NODES; j += 3) {
  238. ret = versal_pm_clock_get_topology(clock[clk_id].clk_id, j,
  239. pm_resp);
  240. if (ret)
  241. return ret;
  242. ret = __versal_clock_get_topology(topology, pm_resp, num_nodes);
  243. if (ret == END_OF_TOPOLOGY_NODE)
  244. return 0;
  245. }
  246. return 0;
  247. }
  248. static int __versal_clock_get_parents(struct clock_parent *parents, u32 *data,
  249. u32 *nparent)
  250. {
  251. int i;
  252. struct clock_parent *parent;
  253. for (i = 0; i < PM_API_PAYLOAD_LEN; i++) {
  254. if (data[i] == NA_PARENT)
  255. return END_OF_PARENTS;
  256. parent = &parents[i];
  257. parent->id = data[i] & CLK_PARENTS_ID_MASK;
  258. if (data[i] == DUMMY_PARENT) {
  259. strcpy(parent->name, "dummy_name");
  260. parent->flag = 0;
  261. } else {
  262. parent->flag = data[i] >> CLK_PARENTS_ID_LEN;
  263. if (versal_get_clock_name(parent->id, parent->name))
  264. continue;
  265. }
  266. debug("parent name:%s\n", parent->name);
  267. *nparent += 1;
  268. }
  269. return 0;
  270. }
  271. static int versal_clock_get_parents(u32 clk_id, struct clock_parent *parents,
  272. u32 *num_parents)
  273. {
  274. int j = 0, ret;
  275. u32 pm_resp[PM_API_PAYLOAD_LEN] = {0};
  276. *num_parents = 0;
  277. do {
  278. /* Get parents from firmware */
  279. ret = versal_pm_clock_get_parents(clock[clk_id].clk_id, j,
  280. pm_resp);
  281. if (ret)
  282. return ret;
  283. ret = __versal_clock_get_parents(&parents[j], pm_resp,
  284. num_parents);
  285. if (ret == END_OF_PARENTS)
  286. return 0;
  287. j += PM_API_PAYLOAD_LEN;
  288. } while (*num_parents <= MAX_PARENT);
  289. return 0;
  290. }
  291. static u32 versal_clock_get_div(u32 clk_id)
  292. {
  293. u32 ret_payload[PAYLOAD_ARG_CNT];
  294. u32 div;
  295. xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
  296. div = ret_payload[1];
  297. return div;
  298. }
  299. static u32 versal_clock_set_div(u32 clk_id, u32 div)
  300. {
  301. u32 ret_payload[PAYLOAD_ARG_CNT];
  302. xilinx_pm_request(PM_CLOCK_SETDIVIDER, clk_id, div, 0, 0, ret_payload);
  303. return div;
  304. }
  305. static u64 versal_clock_ref(u32 clk_id)
  306. {
  307. u32 ret_payload[PAYLOAD_ARG_CNT];
  308. int ref;
  309. xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0, ret_payload);
  310. ref = ret_payload[0];
  311. if (!(ref & 1))
  312. return ref_clk;
  313. if (ref & 2)
  314. return pl_alt_ref_clk;
  315. return 0;
  316. }
  317. static u64 versal_clock_get_pll_rate(u32 clk_id)
  318. {
  319. u32 ret_payload[PAYLOAD_ARG_CNT];
  320. u32 fbdiv;
  321. u32 res;
  322. u32 frac;
  323. u64 freq;
  324. u32 parent_rate, parent_id;
  325. u32 id = clk_id & 0xFFF;
  326. xilinx_pm_request(PM_CLOCK_GETSTATE, clk_id, 0, 0, 0, ret_payload);
  327. res = ret_payload[1];
  328. if (!res) {
  329. printf("0%x PLL not enabled\n", clk_id);
  330. return 0;
  331. }
  332. parent_id = clock[clock[id].parent[0].id].clk_id;
  333. parent_rate = versal_clock_ref(parent_id);
  334. xilinx_pm_request(PM_CLOCK_GETDIVIDER, clk_id, 0, 0, 0, ret_payload);
  335. fbdiv = ret_payload[1];
  336. xilinx_pm_request(PM_CLOCK_PLL_GETPARAM, clk_id, 2, 0, 0, ret_payload);
  337. frac = ret_payload[1];
  338. freq = (fbdiv * parent_rate) >> (1 << frac);
  339. return freq;
  340. }
  341. static u32 versal_clock_mux(u32 clk_id)
  342. {
  343. int i;
  344. u32 id = clk_id & 0xFFF;
  345. for (i = 0; i < clock[id].num_nodes; i++)
  346. if (clock[id].node[i].type == CLOCK_NODE_TYPE_MUX)
  347. return 1;
  348. return 0;
  349. }
  350. static u32 versal_clock_get_parentid(u32 clk_id)
  351. {
  352. u32 parent_id = 0;
  353. u32 ret_payload[PAYLOAD_ARG_CNT];
  354. u32 id = clk_id & 0xFFF;
  355. if (versal_clock_mux(clk_id)) {
  356. xilinx_pm_request(PM_CLOCK_GETPARENT, clk_id, 0, 0, 0,
  357. ret_payload);
  358. parent_id = ret_payload[1];
  359. }
  360. debug("parent_id:0x%x\n", clock[clock[id].parent[parent_id].id].clk_id);
  361. return clock[clock[id].parent[parent_id].id].clk_id;
  362. }
  363. static u32 versal_clock_gate(u32 clk_id)
  364. {
  365. u32 id = clk_id & 0xFFF;
  366. int i;
  367. for (i = 0; i < clock[id].num_nodes; i++)
  368. if (clock[id].node[i].type == CLOCK_NODE_TYPE_GATE)
  369. return 1;
  370. return 0;
  371. }
  372. static u32 versal_clock_div(u32 clk_id)
  373. {
  374. int i;
  375. u32 id = clk_id & 0xFFF;
  376. for (i = 0; i < clock[id].num_nodes; i++)
  377. if (clock[id].node[i].type == CLOCK_NODE_TYPE_DIV)
  378. return 1;
  379. return 0;
  380. }
  381. static u32 versal_clock_pll(u32 clk_id, u64 *clk_rate)
  382. {
  383. if (((clk_id >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK) ==
  384. NODE_SUBCLASS_CLOCK_PLL &&
  385. ((clk_id >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK) ==
  386. NODE_CLASS_CLOCK) {
  387. *clk_rate = versal_clock_get_pll_rate(clk_id);
  388. return 1;
  389. }
  390. return 0;
  391. }
  392. static u64 versal_clock_calc(u32 clk_id)
  393. {
  394. u32 parent_id;
  395. u64 clk_rate;
  396. u32 div;
  397. if (versal_clock_pll(clk_id, &clk_rate))
  398. return clk_rate;
  399. parent_id = versal_clock_get_parentid(clk_id);
  400. if (((parent_id >> NODE_SUBCLASS_SHIFT) &
  401. NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
  402. return versal_clock_ref(clk_id);
  403. if (!parent_id)
  404. return 0;
  405. clk_rate = versal_clock_calc(parent_id);
  406. if (versal_clock_div(clk_id)) {
  407. div = versal_clock_get_div(clk_id);
  408. clk_rate = DIV_ROUND_CLOSEST(clk_rate, div);
  409. }
  410. return clk_rate;
  411. }
  412. static int versal_clock_get_rate(u32 clk_id, u64 *clk_rate)
  413. {
  414. if (((clk_id >> NODE_SUBCLASS_SHIFT) &
  415. NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_REF)
  416. *clk_rate = versal_clock_ref(clk_id);
  417. if (versal_clock_pll(clk_id, clk_rate))
  418. return 0;
  419. if (((clk_id >> NODE_SUBCLASS_SHIFT) &
  420. NODE_CLASS_MASK) == NODE_SUBCLASS_CLOCK_OUT &&
  421. ((clk_id >> NODE_CLASS_SHIFT) &
  422. NODE_CLASS_MASK) == NODE_CLASS_CLOCK) {
  423. if (!versal_clock_gate(clk_id) && !versal_clock_mux(clk_id))
  424. return -EINVAL;
  425. *clk_rate = versal_clock_calc(clk_id);
  426. return 0;
  427. }
  428. return 0;
  429. }
  430. int soc_clk_dump(void)
  431. {
  432. u64 clk_rate = 0;
  433. u32 type, ret, i = 0;
  434. printf("\n ****** VERSAL CLOCKS *****\n");
  435. printf("alt_ref_clk:%ld pl_alt_ref_clk:%ld ref_clk:%ld\n",
  436. alt_ref_clk, pl_alt_ref_clk, ref_clk);
  437. for (i = 0; i < clock_max_idx; i++) {
  438. debug("%s\n", clock[i].clk_name);
  439. ret = versal_get_clock_type(i, &type);
  440. if (ret || type != CLK_TYPE_OUTPUT)
  441. continue;
  442. ret = versal_clock_get_rate(clock[i].clk_id, &clk_rate);
  443. if (ret != -EINVAL)
  444. printf("clk: %s freq:%lld\n",
  445. clock[i].clk_name, clk_rate);
  446. }
  447. return 0;
  448. }
  449. static void versal_get_clock_info(void)
  450. {
  451. int i, ret;
  452. u32 attr, type = 0, nodetype, subclass, class;
  453. for (i = 0; i < clock_max_idx; i++) {
  454. ret = versal_pm_clock_get_attributes(i, &attr);
  455. if (ret)
  456. continue;
  457. clock[i].valid = attr & CLK_VALID_MASK;
  458. /* skip query for Invalid clock */
  459. ret = versal_is_valid_clock(i);
  460. if (ret != CLK_VALID_MASK)
  461. continue;
  462. clock[i].type = ((attr >> CLK_TYPE_SHIFT) & 0x1) ?
  463. CLK_TYPE_EXTERNAL : CLK_TYPE_OUTPUT;
  464. nodetype = (attr >> NODE_TYPE_SHIFT) & NODE_CLASS_MASK;
  465. subclass = (attr >> NODE_SUBCLASS_SHIFT) & NODE_CLASS_MASK;
  466. class = (attr >> NODE_CLASS_SHIFT) & NODE_CLASS_MASK;
  467. clock[i].clk_id = (class << NODE_CLASS_SHIFT) |
  468. (subclass << NODE_SUBCLASS_SHIFT) |
  469. (nodetype << NODE_TYPE_SHIFT) |
  470. (i << NODE_INDEX_SHIFT);
  471. ret = versal_pm_clock_get_name(clock[i].clk_id,
  472. clock[i].clk_name);
  473. if (ret)
  474. continue;
  475. debug("clk name:%s, Valid:%d, type:%d, clk_id:0x%x\n",
  476. clock[i].clk_name, clock[i].valid,
  477. clock[i].type, clock[i].clk_id);
  478. }
  479. /* Get topology of all clock */
  480. for (i = 0; i < clock_max_idx; i++) {
  481. ret = versal_get_clock_type(i, &type);
  482. if (ret || type != CLK_TYPE_OUTPUT)
  483. continue;
  484. debug("clk name:%s\n", clock[i].clk_name);
  485. ret = versal_clock_get_topology(i, clock[i].node,
  486. &clock[i].num_nodes);
  487. if (ret)
  488. continue;
  489. ret = versal_clock_get_parents(i, clock[i].parent,
  490. &clock[i].num_parents);
  491. if (ret)
  492. continue;
  493. }
  494. }
  495. int versal_clock_setup(void)
  496. {
  497. int ret;
  498. ret = versal_pm_clock_get_num_clocks(&clock_max_idx);
  499. if (ret)
  500. return ret;
  501. debug("%s, clock_max_idx:0x%x\n", __func__, clock_max_idx);
  502. clock = calloc(clock_max_idx, sizeof(*clock));
  503. if (!clock)
  504. return -ENOMEM;
  505. versal_get_clock_info();
  506. return 0;
  507. }
  508. static int versal_clock_get_freq_by_name(char *name, struct udevice *dev,
  509. ulong *freq)
  510. {
  511. struct clk clk;
  512. int ret;
  513. ret = clk_get_by_name(dev, name, &clk);
  514. if (ret < 0) {
  515. dev_err(dev, "failed to get %s\n", name);
  516. return ret;
  517. }
  518. *freq = clk_get_rate(&clk);
  519. if (IS_ERR_VALUE(*freq)) {
  520. dev_err(dev, "failed to get rate %s\n", name);
  521. return -EINVAL;
  522. }
  523. return 0;
  524. }
  525. static int versal_clk_probe(struct udevice *dev)
  526. {
  527. int ret;
  528. struct versal_clk_priv *priv = dev_get_priv(dev);
  529. debug("%s\n", __func__);
  530. ret = versal_clock_get_freq_by_name("alt_ref_clk", dev, &alt_ref_clk);
  531. if (ret < 0)
  532. return -EINVAL;
  533. ret = versal_clock_get_freq_by_name("pl_alt_ref_clk",
  534. dev, &pl_alt_ref_clk);
  535. if (ret < 0)
  536. return -EINVAL;
  537. ret = versal_clock_get_freq_by_name("ref_clk", dev, &ref_clk);
  538. if (ret < 0)
  539. return -EINVAL;
  540. versal_clock_setup();
  541. priv->clk = clock;
  542. return ret;
  543. }
  544. static ulong versal_clk_get_rate(struct clk *clk)
  545. {
  546. struct versal_clk_priv *priv = dev_get_priv(clk->dev);
  547. u32 id = clk->id;
  548. u32 clk_id;
  549. u64 clk_rate = 0;
  550. debug("%s\n", __func__);
  551. clk_id = priv->clk[id].clk_id;
  552. versal_clock_get_rate(clk_id, &clk_rate);
  553. return clk_rate;
  554. }
  555. static ulong versal_clk_set_rate(struct clk *clk, ulong rate)
  556. {
  557. struct versal_clk_priv *priv = dev_get_priv(clk->dev);
  558. u32 id = clk->id;
  559. u32 clk_id;
  560. u64 clk_rate = 0;
  561. u32 div;
  562. int ret;
  563. debug("%s\n", __func__);
  564. clk_id = priv->clk[id].clk_id;
  565. ret = versal_clock_get_rate(clk_id, &clk_rate);
  566. if (ret) {
  567. printf("Clock is not a Gate:0x%x\n", clk_id);
  568. return 0;
  569. }
  570. do {
  571. if (versal_clock_div(clk_id)) {
  572. div = versal_clock_get_div(clk_id);
  573. clk_rate *= div;
  574. div = DIV_ROUND_CLOSEST(clk_rate, rate);
  575. versal_clock_set_div(clk_id, div);
  576. debug("%s, div:%d, newrate:%lld\n", __func__,
  577. div, DIV_ROUND_CLOSEST(clk_rate, div));
  578. return DIV_ROUND_CLOSEST(clk_rate, div);
  579. }
  580. clk_id = versal_clock_get_parentid(clk_id);
  581. } while (((clk_id >> NODE_SUBCLASS_SHIFT) &
  582. NODE_CLASS_MASK) != NODE_SUBCLASS_CLOCK_REF);
  583. printf("Clock didn't has Divisors:0x%x\n", priv->clk[id].clk_id);
  584. return clk_rate;
  585. }
  586. static struct clk_ops versal_clk_ops = {
  587. .set_rate = versal_clk_set_rate,
  588. .get_rate = versal_clk_get_rate,
  589. };
  590. static const struct udevice_id versal_clk_ids[] = {
  591. { .compatible = "xlnx,versal-clk" },
  592. { }
  593. };
  594. U_BOOT_DRIVER(versal_clk) = {
  595. .name = "versal-clk",
  596. .id = UCLASS_CLK,
  597. .of_match = versal_clk_ids,
  598. .probe = versal_clk_probe,
  599. .ops = &versal_clk_ops,
  600. .priv_auto_alloc_size = sizeof(struct versal_clk_priv),
  601. };