board.c 4.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2014 - 2018 Xilinx, Inc.
  4. * Michal Simek <michal.simek@xilinx.com>
  5. */
  6. #include <common.h>
  7. #include <cpu_func.h>
  8. #include <fdtdec.h>
  9. #include <init.h>
  10. #include <malloc.h>
  11. #include <time.h>
  12. #include <asm/io.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/sys_proto.h>
  15. #include <dm/device.h>
  16. #include <dm/uclass.h>
  17. #include <versalpl.h>
  18. #include "../common/board.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #if defined(CONFIG_FPGA_VERSALPL)
  21. static xilinx_desc versalpl = XILINX_VERSAL_DESC;
  22. #endif
  23. int board_init(void)
  24. {
  25. printf("EL Level:\tEL%d\n", current_el());
  26. #if defined(CONFIG_FPGA_VERSALPL)
  27. fpga_init();
  28. fpga_add(fpga_xilinx, &versalpl);
  29. #endif
  30. return 0;
  31. }
  32. int board_early_init_r(void)
  33. {
  34. u32 val;
  35. if (current_el() != 3)
  36. return 0;
  37. debug("iou_switch ctrl div0 %x\n",
  38. readl(&crlapb_base->iou_switch_ctrl));
  39. writel(IOU_SWITCH_CTRL_CLKACT_BIT |
  40. (CONFIG_IOU_SWITCH_DIVISOR0 << IOU_SWITCH_CTRL_DIVISOR0_SHIFT),
  41. &crlapb_base->iou_switch_ctrl);
  42. /* Global timer init - Program time stamp reference clk */
  43. val = readl(&crlapb_base->timestamp_ref_ctrl);
  44. val |= CRL_APB_TIMESTAMP_REF_CTRL_CLKACT_BIT;
  45. writel(val, &crlapb_base->timestamp_ref_ctrl);
  46. debug("ref ctrl 0x%x\n",
  47. readl(&crlapb_base->timestamp_ref_ctrl));
  48. /* Clear reset of timestamp reg */
  49. writel(0, &crlapb_base->rst_timestamp);
  50. /*
  51. * Program freq register in System counter and
  52. * enable system counter.
  53. */
  54. writel(COUNTER_FREQUENCY,
  55. &iou_scntr_secure->base_frequency_id_register);
  56. debug("counter val 0x%x\n",
  57. readl(&iou_scntr_secure->base_frequency_id_register));
  58. writel(IOU_SCNTRS_CONTROL_EN,
  59. &iou_scntr_secure->counter_control_register);
  60. debug("scntrs control 0x%x\n",
  61. readl(&iou_scntr_secure->counter_control_register));
  62. debug("timer 0x%llx\n", get_ticks());
  63. debug("timer 0x%llx\n", get_ticks());
  64. return 0;
  65. }
  66. static u8 versal_get_bootmode(void)
  67. {
  68. u8 bootmode;
  69. u32 reg = 0;
  70. reg = readl(&crp_base->boot_mode_usr);
  71. if (reg >> BOOT_MODE_ALT_SHIFT)
  72. reg >>= BOOT_MODE_ALT_SHIFT;
  73. bootmode = reg & BOOT_MODES_MASK;
  74. return bootmode;
  75. }
  76. int board_late_init(void)
  77. {
  78. u8 bootmode;
  79. struct udevice *dev;
  80. int bootseq = -1;
  81. int bootseq_len = 0;
  82. int env_targets_len = 0;
  83. const char *mode;
  84. char *new_targets;
  85. char *env_targets;
  86. if (!(gd->flags & GD_FLG_ENV_DEFAULT)) {
  87. debug("Saved variables - Skipping\n");
  88. return 0;
  89. }
  90. bootmode = versal_get_bootmode();
  91. puts("Bootmode: ");
  92. switch (bootmode) {
  93. case USB_MODE:
  94. puts("USB_MODE\n");
  95. mode = "dfu_usb";
  96. break;
  97. case JTAG_MODE:
  98. puts("JTAG_MODE\n");
  99. mode = "jtag pxe dhcp";
  100. break;
  101. case QSPI_MODE_24BIT:
  102. puts("QSPI_MODE_24\n");
  103. mode = "xspi0";
  104. break;
  105. case QSPI_MODE_32BIT:
  106. puts("QSPI_MODE_32\n");
  107. mode = "xspi0";
  108. break;
  109. case OSPI_MODE:
  110. puts("OSPI_MODE\n");
  111. mode = "xspi0";
  112. break;
  113. case EMMC_MODE:
  114. puts("EMMC_MODE\n");
  115. if (uclass_get_device_by_name(UCLASS_MMC,
  116. "sdhci@f1050000", &dev)) {
  117. puts("Boot from EMMC but without SD1 enabled!\n");
  118. return -1;
  119. }
  120. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  121. mode = "mmc";
  122. bootseq = dev->seq;
  123. break;
  124. case SD_MODE:
  125. puts("SD_MODE\n");
  126. if (uclass_get_device_by_name(UCLASS_MMC,
  127. "sdhci@f1040000", &dev)) {
  128. puts("Boot from SD0 but without SD0 enabled!\n");
  129. return -1;
  130. }
  131. debug("mmc0 device found at %p, seq %d\n", dev, dev->seq);
  132. mode = "mmc";
  133. bootseq = dev->seq;
  134. break;
  135. case SD1_LSHFT_MODE:
  136. puts("LVL_SHFT_");
  137. /* fall through */
  138. case SD_MODE1:
  139. puts("SD_MODE1\n");
  140. if (uclass_get_device_by_name(UCLASS_MMC,
  141. "sdhci@f1050000", &dev)) {
  142. puts("Boot from SD1 but without SD1 enabled!\n");
  143. return -1;
  144. }
  145. debug("mmc1 device found at %p, seq %d\n", dev, dev->seq);
  146. mode = "mmc";
  147. bootseq = dev->seq;
  148. break;
  149. default:
  150. mode = "";
  151. printf("Invalid Boot Mode:0x%x\n", bootmode);
  152. break;
  153. }
  154. if (bootseq >= 0) {
  155. bootseq_len = snprintf(NULL, 0, "%i", bootseq);
  156. debug("Bootseq len: %x\n", bootseq_len);
  157. }
  158. /*
  159. * One terminating char + one byte for space between mode
  160. * and default boot_targets
  161. */
  162. env_targets = env_get("boot_targets");
  163. if (env_targets)
  164. env_targets_len = strlen(env_targets);
  165. new_targets = calloc(1, strlen(mode) + env_targets_len + 2 +
  166. bootseq_len);
  167. if (!new_targets)
  168. return -ENOMEM;
  169. if (bootseq >= 0)
  170. sprintf(new_targets, "%s%x %s", mode, bootseq,
  171. env_targets ? env_targets : "");
  172. else
  173. sprintf(new_targets, "%s %s", mode,
  174. env_targets ? env_targets : "");
  175. env_set("boot_targets", new_targets);
  176. return board_late_init_xilinx();
  177. }
  178. int dram_init_banksize(void)
  179. {
  180. int ret;
  181. ret = fdtdec_setup_memory_banksize();
  182. if (ret)
  183. return ret;
  184. mem_map_fill();
  185. return 0;
  186. }
  187. int dram_init(void)
  188. {
  189. if (fdtdec_setup_mem_size_base() != 0)
  190. return -EINVAL;
  191. return 0;
  192. }
  193. void reset_cpu(ulong addr)
  194. {
  195. }