zynq_sdhci.c 7.0 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 - 2015 Xilinx, Inc.
  4. *
  5. * Xilinx Zynq SD Host Controller Interface
  6. */
  7. #include <clk.h>
  8. #include <common.h>
  9. #include <dm.h>
  10. #include <fdtdec.h>
  11. #include "mmc_private.h"
  12. #include <dm/device_compat.h>
  13. #include <linux/err.h>
  14. #include <linux/libfdt.h>
  15. #include <malloc.h>
  16. #include <sdhci.h>
  17. #include <zynqmp_tap_delay.h>
  18. DECLARE_GLOBAL_DATA_PTR;
  19. struct arasan_sdhci_plat {
  20. struct mmc_config cfg;
  21. struct mmc mmc;
  22. };
  23. struct arasan_sdhci_priv {
  24. struct sdhci_host *host;
  25. u8 deviceid;
  26. u8 bank;
  27. };
  28. #if defined(CONFIG_ARCH_ZYNQMP)
  29. #define MMC_HS200_BUS_SPEED 5
  30. static const u8 mode2timing[] = {
  31. [MMC_LEGACY] = UHS_SDR12_BUS_SPEED,
  32. [MMC_HS] = HIGH_SPEED_BUS_SPEED,
  33. [SD_HS] = HIGH_SPEED_BUS_SPEED,
  34. [MMC_HS_52] = HIGH_SPEED_BUS_SPEED,
  35. [MMC_DDR_52] = HIGH_SPEED_BUS_SPEED,
  36. [UHS_SDR12] = UHS_SDR12_BUS_SPEED,
  37. [UHS_SDR25] = UHS_SDR25_BUS_SPEED,
  38. [UHS_SDR50] = UHS_SDR50_BUS_SPEED,
  39. [UHS_DDR50] = UHS_DDR50_BUS_SPEED,
  40. [UHS_SDR104] = UHS_SDR104_BUS_SPEED,
  41. [MMC_HS_200] = MMC_HS200_BUS_SPEED,
  42. };
  43. #define SDHCI_TUNING_LOOP_COUNT 40
  44. static void arasan_zynqmp_dll_reset(struct sdhci_host *host, u8 deviceid)
  45. {
  46. u16 clk;
  47. unsigned long timeout;
  48. clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL);
  49. clk &= ~(SDHCI_CLOCK_CARD_EN);
  50. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  51. /* Issue DLL Reset */
  52. zynqmp_dll_reset(deviceid);
  53. /* Wait max 20 ms */
  54. timeout = 100;
  55. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  56. & SDHCI_CLOCK_INT_STABLE)) {
  57. if (timeout == 0) {
  58. dev_err(mmc_dev(host->mmc),
  59. ": Internal clock never stabilised.\n");
  60. return;
  61. }
  62. timeout--;
  63. udelay(1000);
  64. }
  65. clk |= SDHCI_CLOCK_CARD_EN;
  66. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  67. }
  68. static int arasan_sdhci_execute_tuning(struct mmc *mmc, u8 opcode)
  69. {
  70. struct mmc_cmd cmd;
  71. struct mmc_data data;
  72. u32 ctrl;
  73. struct sdhci_host *host;
  74. struct arasan_sdhci_priv *priv = dev_get_priv(mmc->dev);
  75. char tuning_loop_counter = SDHCI_TUNING_LOOP_COUNT;
  76. u8 deviceid;
  77. debug("%s\n", __func__);
  78. host = priv->host;
  79. deviceid = priv->deviceid;
  80. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  81. ctrl |= SDHCI_CTRL_EXEC_TUNING;
  82. sdhci_writew(host, ctrl, SDHCI_HOST_CONTROL2);
  83. mdelay(1);
  84. arasan_zynqmp_dll_reset(host, deviceid);
  85. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_INT_ENABLE);
  86. sdhci_writel(host, SDHCI_INT_DATA_AVAIL, SDHCI_SIGNAL_ENABLE);
  87. do {
  88. cmd.cmdidx = opcode;
  89. cmd.resp_type = MMC_RSP_R1;
  90. cmd.cmdarg = 0;
  91. data.blocksize = 64;
  92. data.blocks = 1;
  93. data.flags = MMC_DATA_READ;
  94. if (tuning_loop_counter-- == 0)
  95. break;
  96. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200 &&
  97. mmc->bus_width == 8)
  98. data.blocksize = 128;
  99. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  100. data.blocksize),
  101. SDHCI_BLOCK_SIZE);
  102. sdhci_writew(host, data.blocks, SDHCI_BLOCK_COUNT);
  103. sdhci_writew(host, SDHCI_TRNS_READ, SDHCI_TRANSFER_MODE);
  104. mmc_send_cmd(mmc, &cmd, NULL);
  105. ctrl = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  106. if (cmd.cmdidx == MMC_CMD_SEND_TUNING_BLOCK)
  107. udelay(1);
  108. } while (ctrl & SDHCI_CTRL_EXEC_TUNING);
  109. if (tuning_loop_counter < 0) {
  110. ctrl &= ~SDHCI_CTRL_TUNED_CLK;
  111. sdhci_writel(host, ctrl, SDHCI_HOST_CONTROL2);
  112. }
  113. if (!(ctrl & SDHCI_CTRL_TUNED_CLK)) {
  114. printf("%s:Tuning failed\n", __func__);
  115. return -1;
  116. }
  117. udelay(1);
  118. arasan_zynqmp_dll_reset(host, deviceid);
  119. /* Enable only interrupts served by the SD controller */
  120. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  121. SDHCI_INT_ENABLE);
  122. /* Mask all sdhci interrupt sources */
  123. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  124. return 0;
  125. }
  126. static void arasan_sdhci_set_tapdelay(struct sdhci_host *host)
  127. {
  128. struct arasan_sdhci_priv *priv = dev_get_priv(host->mmc->dev);
  129. struct mmc *mmc = (struct mmc *)host->mmc;
  130. u8 uhsmode;
  131. uhsmode = mode2timing[mmc->selected_mode];
  132. if (uhsmode >= UHS_SDR25_BUS_SPEED)
  133. arasan_zynqmp_set_tapdelay(priv->deviceid, uhsmode,
  134. priv->bank);
  135. }
  136. static void arasan_sdhci_set_control_reg(struct sdhci_host *host)
  137. {
  138. struct mmc *mmc = (struct mmc *)host->mmc;
  139. u32 reg;
  140. if (!IS_SD(mmc))
  141. return;
  142. if (mmc->signal_voltage == MMC_SIGNAL_VOLTAGE_180) {
  143. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  144. reg |= SDHCI_CTRL_VDD_180;
  145. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  146. }
  147. if (mmc->selected_mode > SD_HS &&
  148. mmc->selected_mode <= UHS_DDR50)
  149. sdhci_set_uhs_timing(host);
  150. }
  151. #endif
  152. #if defined(CONFIG_ARCH_ZYNQMP)
  153. const struct sdhci_ops arasan_ops = {
  154. .platform_execute_tuning = &arasan_sdhci_execute_tuning,
  155. .set_delay = &arasan_sdhci_set_tapdelay,
  156. .set_control_reg = &arasan_sdhci_set_control_reg,
  157. };
  158. #endif
  159. static int arasan_sdhci_probe(struct udevice *dev)
  160. {
  161. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  162. struct mmc_uclass_priv *upriv = dev_get_uclass_priv(dev);
  163. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  164. struct sdhci_host *host;
  165. struct clk clk;
  166. unsigned long clock;
  167. int ret;
  168. host = priv->host;
  169. ret = clk_get_by_index(dev, 0, &clk);
  170. if (ret < 0) {
  171. dev_err(dev, "failed to get clock\n");
  172. return ret;
  173. }
  174. clock = clk_get_rate(&clk);
  175. if (IS_ERR_VALUE(clock)) {
  176. dev_err(dev, "failed to get rate\n");
  177. return clock;
  178. }
  179. debug("%s: CLK %ld\n", __func__, clock);
  180. ret = clk_enable(&clk);
  181. if (ret && ret != -ENOSYS) {
  182. dev_err(dev, "failed to enable clock\n");
  183. return ret;
  184. }
  185. host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD |
  186. SDHCI_QUIRK_BROKEN_R1B;
  187. #ifdef CONFIG_ZYNQ_HISPD_BROKEN
  188. host->quirks |= SDHCI_QUIRK_BROKEN_HISPD_MODE;
  189. #endif
  190. plat->cfg.f_max = CONFIG_ZYNQ_SDHCI_MAX_FREQ;
  191. ret = mmc_of_parse(dev, &plat->cfg);
  192. if (ret)
  193. return ret;
  194. host->max_clk = clock;
  195. host->mmc = &plat->mmc;
  196. host->mmc->dev = dev;
  197. host->mmc->priv = host;
  198. ret = sdhci_setup_cfg(&plat->cfg, host, plat->cfg.f_max,
  199. CONFIG_ZYNQ_SDHCI_MIN_FREQ);
  200. if (ret)
  201. return ret;
  202. upriv->mmc = host->mmc;
  203. return sdhci_probe(dev);
  204. }
  205. static int arasan_sdhci_ofdata_to_platdata(struct udevice *dev)
  206. {
  207. struct arasan_sdhci_priv *priv = dev_get_priv(dev);
  208. priv->host = calloc(1, sizeof(struct sdhci_host));
  209. if (!priv->host)
  210. return -1;
  211. priv->host->name = dev->name;
  212. #if defined(CONFIG_ARCH_ZYNQMP)
  213. priv->host->ops = &arasan_ops;
  214. #endif
  215. priv->host->ioaddr = (void *)dev_read_addr(dev);
  216. if (IS_ERR(priv->host->ioaddr))
  217. return PTR_ERR(priv->host->ioaddr);
  218. priv->deviceid = dev_read_u32_default(dev, "xlnx,device_id", -1);
  219. priv->bank = dev_read_u32_default(dev, "xlnx,mio_bank", -1);
  220. return 0;
  221. }
  222. static int arasan_sdhci_bind(struct udevice *dev)
  223. {
  224. struct arasan_sdhci_plat *plat = dev_get_platdata(dev);
  225. return sdhci_bind(dev, &plat->mmc, &plat->cfg);
  226. }
  227. static const struct udevice_id arasan_sdhci_ids[] = {
  228. { .compatible = "arasan,sdhci-8.9a" },
  229. { }
  230. };
  231. U_BOOT_DRIVER(arasan_sdhci_drv) = {
  232. .name = "arasan_sdhci",
  233. .id = UCLASS_MMC,
  234. .of_match = arasan_sdhci_ids,
  235. .ofdata_to_platdata = arasan_sdhci_ofdata_to_platdata,
  236. .ops = &sdhci_ops,
  237. .bind = arasan_sdhci_bind,
  238. .probe = arasan_sdhci_probe,
  239. .priv_auto_alloc_size = sizeof(struct arasan_sdhci_priv),
  240. .platdata_auto_alloc_size = sizeof(struct arasan_sdhci_plat),
  241. };