sdhci.c 22 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2011, Marvell Semiconductor Inc.
  4. * Lei Wen <leiwen@marvell.com>
  5. *
  6. * Back ported to the 8xx platform (from the 8260 platform) by
  7. * Murray.Jensen@cmst.csiro.au, 27-Jan-01.
  8. */
  9. #include <common.h>
  10. #include <cpu_func.h>
  11. #include <dm.h>
  12. #include <errno.h>
  13. #include <malloc.h>
  14. #include <mmc.h>
  15. #include <sdhci.h>
  16. #include <dm.h>
  17. #include <linux/dma-mapping.h>
  18. static void sdhci_reset(struct sdhci_host *host, u8 mask)
  19. {
  20. unsigned long timeout;
  21. /* Wait max 100 ms */
  22. timeout = 100;
  23. sdhci_writeb(host, mask, SDHCI_SOFTWARE_RESET);
  24. while (sdhci_readb(host, SDHCI_SOFTWARE_RESET) & mask) {
  25. if (timeout == 0) {
  26. printf("%s: Reset 0x%x never completed.\n",
  27. __func__, (int)mask);
  28. return;
  29. }
  30. timeout--;
  31. udelay(1000);
  32. }
  33. }
  34. static void sdhci_cmd_done(struct sdhci_host *host, struct mmc_cmd *cmd)
  35. {
  36. int i;
  37. if (cmd->resp_type & MMC_RSP_136) {
  38. /* CRC is stripped so we need to do some shifting. */
  39. for (i = 0; i < 4; i++) {
  40. cmd->response[i] = sdhci_readl(host,
  41. SDHCI_RESPONSE + (3-i)*4) << 8;
  42. if (i != 3)
  43. cmd->response[i] |= sdhci_readb(host,
  44. SDHCI_RESPONSE + (3-i)*4-1);
  45. }
  46. } else {
  47. cmd->response[0] = sdhci_readl(host, SDHCI_RESPONSE);
  48. }
  49. }
  50. static void sdhci_transfer_pio(struct sdhci_host *host, struct mmc_data *data)
  51. {
  52. int i;
  53. char *offs;
  54. for (i = 0; i < data->blocksize; i += 4) {
  55. offs = data->dest + i;
  56. if (data->flags == MMC_DATA_READ)
  57. *(u32 *)offs = sdhci_readl(host, SDHCI_BUFFER);
  58. else
  59. sdhci_writel(host, *(u32 *)offs, SDHCI_BUFFER);
  60. }
  61. }
  62. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  63. static void sdhci_adma_desc(struct sdhci_host *host, dma_addr_t dma_addr,
  64. u16 len, bool end)
  65. {
  66. struct sdhci_adma_desc *desc;
  67. u8 attr;
  68. desc = &host->adma_desc_table[host->desc_slot];
  69. attr = ADMA_DESC_ATTR_VALID | ADMA_DESC_TRANSFER_DATA;
  70. if (!end)
  71. host->desc_slot++;
  72. else
  73. attr |= ADMA_DESC_ATTR_END;
  74. desc->attr = attr;
  75. desc->len = len;
  76. desc->reserved = 0;
  77. desc->addr_lo = lower_32_bits(dma_addr);
  78. #ifdef CONFIG_DMA_ADDR_T_64BIT
  79. desc->addr_hi = upper_32_bits(dma_addr);
  80. #endif
  81. }
  82. static void sdhci_prepare_adma_table(struct sdhci_host *host,
  83. struct mmc_data *data)
  84. {
  85. uint trans_bytes = data->blocksize * data->blocks;
  86. uint desc_count = DIV_ROUND_UP(trans_bytes, ADMA_MAX_LEN);
  87. int i = desc_count;
  88. dma_addr_t dma_addr = host->start_addr;
  89. host->desc_slot = 0;
  90. while (--i) {
  91. sdhci_adma_desc(host, dma_addr, ADMA_MAX_LEN, false);
  92. dma_addr += ADMA_MAX_LEN;
  93. trans_bytes -= ADMA_MAX_LEN;
  94. }
  95. sdhci_adma_desc(host, dma_addr, trans_bytes, true);
  96. flush_cache((dma_addr_t)host->adma_desc_table,
  97. ROUND(desc_count * sizeof(struct sdhci_adma_desc),
  98. ARCH_DMA_MINALIGN));
  99. }
  100. #elif defined(CONFIG_MMC_SDHCI_SDMA)
  101. static void sdhci_prepare_adma_table(struct sdhci_host *host,
  102. struct mmc_data *data)
  103. {}
  104. #endif
  105. #if (defined(CONFIG_MMC_SDHCI_SDMA) || CONFIG_IS_ENABLED(MMC_SDHCI_ADMA))
  106. static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  107. int *is_aligned, int trans_bytes)
  108. {
  109. unsigned char ctrl;
  110. void *buf;
  111. if (data->flags == MMC_DATA_READ)
  112. buf = data->dest;
  113. else
  114. buf = (void *)data->src;
  115. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  116. ctrl &= ~SDHCI_CTRL_DMA_MASK;
  117. if (host->flags & USE_ADMA64)
  118. ctrl |= SDHCI_CTRL_ADMA64;
  119. else if (host->flags & USE_ADMA)
  120. ctrl |= SDHCI_CTRL_ADMA32;
  121. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  122. if (host->flags & USE_SDMA &&
  123. (host->force_align_buffer ||
  124. (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR &&
  125. ((unsigned long)buf & 0x7) != 0x0))) {
  126. *is_aligned = 0;
  127. if (data->flags != MMC_DATA_READ)
  128. memcpy(host->align_buffer, buf, trans_bytes);
  129. buf = host->align_buffer;
  130. }
  131. host->start_addr = dma_map_single(buf, trans_bytes,
  132. mmc_get_dma_dir(data));
  133. if (host->flags & USE_SDMA) {
  134. sdhci_writel(host, host->start_addr, SDHCI_DMA_ADDRESS);
  135. } else if (host->flags & (USE_ADMA | USE_ADMA64)) {
  136. sdhci_prepare_adma_table(host, data);
  137. sdhci_writel(host, lower_32_bits(host->adma_addr),
  138. SDHCI_ADMA_ADDRESS);
  139. if (host->flags & USE_ADMA64)
  140. sdhci_writel(host, upper_32_bits(host->adma_addr),
  141. SDHCI_ADMA_ADDRESS_HI);
  142. }
  143. }
  144. #else
  145. static void sdhci_prepare_dma(struct sdhci_host *host, struct mmc_data *data,
  146. int *is_aligned, int trans_bytes)
  147. {}
  148. #endif
  149. static int sdhci_transfer_data(struct sdhci_host *host, struct mmc_data *data)
  150. {
  151. dma_addr_t start_addr = host->start_addr;
  152. unsigned int stat, rdy, mask, timeout, block = 0;
  153. bool transfer_done = false;
  154. timeout = 1000000;
  155. rdy = SDHCI_INT_SPACE_AVAIL | SDHCI_INT_DATA_AVAIL;
  156. mask = SDHCI_DATA_AVAILABLE | SDHCI_SPACE_AVAILABLE;
  157. do {
  158. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  159. if (stat & SDHCI_INT_ERROR) {
  160. pr_debug("%s: Error detected in status(0x%X)!\n",
  161. __func__, stat);
  162. return -EIO;
  163. }
  164. if (!transfer_done && (stat & rdy)) {
  165. if (!(sdhci_readl(host, SDHCI_PRESENT_STATE) & mask))
  166. continue;
  167. sdhci_writel(host, rdy, SDHCI_INT_STATUS);
  168. sdhci_transfer_pio(host, data);
  169. data->dest += data->blocksize;
  170. if (++block >= data->blocks) {
  171. /* Keep looping until the SDHCI_INT_DATA_END is
  172. * cleared, even if we finished sending all the
  173. * blocks.
  174. */
  175. transfer_done = true;
  176. continue;
  177. }
  178. }
  179. if ((host->flags & USE_DMA) && !transfer_done &&
  180. (stat & SDHCI_INT_DMA_END)) {
  181. sdhci_writel(host, SDHCI_INT_DMA_END, SDHCI_INT_STATUS);
  182. if (host->flags & USE_SDMA) {
  183. start_addr &=
  184. ~(SDHCI_DEFAULT_BOUNDARY_SIZE - 1);
  185. start_addr += SDHCI_DEFAULT_BOUNDARY_SIZE;
  186. sdhci_writel(host, start_addr,
  187. SDHCI_DMA_ADDRESS);
  188. }
  189. }
  190. if (timeout-- > 0)
  191. udelay(10);
  192. else {
  193. printf("%s: Transfer data timeout\n", __func__);
  194. return -ETIMEDOUT;
  195. }
  196. } while (!(stat & SDHCI_INT_DATA_END));
  197. dma_unmap_single(host->start_addr, data->blocks * data->blocksize,
  198. mmc_get_dma_dir(data));
  199. return 0;
  200. }
  201. /*
  202. * No command will be sent by driver if card is busy, so driver must wait
  203. * for card ready state.
  204. * Every time when card is busy after timeout then (last) timeout value will be
  205. * increased twice but only if it doesn't exceed global defined maximum.
  206. * Each function call will use last timeout value.
  207. */
  208. #define SDHCI_CMD_MAX_TIMEOUT 3200
  209. #define SDHCI_CMD_DEFAULT_TIMEOUT 100
  210. #define SDHCI_READ_STATUS_TIMEOUT 1000
  211. #ifdef CONFIG_DM_MMC
  212. static int sdhci_send_command(struct udevice *dev, struct mmc_cmd *cmd,
  213. struct mmc_data *data)
  214. {
  215. struct mmc *mmc = mmc_get_mmc_dev(dev);
  216. #else
  217. static int sdhci_send_command(struct mmc *mmc, struct mmc_cmd *cmd,
  218. struct mmc_data *data)
  219. {
  220. #endif
  221. struct sdhci_host *host = mmc->priv;
  222. unsigned int stat = 0;
  223. int ret = 0;
  224. int trans_bytes = 0, is_aligned = 1;
  225. u32 mask, flags, mode;
  226. unsigned int time = 0;
  227. int mmc_dev = mmc_get_blk_desc(mmc)->devnum;
  228. ulong start = get_timer(0);
  229. host->start_addr = 0;
  230. /* Timeout unit - ms */
  231. static unsigned int cmd_timeout = SDHCI_CMD_DEFAULT_TIMEOUT;
  232. mask = SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT;
  233. /* We shouldn't wait for data inihibit for stop commands, even
  234. though they might use busy signaling */
  235. if (cmd->cmdidx == MMC_CMD_STOP_TRANSMISSION ||
  236. ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  237. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data))
  238. mask &= ~SDHCI_DATA_INHIBIT;
  239. while (sdhci_readl(host, SDHCI_PRESENT_STATE) & mask) {
  240. if (time >= cmd_timeout) {
  241. printf("%s: MMC: %d busy ", __func__, mmc_dev);
  242. if (2 * cmd_timeout <= SDHCI_CMD_MAX_TIMEOUT) {
  243. cmd_timeout += cmd_timeout;
  244. printf("timeout increasing to: %u ms.\n",
  245. cmd_timeout);
  246. } else {
  247. puts("timeout.\n");
  248. return -ECOMM;
  249. }
  250. }
  251. time++;
  252. udelay(1000);
  253. }
  254. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  255. mask = SDHCI_INT_RESPONSE;
  256. if ((cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  257. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200) && !data)
  258. mask = SDHCI_INT_DATA_AVAIL;
  259. if (!(cmd->resp_type & MMC_RSP_PRESENT))
  260. flags = SDHCI_CMD_RESP_NONE;
  261. else if (cmd->resp_type & MMC_RSP_136)
  262. flags = SDHCI_CMD_RESP_LONG;
  263. else if (cmd->resp_type & MMC_RSP_BUSY) {
  264. flags = SDHCI_CMD_RESP_SHORT_BUSY;
  265. if (data)
  266. mask |= SDHCI_INT_DATA_END;
  267. } else
  268. flags = SDHCI_CMD_RESP_SHORT;
  269. if (cmd->resp_type & MMC_RSP_CRC)
  270. flags |= SDHCI_CMD_CRC;
  271. if (cmd->resp_type & MMC_RSP_OPCODE)
  272. flags |= SDHCI_CMD_INDEX;
  273. if (data || cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK ||
  274. cmd->cmdidx == MMC_CMD_SEND_TUNING_BLOCK_HS200)
  275. flags |= SDHCI_CMD_DATA;
  276. /* Set Transfer mode regarding to data flag */
  277. if (data) {
  278. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  279. mode = SDHCI_TRNS_BLK_CNT_EN;
  280. trans_bytes = data->blocks * data->blocksize;
  281. if (data->blocks > 1)
  282. mode |= SDHCI_TRNS_MULTI;
  283. if (data->flags == MMC_DATA_READ)
  284. mode |= SDHCI_TRNS_READ;
  285. if (host->flags & USE_DMA) {
  286. mode |= SDHCI_TRNS_DMA;
  287. sdhci_prepare_dma(host, data, &is_aligned, trans_bytes);
  288. }
  289. sdhci_writew(host, SDHCI_MAKE_BLKSZ(SDHCI_DEFAULT_BOUNDARY_ARG,
  290. data->blocksize),
  291. SDHCI_BLOCK_SIZE);
  292. sdhci_writew(host, data->blocks, SDHCI_BLOCK_COUNT);
  293. sdhci_writew(host, mode, SDHCI_TRANSFER_MODE);
  294. } else if (cmd->resp_type & MMC_RSP_BUSY) {
  295. sdhci_writeb(host, 0xe, SDHCI_TIMEOUT_CONTROL);
  296. }
  297. sdhci_writel(host, cmd->cmdarg, SDHCI_ARGUMENT);
  298. sdhci_writew(host, SDHCI_MAKE_CMD(cmd->cmdidx, flags), SDHCI_COMMAND);
  299. start = get_timer(0);
  300. do {
  301. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  302. if (stat & SDHCI_INT_ERROR)
  303. break;
  304. if (get_timer(start) >= SDHCI_READ_STATUS_TIMEOUT) {
  305. if (host->quirks & SDHCI_QUIRK_BROKEN_R1B) {
  306. return 0;
  307. } else {
  308. printf("%s: Timeout for status update!\n",
  309. __func__);
  310. return -ETIMEDOUT;
  311. }
  312. }
  313. } while ((stat & mask) != mask);
  314. if ((stat & (SDHCI_INT_ERROR | mask)) == mask) {
  315. sdhci_cmd_done(host, cmd);
  316. sdhci_writel(host, mask, SDHCI_INT_STATUS);
  317. } else
  318. ret = -1;
  319. if (!ret && data)
  320. ret = sdhci_transfer_data(host, data);
  321. if (host->quirks & SDHCI_QUIRK_WAIT_SEND_CMD)
  322. udelay(1000);
  323. stat = sdhci_readl(host, SDHCI_INT_STATUS);
  324. sdhci_writel(host, SDHCI_INT_ALL_MASK, SDHCI_INT_STATUS);
  325. if (!ret) {
  326. if ((host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) &&
  327. !is_aligned && (data->flags == MMC_DATA_READ))
  328. memcpy(data->dest, host->align_buffer, trans_bytes);
  329. return 0;
  330. }
  331. sdhci_reset(host, SDHCI_RESET_CMD);
  332. sdhci_reset(host, SDHCI_RESET_DATA);
  333. if (stat & SDHCI_INT_TIMEOUT)
  334. return -ETIMEDOUT;
  335. else
  336. return -ECOMM;
  337. }
  338. #if defined(CONFIG_DM_MMC) && defined(MMC_SUPPORTS_TUNING)
  339. static int sdhci_execute_tuning(struct udevice *dev, uint opcode)
  340. {
  341. int err;
  342. struct mmc *mmc = mmc_get_mmc_dev(dev);
  343. struct sdhci_host *host = mmc->priv;
  344. debug("%s\n", __func__);
  345. if (host->ops && host->ops->platform_execute_tuning) {
  346. err = host->ops->platform_execute_tuning(mmc, opcode);
  347. if (err)
  348. return err;
  349. return 0;
  350. }
  351. return 0;
  352. }
  353. #endif
  354. int sdhci_set_clock(struct mmc *mmc, unsigned int clock)
  355. {
  356. struct sdhci_host *host = mmc->priv;
  357. unsigned int div, clk = 0, timeout;
  358. /* Wait max 20 ms */
  359. timeout = 200;
  360. while (sdhci_readl(host, SDHCI_PRESENT_STATE) &
  361. (SDHCI_CMD_INHIBIT | SDHCI_DATA_INHIBIT)) {
  362. if (timeout == 0) {
  363. printf("%s: Timeout to wait cmd & data inhibit\n",
  364. __func__);
  365. return -EBUSY;
  366. }
  367. timeout--;
  368. udelay(100);
  369. }
  370. sdhci_writew(host, 0, SDHCI_CLOCK_CONTROL);
  371. if (clock == 0)
  372. return 0;
  373. if (host->ops && host->ops->set_delay)
  374. host->ops->set_delay(host);
  375. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  376. /*
  377. * Check if the Host Controller supports Programmable Clock
  378. * Mode.
  379. */
  380. if (host->clk_mul) {
  381. for (div = 1; div <= 1024; div++) {
  382. if ((host->max_clk / div) <= clock)
  383. break;
  384. }
  385. /*
  386. * Set Programmable Clock Mode in the Clock
  387. * Control register.
  388. */
  389. clk = SDHCI_PROG_CLOCK_MODE;
  390. div--;
  391. } else {
  392. /* Version 3.00 divisors must be a multiple of 2. */
  393. if (host->max_clk <= clock) {
  394. div = 1;
  395. } else {
  396. for (div = 2;
  397. div < SDHCI_MAX_DIV_SPEC_300;
  398. div += 2) {
  399. if ((host->max_clk / div) <= clock)
  400. break;
  401. }
  402. }
  403. div >>= 1;
  404. }
  405. } else {
  406. /* Version 2.00 divisors must be a power of 2. */
  407. for (div = 1; div < SDHCI_MAX_DIV_SPEC_200; div *= 2) {
  408. if ((host->max_clk / div) <= clock)
  409. break;
  410. }
  411. div >>= 1;
  412. }
  413. if (host->ops && host->ops->set_clock)
  414. host->ops->set_clock(host, div);
  415. clk |= (div & SDHCI_DIV_MASK) << SDHCI_DIVIDER_SHIFT;
  416. clk |= ((div & SDHCI_DIV_HI_MASK) >> SDHCI_DIV_MASK_LEN)
  417. << SDHCI_DIVIDER_HI_SHIFT;
  418. clk |= SDHCI_CLOCK_INT_EN;
  419. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  420. /* Wait max 20 ms */
  421. timeout = 20;
  422. while (!((clk = sdhci_readw(host, SDHCI_CLOCK_CONTROL))
  423. & SDHCI_CLOCK_INT_STABLE)) {
  424. if (timeout == 0) {
  425. printf("%s: Internal clock never stabilised.\n",
  426. __func__);
  427. return -EBUSY;
  428. }
  429. timeout--;
  430. udelay(1000);
  431. }
  432. clk |= SDHCI_CLOCK_CARD_EN;
  433. sdhci_writew(host, clk, SDHCI_CLOCK_CONTROL);
  434. return 0;
  435. }
  436. static void sdhci_set_power(struct sdhci_host *host, unsigned short power)
  437. {
  438. u8 pwr = 0;
  439. if (power != (unsigned short)-1) {
  440. switch (1 << power) {
  441. case MMC_VDD_165_195:
  442. pwr = SDHCI_POWER_180;
  443. break;
  444. case MMC_VDD_29_30:
  445. case MMC_VDD_30_31:
  446. pwr = SDHCI_POWER_300;
  447. break;
  448. case MMC_VDD_32_33:
  449. case MMC_VDD_33_34:
  450. pwr = SDHCI_POWER_330;
  451. break;
  452. }
  453. }
  454. if (pwr == 0) {
  455. sdhci_writeb(host, 0, SDHCI_POWER_CONTROL);
  456. return;
  457. }
  458. pwr |= SDHCI_POWER_ON;
  459. sdhci_writeb(host, pwr, SDHCI_POWER_CONTROL);
  460. }
  461. void sdhci_set_uhs_timing(struct sdhci_host *host)
  462. {
  463. struct mmc *mmc = host->mmc;
  464. u32 reg;
  465. reg = sdhci_readw(host, SDHCI_HOST_CONTROL2);
  466. reg &= ~SDHCI_CTRL_UHS_MASK;
  467. switch (mmc->selected_mode) {
  468. case UHS_SDR50:
  469. case MMC_HS_52:
  470. reg |= SDHCI_CTRL_UHS_SDR50;
  471. break;
  472. case UHS_DDR50:
  473. case MMC_DDR_52:
  474. reg |= SDHCI_CTRL_UHS_DDR50;
  475. break;
  476. case UHS_SDR104:
  477. case MMC_HS_200:
  478. reg |= SDHCI_CTRL_UHS_SDR104;
  479. break;
  480. default:
  481. reg |= SDHCI_CTRL_UHS_SDR12;
  482. }
  483. sdhci_writew(host, reg, SDHCI_HOST_CONTROL2);
  484. }
  485. #ifdef CONFIG_DM_MMC
  486. static int sdhci_set_ios(struct udevice *dev)
  487. {
  488. struct mmc *mmc = mmc_get_mmc_dev(dev);
  489. #else
  490. static int sdhci_set_ios(struct mmc *mmc)
  491. {
  492. #endif
  493. u32 ctrl;
  494. struct sdhci_host *host = mmc->priv;
  495. if (host->ops && host->ops->set_control_reg)
  496. host->ops->set_control_reg(host);
  497. if (mmc->clock != host->clock)
  498. sdhci_set_clock(mmc, mmc->clock);
  499. if (mmc->clk_disable)
  500. sdhci_set_clock(mmc, 0);
  501. /* Set bus width */
  502. ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL);
  503. if (mmc->bus_width == 8) {
  504. ctrl &= ~SDHCI_CTRL_4BITBUS;
  505. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  506. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  507. ctrl |= SDHCI_CTRL_8BITBUS;
  508. } else {
  509. if ((SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) ||
  510. (host->quirks & SDHCI_QUIRK_USE_WIDE8))
  511. ctrl &= ~SDHCI_CTRL_8BITBUS;
  512. if (mmc->bus_width == 4)
  513. ctrl |= SDHCI_CTRL_4BITBUS;
  514. else
  515. ctrl &= ~SDHCI_CTRL_4BITBUS;
  516. }
  517. if (mmc->clock > 26000000)
  518. ctrl |= SDHCI_CTRL_HISPD;
  519. else
  520. ctrl &= ~SDHCI_CTRL_HISPD;
  521. if ((host->quirks & SDHCI_QUIRK_NO_HISPD_BIT) ||
  522. (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE))
  523. ctrl &= ~SDHCI_CTRL_HISPD;
  524. sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL);
  525. /* If available, call the driver specific "post" set_ios() function */
  526. if (host->ops && host->ops->set_ios_post)
  527. return host->ops->set_ios_post(host);
  528. return 0;
  529. }
  530. static int sdhci_init(struct mmc *mmc)
  531. {
  532. struct sdhci_host *host = mmc->priv;
  533. #if CONFIG_IS_ENABLED(DM_MMC) && CONFIG_IS_ENABLED(DM_GPIO)
  534. struct udevice *dev = mmc->dev;
  535. gpio_request_by_name(dev, "cd-gpios", 0,
  536. &host->cd_gpio, GPIOD_IS_IN);
  537. #endif
  538. sdhci_reset(host, SDHCI_RESET_ALL);
  539. #if defined(CONFIG_FIXED_SDHCI_ALIGNED_BUFFER)
  540. host->align_buffer = (void *)CONFIG_FIXED_SDHCI_ALIGNED_BUFFER;
  541. /*
  542. * Always use this bounce-buffer when CONFIG_FIXED_SDHCI_ALIGNED_BUFFER
  543. * is defined.
  544. */
  545. host->force_align_buffer = true;
  546. #else
  547. if (host->quirks & SDHCI_QUIRK_32BIT_DMA_ADDR) {
  548. host->align_buffer = memalign(8, 512 * 1024);
  549. if (!host->align_buffer) {
  550. printf("%s: Aligned buffer alloc failed!!!\n",
  551. __func__);
  552. return -ENOMEM;
  553. }
  554. }
  555. #endif
  556. sdhci_set_power(host, fls(mmc->cfg->voltages) - 1);
  557. if (host->ops && host->ops->get_cd)
  558. host->ops->get_cd(host);
  559. /* Enable only interrupts served by the SD controller */
  560. sdhci_writel(host, SDHCI_INT_DATA_MASK | SDHCI_INT_CMD_MASK,
  561. SDHCI_INT_ENABLE);
  562. /* Mask all sdhci interrupt sources */
  563. sdhci_writel(host, 0x0, SDHCI_SIGNAL_ENABLE);
  564. return 0;
  565. }
  566. #ifdef CONFIG_DM_MMC
  567. int sdhci_probe(struct udevice *dev)
  568. {
  569. struct mmc *mmc = mmc_get_mmc_dev(dev);
  570. return sdhci_init(mmc);
  571. }
  572. static int sdhci_deferred_probe(struct udevice *dev)
  573. {
  574. int err;
  575. struct mmc *mmc = mmc_get_mmc_dev(dev);
  576. struct sdhci_host *host = mmc->priv;
  577. if (host->ops && host->ops->deferred_probe) {
  578. err = host->ops->deferred_probe(host);
  579. if (err)
  580. return err;
  581. }
  582. return 0;
  583. }
  584. static int sdhci_get_cd(struct udevice *dev)
  585. {
  586. struct mmc *mmc = mmc_get_mmc_dev(dev);
  587. struct sdhci_host *host = mmc->priv;
  588. int value;
  589. /* If nonremovable, assume that the card is always present. */
  590. if (mmc->cfg->host_caps & MMC_CAP_NONREMOVABLE)
  591. return 1;
  592. /* If polling, assume that the card is always present. */
  593. if (mmc->cfg->host_caps & MMC_CAP_NEEDS_POLL)
  594. return 1;
  595. #if CONFIG_IS_ENABLED(DM_GPIO)
  596. value = dm_gpio_get_value(&host->cd_gpio);
  597. if (value >= 0) {
  598. if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
  599. return !value;
  600. else
  601. return value;
  602. }
  603. #endif
  604. value = !!(sdhci_readl(host, SDHCI_PRESENT_STATE) &
  605. SDHCI_CARD_PRESENT);
  606. if (mmc->cfg->host_caps & MMC_CAP_CD_ACTIVE_HIGH)
  607. return !value;
  608. else
  609. return value;
  610. }
  611. const struct dm_mmc_ops sdhci_ops = {
  612. .send_cmd = sdhci_send_command,
  613. .set_ios = sdhci_set_ios,
  614. .get_cd = sdhci_get_cd,
  615. .deferred_probe = sdhci_deferred_probe,
  616. #ifdef MMC_SUPPORTS_TUNING
  617. .execute_tuning = sdhci_execute_tuning,
  618. #endif
  619. };
  620. #else
  621. static const struct mmc_ops sdhci_ops = {
  622. .send_cmd = sdhci_send_command,
  623. .set_ios = sdhci_set_ios,
  624. .init = sdhci_init,
  625. };
  626. #endif
  627. int sdhci_setup_cfg(struct mmc_config *cfg, struct sdhci_host *host,
  628. u32 f_max, u32 f_min)
  629. {
  630. u32 caps, caps_1 = 0;
  631. #if CONFIG_IS_ENABLED(DM_MMC)
  632. u64 dt_caps, dt_caps_mask;
  633. dt_caps_mask = dev_read_u64_default(host->mmc->dev,
  634. "sdhci-caps-mask", 0);
  635. dt_caps = dev_read_u64_default(host->mmc->dev,
  636. "sdhci-caps", 0);
  637. caps = ~(u32)dt_caps_mask &
  638. sdhci_readl(host, SDHCI_CAPABILITIES);
  639. caps |= (u32)dt_caps;
  640. #else
  641. caps = sdhci_readl(host, SDHCI_CAPABILITIES);
  642. #endif
  643. debug("%s, caps: 0x%x\n", __func__, caps);
  644. #ifdef CONFIG_MMC_SDHCI_SDMA
  645. if (!(caps & SDHCI_CAN_DO_SDMA)) {
  646. printf("%s: Your controller doesn't support SDMA!!\n",
  647. __func__);
  648. return -EINVAL;
  649. }
  650. host->flags |= USE_SDMA;
  651. #endif
  652. #if CONFIG_IS_ENABLED(MMC_SDHCI_ADMA)
  653. if (!(caps & SDHCI_CAN_DO_ADMA2)) {
  654. printf("%s: Your controller doesn't support SDMA!!\n",
  655. __func__);
  656. return -EINVAL;
  657. }
  658. host->adma_desc_table = memalign(ARCH_DMA_MINALIGN, ADMA_TABLE_SZ);
  659. host->adma_addr = (dma_addr_t)host->adma_desc_table;
  660. #ifdef CONFIG_DMA_ADDR_T_64BIT
  661. host->flags |= USE_ADMA64;
  662. #else
  663. host->flags |= USE_ADMA;
  664. #endif
  665. #endif
  666. if (host->quirks & SDHCI_QUIRK_REG32_RW)
  667. host->version =
  668. sdhci_readl(host, SDHCI_HOST_VERSION - 2) >> 16;
  669. else
  670. host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
  671. cfg->name = host->name;
  672. #ifndef CONFIG_DM_MMC
  673. cfg->ops = &sdhci_ops;
  674. #endif
  675. /* Check whether the clock multiplier is supported or not */
  676. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  677. #if CONFIG_IS_ENABLED(DM_MMC)
  678. caps_1 = ~(u32)(dt_caps_mask >> 32) &
  679. sdhci_readl(host, SDHCI_CAPABILITIES_1);
  680. caps_1 |= (u32)(dt_caps >> 32);
  681. #else
  682. caps_1 = sdhci_readl(host, SDHCI_CAPABILITIES_1);
  683. #endif
  684. debug("%s, caps_1: 0x%x\n", __func__, caps_1);
  685. host->clk_mul = (caps_1 & SDHCI_CLOCK_MUL_MASK) >>
  686. SDHCI_CLOCK_MUL_SHIFT;
  687. }
  688. if (host->max_clk == 0) {
  689. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  690. host->max_clk = (caps & SDHCI_CLOCK_V3_BASE_MASK) >>
  691. SDHCI_CLOCK_BASE_SHIFT;
  692. else
  693. host->max_clk = (caps & SDHCI_CLOCK_BASE_MASK) >>
  694. SDHCI_CLOCK_BASE_SHIFT;
  695. host->max_clk *= 1000000;
  696. if (host->clk_mul)
  697. host->max_clk *= host->clk_mul;
  698. }
  699. if (host->max_clk == 0) {
  700. printf("%s: Hardware doesn't specify base clock frequency\n",
  701. __func__);
  702. return -EINVAL;
  703. }
  704. if (f_max && (f_max < host->max_clk))
  705. cfg->f_max = f_max;
  706. else
  707. cfg->f_max = host->max_clk;
  708. if (f_min)
  709. cfg->f_min = f_min;
  710. else {
  711. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300)
  712. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_300;
  713. else
  714. cfg->f_min = cfg->f_max / SDHCI_MAX_DIV_SPEC_200;
  715. }
  716. cfg->voltages = 0;
  717. if (caps & SDHCI_CAN_VDD_330)
  718. cfg->voltages |= MMC_VDD_32_33 | MMC_VDD_33_34;
  719. if (caps & SDHCI_CAN_VDD_300)
  720. cfg->voltages |= MMC_VDD_29_30 | MMC_VDD_30_31;
  721. if (caps & SDHCI_CAN_VDD_180)
  722. cfg->voltages |= MMC_VDD_165_195;
  723. if (host->quirks & SDHCI_QUIRK_BROKEN_VOLTAGE)
  724. cfg->voltages |= host->voltages;
  725. cfg->host_caps |= MMC_MODE_HS | MMC_MODE_HS_52MHz | MMC_MODE_4BIT;
  726. /* Since Host Controller Version3.0 */
  727. if (SDHCI_GET_VERSION(host) >= SDHCI_SPEC_300) {
  728. if (!(caps & SDHCI_CAN_DO_8BIT))
  729. cfg->host_caps &= ~MMC_MODE_8BIT;
  730. }
  731. if (host->quirks & SDHCI_QUIRK_BROKEN_HISPD_MODE) {
  732. cfg->host_caps &= ~MMC_MODE_HS;
  733. cfg->host_caps &= ~MMC_MODE_HS_52MHz;
  734. }
  735. if (!(cfg->voltages & MMC_VDD_165_195))
  736. caps_1 &= ~(SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  737. SDHCI_SUPPORT_DDR50);
  738. if (caps_1 & (SDHCI_SUPPORT_SDR104 | SDHCI_SUPPORT_SDR50 |
  739. SDHCI_SUPPORT_DDR50))
  740. cfg->host_caps |= MMC_CAP(UHS_SDR12) | MMC_CAP(UHS_SDR25);
  741. if (caps_1 & SDHCI_SUPPORT_SDR104) {
  742. cfg->host_caps |= MMC_CAP(UHS_SDR104) | MMC_CAP(UHS_SDR50);
  743. /*
  744. * SD3.0: SDR104 is supported so (for eMMC) the caps2
  745. * field can be promoted to support HS200.
  746. */
  747. cfg->host_caps |= MMC_CAP(MMC_HS_200);
  748. } else if (caps_1 & SDHCI_SUPPORT_SDR50) {
  749. cfg->host_caps |= MMC_CAP(UHS_SDR50);
  750. }
  751. if (caps_1 & SDHCI_SUPPORT_DDR50)
  752. cfg->host_caps |= MMC_CAP(UHS_DDR50);
  753. if (host->host_caps)
  754. cfg->host_caps |= host->host_caps;
  755. cfg->b_max = CONFIG_SYS_MMC_MAX_BLK_COUNT;
  756. return 0;
  757. }
  758. #ifdef CONFIG_BLK
  759. int sdhci_bind(struct udevice *dev, struct mmc *mmc, struct mmc_config *cfg)
  760. {
  761. return mmc_bind(dev, mmc, cfg);
  762. }
  763. #else
  764. int add_sdhci(struct sdhci_host *host, u32 f_max, u32 f_min)
  765. {
  766. int ret;
  767. ret = sdhci_setup_cfg(&host->cfg, host, f_max, f_min);
  768. if (ret)
  769. return ret;
  770. host->mmc = mmc_create(&host->cfg, host);
  771. if (host->mmc == NULL) {
  772. printf("%s: mmc create fail!\n", __func__);
  773. return -ENOMEM;
  774. }
  775. return 0;
  776. }
  777. #endif