zynqmp-zcu111-revA.dts 12 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417418419420421422423424425426427428429430431432433434435436437438439440441442443444445446447448449450451452453454455456457458459460461462463464465466467468469470471472473474475476477478479480481482483484485486487488489490491492493494495496497498499500501502503504505506507508509510511512513514515516517518519520521522523524525526527528529530531532533534535536537538539540541542543544545546547548549550551552553554555556557558559560561562563564565566567568569570571572573574575576577578579580581582583584585586587588589590591592593
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * dts file for Xilinx ZynqMP ZCU111
  4. *
  5. * (C) Copyright 2017 - 2020, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk-ccf.dtsi"
  12. #include <dt-bindings/input/input.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. #include <dt-bindings/phy/phy.h>
  15. / {
  16. model = "ZynqMP ZCU111 RevA";
  17. compatible = "xlnx,zynqmp-zcu111-revA", "xlnx,zynqmp-zcu111", "xlnx,zynqmp";
  18. aliases {
  19. ethernet0 = &gem3;
  20. gpio0 = &gpio;
  21. i2c0 = &i2c0;
  22. i2c1 = &i2c1;
  23. mmc0 = &sdhci1;
  24. rtc0 = &rtc;
  25. serial0 = &uart0;
  26. serial1 = &dcc;
  27. spi0 = &qspi;
  28. usb0 = &usb0;
  29. };
  30. chosen {
  31. bootargs = "earlycon";
  32. stdout-path = "serial0:115200n8";
  33. xlnx,eeprom = &eeprom;
  34. };
  35. memory@0 {
  36. device_type = "memory";
  37. reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  38. /* Another 4GB connected to PL */
  39. };
  40. gpio-keys {
  41. compatible = "gpio-keys";
  42. autorepeat;
  43. sw19 {
  44. label = "sw19";
  45. gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  46. linux,code = <KEY_DOWN>;
  47. wakeup-source;
  48. autorepeat;
  49. };
  50. };
  51. leds {
  52. compatible = "gpio-leds";
  53. heartbeat-led {
  54. label = "heartbeat";
  55. gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  56. linux,default-trigger = "heartbeat";
  57. };
  58. };
  59. ina226-u67 {
  60. compatible = "iio-hwmon";
  61. io-channels = <&u67 0>, <&u67 1>, <&u67 2>, <&u67 3>;
  62. };
  63. ina226-u59 {
  64. compatible = "iio-hwmon";
  65. io-channels = <&u59 0>, <&u59 1>, <&u59 2>, <&u59 3>;
  66. };
  67. ina226-u61 {
  68. compatible = "iio-hwmon";
  69. io-channels = <&u61 0>, <&u61 1>, <&u61 2>, <&u61 3>;
  70. };
  71. ina226-u60 {
  72. compatible = "iio-hwmon";
  73. io-channels = <&u60 0>, <&u60 1>, <&u60 2>, <&u60 3>;
  74. };
  75. ina226-u64 {
  76. compatible = "iio-hwmon";
  77. io-channels = <&u64 0>, <&u64 1>, <&u64 2>, <&u64 3>;
  78. };
  79. ina226-u69 {
  80. compatible = "iio-hwmon";
  81. io-channels = <&u69 0>, <&u69 1>, <&u69 2>, <&u69 3>;
  82. };
  83. ina226-u66 {
  84. compatible = "iio-hwmon";
  85. io-channels = <&u66 0>, <&u66 1>, <&u66 2>, <&u66 3>;
  86. };
  87. ina226-u65 {
  88. compatible = "iio-hwmon";
  89. io-channels = <&u65 0>, <&u65 1>, <&u65 2>, <&u65 3>;
  90. };
  91. ina226-u63 {
  92. compatible = "iio-hwmon";
  93. io-channels = <&u63 0>, <&u63 1>, <&u63 2>, <&u63 3>;
  94. };
  95. ina226-u3 {
  96. compatible = "iio-hwmon";
  97. io-channels = <&u3 0>, <&u3 1>, <&u3 2>, <&u3 3>;
  98. };
  99. ina226-u71 {
  100. compatible = "iio-hwmon";
  101. io-channels = <&u71 0>, <&u71 1>, <&u71 2>, <&u71 3>;
  102. };
  103. ina226-u77 {
  104. compatible = "iio-hwmon";
  105. io-channels = <&u77 0>, <&u77 1>, <&u77 2>, <&u77 3>;
  106. };
  107. ina226-u73 {
  108. compatible = "iio-hwmon";
  109. io-channels = <&u73 0>, <&u73 1>, <&u73 2>, <&u73 3>;
  110. };
  111. ina226-u79 {
  112. compatible = "iio-hwmon";
  113. io-channels = <&u79 0>, <&u79 1>, <&u79 2>, <&u79 3>;
  114. };
  115. };
  116. &dcc {
  117. status = "okay";
  118. };
  119. &fpd_dma_chan1 {
  120. status = "okay";
  121. };
  122. &fpd_dma_chan2 {
  123. status = "okay";
  124. };
  125. &fpd_dma_chan3 {
  126. status = "okay";
  127. };
  128. &fpd_dma_chan4 {
  129. status = "okay";
  130. };
  131. &fpd_dma_chan5 {
  132. status = "okay";
  133. };
  134. &fpd_dma_chan6 {
  135. status = "okay";
  136. };
  137. &fpd_dma_chan7 {
  138. status = "okay";
  139. };
  140. &fpd_dma_chan8 {
  141. status = "okay";
  142. };
  143. &gem3 {
  144. status = "okay";
  145. phy-handle = <&phy0>;
  146. phy-mode = "rgmii-id";
  147. phy0: ethernet-phy@c {
  148. reg = <0xc>;
  149. ti,rx-internal-delay = <0x8>;
  150. ti,tx-internal-delay = <0xa>;
  151. ti,fifo-depth = <0x1>;
  152. ti,dp83867-rxctrl-strap-quirk;
  153. };
  154. };
  155. &gpio {
  156. status = "okay";
  157. };
  158. &gpu {
  159. status = "okay";
  160. };
  161. &i2c0 {
  162. status = "okay";
  163. clock-frequency = <400000>;
  164. tca6416_u22: gpio@20 {
  165. compatible = "ti,tca6416";
  166. reg = <0x20>;
  167. gpio-controller; /* interrupt not connected */
  168. #gpio-cells = <2>;
  169. /*
  170. * IRQ not connected
  171. * Lines:
  172. * 0 - MAX6643_OT_B
  173. * 1 - MAX6643_FANFAIL_B
  174. * 2 - MIO26_PMU_INPUT_LS
  175. * 4 - SFP_SI5382_INT_ALM
  176. * 5 - IIC_MUX_RESET_B
  177. * 6 - GEM3_EXP_RESET_B
  178. * 10 - FMCP_HSPC_PRSNT_M2C_B
  179. * 11 - CLK_SPI_MUX_SEL0
  180. * 12 - CLK_SPI_MUX_SEL1
  181. * 16 - IRPS5401_ALERT_B
  182. * 17 - INA226_PMBUS_ALERT
  183. * 3, 7, 13-15 - not connected
  184. */
  185. };
  186. i2c-mux@75 { /* u23 */
  187. compatible = "nxp,pca9544";
  188. #address-cells = <1>;
  189. #size-cells = <0>;
  190. reg = <0x75>;
  191. i2c@0 {
  192. #address-cells = <1>;
  193. #size-cells = <0>;
  194. reg = <0>;
  195. /* PS_PMBUS */
  196. /* PMBUS_ALERT done via pca9544 */
  197. u67: ina226@40 { /* u67 */
  198. compatible = "ti,ina226";
  199. #io-channel-cells = <1>;
  200. label = "ina226-u67";
  201. reg = <0x40>;
  202. shunt-resistor = <2000>;
  203. };
  204. u59: ina226@41 { /* u59 */
  205. compatible = "ti,ina226";
  206. #io-channel-cells = <1>;
  207. label = "ina226-u59";
  208. reg = <0x41>;
  209. shunt-resistor = <5000>;
  210. };
  211. u61: ina226@42 { /* u61 */
  212. compatible = "ti,ina226";
  213. #io-channel-cells = <1>;
  214. label = "ina226-u61";
  215. reg = <0x42>;
  216. shunt-resistor = <5000>;
  217. };
  218. u60: ina226@43 { /* u60 */
  219. compatible = "ti,ina226";
  220. #io-channel-cells = <1>;
  221. label = "ina226-u60";
  222. reg = <0x43>;
  223. shunt-resistor = <5000>;
  224. };
  225. u64: ina226@45 { /* u64 */
  226. compatible = "ti,ina226";
  227. #io-channel-cells = <1>;
  228. label = "ina226-u64";
  229. reg = <0x45>;
  230. shunt-resistor = <5000>;
  231. };
  232. u69: ina226@46 { /* u69 */
  233. compatible = "ti,ina226";
  234. #io-channel-cells = <1>;
  235. label = "ina226-u69";
  236. reg = <0x46>;
  237. shunt-resistor = <2000>;
  238. };
  239. u66: ina226@47 { /* u66 */
  240. compatible = "ti,ina226";
  241. #io-channel-cells = <1>;
  242. label = "ina226-u66";
  243. reg = <0x47>;
  244. shunt-resistor = <5000>;
  245. };
  246. u65: ina226@48 { /* u65 */
  247. compatible = "ti,ina226";
  248. #io-channel-cells = <1>;
  249. label = "ina226-u65";
  250. reg = <0x48>;
  251. shunt-resistor = <5000>;
  252. };
  253. u63: ina226@49 { /* u63 */
  254. compatible = "ti,ina226";
  255. #io-channel-cells = <1>;
  256. label = "ina226-u63";
  257. reg = <0x49>;
  258. shunt-resistor = <5000>;
  259. };
  260. u3: ina226@4a { /* u3 */
  261. compatible = "ti,ina226";
  262. #io-channel-cells = <1>;
  263. label = "ina226-u3";
  264. reg = <0x4a>;
  265. shunt-resistor = <5000>;
  266. };
  267. u71: ina226@4b { /* u71 */
  268. compatible = "ti,ina226";
  269. #io-channel-cells = <1>;
  270. label = "ina226-u71";
  271. reg = <0x4b>;
  272. shunt-resistor = <5000>;
  273. };
  274. u77: ina226@4c { /* u77 */
  275. compatible = "ti,ina226";
  276. #io-channel-cells = <1>;
  277. label = "ina226-u77";
  278. reg = <0x4c>;
  279. shunt-resistor = <5000>;
  280. };
  281. u73: ina226@4d { /* u73 */
  282. compatible = "ti,ina226";
  283. #io-channel-cells = <1>;
  284. label = "ina226-u73";
  285. reg = <0x4d>;
  286. shunt-resistor = <5000>;
  287. };
  288. u79: ina226@4e { /* u79 */
  289. compatible = "ti,ina226";
  290. #io-channel-cells = <1>;
  291. label = "ina226-u79";
  292. reg = <0x4e>;
  293. shunt-resistor = <5000>;
  294. };
  295. };
  296. i2c@1 {
  297. #address-cells = <1>;
  298. #size-cells = <0>;
  299. reg = <1>;
  300. /* NC */
  301. };
  302. i2c@2 {
  303. #address-cells = <1>;
  304. #size-cells = <0>;
  305. reg = <2>;
  306. irps5401_43: irps5401@43 { /* IRPS5401 - u53 check these */
  307. compatible = "infineon,irps5401";
  308. reg = <0x43>;
  309. };
  310. irps5401_44: irps5401@44 { /* IRPS5401 - u55 */
  311. compatible = "infineon,irps5401";
  312. reg = <0x44>;
  313. };
  314. irps5401_45: irps5401@45 { /* IRPS5401 - u57 */
  315. compatible = "infineon,irps5401";
  316. reg = <0x45>;
  317. };
  318. /* u68 IR38064 +0 */
  319. /* u70 IR38060 +1 */
  320. /* u74 IR38060 +2 */
  321. /* u75 IR38060 +6 */
  322. /* J19 header too */
  323. };
  324. i2c@3 {
  325. #address-cells = <1>;
  326. #size-cells = <0>;
  327. reg = <3>;
  328. /* SYSMON */
  329. };
  330. };
  331. };
  332. &i2c1 {
  333. status = "okay";
  334. clock-frequency = <400000>;
  335. i2c-mux@74 { /* u26 */
  336. compatible = "nxp,pca9548";
  337. #address-cells = <1>;
  338. #size-cells = <0>;
  339. reg = <0x74>;
  340. i2c@0 {
  341. #address-cells = <1>;
  342. #size-cells = <0>;
  343. reg = <0>;
  344. /*
  345. * IIC_EEPROM 1kB memory which uses 256B blocks
  346. * where every block has different address.
  347. * 0 - 256B address 0x54
  348. * 256B - 512B address 0x55
  349. * 512B - 768B address 0x56
  350. * 768B - 1024B address 0x57
  351. */
  352. eeprom: eeprom@54 { /* u88 */
  353. compatible = "atmel,24c08";
  354. reg = <0x54>;
  355. };
  356. };
  357. i2c@1 {
  358. #address-cells = <1>;
  359. #size-cells = <0>;
  360. reg = <1>;
  361. si5341: clock-generator@36 { /* SI5341 - u46 */
  362. compatible = "si5341";
  363. reg = <0x36>;
  364. };
  365. };
  366. i2c@2 {
  367. #address-cells = <1>;
  368. #size-cells = <0>;
  369. reg = <2>;
  370. si570_1: clock-generator@5d { /* USER SI570 - u47 */
  371. #clock-cells = <0>;
  372. compatible = "silabs,si570";
  373. reg = <0x5d>;
  374. temperature-stability = <50>;
  375. factory-fout = <300000000>;
  376. clock-frequency = <300000000>;
  377. clock-output-names = "si570_user";
  378. };
  379. };
  380. i2c@3 {
  381. #address-cells = <1>;
  382. #size-cells = <0>;
  383. reg = <3>;
  384. si570_2: clock-generator@5d { /* USER MGT SI570 - u49 */
  385. #clock-cells = <0>;
  386. compatible = "silabs,si570";
  387. reg = <0x5d>;
  388. temperature-stability = <50>;
  389. factory-fout = <156250000>;
  390. clock-frequency = <156250000>;
  391. clock-output-names = "si570_mgt";
  392. };
  393. };
  394. i2c@4 {
  395. #address-cells = <1>;
  396. #size-cells = <0>;
  397. reg = <4>;
  398. si5328: clock-generator@69 { /* SI5328 - u48 */
  399. compatible = "silabs,si5328";
  400. reg = <0x69>;
  401. };
  402. };
  403. i2c@5 {
  404. #address-cells = <1>;
  405. #size-cells = <0>;
  406. reg = <5>;
  407. sc18is603@2f { /* sc18is602 - u93 */
  408. compatible = "nxp,sc18is603";
  409. reg = <0x2f>;
  410. /* 4 gpios for CS not handled by driver */
  411. /*
  412. * USB2ANY cable or
  413. * LMK04208 - u90 or
  414. * LMX2594 - u102 or
  415. * LMX2594 - u103 or
  416. * LMX2594 - u104
  417. */
  418. };
  419. };
  420. i2c@6 {
  421. #address-cells = <1>;
  422. #size-cells = <0>;
  423. reg = <6>;
  424. /* FMC connector */
  425. };
  426. /* 7 NC */
  427. };
  428. i2c-mux@75 {
  429. compatible = "nxp,pca9548"; /* u27 */
  430. #address-cells = <1>;
  431. #size-cells = <0>;
  432. reg = <0x75>;
  433. i2c@0 {
  434. #address-cells = <1>;
  435. #size-cells = <0>;
  436. reg = <0>;
  437. /* FMCP_HSPC_IIC */
  438. };
  439. i2c@1 {
  440. #address-cells = <1>;
  441. #size-cells = <0>;
  442. reg = <1>;
  443. /* NC */
  444. };
  445. i2c@2 {
  446. #address-cells = <1>;
  447. #size-cells = <0>;
  448. reg = <2>;
  449. /* SYSMON */
  450. };
  451. i2c@3 {
  452. #address-cells = <1>;
  453. #size-cells = <0>;
  454. reg = <3>;
  455. /* DDR4 SODIMM */
  456. };
  457. i2c@4 {
  458. #address-cells = <1>;
  459. #size-cells = <0>;
  460. reg = <4>;
  461. /* SFP3 */
  462. };
  463. i2c@5 {
  464. #address-cells = <1>;
  465. #size-cells = <0>;
  466. reg = <5>;
  467. /* SFP2 */
  468. };
  469. i2c@6 {
  470. #address-cells = <1>;
  471. #size-cells = <0>;
  472. reg = <6>;
  473. /* SFP1 */
  474. };
  475. i2c@7 {
  476. #address-cells = <1>;
  477. #size-cells = <0>;
  478. reg = <7>;
  479. /* SFP0 */
  480. };
  481. };
  482. };
  483. &qspi {
  484. status = "okay";
  485. is-dual = <1>;
  486. flash@0 {
  487. compatible = "m25p80", "jedec,spi-nor"; /* 32MB */
  488. #address-cells = <1>;
  489. #size-cells = <1>;
  490. reg = <0x0>;
  491. spi-tx-bus-width = <1>;
  492. spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  493. spi-max-frequency = <108000000>; /* Based on DC1 spec */
  494. partition@0 { /* for testing purpose */
  495. label = "qspi-fsbl-uboot";
  496. reg = <0x0 0x100000>;
  497. };
  498. partition@100000 { /* for testing purpose */
  499. label = "qspi-linux";
  500. reg = <0x100000 0x500000>;
  501. };
  502. partition@600000 { /* for testing purpose */
  503. label = "qspi-device-tree";
  504. reg = <0x600000 0x20000>;
  505. };
  506. partition@620000 { /* for testing purpose */
  507. label = "qspi-rootfs";
  508. reg = <0x620000 0x5E0000>;
  509. };
  510. };
  511. };
  512. &rtc {
  513. status = "okay";
  514. };
  515. &sata {
  516. status = "okay";
  517. /* SATA OOB timing settings */
  518. ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  519. ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  520. ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  521. ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  522. ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  523. ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  524. ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  525. ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  526. phy-names = "sata-phy";
  527. phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
  528. };
  529. /* SD1 with level shifter */
  530. &sdhci1 {
  531. status = "okay";
  532. disable-wp;
  533. /*
  534. * This property should be removed for supporting UHS mode
  535. */
  536. no-1-8-v;
  537. xlnx,mio_bank = <1>;
  538. };
  539. &serdes {
  540. status = "okay";
  541. };
  542. &uart0 {
  543. status = "okay";
  544. };
  545. /* ULPI SMSC USB3320 */
  546. &usb0 {
  547. status = "okay";
  548. };
  549. &dwc3_0 {
  550. status = "okay";
  551. dr_mode = "host";
  552. snps,usb3_lpm_capable;
  553. phy-names = "usb3-phy";
  554. phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
  555. };