123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309 |
- // SPDX-License-Identifier: GPL-2.0+
- /*
- * dts file for Xilinx ZynqMP ZCU104
- *
- * (C) Copyright 2017 - 2020, Xilinx, Inc.
- *
- * Michal Simek <michal.simek@xilinx.com>
- */
- /dts-v1/;
- #include "zynqmp.dtsi"
- #include "zynqmp-clk-ccf.dtsi"
- #include <dt-bindings/gpio/gpio.h>
- #include <dt-bindings/phy/phy.h>
- / {
- model = "ZynqMP ZCU104 RevC";
- compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
- aliases {
- ethernet0 = &gem3;
- gpio0 = &gpio;
- i2c0 = &i2c1;
- mmc0 = &sdhci1;
- rtc0 = &rtc;
- serial0 = &uart0;
- serial1 = &uart1;
- serial2 = &dcc;
- spi0 = &qspi;
- usb0 = &usb0;
- };
- chosen {
- bootargs = "earlycon";
- stdout-path = "serial0:115200n8";
- xlnx,eeprom = &eeprom;
- };
- memory@0 {
- device_type = "memory";
- reg = <0x0 0x0 0x0 0x80000000>;
- };
- ina226 {
- compatible = "iio-hwmon";
- io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
- };
- };
- &can1 {
- status = "okay";
- };
- &dcc {
- status = "okay";
- };
- &fpd_dma_chan1 {
- status = "okay";
- };
- &fpd_dma_chan2 {
- status = "okay";
- };
- &fpd_dma_chan3 {
- status = "okay";
- };
- &fpd_dma_chan4 {
- status = "okay";
- };
- &fpd_dma_chan5 {
- status = "okay";
- };
- &fpd_dma_chan6 {
- status = "okay";
- };
- &fpd_dma_chan7 {
- status = "okay";
- };
- &fpd_dma_chan8 {
- status = "okay";
- };
- &gem3 {
- status = "okay";
- phy-handle = <&phy0>;
- phy-mode = "rgmii-id";
- phy0: ethernet-phy@c {
- reg = <0xc>;
- ti,rx-internal-delay = <0x8>;
- ti,tx-internal-delay = <0xa>;
- ti,fifo-depth = <0x1>;
- ti,dp83867-rxctrl-strap-quirk;
- };
- };
- &gpio {
- status = "okay";
- };
- &gpu {
- status = "okay";
- };
- &i2c1 {
- status = "okay";
- clock-frequency = <400000>;
- tca6416_u97: gpio@20 {
- compatible = "ti,tca6416";
- reg = <0x20>;
- gpio-controller;
- #gpio-cells = <2>;
- /*
- * IRQ not connected
- * Lines:
- * 0 - IRPS5401_ALERT_B
- * 1 - HDMI_8T49N241_INT_ALM
- * 2 - MAX6643_OT_B
- * 3 - MAX6643_FANFAIL_B
- * 5 - IIC_MUX_RESET_B
- * 6 - GEM3_EXP_RESET_B
- * 7 - FMC_LPC_PRSNT_M2C_B
- * 4, 10 - 17 - not connected
- */
- };
- /* Another connection to this bus via PL i2c via PCA9306 - u45 */
- i2c-mux@74 { /* u34 */
- compatible = "nxp,pca9548";
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0x74>;
- i2c@0 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <0>;
- /*
- * IIC_EEPROM 1kB memory which uses 256B blocks
- * where every block has different address.
- * 0 - 256B address 0x54
- * 256B - 512B address 0x55
- * 512B - 768B address 0x56
- * 768B - 1024B address 0x57
- */
- eeprom: eeprom@54 { /* u23 */
- compatible = "atmel,24c08";
- reg = <0x54>;
- #address-cells = <1>;
- #size-cells = <1>;
- };
- };
- i2c@1 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <1>;
- clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
- compatible = "idt,8t49n287";
- reg = <0x6c>;
- };
- };
- i2c@2 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <2>;
- irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
- compatible = "infineon,irps5401";
- reg = <0x43>; /* pmbus / i2c 0x13 */
- };
- irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
- compatible = "infineon,irps5401";
- reg = <0x44>; /* pmbus / i2c 0x14 */
- };
- };
- i2c@3 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <3>;
- u183: ina226@40 { /* u183 */
- compatible = "ti,ina226";
- #io-channel-cells = <1>;
- reg = <0x40>;
- shunt-resistor = <5000>;
- };
- };
- i2c@5 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <5>;
- };
- i2c@7 {
- #address-cells = <1>;
- #size-cells = <0>;
- reg = <7>;
- };
- /* 4, 6 not connected */
- };
- };
- &qspi {
- status = "okay";
- flash@0 {
- compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
- #address-cells = <1>;
- #size-cells = <1>;
- reg = <0x0>;
- spi-tx-bus-width = <1>;
- spi-rx-bus-width = <4>;
- spi-max-frequency = <108000000>; /* Based on DC1 spec */
- partition@0 { /* for testing purpose */
- label = "qspi-fsbl-uboot";
- reg = <0x0 0x100000>;
- };
- partition@100000 { /* for testing purpose */
- label = "qspi-linux";
- reg = <0x100000 0x500000>;
- };
- partition@600000 { /* for testing purpose */
- label = "qspi-device-tree";
- reg = <0x600000 0x20000>;
- };
- partition@620000 { /* for testing purpose */
- label = "qspi-rootfs";
- reg = <0x620000 0x5E0000>;
- };
- };
- };
- &rtc {
- status = "okay";
- };
- &sata {
- status = "okay";
- /* SATA OOB timing settings */
- ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
- ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
- ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
- ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
- ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
- ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
- ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
- ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
- phy-names = "sata-phy";
- phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
- };
- /* SD1 with level shifter */
- &sdhci1 {
- status = "okay";
- no-1-8-v;
- xlnx,mio_bank = <1>;
- disable-wp;
- };
- &serdes {
- status = "okay";
- };
- &uart0 {
- status = "okay";
- };
- &uart1 {
- status = "okay";
- };
- /* ULPI SMSC USB3320 */
- &usb0 {
- status = "okay";
- };
- &dwc3_0 {
- status = "okay";
- dr_mode = "host";
- snps,usb3_lpm_capable;
- phy-names = "usb3-phy";
- phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
- maximum-speed = "super-speed";
- };
- &watchdog0 {
- status = "okay";
- };
- &xilinx_ams {
- status = "okay";
- };
- &ams_ps {
- status = "okay";
- };
- &ams_pl {
- status = "okay";
- };
|