zynqmp-zcu104-revC.dts 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * dts file for Xilinx ZynqMP ZCU104
  4. *
  5. * (C) Copyright 2017 - 2020, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk-ccf.dtsi"
  12. #include <dt-bindings/gpio/gpio.h>
  13. #include <dt-bindings/phy/phy.h>
  14. / {
  15. model = "ZynqMP ZCU104 RevC";
  16. compatible = "xlnx,zynqmp-zcu104-revC", "xlnx,zynqmp-zcu104", "xlnx,zynqmp";
  17. aliases {
  18. ethernet0 = &gem3;
  19. gpio0 = &gpio;
  20. i2c0 = &i2c1;
  21. mmc0 = &sdhci1;
  22. rtc0 = &rtc;
  23. serial0 = &uart0;
  24. serial1 = &uart1;
  25. serial2 = &dcc;
  26. spi0 = &qspi;
  27. usb0 = &usb0;
  28. };
  29. chosen {
  30. bootargs = "earlycon";
  31. stdout-path = "serial0:115200n8";
  32. xlnx,eeprom = &eeprom;
  33. };
  34. memory@0 {
  35. device_type = "memory";
  36. reg = <0x0 0x0 0x0 0x80000000>;
  37. };
  38. ina226 {
  39. compatible = "iio-hwmon";
  40. io-channels = <&u183 0>, <&u183 1>, <&u183 2>, <&u183 3>;
  41. };
  42. };
  43. &can1 {
  44. status = "okay";
  45. };
  46. &dcc {
  47. status = "okay";
  48. };
  49. &fpd_dma_chan1 {
  50. status = "okay";
  51. };
  52. &fpd_dma_chan2 {
  53. status = "okay";
  54. };
  55. &fpd_dma_chan3 {
  56. status = "okay";
  57. };
  58. &fpd_dma_chan4 {
  59. status = "okay";
  60. };
  61. &fpd_dma_chan5 {
  62. status = "okay";
  63. };
  64. &fpd_dma_chan6 {
  65. status = "okay";
  66. };
  67. &fpd_dma_chan7 {
  68. status = "okay";
  69. };
  70. &fpd_dma_chan8 {
  71. status = "okay";
  72. };
  73. &gem3 {
  74. status = "okay";
  75. phy-handle = <&phy0>;
  76. phy-mode = "rgmii-id";
  77. phy0: ethernet-phy@c {
  78. reg = <0xc>;
  79. ti,rx-internal-delay = <0x8>;
  80. ti,tx-internal-delay = <0xa>;
  81. ti,fifo-depth = <0x1>;
  82. ti,dp83867-rxctrl-strap-quirk;
  83. };
  84. };
  85. &gpio {
  86. status = "okay";
  87. };
  88. &gpu {
  89. status = "okay";
  90. };
  91. &i2c1 {
  92. status = "okay";
  93. clock-frequency = <400000>;
  94. tca6416_u97: gpio@20 {
  95. compatible = "ti,tca6416";
  96. reg = <0x20>;
  97. gpio-controller;
  98. #gpio-cells = <2>;
  99. /*
  100. * IRQ not connected
  101. * Lines:
  102. * 0 - IRPS5401_ALERT_B
  103. * 1 - HDMI_8T49N241_INT_ALM
  104. * 2 - MAX6643_OT_B
  105. * 3 - MAX6643_FANFAIL_B
  106. * 5 - IIC_MUX_RESET_B
  107. * 6 - GEM3_EXP_RESET_B
  108. * 7 - FMC_LPC_PRSNT_M2C_B
  109. * 4, 10 - 17 - not connected
  110. */
  111. };
  112. /* Another connection to this bus via PL i2c via PCA9306 - u45 */
  113. i2c-mux@74 { /* u34 */
  114. compatible = "nxp,pca9548";
  115. #address-cells = <1>;
  116. #size-cells = <0>;
  117. reg = <0x74>;
  118. i2c@0 {
  119. #address-cells = <1>;
  120. #size-cells = <0>;
  121. reg = <0>;
  122. /*
  123. * IIC_EEPROM 1kB memory which uses 256B blocks
  124. * where every block has different address.
  125. * 0 - 256B address 0x54
  126. * 256B - 512B address 0x55
  127. * 512B - 768B address 0x56
  128. * 768B - 1024B address 0x57
  129. */
  130. eeprom: eeprom@54 { /* u23 */
  131. compatible = "atmel,24c08";
  132. reg = <0x54>;
  133. #address-cells = <1>;
  134. #size-cells = <1>;
  135. };
  136. };
  137. i2c@1 {
  138. #address-cells = <1>;
  139. #size-cells = <0>;
  140. reg = <1>;
  141. clock_8t49n287: clock-generator@6c { /* 8T49N287 - u182 */
  142. compatible = "idt,8t49n287";
  143. reg = <0x6c>;
  144. };
  145. };
  146. i2c@2 {
  147. #address-cells = <1>;
  148. #size-cells = <0>;
  149. reg = <2>;
  150. irps5401_43: irps5401@43 { /* IRPS5401 - u175 */
  151. compatible = "infineon,irps5401";
  152. reg = <0x43>; /* pmbus / i2c 0x13 */
  153. };
  154. irps5401_44: irps5401@44 { /* IRPS5401 - u180 */
  155. compatible = "infineon,irps5401";
  156. reg = <0x44>; /* pmbus / i2c 0x14 */
  157. };
  158. };
  159. i2c@3 {
  160. #address-cells = <1>;
  161. #size-cells = <0>;
  162. reg = <3>;
  163. u183: ina226@40 { /* u183 */
  164. compatible = "ti,ina226";
  165. #io-channel-cells = <1>;
  166. reg = <0x40>;
  167. shunt-resistor = <5000>;
  168. };
  169. };
  170. i2c@5 {
  171. #address-cells = <1>;
  172. #size-cells = <0>;
  173. reg = <5>;
  174. };
  175. i2c@7 {
  176. #address-cells = <1>;
  177. #size-cells = <0>;
  178. reg = <7>;
  179. };
  180. /* 4, 6 not connected */
  181. };
  182. };
  183. &qspi {
  184. status = "okay";
  185. flash@0 {
  186. compatible = "m25p80", "jedec,spi-nor"; /* n25q512a 128MiB */
  187. #address-cells = <1>;
  188. #size-cells = <1>;
  189. reg = <0x0>;
  190. spi-tx-bus-width = <1>;
  191. spi-rx-bus-width = <4>;
  192. spi-max-frequency = <108000000>; /* Based on DC1 spec */
  193. partition@0 { /* for testing purpose */
  194. label = "qspi-fsbl-uboot";
  195. reg = <0x0 0x100000>;
  196. };
  197. partition@100000 { /* for testing purpose */
  198. label = "qspi-linux";
  199. reg = <0x100000 0x500000>;
  200. };
  201. partition@600000 { /* for testing purpose */
  202. label = "qspi-device-tree";
  203. reg = <0x600000 0x20000>;
  204. };
  205. partition@620000 { /* for testing purpose */
  206. label = "qspi-rootfs";
  207. reg = <0x620000 0x5E0000>;
  208. };
  209. };
  210. };
  211. &rtc {
  212. status = "okay";
  213. };
  214. &sata {
  215. status = "okay";
  216. /* SATA OOB timing settings */
  217. ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  218. ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  219. ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  220. ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  221. ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  222. ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  223. ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  224. ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  225. phy-names = "sata-phy";
  226. phys = <&lane3 PHY_TYPE_SATA 1 1 125000000>;
  227. };
  228. /* SD1 with level shifter */
  229. &sdhci1 {
  230. status = "okay";
  231. no-1-8-v;
  232. xlnx,mio_bank = <1>;
  233. disable-wp;
  234. };
  235. &serdes {
  236. status = "okay";
  237. };
  238. &uart0 {
  239. status = "okay";
  240. };
  241. &uart1 {
  242. status = "okay";
  243. };
  244. /* ULPI SMSC USB3320 */
  245. &usb0 {
  246. status = "okay";
  247. };
  248. &dwc3_0 {
  249. status = "okay";
  250. dr_mode = "host";
  251. snps,usb3_lpm_capable;
  252. phy-names = "usb3-phy";
  253. phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
  254. maximum-speed = "super-speed";
  255. };
  256. &watchdog0 {
  257. status = "okay";
  258. };
  259. &xilinx_ams {
  260. status = "okay";
  261. };
  262. &ams_ps {
  263. status = "okay";
  264. };
  265. &ams_pl {
  266. status = "okay";
  267. };