zynqmp-zcu208-revA.dts 14 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * dts file for Xilinx ZynqMP ZCU208
  4. *
  5. * (C) Copyright 2017 - 2020, Xilinx, Inc.
  6. *
  7. * Michal Simek <michal.simek@xilinx.com>
  8. */
  9. /dts-v1/;
  10. #include "zynqmp.dtsi"
  11. #include "zynqmp-clk-ccf.dtsi"
  12. #include <dt-bindings/input/input.h>
  13. #include <dt-bindings/gpio/gpio.h>
  14. #include <dt-bindings/phy/phy.h>
  15. / {
  16. model = "ZynqMP ZCU208 RevA";
  17. compatible = "xlnx,zynqmp-zcu208-revA", "xlnx,zynqmp-zcu208", "xlnx,zynqmp";
  18. aliases {
  19. ethernet0 = &gem3;
  20. gpio0 = &gpio;
  21. i2c0 = &i2c0;
  22. i2c1 = &i2c1;
  23. mmc0 = &sdhci1;
  24. rtc0 = &rtc;
  25. serial0 = &uart0;
  26. serial1 = &dcc;
  27. spi0 = &qspi;
  28. usb0 = &usb0;
  29. };
  30. chosen {
  31. bootargs = "earlycon";
  32. stdout-path = "serial0:115200n8";
  33. xlnx,eeprom = &eeprom;
  34. };
  35. memory@0 {
  36. device_type = "memory";
  37. reg = <0x0 0x0 0x0 0x80000000>, <0x8 0x00000000 0x0 0x80000000>;
  38. };
  39. gpio-keys {
  40. compatible = "gpio-keys";
  41. autorepeat;
  42. sw19 {
  43. label = "sw19";
  44. gpios = <&gpio 22 GPIO_ACTIVE_HIGH>;
  45. linux,code = <KEY_DOWN>;
  46. wakeup-source;
  47. autorepeat;
  48. };
  49. };
  50. leds {
  51. compatible = "gpio-leds";
  52. heartbeat_led {
  53. label = "heartbeat";
  54. gpios = <&gpio 23 GPIO_ACTIVE_HIGH>;
  55. linux,default-trigger = "heartbeat";
  56. };
  57. };
  58. ina226-vccint {
  59. compatible = "iio-hwmon";
  60. io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>;
  61. };
  62. ina226-vccint-io-bram-ps {
  63. compatible = "iio-hwmon";
  64. io-channels = <&vccint_io_bram_ps 0>, <&vccint_io_bram_ps 1>, <&vccint_io_bram_ps 2>, <&vccint_io_bram_ps 3>;
  65. };
  66. ina226-vcc1v8 {
  67. compatible = "iio-hwmon";
  68. io-channels = <&vcc1v8 0>, <&vcc1v8 1>, <&vcc1v8 2>, <&vcc1v8 3>;
  69. };
  70. ina226-vcc1v2 {
  71. compatible = "iio-hwmon";
  72. io-channels = <&vcc1v2 0>, <&vcc1v2 1>, <&vcc1v2 2>, <&vcc1v2 3>;
  73. };
  74. ina226-vadj-fmc {
  75. compatible = "iio-hwmon";
  76. io-channels = <&vadj_fmc 0>, <&vadj_fmc 1>, <&vadj_fmc 2>, <&vadj_fmc 3>;
  77. };
  78. ina226-mgtavcc {
  79. compatible = "iio-hwmon";
  80. io-channels = <&mgtavcc 0>, <&mgtavcc 1>, <&mgtavcc 2>, <&mgtavcc 3>;
  81. };
  82. ina226-mgt1v2 {
  83. compatible = "iio-hwmon";
  84. io-channels = <&mgt1v2 0>, <&mgt1v2 1>, <&mgt1v2 2>, <&mgt1v2 3>;
  85. };
  86. ina226-mgt1v8 {
  87. compatible = "iio-hwmon";
  88. io-channels = <&mgt1v8 0>, <&mgt1v8 1>, <&mgt1v8 2>, <&mgt1v8 3>;
  89. };
  90. ina226-vccint-ams {
  91. compatible = "iio-hwmon";
  92. io-channels = <&vccint_ams 0>, <&vccint_ams 1>, <&vccint_ams 2>, <&vccint_ams 3>;
  93. };
  94. ina226-dac-avtt {
  95. compatible = "iio-hwmon";
  96. io-channels = <&dac_avtt 0>, <&dac_avtt 1>, <&dac_avtt 2>, <&dac_avtt 3>;
  97. };
  98. ina226-dac-avccaux {
  99. compatible = "iio-hwmon";
  100. io-channels = <&dac_avccaux 0>, <&dac_avccaux 1>, <&dac_avccaux 2>, <&dac_avccaux 3>;
  101. };
  102. ina226-adc-avcc {
  103. compatible = "iio-hwmon";
  104. io-channels = <&adc_avcc 0>, <&adc_avcc 1>, <&adc_avcc 2>, <&adc_avcc 3>;
  105. };
  106. ina226-adc-avccaux {
  107. compatible = "iio-hwmon";
  108. io-channels = <&adc_avccaux 0>, <&adc_avccaux 1>, <&adc_avccaux 2>, <&adc_avccaux 3>;
  109. };
  110. ina226-dac-avcc {
  111. compatible = "iio-hwmon";
  112. io-channels = <&dac_avcc 0>, <&dac_avcc 1>, <&dac_avcc 2>, <&dac_avcc 3>;
  113. };
  114. };
  115. &dcc {
  116. status = "okay";
  117. };
  118. &fpd_dma_chan1 {
  119. status = "okay";
  120. };
  121. &fpd_dma_chan2 {
  122. status = "okay";
  123. };
  124. &fpd_dma_chan3 {
  125. status = "okay";
  126. };
  127. &fpd_dma_chan4 {
  128. status = "okay";
  129. };
  130. &fpd_dma_chan5 {
  131. status = "okay";
  132. };
  133. &fpd_dma_chan6 {
  134. status = "okay";
  135. };
  136. &fpd_dma_chan7 {
  137. status = "okay";
  138. };
  139. &fpd_dma_chan8 {
  140. status = "okay";
  141. };
  142. &gem3 {
  143. status = "okay";
  144. phy-handle = <&phy0>;
  145. phy-mode = "rgmii-id";
  146. phy0: ethernet-phy@c {
  147. reg = <0xc>;
  148. ti,rx-internal-delay = <0x8>;
  149. ti,tx-internal-delay = <0xa>;
  150. ti,fifo-depth = <0x1>;
  151. ti,dp83867-rxctrl-strap-quirk;
  152. };
  153. };
  154. &gpio {
  155. status = "okay";
  156. gpio-line-names = "QSPI_LWR_CLK", "QSPI_LWR_DQ1", "QSPI_LWR_DQ2", "QSPI_LWR_DQ3", "QSPI_LWR_DQ0", /* 0 - 4 */
  157. "QSPI_LWR_CS_B", "", "QSPI_UPR_CS_B", "QSPI_UPR_DQ0", "QSPI_UPR_DQ1", /* 5 - 9 */
  158. "QSPI_UPR_DQ2", "QSPI_UPR_DQ3", "QSPI_UPR_CLK", "PS_GPIO2", "I2C0_SCL", /* 10 - 14 */
  159. "I2C0_SDA", "I2C1_SCL", "I2C1_SDA", "UART0_TXD", "UART0_RXD", /* 15 - 19 */
  160. "", "", "BUTTON", "LED", "", /* 20 - 24 */
  161. "", "PMU_INPUT", "", "", "", /* 25 - 29 */
  162. "", "", "PMU_GPO0", "PMU_GPO1", "PMU_GPO2", /* 30 - 34 */
  163. "PMU_GPO3", "PMU_GPO4", "PMU_GPO5", "PS_GPIO1", "SDIO_SEL", /* 35 - 39 */
  164. "SDIO_DIR_CMD", "SDIO_DIR_DAT0", "SDIO_DIR_DAT1", "", "", /* 40 - 44 */
  165. "SDIO_DETECT", "SDIO_DAT0", "SDIO_DAT1", "SDIO_DAT2", "SDIO_DAT3", /* 45 - 49 */
  166. "SDIO_CMD", "SDIO_CLK", "USB_CLK", "USB_DIR", "USB_DATA2", /* 50 - 54 */
  167. "USB_NXT", "USB_DATA0", "USB_DATA1", "USB_STP", "USB_DATA3", /* 55 - 59 */
  168. "USB_DATA4", "USB_DATA5", "USB_DATA6", "USB_DATA7", "ENET_TX_CLK", /* 60 - 64 */
  169. "ENET_TX_D0", "ENET_TX_D1", "ENET_TX_D2", "ENET_TX_D3", "ENET_TX_CTRL", /* 65 - 69 */
  170. "ENET_RX_CLK", "ENET_RX_D0", "ENET_RX_D1", "ENET_RX_D2", "ENET_RX_D3", /* 70 - 74 */
  171. "ENET_RX_CTRL", "ENET_MDC", "ENET_MDIO", /* 75 - 77, MIO end and EMIO start */
  172. "", "", /* 78 - 79 */
  173. "", "", "", "", "", /* 80 - 84 */
  174. "", "", "", "", "", /* 85 -89 */
  175. "", "", "", "", "", /* 90 - 94 */
  176. "", "", "", "", "", /* 95 - 99 */
  177. "", "", "", "", "", /* 100 - 104 */
  178. "", "", "", "", "", /* 105 - 109 */
  179. "", "", "", "", "", /* 110 - 114 */
  180. "", "", "", "", "", /* 115 - 119 */
  181. "", "", "", "", "", /* 120 - 124 */
  182. "", "", "", "", "", /* 125 - 129 */
  183. "", "", "", "", "", /* 130 - 134 */
  184. "", "", "", "", "", /* 135 - 139 */
  185. "", "", "", "", "", /* 140 - 144 */
  186. "", "", "", "", "", /* 145 - 149 */
  187. "", "", "", "", "", /* 150 - 154 */
  188. "", "", "", "", "", /* 155 - 159 */
  189. "", "", "", "", "", /* 160 - 164 */
  190. "", "", "", "", "", /* 165 - 169 */
  191. "", "", "", ""; /* 170 - 174 */
  192. };
  193. &i2c0 {
  194. status = "okay";
  195. clock-frequency = <400000>;
  196. tca6416_u15: gpio@20 { /* u15 */
  197. compatible = "ti,tca6416";
  198. reg = <0x20>;
  199. gpio-controller; /* interrupt not connected */
  200. #gpio-cells = <2>;
  201. gpio-line-names = "MAX6643_OT_B", "MAX6643_FANFAIL_B", "MIO26_PMU_INPUT_LS", "DAC_AVTT_VOUT_SEL", /* 0 - 3 */
  202. "", "IIC_MUX_RESET_B", "GEM3_EXP_RESET_B", "MAX6643_FULL_SPEED", /* 4 - 7 */
  203. "FMCP_HSPC_PRSNT_M2C_B", "", "", "VCCINT_VRHOT_B", /* 10 - 13 */
  204. "", "8A34001_EXP_RST_B", "IRPS5401_ALERT_B", "INA226_PMBUS_ALERT"; /* 14 - 17 */
  205. };
  206. i2c-mux@75 { /* u17 */
  207. compatible = "nxp,pca9544";
  208. #address-cells = <1>;
  209. #size-cells = <0>;
  210. reg = <0x75>;
  211. i2c@0 {
  212. #address-cells = <1>;
  213. #size-cells = <0>;
  214. reg = <0>;
  215. /* PS_PMBUS */
  216. /* PMBUS_ALERT done via pca9544 */
  217. vccint: ina226@40 { /* u65 */
  218. compatible = "ti,ina226";
  219. #io-channel-cells = <1>;
  220. label = "ina226-vccint";
  221. reg = <0x40>;
  222. shunt-resistor = <5000>;
  223. };
  224. vccint_io_bram_ps: ina226@41 { /* u57 */
  225. compatible = "ti,ina226";
  226. #io-channel-cells = <1>;
  227. label = "ina226-vccint-io-bram-ps";
  228. reg = <0x41>;
  229. shunt-resistor = <5000>;
  230. };
  231. vcc1v8: ina226@42 { /* u60 */
  232. compatible = "ti,ina226";
  233. #io-channel-cells = <1>;
  234. label = "ina226-vcc1v8";
  235. reg = <0x42>;
  236. shunt-resistor = <2000>;
  237. };
  238. vcc1v2: ina226@43 { /* u58 */
  239. compatible = "ti,ina226";
  240. #io-channel-cells = <1>;
  241. label = "ina226-vcc1v2";
  242. reg = <0x43>;
  243. shunt-resistor = <5000>;
  244. };
  245. vadj_fmc: ina226@45 { /* u62 */
  246. compatible = "ti,ina226";
  247. #io-channel-cells = <1>;
  248. label = "ina226-vadj-fmc";
  249. reg = <0x45>;
  250. shunt-resistor = <5000>;
  251. };
  252. mgtavcc: ina226@46 { /* u67 */
  253. compatible = "ti,ina226";
  254. #io-channel-cells = <1>;
  255. label = "ina226-mgtavcc";
  256. reg = <0x46>;
  257. shunt-resistor = <2000>;
  258. };
  259. mgt1v2: ina226@47 { /* u63 */
  260. compatible = "ti,ina226";
  261. #io-channel-cells = <1>;
  262. label = "ina226-mgt1v2";
  263. reg = <0x47>;
  264. shunt-resistor = <5000>;
  265. };
  266. mgt1v8: ina226@48 { /* u64 */
  267. compatible = "ti,ina226";
  268. #io-channel-cells = <1>;
  269. label = "ina226-mgt1v8";
  270. reg = <0x48>;
  271. shunt-resistor = <5000>;
  272. };
  273. vccint_ams: ina226@49 { /* u61 */
  274. compatible = "ti,ina226";
  275. #io-channel-cells = <1>;
  276. label = "ina226-vccint-ams";
  277. reg = <0x49>;
  278. shunt-resistor = <5000>;
  279. };
  280. dac_avtt: ina226@4a { /* u59 */
  281. compatible = "ti,ina226";
  282. #io-channel-cells = <1>;
  283. label = "ina226-dac-avtt";
  284. reg = <0x4a>;
  285. shunt-resistor = <5000>;
  286. };
  287. dac_avccaux: ina226@4b { /* u124 */
  288. compatible = "ti,ina226";
  289. #io-channel-cells = <1>;
  290. label = "ina226-dac-avccaux";
  291. reg = <0x4b>;
  292. shunt-resistor = <5000>;
  293. };
  294. adc_avcc: ina226@4c { /* u75 */
  295. compatible = "ti,ina226";
  296. #io-channel-cells = <1>;
  297. label = "ina226-adc-avcc";
  298. reg = <0x4c>;
  299. shunt-resistor = <5000>;
  300. };
  301. adc_avccaux: ina226@4d { /* u71 */
  302. compatible = "ti,ina226";
  303. #io-channel-cells = <1>;
  304. label = "ina226-adc-avccaux";
  305. reg = <0x4d>;
  306. shunt-resistor = <5000>;
  307. };
  308. dac_avcc: ina226@4e { /* u77 */
  309. compatible = "ti,ina226";
  310. #io-channel-cells = <1>;
  311. label = "ina226-dac-avcc";
  312. reg = <0x4e>;
  313. shunt-resistor = <5000>;
  314. };
  315. };
  316. i2c@1 {
  317. #address-cells = <1>;
  318. #size-cells = <0>;
  319. reg = <1>;
  320. /* NC */
  321. };
  322. i2c@2 {
  323. #address-cells = <1>;
  324. #size-cells = <0>;
  325. reg = <2>;
  326. /* u104 - ir35215 0x10/0x40 */
  327. /* u127 - ir38164 0x1b/0x4b */
  328. /* u112 - ir38164 0x13/0x43 */
  329. /* u123 - ir38164 0x1c/0x4c */
  330. irps5401_44: irps5401@44 { /* IRPS5401 - u53 */
  331. compatible = "infineon,irps5401";
  332. reg = <0x44>; /* i2c addr 0x14 */
  333. };
  334. irps5401_45: irps5401@45 { /* IRPS5401 - u55 */
  335. compatible = "infineon,irps5401";
  336. reg = <0x45>; /* i2c addr 0x15 */
  337. };
  338. /* J21 header too */
  339. };
  340. i2c@3 {
  341. #address-cells = <1>;
  342. #size-cells = <0>;
  343. reg = <3>;
  344. /* SYSMON */
  345. };
  346. };
  347. /* u38 MPS430 */
  348. };
  349. &i2c1 {
  350. status = "okay";
  351. clock-frequency = <400000>;
  352. i2c-mux@74 {
  353. compatible = "nxp,pca9548"; /* u20 */
  354. #address-cells = <1>;
  355. #size-cells = <0>;
  356. reg = <0x74>;
  357. /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
  358. i2c_eeprom: i2c@0 {
  359. #address-cells = <1>;
  360. #size-cells = <0>;
  361. reg = <0>;
  362. /*
  363. * IIC_EEPROM 1kB memory which uses 256B blocks
  364. * where every block has different address.
  365. * 0 - 256B address 0x54
  366. * 256B - 512B address 0x55
  367. * 512B - 768B address 0x56
  368. * 768B - 1024B address 0x57
  369. */
  370. eeprom: eeprom@54 { /* u21 */
  371. compatible = "atmel,24c128";
  372. reg = <0x54>;
  373. };
  374. };
  375. i2c_si5341: i2c@1 {
  376. #address-cells = <1>;
  377. #size-cells = <0>;
  378. reg = <1>;
  379. si5341: clock-generator@36 { /* SI5341 - u43 */
  380. compatible = "si5341";
  381. reg = <0x36>;
  382. };
  383. };
  384. i2c_si570_user_c0: i2c@2 {
  385. #address-cells = <1>;
  386. #size-cells = <0>;
  387. reg = <2>;
  388. si570_1: clock-generator@5d { /* USER C0 SI570 - u47 */
  389. #clock-cells = <0>;
  390. compatible = "silabs,si570";
  391. reg = <0x5d>;
  392. temperature-stability = <50>;
  393. factory-fout = <300000000>;
  394. clock-frequency = <300000000>;
  395. clock-output-names = "si570_user_c0";
  396. };
  397. };
  398. i2c_si570_mgt: i2c@3 {
  399. #address-cells = <1>;
  400. #size-cells = <0>;
  401. reg = <3>;
  402. si570_2: clock-generator@5d { /* USER MGT SI570 - u48 */
  403. #clock-cells = <0>;
  404. compatible = "silabs,si570";
  405. reg = <0x5d>;
  406. temperature-stability = <50>;
  407. factory-fout = <156250000>;
  408. clock-frequency = <148500000>;
  409. clock-output-names = "si570_mgt";
  410. };
  411. };
  412. i2c_8a34001: i2c@4 {
  413. #address-cells = <1>;
  414. #size-cells = <0>;
  415. reg = <4>;
  416. /* U409B - 8a34001 */
  417. };
  418. i2c_clk104: i2c@5 {
  419. #address-cells = <1>;
  420. #size-cells = <0>;
  421. reg = <5>;
  422. /* CLK104_SDA */
  423. };
  424. i2c@6 {
  425. #address-cells = <1>;
  426. #size-cells = <0>;
  427. reg = <6>;
  428. /* RFMCP connector */
  429. };
  430. /* 7 NC */
  431. };
  432. i2c-mux@75 {
  433. compatible = "nxp,pca9548"; /* u22 */
  434. #address-cells = <1>;
  435. #size-cells = <0>;
  436. reg = <0x75>;
  437. /* FIXME reset-gpios = <&tca6416_u15 SYSCTLR_IIC_MUX0_RESET_B GPIO_ACTIVE_HIGH>; */
  438. i2c@0 {
  439. #address-cells = <1>;
  440. #size-cells = <0>;
  441. reg = <0>;
  442. /* FMCP_HSPC_IIC */
  443. };
  444. i2c_si570_user_c1: i2c@1 {
  445. #address-cells = <1>;
  446. #size-cells = <0>;
  447. reg = <1>;
  448. si570_3: clock-generator@5d { /* USER C1 SI570 - u130 */
  449. #clock-cells = <0>;
  450. compatible = "silabs,si570";
  451. reg = <0x5d>;
  452. temperature-stability = <50>;
  453. factory-fout = <300000000>;
  454. clock-frequency = <300000000>;
  455. clock-output-names = "si570_user_c1";
  456. };
  457. };
  458. i2c@2 {
  459. #address-cells = <1>;
  460. #size-cells = <0>;
  461. reg = <2>;
  462. /* SYSMON */
  463. };
  464. i2c@3 {
  465. #address-cells = <1>;
  466. #size-cells = <0>;
  467. reg = <3>;
  468. /* DDR4 SODIMM */
  469. };
  470. i2c@4 {
  471. #address-cells = <1>;
  472. #size-cells = <0>;
  473. reg = <4>;
  474. /* SFP3 */
  475. };
  476. i2c@5 {
  477. #address-cells = <1>;
  478. #size-cells = <0>;
  479. reg = <5>;
  480. /* SFP2 */
  481. };
  482. i2c@6 {
  483. #address-cells = <1>;
  484. #size-cells = <0>;
  485. reg = <6>;
  486. /* SFP1 */
  487. };
  488. i2c@7 {
  489. #address-cells = <1>;
  490. #size-cells = <0>;
  491. reg = <7>;
  492. /* SFP0 */
  493. };
  494. };
  495. /* MSP430 */
  496. };
  497. &qspi {
  498. status = "okay";
  499. is-dual = <1>;
  500. flash@0 {
  501. compatible = "m25p80", "jedec,spi-nor"; /* U11 and U12 MT25QU02GCBBE12 1Gb */
  502. #address-cells = <1>;
  503. #size-cells = <1>;
  504. reg = <0>;
  505. spi-tx-bus-width = <1>;
  506. spi-rx-bus-width = <4>; /* FIXME also DUAL configuration possible */
  507. spi-max-frequency = <108000000>; /* Based on DC1 spec */
  508. };
  509. };
  510. &rtc {
  511. status = "okay";
  512. };
  513. &sata {
  514. status = "okay";
  515. /* SATA OOB timing settings */
  516. ceva,p0-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  517. ceva,p0-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  518. ceva,p0-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  519. ceva,p0-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  520. ceva,p1-cominit-params = /bits/ 8 <0x18 0x40 0x18 0x28>;
  521. ceva,p1-comwake-params = /bits/ 8 <0x06 0x14 0x08 0x0E>;
  522. ceva,p1-burst-params = /bits/ 8 <0x13 0x08 0x4A 0x06>;
  523. ceva,p1-retry-params = /bits/ 16 <0x96A4 0x3FFC>;
  524. phy-names = "sata-phy";
  525. phys = <&lane3 PHY_TYPE_SATA 1 3 125000000>;
  526. };
  527. /* SD1 with level shifter */
  528. &sdhci1 {
  529. status = "okay";
  530. disable-wp;
  531. /*
  532. * This property should be removed for supporting UHS mode
  533. */
  534. no-1-8-v;
  535. xlnx,mio_bank = <1>;
  536. };
  537. &serdes {
  538. status = "okay";
  539. };
  540. &uart0 {
  541. status = "okay";
  542. };
  543. /* ULPI SMSC USB3320 */
  544. &usb0 {
  545. status = "okay";
  546. };
  547. &dwc3_0 {
  548. status = "okay";
  549. dr_mode = "host";
  550. snps,usb3_lpm_capable;
  551. phy-names = "usb3-phy";
  552. phys = <&lane2 PHY_TYPE_USB3 0 2 26000000>;
  553. };