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Blackfin: Remove

The architecture is currently unmaintained, remove.

Cc: Benjamin Matthews <mben12@gmail.com>
Cc: Chong Huang <chuang@ucrobotics.com>
Cc: Dimitar Penev <dpn@switchfin.org>
Cc: Haitao Zhang <hzhang@ucrobotics.com>
Cc: I-SYST Micromodule <support@i-syst.com>
Cc: M.Hasewinkel (MHA) <info@ssv-embedded.de>
Cc: Marek Vasut <marex@denx.de>
Cc: Martin Strubel <strubel@section5.ch>
Cc: Peter Meerwald <devel@bct-electronic.com>
Cc: Sonic Zhang <sonic.adi@gmail.com>
Cc: Valentin Yakovenkov <yakovenkov@niistt.ru>
Cc: Wojtek Skulski <info@skutek.com>
Cc: Wojtek Skulski <skulski@pas.rochester.edu>
Signed-off-by: Tom Rini <trini@konsulko.com>
Tom Rini vor 7 Jahren
Ursprung
Commit
ea3310e8aa
100 geänderte Dateien mit 1 neuen und 25166 gelöschten Zeilen
  1. 1 2
      .travis.yml
  2. 0 6
      MAINTAINERS
  3. 0 8
      README
  4. 0 5
      arch/Kconfig
  5. 0 150
      arch/blackfin/Kconfig
  6. 0 8
      arch/blackfin/Makefile
  7. 0 68
      arch/blackfin/config.mk
  8. 0 2
      arch/blackfin/cpu/.gitignore
  9. 0 45
      arch/blackfin/cpu/Makefile
  10. 0 87
      arch/blackfin/cpu/cache.S
  11. 0 415
      arch/blackfin/cpu/cpu.c
  12. 0 23
      arch/blackfin/cpu/cpu.h
  13. 0 841
      arch/blackfin/cpu/gpio.c
  14. 0 9
      arch/blackfin/cpu/init.S
  15. 0 25
      arch/blackfin/cpu/init.lds.S
  16. 0 1041
      arch/blackfin/cpu/initcode.c
  17. 0 123
      arch/blackfin/cpu/initcode.h
  18. 0 157
      arch/blackfin/cpu/interrupt.S
  19. 0 151
      arch/blackfin/cpu/interrupts.c
  20. 0 228
      arch/blackfin/cpu/jtag-console.c
  21. 0 30
      arch/blackfin/cpu/os_log.c
  22. 0 96
      arch/blackfin/cpu/reset.c
  23. 0 263
      arch/blackfin/cpu/start.S
  24. 0 435
      arch/blackfin/cpu/traps.c
  25. 0 142
      arch/blackfin/cpu/u-boot.lds
  26. 0 2377
      arch/blackfin/include/asm/bfin_logo_230x230_gzip.h
  27. 0 1819
      arch/blackfin/include/asm/bfin_logo_230x230_lzma.h
  28. 0 1242
      arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h
  29. 0 1079
      arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h
  30. 0 358
      arch/blackfin/include/asm/bitops.h
  31. 0 15
      arch/blackfin/include/asm/blackfin.h
  32. 0 91
      arch/blackfin/include/asm/blackfin_cdef.h
  33. 0 145
      arch/blackfin/include/asm/blackfin_def.h
  34. 0 208
      arch/blackfin/include/asm/blackfin_local.h
  35. 0 24
      arch/blackfin/include/asm/byteorder.h
  36. 0 70
      arch/blackfin/include/asm/cache.h
  37. 0 88
      arch/blackfin/include/asm/clock.h
  38. 0 82
      arch/blackfin/include/asm/config-pre.h
  39. 0 176
      arch/blackfin/include/asm/config.h
  40. 0 99
      arch/blackfin/include/asm/cplb.h
  41. 0 20
      arch/blackfin/include/asm/deferred.h
  42. 0 39
      arch/blackfin/include/asm/delay.h
  43. 0 104
      arch/blackfin/include/asm/dma.h
  44. 0 243
      arch/blackfin/include/asm/entry.h
  45. 0 26
      arch/blackfin/include/asm/global_data.h
  46. 0 167
      arch/blackfin/include/asm/gpio.h
  47. 0 228
      arch/blackfin/include/asm/io.h
  48. 0 12
      arch/blackfin/include/asm/linkage.h
  49. 0 1782
      arch/blackfin/include/asm/mach-bf506/BF504_cdef.h
  50. 0 944
      arch/blackfin/include/asm/mach-bf506/BF504_def.h
  51. 0 11
      arch/blackfin/include/asm/mach-bf506/BF506_cdef.h
  52. 0 11
      arch/blackfin/include/asm/mach-bf506/BF506_def.h
  53. 0 145
      arch/blackfin/include/asm/mach-bf506/anomaly.h
  54. 0 5
      arch/blackfin/include/asm/mach-bf506/def_local.h
  55. 0 52
      arch/blackfin/include/asm/mach-bf506/gpio.h
  56. 0 148
      arch/blackfin/include/asm/mach-bf506/portmux.h
  57. 0 59
      arch/blackfin/include/asm/mach-bf506/ports.h
  58. 0 1000
      arch/blackfin/include/asm/mach-bf518/BF512_cdef.h
  59. 0 517
      arch/blackfin/include/asm/mach-bf518/BF512_def.h
  60. 0 68
      arch/blackfin/include/asm/mach-bf518/BF514_cdef.h
  61. 0 40
      arch/blackfin/include/asm/mach-bf518/BF514_def.h
  62. 0 170
      arch/blackfin/include/asm/mach-bf518/BF516_cdef.h
  63. 0 91
      arch/blackfin/include/asm/mach-bf518/BF516_def.h
  64. 0 58
      arch/blackfin/include/asm/mach-bf518/BF518_cdef.h
  65. 0 35
      arch/blackfin/include/asm/mach-bf518/BF518_def.h
  66. 0 170
      arch/blackfin/include/asm/mach-bf518/anomaly.h
  67. 0 5
      arch/blackfin/include/asm/mach-bf518/def_local.h
  68. 0 58
      arch/blackfin/include/asm/mach-bf518/gpio.h
  69. 0 201
      arch/blackfin/include/asm/mach-bf518/portmux.h
  70. 0 59
      arch/blackfin/include/asm/mach-bf518/ports.h
  71. 0 1012
      arch/blackfin/include/asm/mach-bf527/BF522_cdef.h
  72. 0 513
      arch/blackfin/include/asm/mach-bf527/BF522_def.h
  73. 0 1
      arch/blackfin/include/asm/mach-bf527/BF523_cdef.h
  74. 0 1
      arch/blackfin/include/asm/mach-bf527/BF523_def.h
  75. 0 350
      arch/blackfin/include/asm/mach-bf527/BF524_cdef.h
  76. 0 181
      arch/blackfin/include/asm/mach-bf527/BF524_def.h
  77. 0 1
      arch/blackfin/include/asm/mach-bf527/BF525_cdef.h
  78. 0 1
      arch/blackfin/include/asm/mach-bf527/BF525_def.h
  79. 0 170
      arch/blackfin/include/asm/mach-bf527/BF526_cdef.h
  80. 0 91
      arch/blackfin/include/asm/mach-bf527/BF526_def.h
  81. 0 1
      arch/blackfin/include/asm/mach-bf527/BF527_cdef.h
  82. 0 1
      arch/blackfin/include/asm/mach-bf527/BF527_def.h
  83. 0 290
      arch/blackfin/include/asm/mach-bf527/anomaly.h
  84. 0 6
      arch/blackfin/include/asm/mach-bf527/def_local.h
  85. 0 65
      arch/blackfin/include/asm/mach-bf527/gpio.h
  86. 0 21
      arch/blackfin/include/asm/mach-bf527/mem_map.h
  87. 0 220
      arch/blackfin/include/asm/mach-bf527/portmux.h
  88. 0 60
      arch/blackfin/include/asm/mach-bf527/ports.h
  89. 0 872
      arch/blackfin/include/asm/mach-bf533/BF531_cdef.h
  90. 0 444
      arch/blackfin/include/asm/mach-bf533/BF531_def.h
  91. 0 1
      arch/blackfin/include/asm/mach-bf533/BF532_cdef.h
  92. 0 17
      arch/blackfin/include/asm/mach-bf533/BF532_def.h
  93. 0 1
      arch/blackfin/include/asm/mach-bf533/BF533_cdef.h
  94. 0 21
      arch/blackfin/include/asm/mach-bf533/BF533_def.h
  95. 0 383
      arch/blackfin/include/asm/mach-bf533/anomaly.h
  96. 0 5
      arch/blackfin/include/asm/mach-bf533/def_local.h
  97. 0 31
      arch/blackfin/include/asm/mach-bf533/gpio.h
  98. 0 71
      arch/blackfin/include/asm/mach-bf533/portmux.h
  99. 0 10
      arch/blackfin/include/asm/mach-bf533/ports.h
  100. 0 1624
      arch/blackfin/include/asm/mach-bf537/BF534_cdef.h

+ 1 - 2
.travis.yml

@@ -40,7 +40,7 @@ install:
  - ln -s travis-ci /tmp/uboot-test-hooks/py/`hostname`
  # prepare buildman environment
  - echo -e "[toolchain]\nroot = /usr" > ~/.buildman
- - echo -e "\n[toolchain-alias]\nblackfin = bfin\nsh = sh4\nopenrisc = or32" >> ~/.buildman
+ - echo -e "\n[toolchain-alias]\nsh = sh4\nopenrisc = or32" >> ~/.buildman
  - cat ~/.buildman
  - virtualenv /tmp/venv
  - . /tmp/venv/bin/activate
@@ -60,7 +60,6 @@ env:
 before_script:
   # install toolchains based on TOOLCHAIN} variable
   - if [[ "${TOOLCHAIN}" == *avr32* ]]; then ./tools/buildman/buildman --fetch-arch avr32 ; fi
-  - if [[ "${TOOLCHAIN}" == *bfin* ]]; then ./tools/buildman/buildman --fetch-arch bfin ; fi
   - if [[ "${TOOLCHAIN}" == *m68k* ]]; then ./tools/buildman/buildman --fetch-arch m68k ; fi
   - if [[ "${TOOLCHAIN}" == *microblaze* ]]; then ./tools/buildman/buildman --fetch-arch microblaze ; fi
   - if [[ "${TOOLCHAIN}" == *mips* ]]; then ./tools/buildman/buildman --fetch-arch mips ; fi

+ 0 - 6
MAINTAINERS

@@ -222,12 +222,6 @@ S:	Maintained
 T:	git git://git.denx.de/u-boot-avr32.git
 F:	arch/avr32/
 
-BLACKFIN
-M:	Sonic Zhang <sonic.adi@gmail.com>
-S:	Maintained
-T:	git git://git.denx.de/u-boot-blackfin.git
-F:	arch/blackfin/
-
 BUILDMAN
 M:	Simon Glass <sjg@chromium.org>
 S:	Maintained

+ 0 - 8
README

@@ -137,7 +137,6 @@ Directory Hierarchy:
   /arc			Files generic to ARC architecture
   /arm			Files generic to ARM architecture
   /avr32		Files generic to AVR32 architecture
-  /blackfin		Files generic to Analog Devices Blackfin architecture
   /m68k			Files generic to m68k architecture
   /microblaze		Files generic to microblaze architecture
   /mips			Files generic to MIPS architecture
@@ -2869,8 +2868,6 @@ The following options need to be configured:
 
 		CONFIG_AT91SAM9XE
 		enable special bootcounter support on at91sam9xe based boards.
-		CONFIG_BLACKFIN
-		enable special bootcounter support on blackfin based boards.
 		CONFIG_SOC_DA8XX
 		enable special bootcounter support on da850 based boards.
 		CONFIG_BOOTCOUNT_RAM
@@ -5911,11 +5908,6 @@ For PowerPC, the following registers have specific use:
     average for all boards 752 bytes for the whole U-Boot image,
     624 text + 127 data).
 
-On Blackfin, the normal C ABI (except for P3) is followed as documented here:
-	http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
-
-    ==> U-Boot will use P3 to hold a pointer to the global data
-
 On ARM, the following registers are used:
 
 	R0:	function argument word/integer result

+ 0 - 5
arch/Kconfig

@@ -27,10 +27,6 @@ config AVR32
 	bool "AVR32 architecture"
 	select CREATE_ARCH_SYMLINK
 
-config BLACKFIN
-	bool "Blackfin architecture"
-	select ARCH_MISC_INIT
-
 config M68K
 	bool "M68000 architecture"
 	select HAVE_PRIVATE_LIBGCC
@@ -162,7 +158,6 @@ config SYS_CONFIG_NAME
 source "arch/arc/Kconfig"
 source "arch/arm/Kconfig"
 source "arch/avr32/Kconfig"
-source "arch/blackfin/Kconfig"
 source "arch/m68k/Kconfig"
 source "arch/microblaze/Kconfig"
 source "arch/mips/Kconfig"

+ 0 - 150
arch/blackfin/Kconfig

@@ -1,150 +0,0 @@
-menu "Blackfin architecture"
-	depends on BLACKFIN
-
-config SYS_ARCH
-	default "blackfin"
-
-choice
-	prompt "Target select"
-	optional
-
-config TARGET_BCT_BRETTL2
-	bool "Support bct-brettl2"
-
-config TARGET_BF506F_EZKIT
-	bool "Support bf506f-ezkit"
-
-config TARGET_BF518F_EZBRD
-	bool "Support bf518f-ezbrd"
-
-config TARGET_BF525_UCR2
-	bool "Support bf525-ucr2"
-
-config TARGET_BF526_EZBRD
-	bool "Support bf526-ezbrd"
-
-config TARGET_BF527_AD7160_EVAL
-	bool "Support bf527-ad7160-eval"
-
-config TARGET_BF527_EZKIT
-	bool "Support bf527-ezkit"
-
-config TARGET_BF527_SDP
-	bool "Support bf527-sdp"
-
-config TARGET_BF533_EZKIT
-	bool "Support bf533-ezkit"
-
-config TARGET_BF533_STAMP
-	bool "Support bf533-stamp"
-
-config TARGET_BF537_MINOTAUR
-	bool "Support bf537-minotaur"
-
-config TARGET_BF537_PNAV
-	bool "Support bf537-pnav"
-
-config TARGET_BF537_SRV1
-	bool "Support bf537-srv1"
-
-config TARGET_BF537_STAMP
-	bool "Support bf537-stamp"
-
-config TARGET_BF538F_EZKIT
-	bool "Support bf538f-ezkit"
-
-config TARGET_BF548_EZKIT
-	bool "Support bf548-ezkit"
-
-config TARGET_BF561_ACVILON
-	bool "Support bf561-acvilon"
-
-config TARGET_BF561_EZKIT
-	bool "Support bf561-ezkit"
-
-config TARGET_BF609_EZKIT
-	bool "Support bf609-ezkit"
-
-config TARGET_BLACKSTAMP
-	bool "Support blackstamp"
-
-config TARGET_BLACKVME
-	bool "Support blackvme"
-
-config TARGET_BR4
-	bool "Support br4"
-
-config TARGET_CM_BF527
-	bool "Support cm-bf527"
-
-config TARGET_CM_BF533
-	bool "Support cm-bf533"
-
-config TARGET_CM_BF537E
-	bool "Support cm-bf537e"
-
-config TARGET_CM_BF537U
-	bool "Support cm-bf537u"
-
-config TARGET_CM_BF548
-	bool "Support cm-bf548"
-
-config TARGET_CM_BF561
-	bool "Support cm-bf561"
-
-config TARGET_DNP5370
-	bool "Support dnp5370"
-
-config TARGET_IBF_DSP561
-	bool "Support ibf-dsp561"
-
-config TARGET_IP04
-	bool "Support ip04"
-
-config TARGET_PR1
-	bool "Support pr1"
-
-config TARGET_TCM_BF518
-	bool "Support tcm-bf518"
-
-config TARGET_TCM_BF537
-	bool "Support tcm-bf537"
-
-endchoice
-
-source "board/bct-brettl2/Kconfig"
-source "board/bf506f-ezkit/Kconfig"
-source "board/bf518f-ezbrd/Kconfig"
-source "board/bf525-ucr2/Kconfig"
-source "board/bf526-ezbrd/Kconfig"
-source "board/bf527-ad7160-eval/Kconfig"
-source "board/bf527-ezkit/Kconfig"
-source "board/bf527-sdp/Kconfig"
-source "board/bf533-ezkit/Kconfig"
-source "board/bf533-stamp/Kconfig"
-source "board/bf537-minotaur/Kconfig"
-source "board/bf537-pnav/Kconfig"
-source "board/bf537-srv1/Kconfig"
-source "board/bf537-stamp/Kconfig"
-source "board/bf538f-ezkit/Kconfig"
-source "board/bf548-ezkit/Kconfig"
-source "board/bf561-acvilon/Kconfig"
-source "board/bf561-ezkit/Kconfig"
-source "board/bf609-ezkit/Kconfig"
-source "board/blackstamp/Kconfig"
-source "board/blackvme/Kconfig"
-source "board/br4/Kconfig"
-source "board/cm-bf527/Kconfig"
-source "board/cm-bf533/Kconfig"
-source "board/cm-bf537e/Kconfig"
-source "board/cm-bf537u/Kconfig"
-source "board/cm-bf548/Kconfig"
-source "board/cm-bf561/Kconfig"
-source "board/dnp5370/Kconfig"
-source "board/ibf-dsp561/Kconfig"
-source "board/ip04/Kconfig"
-source "board/pr1/Kconfig"
-source "board/tcm-bf518/Kconfig"
-source "board/tcm-bf537/Kconfig"
-
-endmenu

+ 0 - 8
arch/blackfin/Makefile

@@ -1,8 +0,0 @@
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-head-y := arch/blackfin/cpu/start.o
-
-libs-y += arch/blackfin/cpu/
-libs-y += arch/blackfin/lib/

+ 0 - 68
arch/blackfin/config.mk

@@ -1,68 +0,0 @@
-#
-# (C) Copyright 2000-2002
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-ifeq ($(CROSS_COMPILE),)
-CROSS_COMPILE := bfin-uclinux-
-endif
-
-CONFIG_STANDALONE_LOAD_ADDR ?= 0x1000 -m elf32bfin
-
-ifeq ($(CONFIG_BFIN_CPU),)
-CONFIG_BFIN_CPU := \
-	$(shell awk '$$2 == "CONFIG_BFIN_CPU" { print $$3 }' \
-		$(srctree)/include/configs/$(BOARD).h)
-else
-CONFIG_BFIN_CPU := $(strip $(CONFIG_BFIN_CPU:"%"=%))
-endif
-CONFIG_BFIN_BOOT_MODE := $(strip $(CONFIG_BFIN_BOOT_MODE:"%"=%))
-
-PLATFORM_RELFLAGS += -ffixed-P3 -fomit-frame-pointer -mno-fdpic
-
-LDFLAGS_FINAL += --gc-sections
-LDFLAGS += -m elf32bfin
-PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections
-
-PLATFORM_RELFLAGS += -mcpu=$(CONFIG_BFIN_CPU)
-
-ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-ALL-y += u-boot.ldr
-endif
-ifeq ($(CONFIG_ENV_IS_EMBEDDED_IN_LDR),y)
-CREATE_LDR_ENV = tools/envcrc --binary > env-ldr.o
-HOSTCFLAGS_NOPED_ADSP := \
-	$(shell $(CPP) -dD - -mcpu=$(CONFIG_BFIN_CPU) </dev/null \
-		| awk '$$2 ~ /ADSP/ { print "-D" $$2 }')
-HOSTCFLAGS_NOPED += $(HOSTCFLAGS_NOPED_ADSP)
-else
-CREATE_LDR_ENV =
-endif
-
-SYM_PREFIX = _
-export SYM_PREFIX
-
-LDR_FLAGS-y :=
-LDR_FLAGS-$(CONFIG_BFIN_BOOTROM_USES_EVT1) += -J
-
-LDR_FLAGS += --bmode $(subst BFIN_BOOT_,,$(CONFIG_BFIN_BOOT_MODE))
-LDR_FLAGS += --use-vmas
-LDR_FLAGS += --initcode $(CPUDIR)/initcode.o
-ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_UART)
-LDR_FLAGS-$(CONFIG_ENV_IS_EMBEDDED_IN_LDR) += \
-	--punchit $$(($(CONFIG_ENV_OFFSET))):$$(($(CONFIG_ENV_SIZE))):env-ldr.o
-endif
-ifneq (,$(findstring s,$(MAKEFLAGS)))
-LDR_FLAGS += --quiet
-endif
-
-LDR_FLAGS += $(LDR_FLAGS-y)
-
-# Set some default LDR flags based on boot mode.
-LDR_FLAGS += $(LDR_FLAGS-$(CONFIG_BFIN_BOOT_MODE))
-
-ifneq ($(CONFIG_SYS_TEXT_BASE),)
-$(error do not set CONFIG_SYS_TEXT_BASE for Blackfin boards)
-endif

+ 0 - 2
arch/blackfin/cpu/.gitignore

@@ -1,2 +0,0 @@
-init.lds
-init.elf

+ 0 - 45
arch/blackfin/cpu/Makefile

@@ -1,45 +0,0 @@
-#
-# U-Boot - Makefile
-#
-# Copyright (c) 2005-2008 Analog Device Inc.
-#
-# (C) Copyright 2000-2006
-# Wolfgang Denk, DENX Software Engineering, wd@denx.de.
-#
-# SPDX-License-Identifier:	GPL-2.0+
-#
-
-extra-y := init.elf
-extra-y += initcode.o
-extra-y += start.o
-obj-y    := interrupt.o cache.o
-obj-y  += cpu.o
-obj-y += gpio.o
-obj-y  += interrupts.o
-obj-$(CONFIG_JTAG_CONSOLE) += jtag-console.o
-obj-y  += os_log.o
-obj-y  += reset.o
-obj-y  += traps.o
-
-extra-y += check_initcode
-clean-files := init.lds
-
-# make sure our initcode (which goes into LDR) does not
-# have relocs or external references
-CFLAGS_REMOVE_initcode.o := -ffunction-sections -fdata-sections
-READINIT = env LC_ALL=C $(CROSS_COMPILE)readelf -s $<
-$(obj)/check_initcode: $(obj)/initcode.o
-ifneq ($(CONFIG_BFIN_BOOT_MODE),BFIN_BOOT_BYPASS)
-	@if $(READINIT) | grep '\<GLOBAL\>.*\<UND\>' ; then \
-		echo "$< contains external references!" 1>&2 ; \
-		exit 1 ; \
-	fi
-endif
-
-CPPFLAGS_init.lds := -ansi
-
-quiet_cmd_link_init = LD      $@
-      cmd_link_init = $(LD) $(LDFLAGS) -T $^ -o $@
-$(obj)/init.elf: $(obj)/init.lds $(obj)/init.o $(obj)/initcode.o
-	$(call if_changed,link_init)
-targets += init.lds init.o

+ 0 - 87
arch/blackfin/cpu/cache.S

@@ -1,87 +0,0 @@
-/*
- * Blackfin cache control code
- *
- * Copyright 2003-2008 Analog Devices Inc.
- *
- * Enter bugs at http://blackfin.uclinux.org/
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <linux/linkage.h>
-#include <asm/blackfin.h>
-
-.text
-/* Since all L1 caches work the same way, we use the same method for flushing
- * them.  Only the actual flush instruction differs.  We write this in asm as
- * GCC can be hard to coax into writing nice hardware loops.
- *
- * Also, we assume the following register setup:
- * R0 = start address
- * R1 = end address
- */
-.macro do_flush flushins:req optflushins optnopins label
-
-	R2 = -L1_CACHE_BYTES;
-
-	/* start = (start & -L1_CACHE_BYTES) */
-	R0 = R0 & R2;
-
-	/* end = ((end - 1) & -L1_CACHE_BYTES) + L1_CACHE_BYTES; */
-	R1 += -1;
-	R1 = R1 & R2;
-	R1 += L1_CACHE_BYTES;
-
-	/* count = (end - start) >> L1_CACHE_SHIFT */
-	R2 = R1 - R0;
-	R2 >>= L1_CACHE_SHIFT;
-	P1 = R2;
-
-.ifnb \label
-\label :
-.endif
-	P0 = R0;
-	LSETUP (1f, 2f) LC1 = P1;
-1:
-.ifnb \optflushins
-	\optflushins [P0];
-.endif
-#if ANOMALY_05000443
-.ifb \optnopins
-2:
-.endif
-	\flushins [P0++];
-.ifnb \optnopins
-2:	\optnopins;
-.endif
-#else
-2:	\flushins [P0++];
-#endif
-
-	RTS;
-.endm
-
-/* Invalidate all instruction cache lines assocoiated with this memory area */
-ENTRY(_blackfin_icache_flush_range)
-	do_flush IFLUSH, , nop
-ENDPROC(_blackfin_icache_flush_range)
-
-/* Flush all cache lines assocoiated with this area of memory. */
-ENTRY(_blackfin_icache_dcache_flush_range)
-	do_flush FLUSH, IFLUSH
-ENDPROC(_blackfin_icache_dcache_flush_range)
-
-/* Throw away all D-cached data in specified region without any obligation to
- * write them back.  Since the Blackfin ISA does not have an "invalidate"
- * instruction, we use flush/invalidate.  Perhaps as a speed optimization we
- * could bang on the DTEST MMRs ...
- */
-ENTRY(_blackfin_dcache_flush_invalidate_range)
-	do_flush FLUSHINV
-ENDPROC(_blackfin_dcache_flush_invalidate_range)
-
-/* Flush all data cache lines assocoiated with this memory area */
-ENTRY(_blackfin_dcache_flush_range)
-	do_flush FLUSH, , , .Ldfr
-ENDPROC(_blackfin_dcache_flush_range)

+ 0 - 415
arch/blackfin/cpu/cpu.c

@@ -1,415 +0,0 @@
-/*
- * U-Boot - cpu.c CPU specific functions
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <serial.h>
-#include <version.h>
-#include <i2c.h>
-
-#include <asm/blackfin.h>
-#include <asm/cplb.h>
-#include <asm/clock.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/trace.h>
-
-#include "cpu.h"
-#include "initcode.h"
-#include "exports.h"
-
-ulong bfin_poweron_retx;
-DECLARE_GLOBAL_DATA_PTR;
-
-#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
-void bfin_core1_start(void)
-{
-#ifdef BF561_FAMILY
-	/* Enable core 1 */
-	bfin_write_SYSCR(bfin_read_SYSCR() & ~0x0020);
-#else
-	/* Enable core 1 */
-	bfin_write32(RCU0_SVECT1, COREB_L1_CODE_START);
-	bfin_write32(RCU0_CRCTL, 0);
-
-	bfin_write32(RCU0_CRCTL, 0x2);
-
-	/* Check if core 1 starts */
-	while (!(bfin_read32(RCU0_CRSTAT) & 0x2))
-		continue;
-
-	bfin_write32(RCU0_CRCTL, 0);
-
-	/* flag to notify cces core 1 application */
-	bfin_write32(SDU0_MSG_SET, (1 << 19));
-#endif
-}
-#endif
-
-__attribute__((always_inline))
-static inline void serial_early_puts(const char *s)
-{
-#ifdef CONFIG_DEBUG_EARLY_SERIAL
-	serial_puts("Early: ");
-	serial_puts(s);
-#endif
-}
-
-static int global_board_data_init(void)
-{
-#ifndef CONFIG_SYS_GBL_DATA_ADDR
-# define CONFIG_SYS_GBL_DATA_ADDR 0
-#endif
-#ifndef CONFIG_SYS_BD_INFO_ADDR
-# define CONFIG_SYS_BD_INFO_ADDR 0
-#endif
-
-	bd_t *bd;
-
-	if (CONFIG_SYS_GBL_DATA_ADDR) {
-		gd = (gd_t *)(CONFIG_SYS_GBL_DATA_ADDR);
-		memset((void *)gd, 0, GENERATED_GBL_DATA_SIZE);
-	} else {
-		static gd_t _bfin_gd;
-		gd = &_bfin_gd;
-	}
-	if (CONFIG_SYS_BD_INFO_ADDR) {
-		bd = (bd_t *)(CONFIG_SYS_BD_INFO_ADDR);
-		memset(bd, 0, GENERATED_BD_INFO_SIZE);
-	} else {
-		static bd_t _bfin_bd;
-		bd = &_bfin_bd;
-	}
-
-	gd->bd = bd;
-
-	bd->bi_r_version = version_string;
-	bd->bi_cpu = __stringify(CONFIG_BFIN_CPU);
-	bd->bi_board_name = CONFIG_SYS_BOARD;
-	bd->bi_vco = get_vco();
-	bd->bi_cclk = get_cclk();
-	bd->bi_sclk = get_sclk();
-	bd->bi_memstart = CONFIG_SYS_SDRAM_BASE;
-	bd->bi_memsize = CONFIG_SYS_MAX_RAM_SIZE;
-
-	gd->ram_size = CONFIG_SYS_MAX_RAM_SIZE;
-
-	return 0;
-}
-
-static void display_global_data(void)
-{
-	bd_t *bd;
-
-#ifndef CONFIG_DEBUG_EARLY_SERIAL
-	return;
-#endif
-
-	bd = gd->bd;
-	printf(" gd: %p\n", gd);
-	printf(" |-flags: %lx\n", gd->flags);
-	printf(" |-board_type: %lx\n", gd->arch.board_type);
-	printf(" |-baudrate: %u\n", gd->baudrate);
-	printf(" |-have_console: %lx\n", gd->have_console);
-	printf(" |-ram_size: %lx\n", gd->ram_size);
-	printf(" |-env_addr: %lx\n", gd->env_addr);
-	printf(" |-env_valid: %lx\n", gd->env_valid);
-	printf(" |-jt(%p): %p\n", gd->jt, gd->jt->get_version);
-	printf(" \\-bd: %p\n", gd->bd);
-	printf("   |-bi_boot_params: %lx\n", bd->bi_boot_params);
-	printf("   |-bi_memstart: %lx\n", bd->bi_memstart);
-	printf("   |-bi_memsize: %lx\n", bd->bi_memsize);
-	printf("   |-bi_flashstart: %lx\n", bd->bi_flashstart);
-	printf("   |-bi_flashsize: %lx\n", bd->bi_flashsize);
-	printf("   \\-bi_flashoffset: %lx\n", bd->bi_flashoffset);
-}
-
-#define CPLB_PAGE_SIZE (4 * 1024 * 1024)
-#define CPLB_PAGE_MASK (~(CPLB_PAGE_SIZE - 1))
-#if defined(__ADSPBF60x__)
-#define CPLB_EX_PAGE_SIZE (16 * 1024 * 1024)
-#define CPLB_EX_PAGE_MASK (~(CPLB_EX_PAGE_SIZE - 1))
-#else
-#define CPLB_EX_PAGE_SIZE CPLB_PAGE_SIZE
-#define CPLB_EX_PAGE_MASK CPLB_PAGE_MASK
-#endif
-void init_cplbtables(void)
-{
-	uint32_t *ICPLB_ADDR, *ICPLB_DATA;
-	uint32_t *DCPLB_ADDR, *DCPLB_DATA;
-	uint32_t extern_memory;
-	size_t i;
-
-	void icplb_add(uint32_t addr, uint32_t data)
-	{
-		bfin_write32(ICPLB_ADDR + i, addr);
-		bfin_write32(ICPLB_DATA + i, data);
-	}
-	void dcplb_add(uint32_t addr, uint32_t data)
-	{
-		bfin_write32(DCPLB_ADDR + i, addr);
-		bfin_write32(DCPLB_DATA + i, data);
-	}
-
-	/* populate a few common entries ... we'll let
-	 * the memory map and cplb exception handler do
-	 * the rest of the work.
-	 */
-	i = 0;
-	ICPLB_ADDR = (uint32_t *)ICPLB_ADDR0;
-	ICPLB_DATA = (uint32_t *)ICPLB_DATA0;
-	DCPLB_ADDR = (uint32_t *)DCPLB_ADDR0;
-	DCPLB_DATA = (uint32_t *)DCPLB_DATA0;
-
-	icplb_add(0xFFA00000, L1_IMEMORY);
-	dcplb_add(0xFF800000, L1_DMEMORY);
-	++i;
-#if defined(__ADSPBF60x__)
-	icplb_add(0x0, 0x0);
-	dcplb_add(CONFIG_SYS_FLASH_BASE, PAGE_SIZE_16MB | CPLB_DIRTY |
-		CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID);
-	++i;
-#endif
-
-	if (CONFIG_MEM_SIZE) {
-		uint32_t mbase = CONFIG_SYS_MONITOR_BASE;
-		uint32_t mend  = mbase + CONFIG_SYS_MONITOR_LEN - 1;
-		mbase &= CPLB_PAGE_MASK;
-		mend &= CPLB_PAGE_MASK;
-
-		icplb_add(mbase, SDRAM_IKERNEL);
-		dcplb_add(mbase, SDRAM_DKERNEL);
-		++i;
-
-		/*
-		 * If the monitor crosses a 4 meg boundary, we'll need
-		 * to lock two entries for it.  We assume it doesn't
-		 * cross two 4 meg boundaries ...
-		 */
-		if (mbase != mend) {
-			icplb_add(mend, SDRAM_IKERNEL);
-			dcplb_add(mend, SDRAM_DKERNEL);
-			++i;
-		}
-	}
-
-#ifndef __ADSPBF60x__
-	icplb_add(0x20000000, SDRAM_INON_CHBL);
-	dcplb_add(0x20000000, SDRAM_EBIU);
-	++i;
-#endif
-
-	/* Add entries for the rest of external RAM up to the bootrom */
-	extern_memory = 0;
-
-#ifdef CONFIG_DEBUG_NULL_PTR
-	icplb_add(extern_memory,
-		  (SDRAM_IKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
-	dcplb_add(extern_memory,
-		  (SDRAM_DKERNEL & ~PAGE_SIZE_MASK) | PAGE_SIZE_1KB);
-	++i;
-	icplb_add(extern_memory, SDRAM_IKERNEL);
-	dcplb_add(extern_memory, SDRAM_DKERNEL);
-	extern_memory += CPLB_PAGE_SIZE;
-	++i;
-#endif
-
-	while (i < 16 && extern_memory <
-		(CONFIG_SYS_MONITOR_BASE & CPLB_EX_PAGE_MASK)) {
-		icplb_add(extern_memory, SDRAM_IGENERIC);
-		dcplb_add(extern_memory, SDRAM_DGENERIC);
-		extern_memory += CPLB_EX_PAGE_SIZE;
-		++i;
-	}
-	while (i < 16) {
-		icplb_add(0, 0);
-		dcplb_add(0, 0);
-		++i;
-	}
-}
-
-int print_cpuinfo(void)
-{
-	char buf[32];
-
-	printf("CPU:   ADSP %s (Detected Rev: 0.%d) (%s boot)\n",
-	       gd->bd->bi_cpu,
-	       bfin_revid(),
-	       get_bfin_boot_mode(CONFIG_BFIN_BOOT_MODE));
-
-	printf("Clock: VCO: %s MHz, ", strmhz(buf, get_vco()));
-	printf("Core: %s MHz, ", strmhz(buf, get_cclk()));
-#if defined(__ADSPBF60x__)
-	printf("System0: %s MHz, ", strmhz(buf, get_sclk0()));
-	printf("System1: %s MHz, ", strmhz(buf, get_sclk1()));
-	printf("Dclk: %s MHz\n", strmhz(buf, get_dclk()));
-#else
-	printf("System: %s MHz\n", strmhz(buf, get_sclk()));
-#endif
-
-	return 0;
-}
-
-int exception_init(void)
-{
-	bfin_write_EVT3(trap);
-	return 0;
-}
-
-int irq_init(void)
-{
-#ifdef SIC_IMASK0
-	bfin_write_SIC_IMASK0(0);
-	bfin_write_SIC_IMASK1(0);
-# ifdef SIC_IMASK2
-	bfin_write_SIC_IMASK2(0);
-# endif
-#elif defined(SICA_IMASK0)
-	bfin_write_SICA_IMASK0(0);
-	bfin_write_SICA_IMASK1(0);
-#elif defined(SIC_IMASK)
-	bfin_write_SIC_IMASK(0);
-#endif
-	/* Set up a dummy NMI handler if needed.  */
-	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS || ANOMALY_05000219)
-		bfin_write_EVT2(evt_nmi);	/* NMI */
-	bfin_write_EVT5(evt_default);	/* hardware error */
-	bfin_write_EVT6(evt_default);	/* core timer */
-	bfin_write_EVT7(evt_default);
-	bfin_write_EVT8(evt_default);
-	bfin_write_EVT9(evt_default);
-	bfin_write_EVT10(evt_default);
-	bfin_write_EVT11(evt_default);
-	bfin_write_EVT12(evt_default);
-	bfin_write_EVT13(evt_default);
-	bfin_write_EVT14(evt_default);
-	bfin_write_EVT15(evt_default);
-	bfin_write_ILAT(0);
-	CSYNC();
-	/* enable hardware error irq */
-	irq_flags = 0x3f;
-	local_irq_enable();
-	return 0;
-}
-
-__attribute__ ((__noreturn__))
-void cpu_init_f(ulong bootflag, ulong loaded_from_ldr)
-{
-#ifndef CONFIG_BFIN_BOOTROM_USES_EVT1
-	/* Build a NOP slide over the LDR jump block.  Whee! */
-	char nops[0xC];
-	serial_early_puts("NOP Slide\n");
-	memset(nops, 0x00, sizeof(nops));
-	memcpy((void *)L1_INST_SRAM, nops, sizeof(nops));
-#endif
-
-	if (!loaded_from_ldr) {
-		/* Relocate sections into L1 if the LDR didn't do it -- don't
-		 * check length because the linker script does the size
-		 * checking at build time.
-		 */
-		serial_early_puts("L1 Relocate\n");
-		extern char _stext_l1[], _text_l1_lma[], _text_l1_len[];
-		memcpy(&_stext_l1, &_text_l1_lma, (unsigned long)_text_l1_len);
-		extern char _sdata_l1[], _data_l1_lma[], _data_l1_len[];
-		memcpy(&_sdata_l1, &_data_l1_lma, (unsigned long)_data_l1_len);
-	}
-
-	/*
-	 * Make sure our async settings are committed.  Some bootroms
-	 * (like the BF537) will reset some registers on us after it
-	 * has finished loading the LDR.  Or if we're booting over
-	 * JTAG, the initcode never got a chance to run.  Or if we
-	 * aren't booting from parallel flash, the initcode skipped
-	 * this step completely.
-	 */
-	program_async_controller(NULL);
-
-	/* Save RETX so we can pass it while booting Linux */
-	bfin_poweron_retx = bootflag;
-
-#ifdef CONFIG_DEBUG_DUMP
-	/* Turn on hardware trace buffer */
-	bfin_write_TBUFCTL(TBUFPWR | TBUFEN);
-#endif
-
-#ifndef CONFIG_PANIC_HANG
-	/* Reset upon a double exception rather than just hanging.
-	 * Do not do bfin_read on SWRST as that will reset status bits.
-	 */
-# ifdef SWRST
-	bfin_write_SWRST(DOUBLE_FAULT);
-# endif
-#endif
-
-#if defined(CONFIG_CORE1_RUN) && defined(COREB_L1_CODE_START)
-	bfin_core1_start();
-#endif
-
-	serial_early_puts("Init global data\n");
-	global_board_data_init();
-
-	board_init_f(0);
-
-	/* should not be reached */
-	while (1);
-}
-
-int arch_cpu_init(void)
-{
-	serial_early_puts("Init CPLB tables\n");
-	init_cplbtables();
-
-	serial_early_puts("Exceptions setup\n");
-	exception_init();
-
-#ifndef CONFIG_ICACHE_OFF
-	serial_early_puts("Turn on ICACHE\n");
-	icache_enable();
-#endif
-#ifndef CONFIG_DCACHE_OFF
-	serial_early_puts("Turn on DCACHE\n");
-	dcache_enable();
-#endif
-
-#ifdef DEBUG
-	if (GENERATED_GBL_DATA_SIZE < sizeof(*gd))
-		hang();
-#endif
-
-	/* Initialize */
-	serial_early_puts("IRQ init\n");
-	irq_init();
-
-	return 0;
-}
-
-int arch_misc_init(void)
-{
-#if defined(CONFIG_SYS_I2C)
-	i2c_reloc_fixup();
-#endif
-
-	display_global_data();
-
-	if (CONFIG_MEM_SIZE && bfin_os_log_check()) {
-		puts("\nLog buffer from operating system:\n");
-		bfin_os_log_dump();
-		puts("\n");
-	}
-
-	return 0;
-}
-
-int interrupt_init(void)
-{
-	return 0;
-}

+ 0 - 23
arch/blackfin/cpu/cpu.h

@@ -1,23 +0,0 @@
-/*
- *  U-Boot - cpu.h
- *
- *  Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _CPU_H_
-#define _CPU_H_
-
-#include <command.h>
-
-void board_reset(void) __attribute__((__weak__));
-void bfin_dump(struct pt_regs *reg);
-void bfin_panic(struct pt_regs *reg);
-void dump(struct pt_regs *regs);
-
-asmlinkage void trap(void);
-asmlinkage void evt_nmi(void);
-asmlinkage void evt_default(void);
-
-#endif

+ 0 - 841
arch/blackfin/cpu/gpio.c

@@ -1,841 +0,0 @@
-/*
- * ADI GPIO1 Abstraction Layer
- * Support BF50x, BF51x, BF52x, BF53x and BF561 only.
- *
- * Copyright 2006-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#include <common.h>
-#include <linux/errno.h>
-#include <asm/gpio.h>
-#include <asm/portmux.h>
-
-#ifndef CONFIG_ADI_GPIO2
-#if ANOMALY_05000311 || ANOMALY_05000323
-enum {
-	AWA_data = SYSCR,
-	AWA_data_clear = SYSCR,
-	AWA_data_set = SYSCR,
-	AWA_toggle = SYSCR,
-	AWA_maska = UART_SCR,
-	AWA_maska_clear = UART_SCR,
-	AWA_maska_set = UART_SCR,
-	AWA_maska_toggle = UART_SCR,
-	AWA_maskb = UART_GCTL,
-	AWA_maskb_clear = UART_GCTL,
-	AWA_maskb_set = UART_GCTL,
-	AWA_maskb_toggle = UART_GCTL,
-	AWA_dir = SPORT1_STAT,
-	AWA_polar = SPORT1_STAT,
-	AWA_edge = SPORT1_STAT,
-	AWA_both = SPORT1_STAT,
-#if ANOMALY_05000311
-	AWA_inen = TIMER_ENABLE,
-#elif ANOMALY_05000323
-	AWA_inen = DMA1_1_CONFIG,
-#endif
-};
-	/* Anomaly Workaround */
-#define AWA_DUMMY_READ(name) bfin_read16(AWA_ ## name)
-#else
-#define AWA_DUMMY_READ(...)  do { } while (0)
-#endif
-
-static struct gpio_port_t * const gpio_array[] = {
-#if defined(BF533_FAMILY)
-	(struct gpio_port_t *) FIO_FLAG_D,
-#elif defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) \
-	|| defined(BF538_FAMILY) || defined(CONFIG_BF50x)
-	(struct gpio_port_t *) PORTFIO,
-# if !defined(BF538_FAMILY)
-	(struct gpio_port_t *) PORTGIO,
-	(struct gpio_port_t *) PORTHIO,
-# endif
-#elif defined(BF561_FAMILY)
-	(struct gpio_port_t *) FIO0_FLAG_D,
-	(struct gpio_port_t *) FIO1_FLAG_D,
-	(struct gpio_port_t *) FIO2_FLAG_D,
-#else
-# error no gpio arrays defined
-#endif
-};
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \
-    defined(CONFIG_BF50x)
-static unsigned short * const port_fer[] = {
-	(unsigned short *) PORTF_FER,
-	(unsigned short *) PORTG_FER,
-	(unsigned short *) PORTH_FER,
-};
-
-# if !defined(BF537_FAMILY)
-static unsigned short * const port_mux[] = {
-	(unsigned short *) PORTF_MUX,
-	(unsigned short *) PORTG_MUX,
-	(unsigned short *) PORTH_MUX,
-};
-
-static const
-u8 pmux_offset[][16] = {
-#  if defined(CONFIG_BF52x)
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 2, 4, 6, 8, 8, 10, 10 }, /* PORTF */
-	{ 0, 0, 0, 0, 0, 2, 2, 4, 4, 6, 8, 10, 10, 10, 12, 12 }, /* PORTG */
-	{ 0, 0, 0, 0, 0, 0, 0, 0, 2, 4, 4, 4, 4, 4, 4, 4 }, /* PORTH */
-#  elif defined(CONFIG_BF51x)
-	{ 0, 2, 2, 2, 2, 2, 2, 4, 6, 6, 6, 8, 8, 8, 8, 10 }, /* PORTF */
-	{ 0, 0, 0, 2, 4, 6, 6, 6, 8, 10, 10, 12, 14, 14, 14, 14 }, /* PORTG */
-	{ 0, 0, 0, 0, 2, 2, 4, 6, 10, 10, 10, 10, 10, 10, 10, 10 }, /* PORTH */
-#  endif
-};
-# endif
-
-#elif defined(BF538_FAMILY)
-static unsigned short * const port_fer[] = {
-	(unsigned short *) PORTCIO_FER,
-	(unsigned short *) PORTDIO_FER,
-	(unsigned short *) PORTEIO_FER,
-};
-#endif
-
-#ifdef CONFIG_BFIN_GPIO_TRACK
-#define RESOURCE_LABEL_SIZE	16
-
-static struct str_ident {
-	char name[RESOURCE_LABEL_SIZE];
-} str_ident[MAX_RESOURCES];
-
-static void gpio_error(unsigned gpio)
-{
-	printf("bfin-gpio: GPIO %d wasn't requested!\n", gpio);
-}
-
-static void set_label(unsigned short ident, const char *label)
-{
-	if (label) {
-		strncpy(str_ident[ident].name, label,
-			 RESOURCE_LABEL_SIZE);
-		str_ident[ident].name[RESOURCE_LABEL_SIZE - 1] = 0;
-	}
-}
-
-static char *get_label(unsigned short ident)
-{
-	return (*str_ident[ident].name ? str_ident[ident].name : "UNKNOWN");
-}
-
-static int cmp_label(unsigned short ident, const char *label)
-{
-	if (label == NULL)
-		printf("bfin-gpio: please provide none-null label\n");
-
-	if (label)
-		return strcmp(str_ident[ident].name, label);
-	else
-		return -EINVAL;
-}
-
-#define map_entry(m, i)      reserved_##m##_map[gpio_bank(i)]
-#define is_reserved(m, i, e) (map_entry(m, i) & gpio_bit(i))
-#define reserve(m, i)        (map_entry(m, i) |= gpio_bit(i))
-#define unreserve(m, i)      (map_entry(m, i) &= ~gpio_bit(i))
-#define DECLARE_RESERVED_MAP(m, c) static unsigned short reserved_##m##_map[c]
-#else
-#define is_reserved(m, i, e) (!(e))
-#define reserve(m, i)
-#define unreserve(m, i)
-#define DECLARE_RESERVED_MAP(m, c)
-#define gpio_error(gpio)
-#define set_label(...)
-#define get_label(...) ""
-#define cmp_label(...) 1
-#endif
-
-DECLARE_RESERVED_MAP(gpio, GPIO_BANK_NUM);
-DECLARE_RESERVED_MAP(peri, gpio_bank(MAX_RESOURCES));
-
-inline int check_gpio(unsigned gpio)
-{
-	if (gpio >= MAX_BLACKFIN_GPIOS)
-		return -EINVAL;
-	return 0;
-}
-
-static void port_setup(unsigned gpio, unsigned short usage)
-{
-#if defined(BF538_FAMILY)
-	/*
-	 * BF538/9 Port C,D and E are special.
-	 * Inverted PORT_FER polarity on CDE and no PORF_FER on F
-	 * Regular PORT F GPIOs are handled here, CDE are exclusively
-	 * managed by GPIOLIB
-	 */
-
-	if (gpio < MAX_BLACKFIN_GPIOS || gpio >= MAX_RESOURCES)
-		return;
-
-	gpio -= MAX_BLACKFIN_GPIOS;
-
-	if (usage == GPIO_USAGE)
-		*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
-	else
-		*port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
-	SSYNC();
-	return;
-#endif
-
-	if (check_gpio(gpio))
-		return;
-
-#if defined(CONFIG_BF52x) || defined(BF537_FAMILY) || defined(CONFIG_BF51x) || \
-    defined(CONFIG_BF50x)
-	if (usage == GPIO_USAGE)
-		*port_fer[gpio_bank(gpio)] &= ~gpio_bit(gpio);
-	else
-		*port_fer[gpio_bank(gpio)] |= gpio_bit(gpio);
-	SSYNC();
-#endif
-}
-
-#ifdef BF537_FAMILY
-static struct {
-	unsigned short res;
-	unsigned short offset;
-} port_mux_lut[] = {
-	{.res = P_PPI0_D13, .offset = 11},
-	{.res = P_PPI0_D14, .offset = 11},
-	{.res = P_PPI0_D15, .offset = 11},
-	{.res = P_SPORT1_TFS, .offset = 11},
-	{.res = P_SPORT1_TSCLK, .offset = 11},
-	{.res = P_SPORT1_DTPRI, .offset = 11},
-	{.res = P_PPI0_D10, .offset = 10},
-	{.res = P_PPI0_D11, .offset = 10},
-	{.res = P_PPI0_D12, .offset = 10},
-	{.res = P_SPORT1_RSCLK, .offset = 10},
-	{.res = P_SPORT1_RFS, .offset = 10},
-	{.res = P_SPORT1_DRPRI, .offset = 10},
-	{.res = P_PPI0_D8, .offset = 9},
-	{.res = P_PPI0_D9, .offset = 9},
-	{.res = P_SPORT1_DRSEC, .offset = 9},
-	{.res = P_SPORT1_DTSEC, .offset = 9},
-	{.res = P_TMR2, .offset = 8},
-	{.res = P_PPI0_FS3, .offset = 8},
-	{.res = P_TMR3, .offset = 7},
-	{.res = P_SPI0_SSEL4, .offset = 7},
-	{.res = P_TMR4, .offset = 6},
-	{.res = P_SPI0_SSEL5, .offset = 6},
-	{.res = P_TMR5, .offset = 5},
-	{.res = P_SPI0_SSEL6, .offset = 5},
-	{.res = P_UART1_RX, .offset = 4},
-	{.res = P_UART1_TX, .offset = 4},
-	{.res = P_TMR6, .offset = 4},
-	{.res = P_TMR7, .offset = 4},
-	{.res = P_UART0_RX, .offset = 3},
-	{.res = P_UART0_TX, .offset = 3},
-	{.res = P_DMAR0, .offset = 3},
-	{.res = P_DMAR1, .offset = 3},
-	{.res = P_SPORT0_DTSEC, .offset = 1},
-	{.res = P_SPORT0_DRSEC, .offset = 1},
-	{.res = P_CAN0_RX, .offset = 1},
-	{.res = P_CAN0_TX, .offset = 1},
-	{.res = P_SPI0_SSEL7, .offset = 1},
-	{.res = P_SPORT0_TFS, .offset = 0},
-	{.res = P_SPORT0_DTPRI, .offset = 0},
-	{.res = P_SPI0_SSEL2, .offset = 0},
-	{.res = P_SPI0_SSEL3, .offset = 0},
-};
-
-static void portmux_setup(unsigned short per)
-{
-	u16 y, offset, muxreg, mask;
-	u16 function = P_FUNCT2MUX(per);
-
-	for (y = 0; y < ARRAY_SIZE(port_mux_lut); y++) {
-		if (port_mux_lut[y].res == per) {
-
-			/* SET PORTMUX REG */
-
-			offset = port_mux_lut[y].offset;
-			muxreg = bfin_read_PORT_MUX();
-
-			if (offset == 1)
-				mask = 3;
-			else
-				mask = 1;
-
-			muxreg &= ~(mask << offset);
-			muxreg |= ((function & mask) << offset);
-			bfin_write_PORT_MUX(muxreg);
-		}
-	}
-}
-#elif defined(CONFIG_BF52x) || defined(CONFIG_BF51x)
-inline void portmux_setup(unsigned short per)
-{
-	u16 pmux, ident = P_IDENT(per), function = P_FUNCT2MUX(per);
-	u8 offset = pmux_offset[gpio_bank(ident)][gpio_sub_n(ident)];
-
-	pmux = *port_mux[gpio_bank(ident)];
-	pmux &= ~(3 << offset);
-	pmux |= (function & 3) << offset;
-	*port_mux[gpio_bank(ident)] = pmux;
-	SSYNC();
-}
-#else
-# define portmux_setup(...)  do { } while (0)
-#endif
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin General Purpose Ports Access Functions
-*
-* INPUTS/OUTPUTS:
-* gpio - GPIO Number between 0 and MAX_BLACKFIN_GPIOS
-*
-*
-* DESCRIPTION: These functions abstract direct register access
-*              to Blackfin processor General Purpose
-*              Ports Regsiters
-*
-* CAUTION: These functions do not belong to the GPIO Driver API
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-/* Set a specific bit */
-
-#define SET_GPIO(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
-	unsigned long flags; \
-	local_irq_save(flags); \
-	if (arg) \
-		gpio_array[gpio_bank(gpio)]->name |= gpio_bit(gpio); \
-	else \
-		gpio_array[gpio_bank(gpio)]->name &= ~gpio_bit(gpio); \
-	AWA_DUMMY_READ(name); \
-	local_irq_restore(flags); \
-}
-
-SET_GPIO(dir)   /* set_gpio_dir() */
-SET_GPIO(inen)  /* set_gpio_inen() */
-SET_GPIO(polar) /* set_gpio_polar() */
-SET_GPIO(edge)  /* set_gpio_edge() */
-SET_GPIO(both)  /* set_gpio_both() */
-
-
-#define SET_GPIO_SC(name) \
-void set_gpio_ ## name(unsigned gpio, unsigned short arg) \
-{ \
-	unsigned long flags; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) \
-		local_irq_save(flags); \
-	if (arg) \
-		gpio_array[gpio_bank(gpio)]->name ## _set = gpio_bit(gpio); \
-	else \
-		gpio_array[gpio_bank(gpio)]->name ## _clear = gpio_bit(gpio); \
-	if (ANOMALY_05000311 || ANOMALY_05000323) { \
-		AWA_DUMMY_READ(name); \
-		local_irq_restore(flags); \
-	} \
-}
-
-SET_GPIO_SC(maska)
-SET_GPIO_SC(maskb)
-SET_GPIO_SC(data)
-
-void set_gpio_toggle(unsigned gpio)
-{
-	unsigned long flags;
-	if (ANOMALY_05000311 || ANOMALY_05000323)
-		local_irq_save(flags);
-	gpio_array[gpio_bank(gpio)]->toggle = gpio_bit(gpio);
-	if (ANOMALY_05000311 || ANOMALY_05000323) {
-		AWA_DUMMY_READ(toggle);
-		local_irq_restore(flags);
-	}
-}
-
-/* Set current PORT date (16-bit word) */
-
-#define SET_GPIO_P(name) \
-void set_gpiop_ ## name(unsigned gpio, unsigned short arg) \
-{ \
-	unsigned long flags; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) \
-		local_irq_save(flags); \
-	gpio_array[gpio_bank(gpio)]->name = arg; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) { \
-		AWA_DUMMY_READ(name); \
-		local_irq_restore(flags); \
-	} \
-}
-
-SET_GPIO_P(data)
-SET_GPIO_P(dir)
-SET_GPIO_P(inen)
-SET_GPIO_P(polar)
-SET_GPIO_P(edge)
-SET_GPIO_P(both)
-SET_GPIO_P(maska)
-SET_GPIO_P(maskb)
-
-/* Get a specific bit */
-#define GET_GPIO(name) \
-unsigned short get_gpio_ ## name(unsigned gpio) \
-{ \
-	unsigned long flags; \
-	unsigned short ret; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) \
-		local_irq_save(flags); \
-	ret = 0x01 & (gpio_array[gpio_bank(gpio)]->name >> gpio_sub_n(gpio)); \
-	if (ANOMALY_05000311 || ANOMALY_05000323) { \
-		AWA_DUMMY_READ(name); \
-		local_irq_restore(flags); \
-	} \
-	return ret; \
-}
-
-GET_GPIO(data)
-GET_GPIO(dir)
-GET_GPIO(inen)
-GET_GPIO(polar)
-GET_GPIO(edge)
-GET_GPIO(both)
-GET_GPIO(maska)
-GET_GPIO(maskb)
-
-/* Get current PORT date (16-bit word) */
-
-#define GET_GPIO_P(name) \
-unsigned short get_gpiop_ ## name(unsigned gpio) \
-{ \
-	unsigned long flags; \
-	unsigned short ret; \
-	if (ANOMALY_05000311 || ANOMALY_05000323) \
-		local_irq_save(flags); \
-	ret = (gpio_array[gpio_bank(gpio)]->name); \
-	if (ANOMALY_05000311 || ANOMALY_05000323) { \
-		AWA_DUMMY_READ(name); \
-		local_irq_restore(flags); \
-	} \
-	return ret; \
-}
-
-GET_GPIO_P(data)
-GET_GPIO_P(dir)
-GET_GPIO_P(inen)
-GET_GPIO_P(polar)
-GET_GPIO_P(edge)
-GET_GPIO_P(both)
-GET_GPIO_P(maska)
-GET_GPIO_P(maskb)
-
-/***********************************************************
-*
-* FUNCTIONS:	Blackfin Peripheral Resource Allocation
-*		and PortMux Setup
-*
-* INPUTS/OUTPUTS:
-* per	Peripheral Identifier
-* label	String
-*
-* DESCRIPTION: Blackfin Peripheral Resource Allocation and Setup API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int peripheral_request(unsigned short per, const char *label)
-{
-	unsigned short ident = P_IDENT(per);
-
-	/*
-	 * Don't cares are pins with only one dedicated function
-	 */
-
-	if (per & P_DONTCARE)
-		return 0;
-
-	if (!(per & P_DEFINED))
-		return -ENODEV;
-
-	BUG_ON(ident >= MAX_RESOURCES);
-
-	/* If a pin can be muxed as either GPIO or peripheral, make
-	 * sure it is not already a GPIO pin when we request it.
-	 */
-	if (unlikely(!check_gpio(ident) && is_reserved(gpio, ident, 1))) {
-		printf("%s: Peripheral %d is already reserved as GPIO by %s !\n",
-		       __func__, ident, get_label(ident));
-		return -EBUSY;
-	}
-
-	if (unlikely(is_reserved(peri, ident, 1))) {
-
-		/*
-		 * Pin functions like AMC address strobes my
-		 * be requested and used by several drivers
-		 */
-
-		if (!(per & P_MAYSHARE)) {
-			/*
-			 * Allow that the identical pin function can
-			 * be requested from the same driver twice
-			 */
-
-			if (cmp_label(ident, label) == 0)
-				goto anyway;
-
-			printf("%s: Peripheral %d function %d is already reserved by %s !\n",
-			       __func__, ident, P_FUNCT2MUX(per), get_label(ident));
-			return -EBUSY;
-		}
-	}
-
- anyway:
-	reserve(peri, ident);
-
-	portmux_setup(per);
-	port_setup(ident, PERIPHERAL_USAGE);
-
-	set_label(ident, label);
-
-	return 0;
-}
-
-int peripheral_request_list(const unsigned short per[], const char *label)
-{
-	u16 cnt;
-	int ret;
-
-	for (cnt = 0; per[cnt] != 0; cnt++) {
-
-		ret = peripheral_request(per[cnt], label);
-
-		if (ret < 0) {
-			for ( ; cnt > 0; cnt--)
-				peripheral_free(per[cnt - 1]);
-
-			return ret;
-		}
-	}
-
-	return 0;
-}
-
-void peripheral_free(unsigned short per)
-{
-	unsigned short ident = P_IDENT(per);
-
-	if (per & P_DONTCARE)
-		return;
-
-	if (!(per & P_DEFINED))
-		return;
-
-	if (unlikely(!is_reserved(peri, ident, 0)))
-		return;
-
-	if (!(per & P_MAYSHARE))
-		port_setup(ident, GPIO_USAGE);
-
-	unreserve(peri, ident);
-
-	set_label(ident, "free");
-}
-
-void peripheral_free_list(const unsigned short per[])
-{
-	u16 cnt;
-	for (cnt = 0; per[cnt] != 0; cnt++)
-		peripheral_free(per[cnt]);
-}
-
-/***********************************************************
-*
-* FUNCTIONS: Blackfin GPIO Driver
-*
-* INPUTS/OUTPUTS:
-* gpio	PIO Number between 0 and MAX_BLACKFIN_GPIOS
-* label	String
-*
-* DESCRIPTION: Blackfin GPIO Driver API
-*
-* CAUTION:
-*************************************************************
-* MODIFICATION HISTORY :
-**************************************************************/
-
-int gpio_request(unsigned gpio, const char *label)
-{
-	if (check_gpio(gpio) < 0)
-		return -EINVAL;
-
-	/*
-	 * Allow that the identical GPIO can
-	 * be requested from the same driver twice
-	 * Do nothing and return -
-	 */
-
-	if (cmp_label(gpio, label) == 0)
-		return 0;
-
-	if (unlikely(is_reserved(gpio, gpio, 1))) {
-		printf("bfin-gpio: GPIO %d is already reserved by %s !\n",
-		       gpio, get_label(gpio));
-		return -EBUSY;
-	}
-	if (unlikely(is_reserved(peri, gpio, 1))) {
-		printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
-		       gpio, get_label(gpio));
-		return -EBUSY;
-	}
-	else {	/* Reset POLAR setting when acquiring a gpio for the first time */
-		set_gpio_polar(gpio, 0);
-	}
-
-	reserve(gpio, gpio);
-	set_label(gpio, label);
-
-	port_setup(gpio, GPIO_USAGE);
-
-	return 0;
-}
-
-int gpio_free(unsigned gpio)
-{
-	if (check_gpio(gpio) < 0)
-		return -1;
-
-	if (unlikely(!is_reserved(gpio, gpio, 0))) {
-		gpio_error(gpio);
-		return -1;
-	}
-
-	unreserve(gpio, gpio);
-
-	set_label(gpio, "free");
-
-	return 0;
-}
-
-#ifdef ADI_SPECIAL_GPIO_BANKS
-DECLARE_RESERVED_MAP(special_gpio, gpio_bank(MAX_RESOURCES));
-
-int special_gpio_request(unsigned gpio, const char *label)
-{
-	/*
-	 * Allow that the identical GPIO can
-	 * be requested from the same driver twice
-	 * Do nothing and return -
-	 */
-
-	if (cmp_label(gpio, label) == 0)
-		return 0;
-
-	if (unlikely(is_reserved(special_gpio, gpio, 1))) {
-		printf("bfin-gpio: GPIO %d is already reserved by %s !\n",
-		       gpio, get_label(gpio));
-		return -EBUSY;
-	}
-	if (unlikely(is_reserved(peri, gpio, 1))) {
-		printf("bfin-gpio: GPIO %d is already reserved as Peripheral by %s !\n",
-		       gpio, get_label(gpio));
-
-		return -EBUSY;
-	}
-
-	reserve(special_gpio, gpio);
-	reserve(peri, gpio);
-
-	set_label(gpio, label);
-	port_setup(gpio, GPIO_USAGE);
-
-	return 0;
-}
-
-void special_gpio_free(unsigned gpio)
-{
-	if (unlikely(!is_reserved(special_gpio, gpio, 0))) {
-		gpio_error(gpio);
-		return;
-	}
-
-	unreserve(special_gpio, gpio);
-	unreserve(peri, gpio);
-	set_label(gpio, "free");
-}
-#endif
-
-static inline void __gpio_direction_input(unsigned gpio)
-{
-	gpio_array[gpio_bank(gpio)]->dir &= ~gpio_bit(gpio);
-	gpio_array[gpio_bank(gpio)]->inen |= gpio_bit(gpio);
-}
-
-int gpio_direction_input(unsigned gpio)
-{
-	unsigned long flags;
-
-	if (!is_reserved(gpio, gpio, 0)) {
-		gpio_error(gpio);
-		return -EINVAL;
-	}
-
-	local_irq_save(flags);
-	__gpio_direction_input(gpio);
-	AWA_DUMMY_READ(inen);
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-int gpio_set_value(unsigned gpio, int arg)
-{
-	if (arg)
-		gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
-	else
-		gpio_array[gpio_bank(gpio)]->data_clear = gpio_bit(gpio);
-
-	return 0;
-}
-
-int gpio_direction_output(unsigned gpio, int value)
-{
-	unsigned long flags;
-
-	if (!is_reserved(gpio, gpio, 0)) {
-		gpio_error(gpio);
-		return -EINVAL;
-	}
-
-	local_irq_save(flags);
-
-	gpio_array[gpio_bank(gpio)]->inen &= ~gpio_bit(gpio);
-	gpio_set_value(gpio, value);
-	gpio_array[gpio_bank(gpio)]->dir |= gpio_bit(gpio);
-
-	AWA_DUMMY_READ(dir);
-	local_irq_restore(flags);
-
-	return 0;
-}
-
-int gpio_get_value(unsigned gpio)
-{
-	unsigned long flags;
-
-	if (unlikely(get_gpio_edge(gpio))) {
-		int ret;
-		local_irq_save(flags);
-		set_gpio_edge(gpio, 0);
-		ret = get_gpio_data(gpio);
-		set_gpio_edge(gpio, 1);
-		local_irq_restore(flags);
-		return ret;
-	} else
-		return get_gpio_data(gpio);
-}
-
-/* If we are booting from SPI and our board lacks a strong enough pull up,
- * the core can reset and execute the bootrom faster than the resistor can
- * pull the signal logically high.  To work around this (common) error in
- * board design, we explicitly set the pin back to GPIO mode, force /CS
- * high, and wait for the electrons to do their thing.
- *
- * This function only makes sense to be called from reset code, but it
- * lives here as we need to force all the GPIO states w/out going through
- * BUG() checks and such.
- */
-void bfin_reset_boot_spi_cs(unsigned short pin)
-{
-	unsigned short gpio = P_IDENT(pin);
-	port_setup(gpio, GPIO_USAGE);
-	gpio_array[gpio_bank(gpio)]->data_set = gpio_bit(gpio);
-	AWA_DUMMY_READ(data_set);
-	udelay(1);
-}
-
-int name_to_gpio(const char *name)
-{
-	int port_base;
-
-	if (tolower(*name) == 'p') {
-		++name;
-
-		switch (tolower(*name)) {
-#ifdef GPIO_PA0
-		case 'a': port_base = GPIO_PA0; break;
-#endif
-#ifdef GPIO_PB0
-		case 'b': port_base = GPIO_PB0; break;
-#endif
-#ifdef GPIO_PC0
-		case 'c': port_base = GPIO_PC0; break;
-#endif
-#ifdef GPIO_PD0
-		case 'd': port_base = GPIO_PD0; break;
-#endif
-#ifdef GPIO_PE0
-		case 'e': port_base = GPIO_PE0; break;
-#endif
-#ifdef GPIO_PF0
-		case 'f': port_base = GPIO_PF0; break;
-#endif
-#ifdef GPIO_PG0
-		case 'g': port_base = GPIO_PG0; break;
-#endif
-#ifdef GPIO_PH0
-		case 'h': port_base = GPIO_PH0; break;
-#endif
-#ifdef GPIO_PI0
-		case 'i': port_base = GPIO_PI0; break;
-#endif
-#ifdef GPIO_PJ
-		case 'j': port_base = GPIO_PJ0; break;
-#endif
-		default:  return -1;
-		}
-
-		++name;
-	} else
-		port_base = 0;
-
-	return port_base + simple_strtoul(name, NULL, 10);
-}
-
-void gpio_labels(void)
-{
-	int c, gpio;
-
-	for (c = 0; c < MAX_RESOURCES; c++) {
-		gpio = is_reserved(gpio, c, 1);
-		if (!check_gpio(c) && gpio)
-			printf("GPIO_%d:\t%s\tGPIO %s\n", c,
-				get_label(c),
-				get_gpio_dir(c) ? "OUTPUT" : "INPUT");
-		else if (is_reserved(peri, c, 1))
-			printf("GPIO_%d:\t%s\tPeripheral\n", c, get_label(c));
-		else
-			continue;
-	}
-}
-#else
-struct gpio_port_t * const gpio_array[] = {
-	(struct gpio_port_t *)PORTA_FER,
-	(struct gpio_port_t *)PORTB_FER,
-	(struct gpio_port_t *)PORTC_FER,
-	(struct gpio_port_t *)PORTD_FER,
-	(struct gpio_port_t *)PORTE_FER,
-	(struct gpio_port_t *)PORTF_FER,
-	(struct gpio_port_t *)PORTG_FER,
-#if defined(CONFIG_BF54x)
-	(struct gpio_port_t *)PORTH_FER,
-	(struct gpio_port_t *)PORTI_FER,
-	(struct gpio_port_t *)PORTJ_FER,
-#endif
-};
-#endif

+ 0 - 9
arch/blackfin/cpu/init.S

@@ -1,9 +0,0 @@
-#include <asm/blackfin.h>
-ENTRY(_start)
-	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
-	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
-	call _initcode;
-1:
-	emuexcpt;
-	jump 1b;
-END(_start)

+ 0 - 25
arch/blackfin/cpu/init.lds.S

@@ -1,25 +0,0 @@
-/*
- * linker script for simple init.elf
- *
- * Copyright (c) 2005-2011 Analog Device Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#undef ALIGN
-#undef ENTRY
-
-OUTPUT_ARCH(bfin)
-
-MEMORY
-{
-	l1_code : ORIGIN = L1_INST_SRAM, LENGTH = L1_INST_SRAM_SIZE
-}
-
-ENTRY(_start)
-SECTIONS
-{
-	.text.l1 : { *(.text .text.*) } >l1_code
-}

+ 0 - 1041
arch/blackfin/cpu/initcode.c

@@ -1,1041 +0,0 @@
-/*
- * initcode.c - Initialize the processor.  This is usually entails things
- * like external memory, voltage regulators, etc...  Note that this file
- * cannot make any function calls as it may be executed all by itself by
- * the Blackfin's bootrom in LDR format.
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#define BFIN_IN_INITCODE
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/watchdog.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/serial.h>
-
-#ifndef __ADSPBF60x__
-#include <asm/mach-common/bits/ebiu.h>
-#include <asm/mach-common/bits/pll.h>
-#else /* __ADSPBF60x__ */
-#include <asm/mach-common/bits/cgu.h>
-
-#define CONFIG_BFIN_GET_DCLK_M \
-	((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
-
-#ifndef CONFIG_DMC_DDRCFG
-#if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
-	(CONFIG_BFIN_GET_DCLK_M != 133) && \
-	(CONFIG_BFIN_GET_DCLK_M != 150) && \
-	(CONFIG_BFIN_GET_DCLK_M != 166) && \
-	(CONFIG_BFIN_GET_DCLK_M != 200) && \
-	(CONFIG_BFIN_GET_DCLK_M != 225) && \
-	(CONFIG_BFIN_GET_DCLK_M != 250))
-#error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
-#endif
-#endif
-
-/* DMC control bits */
-#define SRREQ			0x8
-
-/* DMC status bits */
-#define IDLE                    0x1
-#define MEMINITDONE             0x4
-#define SRACK                   0x8
-#define PDACK                   0x10
-#define DPDACK                  0x20
-#define DLLCALDONE              0x2000
-#define PENDREF                 0xF0000
-#define PHYRDPHASE              0xF00000
-#define PHYRDPHASE_OFFSET       20
-
-/* DMC DLL control bits */
-#define DLLCALRDCNT             0xFF
-#define DATACYC_OFFSET          8
-
-struct ddr_config {
-	u32 ddr_clk;
-	u32 dmc_ddrctl;
-	u32 dmc_ddrcfg;
-	u32 dmc_ddrtr0;
-	u32 dmc_ddrtr1;
-	u32 dmc_ddrtr2;
-	u32 dmc_ddrmr;
-	u32 dmc_ddrmr1;
-};
-
-static struct ddr_config ddr_config_table[] = {
-	[0] = {
-		.ddr_clk    = 125,	/* 125MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20705212,
-		.dmc_ddrtr1 = 0x201003CF,
-		.dmc_ddrtr2 = 0x00320107,
-		.dmc_ddrmr  = 0x00000422,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[1] = {
-		.ddr_clk    = 133,	/* 133MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20806313,
-		.dmc_ddrtr1 = 0x2013040D,
-		.dmc_ddrtr2 = 0x00320108,
-		.dmc_ddrmr  = 0x00000632,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[2] = {
-		.ddr_clk    = 150,	/* 150MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20A07323,
-		.dmc_ddrtr1 = 0x20160492,
-		.dmc_ddrtr2 = 0x00320209,
-		.dmc_ddrmr  = 0x00000632,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[3] = {
-		.ddr_clk    = 166,	/* 166MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20A07323,
-		.dmc_ddrtr1 = 0x2016050E,
-		.dmc_ddrtr2 = 0x00320209,
-		.dmc_ddrmr  = 0x00000632,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[4] = {
-		.ddr_clk    = 200,	/* 200MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20a07323,
-		.dmc_ddrtr1 = 0x2016050f,
-		.dmc_ddrtr2 = 0x00320509,
-		.dmc_ddrmr  = 0x00000632,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[5] = {
-		.ddr_clk    = 225,	/* 225MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20E0A424,
-		.dmc_ddrtr1 = 0x302006DB,
-		.dmc_ddrtr2 = 0x0032020D,
-		.dmc_ddrmr  = 0x00000842,
-		.dmc_ddrmr1 = 0x4,
-	},
-	[6] = {
-		.ddr_clk    = 250,	/* 250MHz */
-		.dmc_ddrctl = 0x00000904,
-		.dmc_ddrcfg = 0x00000422,
-		.dmc_ddrtr0 = 0x20E0A424,
-		.dmc_ddrtr1 = 0x3020079E,
-		.dmc_ddrtr2 = 0x0032050D,
-		.dmc_ddrmr  = 0x00000842,
-		.dmc_ddrmr1 = 0x4,
-	},
-};
-#endif /* __ADSPBF60x__ */
-
-__attribute__((always_inline))
-static inline void serial_init(void)
-{
-#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
-# ifdef BFIN_BOOT_UART_USE_RTS
-#  define BFIN_UART_USE_RTS 1
-# else
-#  define BFIN_UART_USE_RTS 0
-# endif
-	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-		uint32_t uart_base = UART_BASE;
-		size_t i;
-
-		/* force RTS rather than relying on auto RTS */
-#if BFIN_UART_HW_VER < 4
-		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
-#else
-		bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
-				FCPOL);
-#endif
-
-		/* Wait for the line to clear up.  We cannot rely on UART
-		 * registers as none of them reflect the status of the RSR.
-		 * Instead, we'll sleep for ~10 bit times at 9600 baud.
-		 * We can precalc things here by assuming boot values for
-		 * PLL rather than loading registers and calculating.
-		 *	baud    = SCLK / (16 ^ (1 - EDBO) * Divisor)
-		 *	EDB0    = 0
-		 *	Divisor = (SCLK / baud) / 16
-		 *	SCLK    = baud * 16 * Divisor
-		 *	SCLK    = (0x14 * CONFIG_CLKIN_HZ) / 5
-		 *	CCLK    = (16 * Divisor * 5) * (9600 / 10)
-		 * In reality, this will probably be just about 1 second delay,
-		 * so assuming 9600 baud is OK (both as a very low and too high
-		 * speed as this will buffer things enough).
-		 */
-#define _NUMBITS (10)                                   /* how many bits to delay */
-#define _LOWBAUD (9600)                                 /* low baud rate */
-#define _SCLK    ((0x14 * CONFIG_CLKIN_HZ) / 5)         /* SCLK based on PLL */
-#define _DIVISOR ((_SCLK / _LOWBAUD) / 16)              /* UART DLL/DLH */
-#define _NUMINS  (3)                                    /* how many instructions in loop */
-#define _CCLK    (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
-		i = _CCLK;
-		while (i--)
-			asm volatile("" : : : "memory");
-	}
-#endif
-
-#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
-	if (BFIN_DEBUG_EARLY_SERIAL) {
-		serial_early_init(UART_BASE);
-		serial_early_set_baud(UART_BASE, CONFIG_BAUDRATE);
-	}
-#endif
-}
-
-__attribute__((always_inline))
-static inline void serial_deinit(void)
-{
-#if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
-	uint32_t uart_base = UART_BASE;
-
-	if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-		/* clear forced RTS rather than relying on auto RTS */
-#if BFIN_UART_HW_VER < 4
-		bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
-#else
-		bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
-				~FCPOL);
-#endif
-	}
-#endif
-}
-
-__attribute__((always_inline))
-static inline void serial_putc(char c)
-{
-	uint32_t uart_base = UART_BASE;
-
-	if (!BFIN_DEBUG_EARLY_SERIAL)
-		return;
-
-	if (c == '\n')
-		serial_putc('\r');
-
-	bfin_write(&pUART->thr, c);
-
-	while (!(_lsr_read(pUART) & TEMT))
-		continue;
-}
-
-#include "initcode.h"
-
-__attribute__((always_inline)) static inline void
-program_nmi_handler(void)
-{
-	u32 tmp1, tmp2;
-
-	/* Older bootroms don't create a dummy NMI handler,
-	 * so make one ourselves ASAP in case it fires.
-	 */
-	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
-		return;
-
-	asm volatile (
-		"%0 = RETS;" /* Save current RETS */
-		"CALL 1f;"   /* Figure out current PC */
-		"RTN;"       /* The simple NMI handler */
-		"1:"
-		"%1 = RETS;" /* Load addr of NMI handler */
-		"RETS = %0;" /* Restore RETS */
-		"[%2] = %1;" /* Write NMI handler */
-		: "=d"(tmp1), "=d"(tmp2)
-		: "ab"(EVT2)
-	);
-}
-
-/* Max SCLK can be 133MHz ... dividing that by (2*4) gives
- * us a freq of 16MHz for SPI which should generally be
- * slow enough for the slow reads the bootrom uses.
- */
-#if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
-    ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
-     (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
-# define BOOTROM_SUPPORTS_SPI_FAST_READ 1
-#else
-# define BOOTROM_SUPPORTS_SPI_FAST_READ 0
-#endif
-#ifndef CONFIG_SPI_BAUD_INITBLOCK
-# define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
-#endif
-#ifdef SPI0_BAUD
-# define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
-#endif
-
-#ifdef __ADSPBF60x__
-
-#ifndef CONFIG_CGU_CTL_VAL
-# define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
-#endif
-
-#ifndef CONFIG_CGU_DIV_VAL
-# define CONFIG_CGU_DIV_VAL \
-	((CONFIG_CCLK_DIV   << CSEL_P)   | \
-	 (CONFIG_SCLK0_DIV  << S0SEL_P)  | \
-	 (CONFIG_SCLK_DIV << SYSSEL_P) | \
-	 (CONFIG_SCLK1_DIV  << S1SEL_P)  | \
-	 (CONFIG_DCLK_DIV   << DSEL_P)   | \
-	 (CONFIG_OCLK_DIV   << OSEL_P))
-#endif
-
-#else /* __ADSPBF60x__ */
-
-/* PLL_DIV defines */
-#ifndef CONFIG_PLL_DIV_VAL
-# if (CONFIG_CCLK_DIV == 1)
-#  define CONFIG_CCLK_ACT_DIV CCLK_DIV1
-# elif (CONFIG_CCLK_DIV == 2)
-#  define CONFIG_CCLK_ACT_DIV CCLK_DIV2
-# elif (CONFIG_CCLK_DIV == 4)
-#  define CONFIG_CCLK_ACT_DIV CCLK_DIV4
-# elif (CONFIG_CCLK_DIV == 8)
-#  define CONFIG_CCLK_ACT_DIV CCLK_DIV8
-# else
-#  define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
-# endif
-# define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
-#endif
-
-#ifndef CONFIG_PLL_LOCKCNT_VAL
-# define CONFIG_PLL_LOCKCNT_VAL 0x0300
-#endif
-
-#ifndef CONFIG_PLL_CTL_VAL
-# define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
-#endif
-
-/* Make sure our voltage value is sane so we don't blow up! */
-#ifndef CONFIG_VR_CTL_VAL
-# define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
-# if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
-#  define CCLK_VLEV_120	400000000
-#  define CCLK_VLEV_125	533000000
-# elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
-#  define CCLK_VLEV_120	401000000
-#  define CCLK_VLEV_125	401000000
-# elif defined(__ADSPBF561__)
-#  define CCLK_VLEV_120	300000000
-#  define CCLK_VLEV_125	501000000
-# endif
-# if BFIN_CCLK < CCLK_VLEV_120
-#  define CONFIG_VR_CTL_VLEV VLEV_120
-# elif BFIN_CCLK < CCLK_VLEV_125
-#  define CONFIG_VR_CTL_VLEV VLEV_125
-# else
-#  define CONFIG_VR_CTL_VLEV VLEV_130
-# endif
-# if defined(__ADSPBF52x__)	/* TBD; use default */
-#  undef CONFIG_VR_CTL_VLEV
-#  define CONFIG_VR_CTL_VLEV VLEV_110
-# elif defined(__ADSPBF54x__)	/* TBD; use default */
-#  undef CONFIG_VR_CTL_VLEV
-#  define CONFIG_VR_CTL_VLEV VLEV_120
-# elif defined(__ADSPBF538__) || defined(__ADSPBF539__)	/* TBD; use default */
-#  undef CONFIG_VR_CTL_VLEV
-#  define CONFIG_VR_CTL_VLEV VLEV_125
-# endif
-
-# ifdef CONFIG_BFIN_MAC
-#  define CONFIG_VR_CTL_CLKBUF CLKBUFOE
-# else
-#  define CONFIG_VR_CTL_CLKBUF 0
-# endif
-
-# if defined(__ADSPBF52x__)
-#  define CONFIG_VR_CTL_FREQ FREQ_1000
-# else
-#  define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
-# endif
-
-# define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
-#endif
-
-/* some parts do not have an on-chip voltage regulator */
-#if defined(__ADSPBF51x__)
-# define CONFIG_HAS_VR 0
-# undef CONFIG_VR_CTL_VAL
-# define CONFIG_VR_CTL_VAL 0
-#else
-# define CONFIG_HAS_VR 1
-#endif
-
-#if CONFIG_MEM_SIZE
-#ifndef EBIU_RSTCTL
-/* Blackfin with SDRAM */
-#ifndef CONFIG_EBIU_SDBCTL_VAL
-# if CONFIG_MEM_SIZE == 16
-#  define CONFIG_EBSZ_VAL EBSZ_16
-# elif CONFIG_MEM_SIZE == 32
-#  define CONFIG_EBSZ_VAL EBSZ_32
-# elif CONFIG_MEM_SIZE == 64
-#  define CONFIG_EBSZ_VAL EBSZ_64
-# elif CONFIG_MEM_SIZE == 128
-#  define CONFIG_EBSZ_VAL EBSZ_128
-# elif CONFIG_MEM_SIZE == 256
-#  define CONFIG_EBSZ_VAL EBSZ_256
-# elif CONFIG_MEM_SIZE == 512
-#  define CONFIG_EBSZ_VAL EBSZ_512
-# else
-#  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
-# endif
-# if CONFIG_MEM_ADD_WDTH == 8
-#  define CONFIG_EBCAW_VAL EBCAW_8
-# elif CONFIG_MEM_ADD_WDTH == 9
-#  define CONFIG_EBCAW_VAL EBCAW_9
-# elif CONFIG_MEM_ADD_WDTH == 10
-#  define CONFIG_EBCAW_VAL EBCAW_10
-# elif CONFIG_MEM_ADD_WDTH == 11
-#  define CONFIG_EBCAW_VAL EBCAW_11
-# else
-#  error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
-# endif
-# define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
-#endif
-#endif
-#endif
-
-/* Conflicting Column Address Widths Causes SDRAM Errors:
- * EB2CAW and EB3CAW must be the same
- */
-#if ANOMALY_05000362
-# if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
-#  error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
-# endif
-#endif
-
-#endif /*  __ADSPBF60x__ */
-
-__attribute__((always_inline)) static inline void
-program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
-{
-	serial_putc('a');
-
-	/* Save the clock pieces that are used in baud rate calculation */
-	if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-		serial_putc('b');
-#ifdef __ADSPBF60x__
-		*sdivB = bfin_read_CGU_DIV();
-		*sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
-		*vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
-#else
-		*sdivB = bfin_read_PLL_DIV() & 0xf;
-		*vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
-#endif
-		*divB = serial_early_get_div();
-		serial_putc('c');
-	}
-
-	serial_putc('d');
-
-#ifdef CONFIG_HW_WATCHDOG
-# ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
-#  define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
-# endif
-	/* Program the watchdog with an initial timeout of ~20 seconds.
-	 * Hopefully that should be long enough to load the u-boot LDR
-	 * (from wherever) and then the common u-boot code can take over.
-	 * In bypass mode, the start.S would have already set a much lower
-	 * timeout, so don't clobber that.
-	 */
-	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
-		serial_putc('e');
-#ifdef __ADSPBF60x__
-		/* Reset system event controller */
-		bfin_write_SEC_GCTL(0x2);
-		bfin_write_SEC_CCTL(0x2);
-		SSYNC();
-
-		/* Enable fault event input and system reset action in fault
-		 * controller. Route watchdog timeout event to fault interface.
-		 */
-		bfin_write_SEC_FCTL(0xc1);
-		/* Enable watchdog interrupt source */
-		bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
-		SSYNC();
-
-		/* Enable system event controller */
-		bfin_write_SEC_GCTL(0x1);
-		bfin_write_SEC_CCTL(0x1);
-		SSYNC();
-#endif
-		bfin_write_WDOG_CTL(WDDIS);
-		SSYNC();
-		bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
-#if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
-		bfin_write_WDOG_CTL(WDEN);
-#endif
-		serial_putc('f');
-	}
-#endif
-
-	serial_putc('g');
-
-	/* Blackfin bootroms use the SPI slow read opcode instead of the SPI
-	 * fast read, so we need to slow down the SPI clock a lot more during
-	 * boot.  Once we switch over to u-boot's SPI flash driver, we'll
-	 * increase the speed appropriately.
-	 */
-#ifdef SPI_BAUD
-	if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
-		serial_putc('h');
-		if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
-			bs->dFlags |= BFLAG_FASTREAD;
-		bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
-		serial_putc('i');
-	}
-#endif
-
-	serial_putc('j');
-}
-
-__attribute__((always_inline)) static inline bool
-maybe_self_refresh(ADI_BOOT_DATA *bs)
-{
-	serial_putc('a');
-
-	if (!CONFIG_MEM_SIZE)
-		return false;
-
-#ifdef __ADSPBF60x__
-	/* resume from hibernate, return false let ddr initialize */
-	if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
-		serial_putc('b');
-		return false;
-	}
-
-#else /* __ADSPBF60x__ */
-
-	/* If external memory is enabled, put it into self refresh first. */
-#if defined(EBIU_RSTCTL)
-	if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
-		serial_putc('b');
-		bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
-		return true;
-	}
-#elif defined(EBIU_SDGCTL)
-	if (bfin_read_EBIU_SDBCTL() & EBE) {
-		serial_putc('b');
-		bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
-		return true;
-	}
-#endif
-
-#endif /* __ADSPBF60x__ */
-	serial_putc('c');
-
-	return false;
-}
-
-__attribute__((always_inline)) static inline u16
-program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
-{
-	u16 vr_ctl = 0;
-
-	serial_putc('a');
-
-#ifdef __ADSPBF60x__
-	if (bfin_read_DMC0_STAT() & MEMINITDONE) {
-		bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
-		SSYNC();
-		while (!(bfin_read_DMC0_STAT() & SRACK))
-			continue;
-	}
-
-	/* Don't set the same value of MSEL and DF to CGU_CTL */
-	if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
-			!= CONFIG_CGU_CTL_VAL) {
-		bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
-		bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
-		while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
-				!(bfin_read_CGU_STAT() & PLLLK))
-			continue;
-	}
-
-	bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
-	while (bfin_read_CGU_STAT() & CLKSALGN)
-		continue;
-
-	if (bfin_read_DMC0_STAT() & MEMINITDONE) {
-		bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
-		SSYNC();
-		while (bfin_read_DMC0_STAT() & SRACK)
-			continue;
-	}
-
-#else /* __ADSPBF60x__ */
-
-	vr_ctl = bfin_read_VR_CTL();
-
-	serial_putc('b');
-
-	/* If we're entering self refresh, make sure it has happened. */
-	if (put_into_srfs)
-#if defined(EBIU_RSTCTL)
-		while (!(bfin_read_EBIU_RSTCTL() & SRACK))
-			continue;
-#elif defined(EBIU_SDGCTL)
-		while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
-			continue;
-#else
-		;
-#endif
-
-	serial_putc('c');
-
-	/* With newer bootroms, we use the helper function to set up
-	 * the memory controller.  Older bootroms lacks such helpers
-	 * so we do it ourselves.
-	 */
-	if (!ANOMALY_05000386) {
-		serial_putc('d');
-
-		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
-		ADI_SYSCTRL_VALUES memory_settings;
-		uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
-		if (!ANOMALY_05000440)
-			actions |= SYSCTRL_PLLDIV;
-		if (CONFIG_HAS_VR) {
-			actions |= SYSCTRL_VRCTL;
-			if (CONFIG_VR_CTL_VAL & FREQ_MASK)
-				actions |= SYSCTRL_INTVOLTAGE;
-			else
-				actions |= SYSCTRL_EXTVOLTAGE;
-			memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
-		} else
-			actions |= SYSCTRL_EXTVOLTAGE;
-		memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
-		memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
-		memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
-#if ANOMALY_05000432
-		bfin_write_SIC_IWR1(0);
-#endif
-		serial_putc('e');
-		bfrom_SysControl(actions, &memory_settings, NULL);
-		serial_putc('f');
-		if (ANOMALY_05000440)
-			bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
-#if ANOMALY_05000432
-		bfin_write_SIC_IWR1(-1);
-#endif
-#if ANOMALY_05000171
-		bfin_write_SICA_IWR0(-1);
-		bfin_write_SICA_IWR1(-1);
-#endif
-		serial_putc('g');
-	} else {
-		serial_putc('h');
-
-		/* Disable all peripheral wakeups except for the PLL event. */
-#ifdef SIC_IWR0
-		bfin_write_SIC_IWR0(1);
-		bfin_write_SIC_IWR1(0);
-# ifdef SIC_IWR2
-		bfin_write_SIC_IWR2(0);
-# endif
-#elif defined(SICA_IWR0)
-		bfin_write_SICA_IWR0(1);
-		bfin_write_SICA_IWR1(0);
-#elif defined(SIC_IWR)
-		bfin_write_SIC_IWR(1);
-#endif
-
-		serial_putc('i');
-
-		/* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
-		bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
-
-		serial_putc('j');
-
-		/* Only reprogram when needed to avoid triggering unnecessary
-		 * PLL relock sequences.
-		 */
-		if (vr_ctl != CONFIG_VR_CTL_VAL) {
-			serial_putc('?');
-			bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
-			asm("idle;");
-			serial_putc('!');
-		}
-
-		serial_putc('k');
-
-		bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
-
-		serial_putc('l');
-
-		/* Only reprogram when needed to avoid triggering unnecessary
-		 * PLL relock sequences.
-		 */
-		if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
-			serial_putc('?');
-			bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
-			asm("idle;");
-			serial_putc('!');
-		}
-
-		serial_putc('m');
-
-		/* Restore all peripheral wakeups. */
-#ifdef SIC_IWR0
-		bfin_write_SIC_IWR0(-1);
-		bfin_write_SIC_IWR1(-1);
-# ifdef SIC_IWR2
-		bfin_write_SIC_IWR2(-1);
-# endif
-#elif defined(SICA_IWR0)
-		bfin_write_SICA_IWR0(-1);
-		bfin_write_SICA_IWR1(-1);
-#elif defined(SIC_IWR)
-		bfin_write_SIC_IWR(-1);
-#endif
-
-		serial_putc('n');
-	}
-
-#endif /* __ADSPBF60x__ */
-
-	serial_putc('o');
-
-	return vr_ctl;
-}
-
-__attribute__((always_inline)) static inline void
-update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
-{
-	/* Since we've changed the SCLK above, we may need to update
-	 * the UART divisors (UART baud rates are based on SCLK).
-	 * Do the division by hand as there are no native instructions
-	 * for dividing which means we'd generate a libgcc reference.
-	 */
-	unsigned int sdivR, vcoR;
-	unsigned int dividend;
-	unsigned int divisor;
-	unsigned int quotient;
-
-	serial_putc('a');
-
-	if (BFIN_DEBUG_EARLY_SERIAL ||
-		CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
-#ifdef __ADSPBF60x__
-	sdivR = bfin_read_CGU_DIV();
-	sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
-	vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
-#else
-	sdivR = bfin_read_PLL_DIV() & 0xf;
-	vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
-#endif
-
-	dividend = sdivB * divB * vcoR;
-	divisor = vcoB * sdivR;
-	quotient = early_division(dividend, divisor);
-	serial_early_put_div(quotient - ANOMALY_05000230);
-	}
-
-	serial_putc('c');
-}
-
-__attribute__((always_inline)) static inline void
-program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
-{
-	serial_putc('a');
-
-	if (!CONFIG_MEM_SIZE)
-		return;
-
-	serial_putc('b');
-
-#ifdef __ADSPBF60x__
-	int dlldatacycle;
-	int dll_ctl;
-	int i = 0;
-
-	if (CONFIG_BFIN_GET_DCLK_M ==  125)
-		i = 0;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  133)
-		i = 1;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  150)
-		i = 2;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  166)
-		i = 3;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  200)
-		i = 4;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  225)
-		i = 5;
-	else if (CONFIG_BFIN_GET_DCLK_M ==  250)
-		i = 6;
-
-#if 0
-	for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
-		if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
-			break;
-#endif
-
-#ifndef CONFIG_DMC_DDRCFG
-	bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
-#else
-	bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
-#endif
-#ifndef CONFIG_DMC_DDRTR0
-	bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
-#else
-	bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
-#endif
-#ifndef CONFIG_DMC_DDRTR1
-	bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
-#else
-	bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
-#endif
-#ifndef CONFIG_DMC_DDRTR2
-	bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
-#else
-	bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
-#endif
-#ifndef CONFIG_DMC_DDRMR
-	bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
-#else
-	bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
-#endif
-#ifndef CONFIG_DMC_DDREMR1
-	bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
-#else
-	bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
-#endif
-#ifndef CONFIG_DMC_DDRCTL
-	bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
-#else
-	bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
-#endif
-
-	SSYNC();
-	while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
-		continue;
-
-	dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
-			PHYRDPHASE_OFFSET;
-	dll_ctl = bfin_read_DMC0_DLLCTL();
-	dll_ctl &= 0x0ff;
-	bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
-
-	SSYNC();
-	while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
-		continue;
-	serial_putc('!');
-
-#else /* __ADSPBF60x__ */
-
-	/* Program the external memory controller before we come out of
-	 * self-refresh.  This only works with our SDRAM controller.
-	 */
-#ifdef EBIU_SDGCTL
-# ifdef CONFIG_EBIU_SDRRC_VAL
-	bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
-# endif
-# ifdef CONFIG_EBIU_SDBCTL_VAL
-	bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
-# endif
-# ifdef CONFIG_EBIU_SDGCTL_VAL
-	bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
-# endif
-#endif
-
-	serial_putc('c');
-
-	/* Now that we've reprogrammed, take things out of self refresh. */
-	if (put_into_srfs)
-#if defined(EBIU_RSTCTL)
-		bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
-#elif defined(EBIU_SDGCTL)
-		bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
-#endif
-
-	serial_putc('d');
-
-	/* Our DDR controller sucks and cannot be programmed while in
-	 * self-refresh.  So we have to pull it out before programming.
-	 */
-#ifdef EBIU_RSTCTL
-# ifdef CONFIG_EBIU_RSTCTL_VAL
-	bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL0_VAL
-	bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL1_VAL
-	bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL2_VAL
-	bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRCTL3_VAL
-	/* default is disable, so don't need to force this */
-	bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
-# endif
-# ifdef CONFIG_EBIU_DDRQUE_VAL
-	bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
-# endif
-#endif
-
-#endif /* __ADSPBF60x__ */
-	serial_putc('e');
-}
-
-__attribute__((always_inline)) static inline void
-check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
-{
-	serial_putc('a');
-
-	if (!CONFIG_MEM_SIZE)
-		return;
-
-	serial_putc('b');
-#ifdef __ADSPBF60x__
-	if (bfin_read32(DPM0_RESTORE0) != 0) {
-		uint32_t reg = bfin_read_DMC0_CTL();
-		reg &= ~0x8;
-		bfin_write_DMC0_CTL(reg);
-
-		while ((bfin_read_DMC0_STAT() & 0x8))
-			continue;
-		while (!(bfin_read_DMC0_STAT() & 0x1))
-			continue;
-
-		serial_putc('z');
-		uint32_t *hibernate_magic =
-			(uint32_t *)bfin_read32(DPM0_RESTORE4);
-		SSYNC(); /* make sure memory controller is done */
-		if (hibernate_magic[0] == 0xDEADBEEF) {
-			serial_putc('c');
-			SSYNC();
-			bfin_write_EVT15(hibernate_magic[1]);
-			bfin_write_IMASK(EVT_IVG15);
-			__asm__ __volatile__ (
-				/* load reti early to avoid anomaly 281 */
-				"reti = %2;"
-				/* clear hibernate magic */
-				"[%0] = %1;"
-				/* load stack pointer */
-				"SP = [%0 + 8];"
-				/* lower ourselves from reset ivg to ivg15 */
-				"raise 15;"
-				"nop;nop;nop;"
-				"rti;"
-				:
-				: "p"(hibernate_magic),
-				"d"(0x2000 /* jump.s 0 */),
-				"d"(0xffa00000)
-			);
-		}
-
-
-	}
-#else
-	/* Are we coming out of hibernate (suspend to memory) ?
-	 * The memory layout is:
-	 * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
-	 * 0x4: return address
-	 * 0x8: stack pointer
-	 *
-	 * SCKELOW is unreliable on older parts (anomaly 307)
-	 */
-	if (ANOMALY_05000307 || vr_ctl & 0x8000) {
-		uint32_t *hibernate_magic = 0;
-
-		SSYNC();
-		/* cppcheck-suppress nullPointer */
-		if (hibernate_magic[0] == 0xDEADBEEF) {
-			serial_putc('c');
-			bfin_write_EVT15(hibernate_magic[1]);
-			bfin_write_IMASK(EVT_IVG15);
-			__asm__ __volatile__ (
-				/* load reti early to avoid anomaly 281 */
-				"reti = %0;"
-				/* clear hibernate magic */
-				"[%0] = %1;"
-				/* load stack pointer */
-				"SP = [%0 + 8];"
-				/* lower ourselves from reset ivg to ivg15 */
-				"raise 15;"
-				"rti;"
-				:
-				: "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
-			);
-		}
-		serial_putc('d');
-	}
-#endif
-
-	serial_putc('e');
-}
-
-BOOTROM_CALLED_FUNC_ATTR
-void initcode(ADI_BOOT_DATA *bs)
-{
-	ADI_BOOT_DATA bootstruct_scratch;
-
-	/* Setup NMI handler before anything else */
-	program_nmi_handler();
-
-	serial_init();
-
-	serial_putc('A');
-
-	/* If the bootstruct is NULL, then it's because we're loading
-	 * dynamically and not via LDR (bootrom).  So set the struct to
-	 * some scratch space.
-	 */
-	if (!bs)
-		bs = &bootstruct_scratch;
-
-	serial_putc('B');
-	bool put_into_srfs = maybe_self_refresh(bs);
-
-	serial_putc('C');
-	uint sdivB, divB, vcoB;
-	program_early_devices(bs, &sdivB, &divB, &vcoB);
-
-	serial_putc('D');
-	u16 vr_ctl = program_clocks(bs, put_into_srfs);
-
-	serial_putc('E');
-	update_serial_clocks(bs, sdivB, divB, vcoB);
-
-	serial_putc('F');
-	program_memory_controller(bs, put_into_srfs);
-
-	serial_putc('G');
-	check_hibernation(bs, vr_ctl, put_into_srfs);
-
-	serial_putc('H');
-	program_async_controller(bs);
-
-#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
-	serial_putc('I');
-	/* Tell the bootrom where our entry point is so that it knows
-	 * where to jump to when finishing processing the LDR.  This
-	 * allows us to avoid small jump blocks in the LDR, and also
-	 * works around anomaly 05000389 (init address in external
-	 * memory causes bootrom to trigger external addressing IVHW).
-	 */
-	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
-		bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
-#endif
-
-	serial_putc('>');
-	serial_putc('\n');
-
-	serial_deinit();
-}

+ 0 - 123
arch/blackfin/cpu/initcode.h

@@ -1,123 +0,0 @@
-/*
- * Code for early processor initialization
- *
- * Copyright (c) 2004-2011 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BFIN_INITCODE_H__
-#define __BFIN_INITCODE_H__
-
-#include <asm/mach-common/bits/bootrom.h>
-
-#ifndef BFIN_IN_INITCODE
-# define serial_putc(c)
-#endif
-
-#ifndef __ADSPBF60x__
-
-#ifndef CONFIG_EBIU_RSTCTL_VAL
-# define CONFIG_EBIU_RSTCTL_VAL 0 /* only MDDRENABLE is useful */
-#endif
-#if ((CONFIG_EBIU_RSTCTL_VAL & 0xFFFFFFC4) != 0)
-# error invalid EBIU_RSTCTL value: must not set reserved bits
-#endif
-
-#ifndef CONFIG_EBIU_MBSCTL_VAL
-# define CONFIG_EBIU_MBSCTL_VAL 0
-#endif
-
-#if defined(CONFIG_EBIU_DDRQUE_VAL) && ((CONFIG_EBIU_DDRQUE_VAL & 0xFFFF8000) != 0)
-# error invalid EBIU_DDRQUE value: must not set reserved bits
-#endif
-
-#endif /* __ADSPBF60x__ */
-
-__attribute__((always_inline)) static inline void
-program_async_controller(ADI_BOOT_DATA *bs)
-{
-#ifdef BFIN_IN_INITCODE
-	/*
-	 * We really only need to setup the async banks early if we're
-	 * booting out of it.  Otherwise, do it later on in cpu_init.
-	 */
-	if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS &&
-	    CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_PARA)
-		return;
-#endif
-
-	serial_putc('a');
-
-#ifndef __ADSPBF60x__
-	/* Program the async banks controller. */
-#ifdef EBIU_AMGCTL
-	bfin_write_EBIU_AMBCTL0(CONFIG_EBIU_AMBCTL0_VAL);
-	bfin_write_EBIU_AMBCTL1(CONFIG_EBIU_AMBCTL1_VAL);
-	bfin_write_EBIU_AMGCTL(CONFIG_EBIU_AMGCTL_VAL);
-#endif
-
-	serial_putc('b');
-
-	/* Not all parts have these additional MMRs. */
-#ifdef EBIU_MBSCTL
-	bfin_write_EBIU_MBSCTL(CONFIG_EBIU_MBSCTL_VAL);
-#endif
-#ifdef EBIU_MODE
-# ifdef CONFIG_EBIU_MODE_VAL
-	bfin_write_EBIU_MODE(CONFIG_EBIU_MODE_VAL);
-# endif
-# ifdef CONFIG_EBIU_FCTL_VAL
-	bfin_write_EBIU_FCTL(CONFIG_EBIU_FCTL_VAL);
-# endif
-#endif
-
-	serial_putc('c');
-
-#else 	/* __ADSPBF60x__ */
-	/* Program the static memory controller. */
-# ifdef CONFIG_SMC_GCTL_VAL
-	bfin_write_SMC_GCTL(CONFIG_SMC_GCTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B0CTL_VAL
-	bfin_write_SMC_B0CTL(CONFIG_SMC_B0CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B0TIM_VAL
-	bfin_write_SMC_B0TIM(CONFIG_SMC_B0TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B0ETIM_VAL
-	bfin_write_SMC_B0ETIM(CONFIG_SMC_B0ETIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B1CTL_VAL
-	bfin_write_SMC_B1CTL(CONFIG_SMC_B1CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B1TIM_VAL
-	bfin_write_SMC_B1TIM(CONFIG_SMC_B1TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B1ETIM_VAL
-	bfin_write_SMC_B1ETIM(CONFIG_SMC_B1ETIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B2CTL_VAL
-	bfin_write_SMC_B2CTL(CONFIG_SMC_B2CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B2TIM_VAL
-	bfin_write_SMC_B2TIM(CONFIG_SMC_B2TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B2ETIM_VAL
-	bfin_write_SMC_B2ETIM(CONFIG_SMC_B2ETIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B3CTL_VAL
-	bfin_write_SMC_B3CTL(CONFIG_SMC_B3CTL_VAL);
-# endif
-# ifdef CONFIG_SMC_B3TIM_VAL
-	bfin_write_SMC_B3TIM(CONFIG_SMC_B3TIM_VAL);
-# endif
-# ifdef CONFIG_SMC_B3ETIM_VAL
-	bfin_write_SMC_B3ETIM(CONFIG_SMC_B3ETIM_VAL);
-# endif
-
-#endif /* __ADSPBF60x__ */
-	serial_putc('d');
-}
-
-#endif

+ 0 - 157
arch/blackfin/cpu/interrupt.S

@@ -1,157 +0,0 @@
-/*
- * interrupt.S - trampoline default exceptions/interrupts to C handlers
- *
- * Copyright (c) 2005-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/entry.h>
-#include <asm/ptrace.h>
-#include <asm/deferred.h>
-#include <asm/mach-common/bits/core.h>
-
-.text
-
-/* default entry point for exceptions */
-ENTRY(_trap)
-	CONFIG_BFIN_SCRATCH_REG = sp;
-	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
-	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
-	SAVE_ALL_SYS
-
-	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
-	r1 = 3;		/* EVT3 space */
-	sp += -12;
-	call _trap_c;
-	sp += 12;
-
-#ifdef CONFIG_EXCEPTION_DEFER
-	CC = R0 == 0;
-	IF CC JUMP .Lexit_trap;
-
-	/* To avoid double faults, lower our priority to IRQ5 */
-	p4.l = lo(COREMMR_BASE);
-	p4.h = hi(COREMMR_BASE);
-
-	r7.h = _exception_to_level5;
-	r7.l = _exception_to_level5;
-	[p4 + (EVT5 - COREMMR_BASE)] = r7;
-
-	/*
-	 * Save these registers, as they are only valid in exception context
-	 *  (where we are now - as soon as we defer to IRQ5, they can change)
-	 */
-	p5.l = _deferred_regs;
-	p5.h = _deferred_regs;
-	r6 = [p4 + (DCPLB_FAULT_ADDR - COREMMR_BASE)];
-	[p5 + (deferred_regs_DCPLB_FAULT_ADDR * 4)] = r6;
-
-	r6 = [p4 + (ICPLB_FAULT_ADDR - COREMMR_BASE)];
-	[p5 + (deferred_regs_ICPLB_FAULT_ADDR * 4)] = r6;
-
-	/* Save the state of single stepping */
-	r6 = SYSCFG;
-	[p5 + (deferred_regs_SYSCFG * 4)] = r6;
-	/* Clear it while we handle the exception in IRQ5 mode
-	 * RESTORE_ALL_SYS will load it, so all we need to do is store it
-	 * in the right place
-	 */
-	BITCLR(r6, SYSCFG_SSSTEP_P);
-	[SP + PT_SYSCFG] = r6;
-
-	/* Since we are going to clobber RETX, we need to save it */
-	r6 = retx;
-	[p5 + (deferred_regs_retx * 4)] = r6;
-
-	/* Save the current IMASK, since we change in order to jump to level 5 */
-	cli r6;
-	[p5 + (deferred_regs_IMASK * 4)] = r6;
-
-	/* Disable all interrupts, but make sure level 5 is enabled so
-	 * we can switch to that level.
-	 */
-	r6 = 0x3f;
-	sti r6;
-
-	/* Clobber RETX so we don't end up back at a faulting instruction */
-	[sp + PT_RETX] = r7;
-
-	/* In case interrupts are disabled IPEND[4] (global interrupt disable bit)
-	 * clear it (re-enabling interrupts again) by the special sequence of pushing
-	 * RETI onto the stack.  This way we can lower ourselves to IVG5 even if the
-	 * exception was taken after the interrupt handler was called but before it
-	 * got a chance to enable global interrupts itself.
-	 */
-	[--sp] = reti;
-	sp += 4;
-
-	RAISE 5;
-.Lexit_trap:
-#endif
-
-#if ANOMALY_05000257
-	R7  = LC0;
-	LC0 = R7;
-	R7  = LC1;
-	LC1 = R7;
-#endif
-
-	RESTORE_ALL_SYS
-	sp = CONFIG_BFIN_SCRATCH_REG;
-	rtx;
-ENDPROC(_trap)
-
-#ifdef CONFIG_EXCEPTION_DEFER
-/* Deferred (IRQ5) exceptions */
-ENTRY(_exception_to_level5)
-	SAVE_ALL_SYS
-
-	/* Now we have to fix things up */
-	p4.l = lo(EVT5);
-	p4.h = hi(EVT5);
-	r0.l = _evt_default;
-	r0.h = _evt_default;
-	[p4] = r0;
-	csync;
-
-	p4.l = _deferred_regs;
-	p4.h = _deferred_regs;
-	r0 = [p4 + (deferred_regs_retx * 4)];
-	[sp + PT_PC] = r0;
-
-	r0 = [p4 + (deferred_regs_SYSCFG * 4)];
-	[sp + PT_SYSCFG] = r0;
-
-	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
-	r1 = 5;	/* EVT5 space */
-	sp += -12;
-	call _trap_c;
-	sp += 12;
-
-	/* Restore IMASK */
-	r0 = [p4 + (deferred_regs_IMASK * 4)];
-	sti r0;
-
-	RESTORE_ALL_SYS
-
-	rti;
-ENDPROC(_exception_to_level5)
-#endif
-
-/* default entry point for interrupts */
-ENTRY(_evt_default)
-	SAVE_ALL_SYS
-	r0 = sp;	/* stack frame pt_regs pointer argument ==> r0 */
-	sp += -12;
-	call _bfin_panic;
-	sp += 12;
-	RESTORE_ALL_SYS
-	rti;
-ENDPROC(_evt_default)
-
-/* NMI handler */
-ENTRY(_evt_nmi)
-	rtn;
-ENDPROC(_evt_nmi)

+ 0 - 151
arch/blackfin/cpu/interrupts.c

@@ -1,151 +0,0 @@
-/*
- * U-Boot - interrupts.c Interrupt related routines
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * This file is based on interrupts.c
- * Copyright 1996 Roman Zippel
- * Copyright 1999 D. Jeff Dionne <jeff@uclinux.org>
- * Copyright 2000-2001 Lineo, Inc. D. Jefff Dionne <jeff@lineo.ca>
- * Copyright 2002 Arcturus Networks Inc. MaTed <mated@sympatico.ca>
- * Copyright 2003 Metrowerks/Motorola
- * Copyright 2003 Bas Vermeulen <bas@buyways.nl>,
- *			BuyWays B.V. (www.buyways.nl)
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <config.h>
-#include <watchdog.h>
-#include <asm/blackfin.h>
-#include "cpu.h"
-
-static ulong timestamp;
-static ulong last_time;
-static int int_flag;
-
-int irq_flags;			/* needed by asm-blackfin/system.h */
-
-/* Functions just to satisfy the linker */
-
-/*
- * This function is derived from PowerPC code (read timebase as long long).
- * On Blackfin it just returns the timer value.
- */
-unsigned long long get_ticks(void)
-{
-	return get_timer(0);
-}
-
-/*
- * This function is derived from PowerPC code (timebase clock frequency).
- * On Blackfin it returns the number of timer ticks per second.
- */
-ulong get_tbclk(void)
-{
-	return CONFIG_SYS_HZ;
-}
-
-void enable_interrupts(void)
-{
-	local_irq_restore(int_flag);
-}
-
-int disable_interrupts(void)
-{
-	local_irq_save(int_flag);
-	return 1;
-}
-
-void __udelay(unsigned long usec)
-{
-	unsigned long delay, start, stop;
-	unsigned long cclk;
-	cclk = (CONFIG_CCLK_HZ);
-
-	while (usec > 1) {
-		WATCHDOG_RESET();
-
-		/*
-		 * how many clock ticks to delay?
-		 *  - request(in useconds) * clock_ticks(Hz) / useconds/second
-		 */
-		if (usec < 1000) {
-			delay = (usec * (cclk / 244)) >> 12;
-			usec = 0;
-		} else {
-			delay = (1000 * (cclk / 244)) >> 12;
-			usec -= 1000;
-		}
-
-		asm volatile (" %0 = CYCLES;" : "=r" (start));
-		do {
-			asm volatile (" %0 = CYCLES; " : "=r" (stop));
-		} while (stop - start < delay);
-	}
-
-	return;
-}
-
-#define MAX_TIM_LOAD	0xFFFFFFFF
-int timer_init(void)
-{
-	bfin_write_TCNTL(0x1);
-	CSYNC();
-	bfin_write_TSCALE(0x0);
-	bfin_write_TCOUNT(MAX_TIM_LOAD);
-	bfin_write_TPERIOD(MAX_TIM_LOAD);
-	bfin_write_TCNTL(0x7);
-	CSYNC();
-
-	timestamp = 0;
-	last_time = 0;
-
-	return 0;
-}
-
-/*
- * Any network command or flash
- * command is started get_timer shall
- * be called before TCOUNT gets reset,
- * to implement the accurate timeouts.
- *
- * How ever milliconds doesn't return
- * the number that has been elapsed from
- * the last reset.
- *
- * As get_timer is used in the u-boot
- * only for timeouts this should be
- * sufficient
- */
-ulong get_timer(ulong base)
-{
-	ulong milisec;
-
-	/* Number of clocks elapsed */
-	ulong clocks = (MAX_TIM_LOAD - bfin_read_TCOUNT());
-
-	/*
-	 * Find if the TCOUNT is reset
-	 * timestamp gives the number of times
-	 * TCOUNT got reset
-	 */
-	if (clocks < last_time)
-		timestamp++;
-	last_time = clocks;
-
-	/* Get the number of milliseconds */
-	milisec = clocks / (CONFIG_CCLK_HZ / 1000);
-
-	/*
-	 * Find the number of millisonds that
-	 * got elapsed before this TCOUNT cycle
-	 */
-	milisec += timestamp * (MAX_TIM_LOAD / (CONFIG_CCLK_HZ / 1000));
-
-	return (milisec - base);
-}

+ 0 - 228
arch/blackfin/cpu/jtag-console.c

@@ -1,228 +0,0 @@
-/*
- * jtag-console.c - console driver over Blackfin JTAG
- *
- * Copyright (c) 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <malloc.h>
-#include <stdio_dev.h>
-#include <asm/blackfin.h>
-
-#ifdef DEBUG
-# define dprintf(...) serial_printf(__VA_ARGS__)
-#else
-# define dprintf(...) do { if (0) printf(__VA_ARGS__); } while (0)
-#endif
-
-static inline void dprintf_decode(const char *s, uint32_t len)
-{
-	uint32_t i;
-	for (i = 0; i < len; ++i)
-		if (s[i] < 0x20 || s[i] >= 0x7f)
-			dprintf("\\%o", s[i]);
-		else
-			dprintf("%c", s[i]);
-}
-
-static inline uint32_t bfin_write_emudat(uint32_t emudat)
-{
-	__asm__ __volatile__("emudat = %0;" : : "d"(emudat));
-	return emudat;
-}
-
-static inline uint32_t bfin_read_emudat(void)
-{
-	uint32_t emudat;
-	__asm__ __volatile__("%0 = emudat;" : "=d"(emudat));
-	return emudat;
-}
-
-#ifndef CONFIG_JTAG_CONSOLE_TIMEOUT
-# define CONFIG_JTAG_CONSOLE_TIMEOUT 500
-#endif
-
-/* The Blackfin tends to be much much faster than the JTAG hardware. */
-static bool jtag_write_emudat(uint32_t emudat)
-{
-	static bool overflowed = false;
-	ulong timeout = get_timer(0);
-	while (bfin_read_DBGSTAT() & 0x1) {
-		if (overflowed)
-			return overflowed;
-		if (get_timer(timeout) > CONFIG_JTAG_CONSOLE_TIMEOUT)
-			overflowed = true;
-	}
-	overflowed = false;
-	bfin_write_emudat(emudat);
-	return overflowed;
-}
-/* Transmit a buffer.  The format is:
- * [32bit length][actual data]
- */
-static void jtag_send(const char *raw_str, uint32_t len)
-{
-	const char *cooked_str;
-	uint32_t i, ex;
-
-	if (len == 0)
-		return;
-
-	/* Ugh, need to output \r after \n */
-	ex = 0;
-	for (i = 0; i < len; ++i)
-		if (raw_str[i] == '\n')
-			++ex;
-	if (ex) {
-		char *c = malloc(len + ex);
-		cooked_str = c;
-		for (i = 0; i < len; ++i) {
-			*c++ = raw_str[i];
-			if (raw_str[i] == '\n')
-				*c++ = '\r';
-		}
-		len += ex;
-	} else
-		cooked_str = raw_str;
-
-	dprintf("%s(\"", __func__);
-	dprintf_decode(cooked_str, len);
-	dprintf("\", %i)\n", len);
-
-	/* First send the length */
-	if (jtag_write_emudat(len))
-		goto done;
-
-	/* Then send the data */
-	for (i = 0; i < len; i += 4) {
-		uint32_t emudat =
-			(cooked_str[i + 0] <<  0) |
-			(cooked_str[i + 1] <<  8) |
-			(cooked_str[i + 2] << 16) |
-			(cooked_str[i + 3] << 24);
-		if (jtag_write_emudat(emudat)) {
-			bfin_write_emudat(0);
-			goto done;
-		}
-	}
-
- done:
-	if (cooked_str != raw_str)
-		free((char *)cooked_str);
-}
-static void jtag_putc(struct stdio_dev *dev, const char c)
-{
-	jtag_send(&c, 1);
-}
-static void jtag_puts(struct stdio_dev *dev, const char *s)
-{
-	jtag_send(s, strlen(s));
-}
-
-static size_t inbound_len, leftovers_len;
-
-/* Lower layers want to know when jtag has data */
-static int jtag_tstc_dbg(void)
-{
-	int ret = (bfin_read_DBGSTAT() & 0x2);
-	if (ret)
-		dprintf("%s: ret:%i\n", __func__, ret);
-	return ret;
-}
-
-/* Higher layers want to know when any data is available */
-static int jtag_tstc(struct stdio_dev *dev)
-{
-	return jtag_tstc_dbg() || leftovers_len;
-}
-
-/* Receive a buffer.  The format is:
- * [32bit length][actual data]
- */
-static uint32_t leftovers;
-static int jtag_getc(struct stdio_dev *dev)
-{
-	int ret;
-	uint32_t emudat;
-
-	dprintf("%s: inlen:%zu leftlen:%zu left:%x\n", __func__,
-		inbound_len, leftovers_len, leftovers);
-
-	/* see if any data is left over */
-	if (leftovers_len) {
-		--leftovers_len;
-		ret = leftovers & 0xff;
-		leftovers >>= 8;
-		return ret;
-	}
-
-	/* wait for new data ! */
-	while (!jtag_tstc_dbg())
-		continue;
-	emudat = bfin_read_emudat();
-
-	if (inbound_len == 0) {
-		/* grab the length */
-		inbound_len = emudat;
-	} else {
-		/* store the bytes */
-		leftovers_len = min((size_t)4, inbound_len);
-		inbound_len -= leftovers_len;
-		leftovers = emudat;
-	}
-
-	return jtag_getc(dev);
-}
-
-int drv_jtag_console_init(void)
-{
-	struct stdio_dev dev;
-	int ret;
-
-	memset(&dev, 0x00, sizeof(dev));
-	strcpy(dev.name, "jtag");
-	dev.flags = DEV_FLAGS_OUTPUT | DEV_FLAGS_INPUT;
-	dev.putc = jtag_putc;
-	dev.puts = jtag_puts;
-	dev.tstc = jtag_tstc;
-	dev.getc = jtag_getc;
-
-	ret = stdio_register(&dev);
-	return (ret == 0 ? 1 : ret);
-}
-
-#ifdef CONFIG_UART_CONSOLE_IS_JTAG
-#include <serial.h>
-/* Since the JTAG is always available (at power on), allow it to fake a UART */
-void jtag_serial_setbrg(void)
-{
-}
-
-int jtag_serial_init(void)
-{
-	return 0;
-}
-
-static struct serial_device serial_jtag_drv = {
-	.name	= "jtag",
-	.start	= jtag_serial_init,
-	.stop	= NULL,
-	.setbrg	= jtag_serial_setbrg,
-	.putc	= jtag_putc,
-	.puts	= jtag_puts,
-	.tstc	= jtag_tstc,
-	.getc	= jtag_getc,
-};
-
-void bfin_jtag_initialize(void)
-{
-	serial_register(&serial_jtag_drv);
-}
-
-struct serial_device *default_serial_console(void)
-{
-	return &serial_jtag_drv;
-}
-#endif

+ 0 - 30
arch/blackfin/cpu/os_log.c

@@ -1,30 +0,0 @@
-/*
- * functions for handling OS log buffer
- *
- * Copyright (c) 2009 Analog Devices Inc.
- *
- * Licensed under the 2-clause BSD.
- */
-
-#include <common.h>
-
-#define OS_LOG_MAGIC       0xDEADBEEF
-#define OS_LOG_MAGIC_ADDR  ((unsigned long *)0x4f0)
-#define OS_LOG_PTR_ADDR    ((char **)0x4f4)
-
-int bfin_os_log_check(void)
-{
-	if (*OS_LOG_MAGIC_ADDR != OS_LOG_MAGIC)
-		return 0;
-	*OS_LOG_MAGIC_ADDR = 0;
-	return 1;
-}
-
-void bfin_os_log_dump(void)
-{
-	char *log = *OS_LOG_PTR_ADDR;
-	while (*log) {
-		puts(log);
-		log += strlen(log) + 1;
-	}
-}

+ 0 - 96
arch/blackfin/cpu/reset.c

@@ -1,96 +0,0 @@
-/*
- * reset.c - logic for resetting the cpu
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <command.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/bootrom.h>
-#include "cpu.h"
-
-/* A system soft reset makes external memory unusable so force
- * this function into L1.  We use the compiler ssync here rather
- * than SSYNC() because it's safe (no interrupts and such) and
- * we save some L1.  We do not need to force sanity in the SYSCR
- * register as the BMODE selection bit is cleared by the soft
- * reset while the Core B bit (on dual core parts) is cleared by
- * the core reset.
- */
-__attribute__ ((__l1_text__, __noreturn__))
-static void bfin_reset(void)
-{
-#ifdef SWRST
-	/* Wait for completion of "system" events such as cache line
-	 * line fills so that we avoid infinite stalls later on as
-	 * much as possible.  This code is in L1, so it won't trigger
-	 * any such event after this point in time.
-	 */
-	__builtin_bfin_ssync();
-
-	/* Initiate System software reset. */
-	bfin_write_SWRST(0x7);
-
-	/* Due to the way reset is handled in the hardware, we need
-	 * to delay for 10 SCLKS.  The only reliable way to do this is
-	 * to calculate the CCLK/SCLK ratio and multiply 10.  For now,
-	 * we'll assume worse case which is a 1:15 ratio.
-	 */
-	asm(
-		"LSETUP (1f, 1f) LC0 = %0\n"
-		"1: nop;"
-		:
-		: "a" (15 * 10)
-		: "LC0", "LB0", "LT0"
-	);
-
-	/* Clear System software reset */
-	bfin_write_SWRST(0);
-
-	/* The BF526 ROM will crash during reset */
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-	/* Seems to be fixed with newer parts though ... */
-	if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
-		bfin_read_SWRST();
-#endif
-
-	/* Wait for the SWRST write to complete.  Cannot rely on SSYNC
-	 * though as the System state is all reset now.
-	 */
-	asm(
-		"LSETUP (1f, 1f) LC1 = %0\n"
-		"1: nop;"
-		:
-		: "a" (15 * 1)
-		: "LC1", "LB1", "LT1"
-	);
-#endif
-
-	while (1)
-#if defined(__ADSPBF60x__)
-		bfin_write_RCU0_CTL(0x1);
-#else
-		/* Issue core reset */
-		asm("raise 1");
-#endif
-}
-
-/* We need to trampoline ourselves up into L1 since our linker
- * does not have relaxtion support and will only generate a
- * PC relative call with a 25 bit immediate.  This is not enough
- * to get us from the top of SDRAM into L1.
- */
-int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
-{
-	if (board_reset)
-		board_reset();
-	if (ANOMALY_05000353 || ANOMALY_05000386)
-		while (1)
-			asm("jump (%0);" : : "a" (bfin_reset));
-	else
-		bfrom_SoftReset((void *)(L1_SRAM_SCRATCH_END - 20));
-	return 0;
-}

+ 0 - 263
arch/blackfin/cpu/start.S

@@ -1,263 +0,0 @@
-/*
- * U-Boot - start.S Startup file for Blackfin U-Boot
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * This file is based on head.S
- * Copyright (c) 2003  Metrowerks/Motorola
- * Copyright (C) 1998  D. Jeff Dionne <jeff@ryeham.ee.ryerson.ca>,
- *                     Kenneth Albanowski <kjahds@kjahds.com>,
- *                     The Silver Hammer Group, Ltd.
- * (c) 1995, Dionne & Associates
- * (c) 1995, DKG Display Tech.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#include <asm/mach-common/bits/watchdog.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/pll.h>
-#include <asm/serial.h>
-
-/* It may seem odd that we make calls to functions even though we haven't
- * relocated ourselves yet out of {flash,ram,wherever}.  This is OK because
- * the "call" instruction in the Blackfin architecture is actually PC
- * relative.  So we can call functions all we want and not worry about them
- * not being relocated yet.
- */
-
-.text
-ENTRY(_start)
-
-	/* Set our initial stack to L1 scratch space */
-	sp.l = LO(L1_SRAM_SCRATCH_END - 20);
-	sp.h = HI(L1_SRAM_SCRATCH_END - 20);
-
-	/* Optimization register tricks: keep a base value in the
-	 * reserved P registers so we use the load/store with an
-	 * offset syntax.  R0 = [P5 + <constant>];
-	 *   P4 - system MMR base
-	 *   P5 - core MMR base
-	 */
-#ifdef CONFIG_HW_WATCHDOG
-	p4.l = 0;
-	p4.h = HI(SYSMMR_BASE);
-#endif
-	p5.l = 0;
-	p5.h = HI(COREMMR_BASE);
-
-#ifdef CONFIG_HW_WATCHDOG
-	/* Program the watchdog with default timeout of ~5 seconds.
-	 * That should be long enough to bootstrap ourselves up and
-	 * then the common U-Boot code can take over.
-	 */
-	r1 = WDDIS;
-# ifdef __ADSPBF60x__
-	[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# else
-	W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# endif
-	SSYNC;
-	r0 = 0;
-	r0.h = HI(MSEC_TO_SCLK(CONFIG_WATCHDOG_TIMEOUT_MSECS));
-	[p4 + (WDOG_CNT - SYSMMR_BASE)] = r0;
-	SSYNC;
-	r1 = WDEN;
-	/* fire up the watchdog - R0.L above needs to be 0x0000 */
-# ifdef __ADSPBF60x__
-	[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# else
-	W[p4 + (WDOG_CTL - SYSMMR_BASE)] = r1;
-# endif
-	SSYNC;
-#endif
-
-	/* Turn on the serial for debugging the init process */
-	serial_early_init
-	serial_early_set_baud
-
-	serial_early_puts("Init Registers");
-
-	/* Disable self-nested interrupts and enable CYCLES for udelay() */
-	R0 = CCEN | 0x30;
-	SYSCFG = R0;
-
-	/* Zero out registers required by Blackfin ABI.
-	 * http://docs.blackfin.uclinux.org/doku.php?id=application_binary_interface
-	 */
-	r1 = 0 (x);
-	/* Disable circular buffers */
-	l0 = r1;
-	l1 = r1;
-	l2 = r1;
-	l3 = r1;
-	/* Disable hardware loops in case we were started by 'go' */
-	lc0 = r1;
-	lc1 = r1;
-
-	/* Save RETX so we can pass it while booting Linux */
-	r7 = RETX;
-
-#if CONFIG_MEM_SIZE
-	/* Figure out where we are currently executing so that we can decide
-	 * how to best reprogram and relocate things.  We'll pass below:
-	 *  R4: load address of _start
-	 *  R5: current (not load) address of _start
-	 */
-	serial_early_puts("Find ourselves");
-
-	call _get_pc;
-.Loffset:
-	r1.l = .Loffset;
-	r1.h = .Loffset;
-	r4.l = _start;
-	r4.h = _start;
-	r3 = r1 - r4;
-	r5 = r0 - r3;
-
-	/* Inform upper layers if we had to do the relocation ourselves.
-	 * This allows us to detect whether we were loaded by 'go 0x1000'
-	 * or by the bootrom from an LDR.  "R6" is "loaded_from_ldr".
-	 */
-	r6 = 1 (x);
-	cc = r4 == r5;
-	if cc jump .Lnorelocate;
-	r6 = 0 (x);
-
-	/* Turn off caches as they require CPLBs and a CPLB miss requires
-	 * a software exception handler to process it.  But we're about to
-	 * clobber any previous executing software (like U-Boot that just
-	 * launched a new U-Boot via 'go'), so any handler state will be
-	 * unreliable after the memcpy below.
-	 */
-	serial_early_puts("Kill Caches");
-	r0 = 0;
-	[p5 + (IMEM_CONTROL - COREMMR_BASE)] = r0;
-	[p5 + (DMEM_CONTROL - COREMMR_BASE)] = r0;
-	ssync;
-
-	/* In bypass mode, we don't have an LDR with an init block
-	 * so we need to explicitly call it ourselves.  This will
-	 * reprogram our clocks, memory, and setup our async banks.
-	 */
-	serial_early_puts("Program Clocks");
-
-	/* if we're executing >=0x20000000, then we dont need to dma */
-	r3 = 0x0;
-	r3.h = 0x2000;
-	cc = r5 < r3 (iu);
-	if cc jump .Ldma_and_reprogram;
-#else
-	r6 = 1 (x);	/* fake loaded_from_ldr = 1 */
-#endif
-	r0 = 0 (x);	/* set bootstruct to NULL */
-	call _initcode;
-	jump .Lprogrammed;
-
-	/* we're sitting in external memory, so dma into L1 and reprogram */
-.Ldma_and_reprogram:
-	r0.l = LO(L1_INST_SRAM);
-	r0.h = HI(L1_INST_SRAM);
-	r1.l = __initcode_lma;
-	r1.h = __initcode_lma;
-	r2.l = __initcode_len;
-	r2.h = __initcode_len;
-	r1 = r1 - r4;	/* convert r1 from load address of initcode ... */
-	r1 = r1 + r5;	/* ... to current (not load) address of initcode */
-	p3 = r0;
-	call _dma_memcpy_nocache;
-	r0 = 0 (x);	/* set bootstruct to NULL */
-	call (p3);
-
-	/* Since we reprogrammed SCLK, we need to update the serial divisor */
-.Lprogrammed:
-	serial_early_set_baud
-
-#if CONFIG_MEM_SIZE
-	/* Relocate from wherever we are (FLASH/RAM/etc...) to the hardcoded
-	 * monitor location in the end of RAM.  We know that memcpy() only
-	 * uses registers, so it is safe to call here.  Note that this only
-	 * copies to external memory ... we do not start executing out of
-	 * it yet (see "lower to 15" below).
-	 */
-	serial_early_puts("Relocate");
-	r0 = r4;
-	r1 = r5;
-	r2.l = LO(CONFIG_SYS_MONITOR_LEN);
-	r2.h = HI(CONFIG_SYS_MONITOR_LEN);
-	call _memcpy_ASM;
-#endif
-
-.Lnorelocate:
-	/* Initialize BSS section ... we know that memset() does not
-	 * use the BSS, so it is safe to call here.  The bootrom LDR
-	 * takes care of clearing things for us.
-	 */
-	serial_early_puts("Zero BSS");
-	r0.l = __bss_start;
-	r0.h = __bss_start;
-	r1 = 0 (x);
-	r2.l = __bss_len;
-	r2.h = __bss_len;
-	call _memset;
-
-
-	/* Setup the actual stack in external memory */
-	sp.h = HI(CONFIG_STACKBASE);
-	sp.l = LO(CONFIG_STACKBASE);
-	fp = sp;
-
-	/* Now lower ourselves from the highest interrupt level to
-	 * the lowest.  We do this by masking all interrupts but 15,
-	 * setting the 15 handler to ".Lenable_nested", raising the 15
-	 * interrupt, and then returning from the highest interrupt
-	 * level to the dummy "jump" until the interrupt controller
-	 * services the pending 15 interrupt.  If executing out of
-	 * flash, these steps also changes the code flow from flash
-	 * to external memory.
-	 */
-	serial_early_puts("Lower to 15");
-	r0 = r7;
-	r1 = r6;
-	p1.l = .Lenable_nested;
-	p1.h = .Lenable_nested;
-	[p5 + (EVT15 - COREMMR_BASE)] = p1;
-	r7 = EVT_IVG15 (z);
-	sti r7;
-	raise 15;
-	p3.l = .LWAIT_HERE;
-	p3.h = .LWAIT_HERE;
-	reti = p3;
-	rti;
-
-	/* Enable nested interrupts before continuing with cpu init */
-.Lenable_nested:
-	cli r7;
-	[--sp] = reti;
-	jump.l _cpu_init_f;
-
-.LWAIT_HERE:
-	jump .LWAIT_HERE;
-ENDPROC(_start)
-
-LENTRY(_get_pc)
-	r0 = rets;
-#if ANOMALY_05000371
-	NOP;
-	NOP;
-	NOP;
-#endif
-	rts;
-ENDPROC(_get_pc)
-
-ENTRY(_relocate_code)
-	/* Fake relocate code. Setup the new stack only */
-	sp = r0;
-	fp = sp;
-	r0 = p3;
-	r1.h = 0x2000;
-	r1.l = 0x10;
-	jump.l _board_init_r
-ENDPROC(_relocate_code)

+ 0 - 435
arch/blackfin/cpu/traps.c

@@ -1,435 +0,0 @@
-/*
- * U-Boot - traps.c Routines related to interrupts and exceptions
- *
- * Copyright (c) 2005-2008 Analog Devices Inc.
- *
- * This file is based on
- * No original Copyright holder listed,
- * Probabily original (C) Roman Zippel (assigned DJD, 1999)
- *
- * Copyright 2003 Metrowerks - for Blackfin
- * Copyright 2000-2001 Lineo, Inc. D. Jeff Dionne <jeff@lineo.ca>
- * Copyright 1999-2000 D. Jeff Dionne, <jeff@uclinux.org>
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#include <common.h>
-#include <kgdb.h>
-#include <linux/types.h>
-#include <asm/traps.h>
-#include <asm/cplb.h>
-#include <asm/io.h>
-#include <asm/mach-common/bits/core.h>
-#include <asm/mach-common/bits/mpu.h>
-#include <asm/mach-common/bits/trace.h>
-#include <asm/deferred.h>
-#include "cpu.h"
-
-#ifdef CONFIG_DEBUG_DUMP
-# define ENABLE_DUMP 1
-#else
-# define ENABLE_DUMP 0
-#endif
-
-#define trace_buffer_save(x) \
-	do { \
-		if (!ENABLE_DUMP) \
-			break; \
-		(x) = bfin_read_TBUFCTL(); \
-		bfin_write_TBUFCTL((x) & ~TBUFEN); \
-	} while (0)
-
-#define trace_buffer_restore(x) \
-	do { \
-		if (!ENABLE_DUMP) \
-			break; \
-		bfin_write_TBUFCTL((x)); \
-	} while (0);
-
-/* The purpose of this map is to provide a mapping of address<->cplb settings
- * rather than an exact map of what is actually addressable on the part.  This
- * map covers all current Blackfin parts.  If you try to access an address that
- * is in this map but not actually on the part, you won't get an exception and
- * reboot, you'll get an external hardware addressing error and reboot.  Since
- * only the ends matter (you did something wrong and the board reset), the means
- * are largely irrelevant.
- */
-struct memory_map {
-	uint32_t start, end;
-	uint32_t data_flags, inst_flags;
-};
-const struct memory_map const bfin_memory_map[] = {
-	{	/* external memory */
-		.start = 0x00000000,
-		.end   = 0x20000000,
-		.data_flags = SDRAM_DGENERIC,
-		.inst_flags = SDRAM_IGENERIC,
-	},
-	{	/* async banks */
-		.start = 0x20000000,
-		.end   = 0x30000000,
-		.data_flags = SDRAM_EBIU,
-		.inst_flags = SDRAM_INON_CHBL,
-	},
-	{	/* everything on chip */
-		.start = 0xE0000000,
-		.end   = 0xFFFFFFFF,
-		.data_flags = L1_DMEMORY,
-		.inst_flags = L1_IMEMORY,
-	}
-};
-
-#ifdef CONFIG_EXCEPTION_DEFER
-unsigned int deferred_regs[deferred_regs_last];
-#endif
-
-/*
- * Handle all exceptions while running in EVT3 or EVT5
- */
-int trap_c(struct pt_regs *regs, uint32_t level)
-{
-	uint32_t ret = 0;
-	uint32_t trapnr = (regs->seqstat & EXCAUSE);
-	unsigned long tflags;
-	bool data = false;
-
-	/*
-	 * Keep the trace buffer so that a miss here points people
-	 * to the right place (their code).  Crashes here rarely
-	 * happen.  If they do, only the Blackfin maintainer cares.
-	 */
-	trace_buffer_save(tflags);
-
-	switch (trapnr) {
-	/* 0x26 - Data CPLB Miss */
-	case VEC_CPLB_M:
-
-		if (ANOMALY_05000261) {
-			static uint32_t last_cplb_fault_retx;
-			/*
-			 * Work around an anomaly: if we see a new DCPLB fault,
-			 * return without doing anything. Then,
-			 * if we get the same fault again, handle it.
-			 */
-			if (last_cplb_fault_retx != regs->retx) {
-				last_cplb_fault_retx = regs->retx;
-				break;
-			}
-		}
-
-		data = true;
-		/* fall through */
-
-	/* 0x27 - Instruction CPLB Miss */
-	case VEC_CPLB_I_M: {
-		volatile uint32_t *CPLB_ADDR_BASE, *CPLB_DATA_BASE, *CPLB_ADDR, *CPLB_DATA;
-		uint32_t new_cplb_addr = 0, new_cplb_data = 0;
-		static size_t last_evicted;
-		size_t i;
-
-#ifdef CONFIG_EXCEPTION_DEFER
-		/* This should never happen */
-		if (level == 5)
-			bfin_panic(regs);
-#endif
-
-		new_cplb_addr = (data ? bfin_read_DCPLB_FAULT_ADDR() : bfin_read_ICPLB_FAULT_ADDR()) & ~(4 * 1024 * 1024 - 1);
-
-		for (i = 0; i < ARRAY_SIZE(bfin_memory_map); ++i) {
-			/* if the exception is inside this range, lets use it */
-			if (new_cplb_addr >= bfin_memory_map[i].start &&
-			    new_cplb_addr < bfin_memory_map[i].end)
-				break;
-		}
-		if (i == ARRAY_SIZE(bfin_memory_map)) {
-			printf("%cCPLB exception outside of memory map at 0x%p\n",
-				(data ? 'D' : 'I'), (void *)new_cplb_addr);
-			bfin_panic(regs);
-		} else
-			debug("CPLB addr %p matches map 0x%p - 0x%p\n",
-				(void *)new_cplb_addr,
-				(void *)bfin_memory_map[i].start,
-				(void *)bfin_memory_map[i].end);
-		new_cplb_data = (data ? bfin_memory_map[i].data_flags : bfin_memory_map[i].inst_flags);
-
-		if (data) {
-			CPLB_ADDR_BASE = (uint32_t *)DCPLB_ADDR0;
-			CPLB_DATA_BASE = (uint32_t *)DCPLB_DATA0;
-		} else {
-			CPLB_ADDR_BASE = (uint32_t *)ICPLB_ADDR0;
-			CPLB_DATA_BASE = (uint32_t *)ICPLB_DATA0;
-		}
-
-		/* find the next unlocked entry and evict it */
-		i = last_evicted & 0xF;
-		debug("last evicted = %zu\n", i);
-		CPLB_DATA = CPLB_DATA_BASE + i;
-		while (*CPLB_DATA & CPLB_LOCK) {
-			debug("skipping %zu %p - %08X\n", i, CPLB_DATA, *CPLB_DATA);
-			i = (i + 1) & 0xF;	/* wrap around */
-			CPLB_DATA = CPLB_DATA_BASE + i;
-		}
-		CPLB_ADDR = CPLB_ADDR_BASE + i;
-
-		debug("evicting entry %zu: 0x%p 0x%08X\n", i,
-			(void *)*CPLB_ADDR, *CPLB_DATA);
-		last_evicted = i + 1;
-
-		/* need to turn off cplbs whenever we muck with the cplb table */
-#if ENDCPLB != ENICPLB
-# error cplb enable bit violates my sanity
-#endif
-		uint32_t mem_control = (data ? DMEM_CONTROL : IMEM_CONTROL);
-		bfin_write32(mem_control, bfin_read32(mem_control) & ~ENDCPLB);
-		*CPLB_ADDR = new_cplb_addr;
-		*CPLB_DATA = new_cplb_data;
-		bfin_write32(mem_control, bfin_read32(mem_control) | ENDCPLB);
-		SSYNC();
-
-		/* dump current table for debugging purposes */
-		CPLB_ADDR = CPLB_ADDR_BASE;
-		CPLB_DATA = CPLB_DATA_BASE;
-		for (i = 0; i < 16; ++i)
-			debug("%2zu 0x%p 0x%08X\n", i,
-				(void *)*CPLB_ADDR++, *CPLB_DATA++);
-
-		break;
-	}
-#ifdef CONFIG_CMD_KGDB
-	/* Single step
-	 * if we are in IRQ5, just ignore, otherwise defer, and handle it in kgdb
-	 */
-	case VEC_STEP:
-		if (level == 3) {
-			/* If we just returned from an interrupt, the single step
-			 * event is for the RTI instruction.
-			 */
-			if (regs->retx == regs->pc)
-				break;
-			/* we just return if we are single stepping through IRQ5 */
-			if (regs->ipend & 0x20)
-				break;
-			/* Otherwise, turn single stepping off & fall through,
-			 * which defers to IRQ5
-			 */
-			regs->syscfg &= ~1;
-		}
-		/* fall through */
-#endif
-	default:
-#ifdef CONFIG_CMD_KGDB
-		if (level == 3) {
-			/* We need to handle this at EVT5, so try again */
-			bfin_dump(regs);
-			ret = 1;
-			break;
-		}
-		if (debugger_exception_handler && (*debugger_exception_handler)(regs))
-			break;
-#endif
-		bfin_panic(regs);
-	}
-
-	trace_buffer_restore(tflags);
-
-	return ret;
-}
-
-#ifndef CONFIG_KALLSYMS
-const char *symbol_lookup(unsigned long addr, unsigned long *caddr)
-{
-	*caddr = addr;
-	return "N/A";
-}
-#endif
-
-static void decode_address(char *buf, unsigned long address)
-{
-	unsigned long sym_addr;
-	void *paddr = (void *)address;
-	const char *sym = symbol_lookup(address, &sym_addr);
-
-	if (sym) {
-		sprintf(buf, "<0x%p> { %s + 0x%lx }", paddr, sym, address - sym_addr);
-		return;
-	}
-
-	if (!address)
-		sprintf(buf, "<0x%p> /* Maybe null pointer? */", paddr);
-	else if (address >= CONFIG_SYS_MONITOR_BASE &&
-		 address < CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
-		sprintf(buf, "<0x%p> /* somewhere in u-boot */", paddr);
-	else
-		sprintf(buf, "<0x%p> /* unknown address */", paddr);
-}
-
-static char *strhwerrcause(uint16_t hwerrcause)
-{
-	switch (hwerrcause) {
-		case 0x02: return "system mmr error";
-		case 0x03: return "external memory addressing error";
-		case 0x12: return "performance monitor overflow";
-		case 0x18: return "raise 5 instruction";
-		default:   return "undef";
-	}
-}
-
-static char *strexcause(uint16_t excause)
-{
-	switch (excause) {
-		case 0x00 ... 0xf: return "custom exception";
-		case 0x10: return "single step";
-		case 0x11: return "trace buffer full";
-		case 0x21: return "undef inst";
-		case 0x22: return "illegal inst";
-		case 0x23: return "dcplb prot violation";
-		case 0x24: return "misaligned data";
-		case 0x25: return "unrecoverable event";
-		case 0x26: return "dcplb miss";
-		case 0x27: return "multiple dcplb hit";
-		case 0x28: return "emulation watchpoint";
-		case 0x2a: return "misaligned inst";
-		case 0x2b: return "icplb prot violation";
-		case 0x2c: return "icplb miss";
-		case 0x2d: return "multiple icplb hit";
-		case 0x2e: return "illegal use of supervisor resource";
-		default:   return "undef";
-	}
-}
-
-void dump(struct pt_regs *fp)
-{
-	char buf[150];
-	int i;
-	uint16_t hwerrcause, excause;
-
-	if (!ENABLE_DUMP)
-		return;
-
-#ifndef CONFIG_CMD_KGDB
-	/* fp->ipend is normally garbage, so load it ourself */
-	fp->ipend = bfin_read_IPEND();
-#endif
-
-	hwerrcause = (fp->seqstat & HWERRCAUSE) >> HWERRCAUSE_P;
-	excause = (fp->seqstat & EXCAUSE) >> EXCAUSE_P;
-
-	printf("SEQUENCER STATUS:\n");
-	printf(" SEQSTAT: %08lx  IPEND: %04lx  SYSCFG: %04lx\n",
-		fp->seqstat, fp->ipend, fp->syscfg);
-	printf("  HWERRCAUSE: 0x%x: %s\n", hwerrcause, strhwerrcause(hwerrcause));
-	printf("  EXCAUSE   : 0x%x: %s\n", excause, strexcause(excause));
-	for (i = 6; i <= 15; ++i) {
-		if (fp->ipend & (1 << i)) {
-			decode_address(buf, bfin_read32(EVT0 + 4*i));
-			printf("  physical IVG%i asserted : %s\n", i, buf);
-		}
-	}
-	decode_address(buf, fp->rete);
-	printf(" RETE: %s\n", buf);
-	decode_address(buf, fp->retn);
-	printf(" RETN: %s\n", buf);
-	decode_address(buf, fp->retx);
-	printf(" RETX: %s\n", buf);
-	decode_address(buf, fp->rets);
-	printf(" RETS: %s\n", buf);
-	/* we lie and store RETI in "pc" */
-	decode_address(buf, fp->pc);
-	printf(" RETI: %s\n", buf);
-
-	if (fp->seqstat & EXCAUSE) {
-		decode_address(buf, bfin_read_DCPLB_FAULT_ADDR());
-		printf("DCPLB_FAULT_ADDR: %s\n", buf);
-		decode_address(buf, bfin_read_ICPLB_FAULT_ADDR());
-		printf("ICPLB_FAULT_ADDR: %s\n", buf);
-	}
-
-	printf("\nPROCESSOR STATE:\n");
-	printf(" R0 : %08lx    R1 : %08lx    R2 : %08lx    R3 : %08lx\n",
-		fp->r0, fp->r1, fp->r2, fp->r3);
-	printf(" R4 : %08lx    R5 : %08lx    R6 : %08lx    R7 : %08lx\n",
-		fp->r4, fp->r5, fp->r6, fp->r7);
-	printf(" P0 : %08lx    P1 : %08lx    P2 : %08lx    P3 : %08lx\n",
-		fp->p0, fp->p1, fp->p2, fp->p3);
-	printf(" P4 : %08lx    P5 : %08lx    FP : %08lx    SP : %08lx\n",
-		fp->p4, fp->p5, fp->fp, (unsigned long)fp);
-	printf(" LB0: %08lx    LT0: %08lx    LC0: %08lx\n",
-		fp->lb0, fp->lt0, fp->lc0);
-	printf(" LB1: %08lx    LT1: %08lx    LC1: %08lx\n",
-		fp->lb1, fp->lt1, fp->lc1);
-	printf(" B0 : %08lx    L0 : %08lx    M0 : %08lx    I0 : %08lx\n",
-		fp->b0, fp->l0, fp->m0, fp->i0);
-	printf(" B1 : %08lx    L1 : %08lx    M1 : %08lx    I1 : %08lx\n",
-		fp->b1, fp->l1, fp->m1, fp->i1);
-	printf(" B2 : %08lx    L2 : %08lx    M2 : %08lx    I2 : %08lx\n",
-		fp->b2, fp->l2, fp->m2, fp->i2);
-	printf(" B3 : %08lx    L3 : %08lx    M3 : %08lx    I3 : %08lx\n",
-		fp->b3, fp->l3, fp->m3, fp->i3);
-	printf("A0.w: %08lx   A0.x: %08lx   A1.w: %08lx   A1.x: %08lx\n",
-		fp->a0w, fp->a0x, fp->a1w, fp->a1x);
-
-	printf("USP : %08lx  ASTAT: %08lx\n",
-		fp->usp, fp->astat);
-
-	printf("\n");
-}
-
-static void _dump_bfin_trace_buffer(void)
-{
-	char buf[150];
-	int i = 0;
-
-	if (!ENABLE_DUMP)
-		return;
-
-	printf("Hardware Trace:\n");
-
-	if (bfin_read_TBUFSTAT() & TBUFCNT) {
-		for (; bfin_read_TBUFSTAT() & TBUFCNT; i++) {
-			decode_address(buf, bfin_read_TBUF());
-			printf("%4i Target : %s\n", i, buf);
-			decode_address(buf, bfin_read_TBUF());
-			printf("     Source : %s\n", buf);
-		}
-	}
-}
-
-void dump_bfin_trace_buffer(void)
-{
-	unsigned long tflags;
-	trace_buffer_save(tflags);
-	_dump_bfin_trace_buffer();
-	trace_buffer_restore(tflags);
-}
-
-void bfin_dump(struct pt_regs *regs)
-{
-	unsigned long tflags;
-
-	trace_buffer_save(tflags);
-
-	puts(
-		"\n"
-		"\n"
-		"\n"
-		"Ack! Something bad happened to the Blackfin!\n"
-		"\n"
-	);
-	dump(regs);
-	_dump_bfin_trace_buffer();
-	puts("\n");
-
-	trace_buffer_restore(tflags);
-}
-
-void bfin_panic(struct pt_regs *regs)
-{
-	unsigned long tflags;
-	trace_buffer_save(tflags);
-	bfin_dump(regs);
-	panic("PANIC: Blackfin internal error");
-}

+ 0 - 142
arch/blackfin/cpu/u-boot.lds

@@ -1,142 +0,0 @@
-/*
- * U-Boot - u-boot.lds.S
- *
- * Copyright (c) 2005-2010 Analog Device Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#include <config.h>
-#include <asm/blackfin.h>
-#undef ALIGN
-#undef ENTRY
-
-#ifndef LDS_BOARD_TEXT
-# define LDS_BOARD_TEXT
-#endif
-
-/* If we don't actually load anything into L1 data, this will avoid
- * a syntax error.  If we do actually load something into L1 data,
- * we'll get a linker memory load error (which is what we'd want).
- * This is here in the first place so we can quickly test building
- * for different CPU's which may lack non-cache L1 data.
- */
-#ifndef L1_DATA_A_SRAM
-# define L1_DATA_A_SRAM      0
-# define L1_DATA_A_SRAM_SIZE 0
-#endif
-#ifndef L1_DATA_B_SRAM
-# define L1_DATA_B_SRAM      L1_DATA_A_SRAM
-# define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE
-#endif
-
-/* The 0xC offset is so we don't clobber the tiny LDR jump block. */
-#ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
-# define L1_CODE_ORIGIN L1_INST_SRAM
-#else
-# define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
-#endif
-
-OUTPUT_ARCH(bfin)
-
-MEMORY
-{
-#if CONFIG_MEM_SIZE
-	ram     : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
-# define ram_code ram
-# define ram_data ram
-#else
-# define ram_code l1_code
-# define ram_data l1_data
-#endif
-	l1_code : ORIGIN = L1_CODE_ORIGIN,          LENGTH = L1_INST_SRAM_SIZE
-	l1_data : ORIGIN = L1_DATA_B_SRAM,          LENGTH = L1_DATA_B_SRAM_SIZE
-}
-
-ENTRY(_start)
-SECTIONS
-{
-	.text.pre :
-	{
-		arch/blackfin/cpu/start.o (.text .text.*)
-
-		LDS_BOARD_TEXT
-	} >ram_code
-
-	.text.init :
-	{
-		arch/blackfin/cpu/initcode.o (.text .text.*)
-	} >ram_code
-	__initcode_lma = LOADADDR(.text.init);
-	__initcode_len = SIZEOF(.text.init);
-
-	.text :
-	{
-		*(.text .text.*)
-	} >ram_code
-
-	.rodata :
-	{
-		. = ALIGN(4);
-		*(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
-		. = ALIGN(4);
-	} >ram_data
-
-	.data :
-	{
-		. = ALIGN(4);
-		*(.data .data.*)
-		*(.data1)
-		*(.sdata)
-		*(.sdata2)
-		*(.dynamic)
-		CONSTRUCTORS
-	} >ram_data
-
-
-	.u_boot_list : {
-		KEEP(*(SORT(.u_boot_list*)));
-	} >ram_data
-
-	.text_l1 :
-	{
-		. = ALIGN(4);
-		__stext_l1 = .;
-		*(.l1.text)
-		. = ALIGN(4);
-		__etext_l1 = .;
-	} >l1_code AT>ram_code
-	__text_l1_lma = LOADADDR(.text_l1);
-	__text_l1_len = SIZEOF(.text_l1);
-	ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
-
-	.data_l1 :
-	{
-		. = ALIGN(4);
-		__sdata_l1 = .;
-		*(.l1.data)
-		*(.l1.bss)
-		. = ALIGN(4);
-		__edata_l1 = .;
-	} >l1_data AT>ram_data
-	__data_l1_lma = LOADADDR(.data_l1);
-	__data_l1_len = SIZEOF(.data_l1);
-	ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!")
-
-	.bss :
-	{
-		. = ALIGN(4);
-		*(.sbss) *(.scommon)
-		*(.dynbss)
-		*(.bss .bss.*)
-		*(COMMON)
-		. = ALIGN(4);
-	} >ram_data
-	__bss_end = .;
-	__bss_start = ADDR(.bss);
-	__bss_len = SIZEOF(.bss);
-	__init_end = .;
-}

+ 0 - 2377
arch/blackfin/include/asm/bfin_logo_230x230_gzip.h

@@ -1,2377 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where:	'screen'	is the pointer to the frame buffer
- *		'width'	is the screen width
- *		'x'		is the horizontal position
- *		'y'		is the vertical position
- */
-
-#define EASYLOGO_ENABLE_GZIP 37470
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[158700];
-
-#include <video_easylogo.h>
-
-#define	DEF_BFIN_LOGO_WIDTH		230
-#define	DEF_BFIN_LOGO_HEIGHT		230
-#define	DEF_BFIN_LOGO_PIXELS		52900
-#define	DEF_BFIN_LOGO_BPP		24
-#define	DEF_BFIN_LOGO_PIXEL_SIZE	3
-#define	DEF_BFIN_LOGO_SIZE		158700
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x1f, 0x8b, 0x08, 0x00, 0x58, 0x7e, 0x68, 0x47, 0x00, 0x03, 0xec, 0x9d, 0x07, 0x5c, 0x53, 0xe7,
- 0xfe, 0xc6, 0x55, 0xb6, 0x04, 0x42, 0x80, 0x40, 0x26, 0x59, 0x24, 0x04, 0x02, 0x01, 0xc2, 0x86,
- 0x00, 0x61, 0x84, 0xbd, 0xf7, 0x5e, 0x22, 0x22, 0x88, 0xb6, 0x55, 0x71, 0xd4, 0x75, 0x6b, 0x7b,
- 0xfd, 0x54, 0x6b, 0xeb, 0xac, 0xb7, 0xe3, 0x52, 0xad, 0x5e, 0x57, 0xd5, 0xf6, 0xfe, 0x6b, 0x5b,
- 0xab, 0xd6, 0xd6, 0xb6, 0xee, 0x81, 0x5a, 0x95, 0xdb, 0xd6, 0x5d, 0x17, 0x52, 0x07, 0x60, 0xbc,
- 0xc5, 0xf5, 0xbf, 0x4f, 0x38, 0x35, 0x0d, 0x43, 0x2a, 0xdc, 0xaa, 0xb7, 0xf1, 0x3c, 0x9f, 0xa8,
- 0x90, 0x9c, 0x93, 0xf7, 0x3d, 0x9e, 0xef, 0x79, 0xde, 0xe7, 0xf7, 0xe6, 0x9c, 0x93, 0x41, 0x83,
- 0x48, 0xfd, 0x31, 0x1a, 0xdc, 0x9b, 0x9e, 0x76, 0xa7, 0x48, 0x91, 0xd2, 0x8a, 0xa0, 0x71, 0x48,
- 0xa7, 0x8c, 0x8d, 0x8d, 0x4d, 0x3a, 0x65, 0xd6, 0x43, 0xa6, 0xa6, 0xa6, 0x78, 0xde, 0xb8, 0x53,
- 0x46, 0x46, 0x46, 0x24, 0xc3, 0xa4, 0x9e, 0xa4, 0x74, 0x94, 0x82, 0x3d, 0xa0, 0x68, 0x6e, 0x6e,
- 0x6e, 0x61, 0x61, 0x61, 0x69, 0x69, 0x69, 0x6d, 0x6d, 0x6d, 0x63, 0x63, 0x63, 0x6b, 0x6b, 0x67,
- 0x6f, 0x4f, 0x77, 0xe8, 0x2a, 0x7b, 0x7b, 0x7b, 0x5b, 0x5b, 0x5b, 0xbc, 0x6a, 0x65, 0x65, 0x85,
- 0x25, 0xb1, 0x0a, 0x56, 0x24, 0xe8, 0xc5, 0xfb, 0x90, 0xf4, 0x92, 0x7a, 0x4c, 0x22, 0x40, 0x05,
- 0x69, 0xb0, 0xcd, 0xa1, 0x43, 0x87, 0x5a, 0x59, 0x59, 0x83, 0x43, 0x00, 0xc9, 0x62, 0xb1, 0x79,
- 0x3c, 0x9e, 0x48, 0x24, 0x92, 0x4a, 0xa5, 0xee, 0xee, 0xee, 0x5e, 0x5e, 0x5e, 0xde, 0xde, 0x0a,
- 0x85, 0xc2, 0x87, 0x78, 0x78, 0x7b, 0x7b, 0xcb, 0xe5, 0x9e, 0x32, 0x99, 0xcc, 0xc5, 0xc5, 0x45,
- 0x28, 0x14, 0x72, 0x38, 0x1c, 0x47, 0x47, 0x47, 0x80, 0x0d, 0xc2, 0x09, 0x7a, 0x61, 0xbf, 0x84,
- 0xf1, 0x3e, 0xed, 0xed, 0x23, 0x65, 0x38, 0x02, 0x4e, 0x80, 0x0a, 0x68, 0xc1, 0x4e, 0x41, 0x9a,
- 0x9d, 0x9d, 0x1d, 0x8b, 0xc5, 0x12, 0x08, 0x84, 0x6e, 0x6e, 0x6e, 0x00, 0x32, 0x30, 0x30, 0x30,
- 0x3c, 0x5c, 0x15, 0x13, 0x13, 0x9b, 0x9c, 0x9c, 0x9c, 0x99, 0x99, 0x99, 0x97, 0x97, 0x57, 0x58,
- 0x58, 0x58, 0xf4, 0x40, 0x05, 0x05, 0x05, 0xb9, 0xb9, 0xb9, 0x19, 0x19, 0x19, 0x89, 0x89, 0x89,
- 0x51, 0x51, 0xd1, 0x21, 0x21, 0x4a, 0x1f, 0x1f, 0x1f, 0x00, 0x0c, 0xc2, 0xd9, 0x6c, 0x36, 0x9d,
- 0x4e, 0xa7, 0x52, 0xa9, 0xe0, 0x1f, 0xae, 0x4b, 0x72, 0x4b, 0xea, 0xbf, 0x97, 0xce, 0x54, 0xe1,
- 0x87, 0x18, 0xd6, 0x99, 0x4c, 0x96, 0x50, 0x28, 0xf2, 0xf0, 0xf0, 0x08, 0x0c, 0x0c, 0x8a, 0x8e,
- 0x8e, 0x4e, 0x4d, 0x4d, 0xcd, 0xcf, 0xcf, 0x2f, 0x2f, 0x2f, 0xaf, 0xae, 0xae, 0xae, 0xa9, 0xa9,
- 0xc1, 0x0f, 0x59, 0x59, 0x59, 0x49, 0x49, 0xc9, 0xb1, 0xb1, 0xb1, 0x11, 0x11, 0x11, 0xa1, 0xa1,
- 0xa1, 0x51, 0x51, 0x51, 0x09, 0x09, 0x89, 0x19, 0x19, 0x99, 0xc5, 0xc5, 0x25, 0x58, 0xa6, 0xb6,
- 0xb6, 0x76, 0xd8, 0xb0, 0xca, 0x82, 0x82, 0xc2, 0xf4, 0xf4, 0x0c, 0x2c, 0x13, 0x12, 0x12, 0xe2,
- 0xe9, 0xe9, 0x29, 0x12, 0x39, 0x83, 0x7f, 0xd8, 0x35, 0x85, 0x42, 0x41, 0x43, 0x64, 0xd0, 0x25,
- 0x35, 0x30, 0x11, 0xac, 0x62, 0xd4, 0x46, 0xf8, 0xa4, 0xd3, 0x1d, 0x9c, 0x9c, 0x78, 0x6e, 0x6e,
- 0x32, 0x80, 0x0a, 0xd2, 0xb2, 0xb3, 0x73, 0x4a, 0x4a, 0x4a, 0x2b, 0x2a, 0x86, 0x95, 0x95, 0x95,
- 0xc5, 0xc7, 0x27, 0x20, 0x06, 0xc0, 0x2a, 0x41, 0xda, 0xef, 0xbe, 0x27, 0x98, 0x94, 0x48, 0x24,
- 0x6a, 0x75, 0x0c, 0xbc, 0xb7, 0xbc, 0xbc, 0xa2, 0xb4, 0xb4, 0x14, 0xc0, 0x27, 0x24, 0x24, 0x04,
- 0x07, 0x07, 0x23, 0x4e, 0xf0, 0xf9, 0x7c, 0x64, 0x0c, 0x78, 0xb8, 0x8e, 0xdb, 0x27, 0xb0, 0x99,
- 0xa4, 0x0c, 0x40, 0x44, 0x06, 0x00, 0x36, 0x60, 0x15, 0x08, 0x01, 0x24, 0xb9, 0x5c, 0x0e, 0xc3,
- 0x4c, 0x4e, 0x4e, 0x01, 0xa8, 0x70, 0xcb, 0xac, 0xac, 0x6c, 0x95, 0x4a, 0xe5, 0xec, 0xec, 0x8c,
- 0x9c, 0x30, 0xb0, 0x26, 0x70, 0x2c, 0x30, 0x99, 0xcc, 0x80, 0x80, 0x80, 0xf4, 0xf4, 0xf4, 0xa2,
- 0xa2, 0xe2, 0x92, 0x92, 0x92, 0xb4, 0xb4, 0xb4, 0xb0, 0xb0, 0x30, 0x34, 0x84, 0xe6, 0x50, 0xa9,
- 0xc1, 0xd2, 0x91, 0x13, 0xc8, 0xba, 0x8c, 0xd4, 0xef, 0x8a, 0xb0, 0x56, 0x04, 0x4b, 0x0c, 0xd3,
- 0xa8, 0xa7, 0x80, 0x50, 0x78, 0x78, 0x38, 0x06, 0x71, 0x8c, 0xe6, 0x30, 0xc6, 0xc8, 0xc8, 0x48,
- 0x57, 0x57, 0x57, 0x90, 0xfc, 0x47, 0x81, 0x04, 0x0f, 0x07, 0xf9, 0x88, 0x10, 0x88, 0xbe, 0x08,
- 0x15, 0x00, 0x58, 0xa9, 0x0c, 0x45, 0x13, 0xa8, 0xe6, 0x10, 0x42, 0x10, 0x9b, 0xd1, 0x19, 0x12,
- 0x5a, 0x52, 0x0f, 0x13, 0x70, 0x85, 0xb3, 0x61, 0xec, 0x86, 0xb5, 0x8a, 0xc5, 0x62, 0x0c, 0xd6,
- 0x48, 0xaa, 0x95, 0x95, 0x95, 0xa5, 0xa5, 0x65, 0xf0, 0x58, 0x00, 0x3c, 0x60, 0x53, 0xed, 0x5b,
- 0x78, 0x5b, 0x2e, 0x97, 0xab, 0x54, 0x2a, 0xcb, 0xca, 0x80, 0x6d, 0x39, 0x92, 0x86, 0xaf, 0xaf,
- 0x2f, 0x4a, 0x33, 0x74, 0x03, 0x9d, 0x21, 0xcc, 0xf6, 0x71, 0xb4, 0x4b, 0xea, 0x4f, 0x2d, 0x02,
- 0x57, 0xc4, 0x48, 0xd4, 0x41, 0xa8, 0xe5, 0x61, 0xa7, 0x18, 0xac, 0x47, 0x8d, 0x1a, 0x15, 0x1b,
- 0x1b, 0x87, 0x67, 0xf0, 0xd2, 0xe3, 0xee, 0x00, 0x9a, 0x60, 0x30, 0x18, 0x28, 0xe8, 0xd0, 0x68,
- 0x6e, 0x6e, 0x2e, 0x82, 0x07, 0xba, 0xc1, 0x66, 0xb3, 0xa9, 0x54, 0x2a, 0x99, 0x6c, 0x49, 0x75,
- 0x13, 0x81, 0x2b, 0xd8, 0x70, 0x72, 0x72, 0x52, 0x28, 0x14, 0x89, 0x89, 0x89, 0x55, 0x55, 0x55,
- 0x70, 0x3c, 0x81, 0x40, 0xf0, 0x18, 0xc7, 0xe5, 0xde, 0xde, 0x16, 0xcd, 0xc1, 0xcc, 0x8b, 0x8b,
- 0x8b, 0x87, 0x0d, 0x1b, 0x96, 0x9c, 0x9c, 0xec, 0xe7, 0xe7, 0x2f, 0x14, 0x0a, 0x11, 0x51, 0xc8,
- 0x84, 0x40, 0x4a, 0x27, 0xe0, 0x8a, 0x71, 0x19, 0xb8, 0x02, 0x15, 0x3f, 0x3f, 0x3f, 0x84, 0x49,
- 0xe0, 0x9a, 0x91, 0x91, 0x01, 0x67, 0x7b, 0x5c, 0x4d, 0xa2, 0xb8, 0x33, 0x33, 0xb3, 0xa0, 0x52,
- 0xcd, 0x29, 0x14, 0x23, 0x53, 0xd3, 0x9e, 0x1c, 0x22, 0x48, 0x87, 0x85, 0x85, 0x03, 0xda, 0xbc,
- 0xbc, 0x7c, 0x04, 0x69, 0x89, 0x44, 0x82, 0x84, 0x80, 0x72, 0x0c, 0xfd, 0x24, 0xa1, 0x7d, 0xc6,
- 0x05, 0x00, 0xe0, 0x5d, 0x88, 0x8b, 0x18, 0x7f, 0x7d, 0x7c, 0x7c, 0x80, 0x2b, 0x92, 0x24, 0xca,
- 0x76, 0xd4, 0x44, 0x8f, 0xaf, 0x51, 0x54, 0x77, 0x34, 0x16, 0x53, 0x22, 0x97, 0x4b, 0xbd, 0xbd,
- 0xb8, 0x62, 0x89, 0xb5, 0x9d, 0x9d, 0x09, 0x8e, 0x8e, 0xae, 0x28, 0xc2, 0xf3, 0x51, 0xf7, 0xa1,
- 0x22, 0x2b, 0x2d, 0x2d, 0x45, 0x69, 0x86, 0x72, 0xcc, 0xd1, 0xd1, 0x11, 0xd0, 0x92, 0xf1, 0xe0,
- 0x19, 0x17, 0x00, 0x80, 0xa1, 0xc1, 0xc1, 0x3c, 0x3c, 0x3c, 0x30, 0x0a, 0x23, 0x09, 0x04, 0x05,
- 0x05, 0x61, 0x08, 0x7e, 0xac, 0x8d, 0x9a, 0x98, 0x9b, 0xf3, 0xa4, 0xd2, 0xb0, 0x98, 0x98, 0xf8,
- 0xf4, 0xf4, 0xa8, 0xc4, 0x44, 0x45, 0x70, 0x30, 0x57, 0x2c, 0xa6, 0xd0, 0x68, 0x20, 0x59, 0x7f,
- 0x31, 0x90, 0x89, 0x94, 0x92, 0x9d, 0x9d, 0x53, 0x51, 0x51, 0x81, 0x5c, 0xed, 0xe2, 0x22, 0xb5,
- 0xb7, 0xa7, 0xa3, 0x6f, 0x8f, 0x32, 0xf7, 0x4b, 0xca, 0x20, 0x45, 0xc4, 0x57, 0xa4, 0x44, 0xb1,
- 0x58, 0xac, 0x56, 0xab, 0x4b, 0x4b, 0xcb, 0x30, 0x04, 0x03, 0xe0, 0xc7, 0xdd, 0x2e, 0xc2, 0x80,
- 0x1b, 0xfc, 0x3c, 0x37, 0xaf, 0xaa, 0xa6, 0x66, 0x04, 0xea, 0xac, 0x92, 0x92, 0xc8, 0x84, 0x04,
- 0x99, 0x8f, 0x8f, 0x1d, 0x8b, 0x65, 0xd4, 0xa3, 0xc4, 0x03, 0xa5, 0x28, 0xc4, 0xca, 0xca, 0xb4,
- 0x7d, 0x73, 0x76, 0x16, 0xa3, 0xb7, 0x88, 0x2b, 0xe4, 0xec, 0xc1, 0x33, 0x28, 0x22, 0x0f, 0x58,
- 0x59, 0x59, 0x71, 0xb9, 0xdc, 0xc0, 0xc0, 0xc0, 0xa2, 0xa2, 0xe2, 0xcc, 0xcc, 0xcc, 0x27, 0x80,
- 0x2b, 0x44, 0xb1, 0xb1, 0xf1, 0x0b, 0x0b, 0x2d, 0x19, 0x36, 0x6c, 0xca, 0xb4, 0xe9, 0xb3, 0x5e,
- 0x9d, 0x3d, 0xe1, 0xc5, 0x29, 0xc3, 0x46, 0x8c, 0x48, 0xcc, 0xc8, 0x80, 0xd9, 0x32, 0xf8, 0x3c,
- 0xa3, 0x1e, 0xf9, 0x19, 0x79, 0xa0, 0xa0, 0xa0, 0x00, 0x09, 0x21, 0x38, 0x38, 0x18, 0x61, 0x1b,
- 0x91, 0x9b, 0x0c, 0xb4, 0xcf, 0xa0, 0x60, 0x53, 0x18, 0x61, 0x01, 0x03, 0xe2, 0x62, 0x5a, 0x5a,
- 0x5a, 0x65, 0x65, 0xa5, 0x9d, 0x9d, 0xdd, 0x93, 0x68, 0x78, 0xf0, 0x60, 0xaa, 0x83, 0x03, 0x22,
- 0x41, 0xcd, 0xe8, 0xd1, 0xaf, 0xce, 0x79, 0x6d, 0xfe, 0xc2, 0x45, 0xb3, 0x5f, 0x9b, 0x3b, 0x61,
- 0xf2, 0xe4, 0x8a, 0xea, 0xea, 0xc4, 0x8c, 0x4c, 0xdf, 0x90, 0x10, 0x06, 0x9f, 0x6f, 0xd4, 0x35,
- 0x45, 0x03, 0x4e, 0x0e, 0x87, 0x53, 0x5c, 0x5c, 0x92, 0x93, 0x93, 0xe3, 0xef, 0xef, 0xcf, 0x66,
- 0x73, 0x10, 0x68, 0xc9, 0xa9, 0x83, 0x67, 0x4d, 0xd8, 0xe3, 0x30, 0x2b, 0x91, 0x48, 0x14, 0x11,
- 0x11, 0x39, 0x7c, 0x78, 0x95, 0xa7, 0xa7, 0xe7, 0x93, 0x69, 0x77, 0xf0, 0x90, 0x21, 0xf6, 0x6c,
- 0xb6, 0x3a, 0x29, 0xe9, 0xf9, 0xf1, 0xe3, 0xe7, 0xbe, 0xfe, 0xc6, 0xeb, 0xf3, 0xe6, 0xbf, 0x3c,
- 0x6b, 0xd6, 0xd8, 0x09, 0x13, 0x2b, 0x47, 0x8e, 0xcc, 0x2a, 0x28, 0x50, 0xc5, 0xc6, 0xba, 0x29,
- 0x14, 0x34, 0x16, 0x6b, 0x48, 0xd7, 0x78, 0x80, 0xe3, 0xcb, 0xdd, 0xdd, 0x1d, 0x55, 0x61, 0x4a,
- 0x4a, 0x0a, 0x22, 0x37, 0x9d, 0x4e, 0x47, 0x6d, 0x48, 0x66, 0x83, 0x67, 0x47, 0xd8, 0xd7, 0xd8,
- 0xe3, 0x30, 0x58, 0x6f, 0x6f, 0xef, 0xec, 0xec, 0xec, 0x92, 0x92, 0x92, 0x27, 0xf0, 0x19, 0xc1,
- 0xaf, 0x4d, 0x1b, 0x19, 0x39, 0xf2, 0x78, 0xf1, 0xa9, 0x69, 0xcf, 0x8f, 0x1b, 0xff, 0x97, 0x99,
- 0x33, 0x27, 0x4e, 0x99, 0x52, 0x3b, 0xe6, 0xb9, 0x92, 0xca, 0xca, 0xf4, 0xbc, 0x3c, 0x60, 0x1c,
- 0xa0, 0x52, 0x49, 0xbd, 0xbd, 0xe9, 0x3c, 0x27, 0xe3, 0x1e, 0xf9, 0x04, 0x1d, 0x8e, 0x8a, 0x8a,
- 0x2a, 0x2f, 0xd7, 0x56, 0x61, 0x42, 0xa1, 0xd0, 0xc6, 0xc6, 0xc6, 0xb4, 0xb7, 0x99, 0x31, 0x52,
- 0x06, 0x29, 0x94, 0xdb, 0x48, 0xb0, 0x7c, 0x3e, 0x5f, 0xa5, 0x52, 0x21, 0x0f, 0x78, 0x78, 0xc8,
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- 0xc3, 0xc3, 0x83, 0x51, 0x5d, 0x9d, 0x98, 0x94, 0xe4, 0xe9, 0xe9, 0x69, 0x41, 0x74, 0x87, 0xad,
- 0x9f, 0x3f, 0x7f, 0x3e, 0x90, 0x40, 0x8d, 0xa4, 0xfd, 0xa3, 0xa1, 0x3a, 0x86, 0x49, 0xa0, 0x17,
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- 0xcd, 0x9a, 0xb5, 0x88, 0x89, 0x0e, 0x19, 0x1b, 0x9f, 0xb4, 0x3c, 0x78, 0xeb, 0x88, 0x76, 0x80,
- 0xe5, 0xfa, 0x48, 0xeb, 0xa5, 0x09, 0xd6, 0x4a, 0x80, 0x6e, 0x3a, 0xd9, 0xc2, 0x00, 0xe2, 0x45,
- 0xec, 0x5f, 0xe0, 0xa2, 0x50, 0xe0, 0xaa, 0x00, 0x06, 0x16, 0xa7, 0x7c, 0x17, 0x22, 0x82, 0xcb,
- 0x39, 0x4d, 0x4b, 0x3f, 0x41, 0xa8, 0x8b, 0x58, 0x0b, 0x7a, 0x88, 0xc5, 0xd2, 0xeb, 0x36, 0x7a,
- 0x46, 0x07, 0x0c, 0xd7, 0xac, 0x59, 0x03, 0x4a, 0x9f, 0x32, 0x65, 0x0a, 0x50, 0x8a, 0x1f, 0xa5,
- 0xa4, 0x0b, 0x70, 0x3b, 0x87, 0xdc, 0xea, 0xd4, 0xc6, 0xd6, 0x36, 0x28, 0xe8, 0x49, 0x41, 0x61,
- 0x91, 0xa3, 0xe3, 0xf1, 0x31, 0xfb, 0x2e, 0x2f, 0x5e, 0xbc, 0x48, 0x2d, 0xfe, 0xcc, 0x25, 0x37,
- 0xf7, 0xe4, 0x0e, 0x0d, 0x49, 0xaf, 0xed, 0xf9, 0x97, 0xbd, 0x8d, 0x81, 0x2e, 0xbc, 0xbc, 0xbc,
- 0x10, 0xda, 0x46, 0x45, 0x47, 0xbb, 0x7b, 0x5c, 0x3c, 0x70, 0xc0, 0xe8, 0xfb, 0xa5, 0x4b, 0xc1,
- 0x5a, 0xc8, 0xf6, 0x3f, 0x44, 0xd0, 0xbe, 0x93, 0x8d, 0x6e, 0x76, 0x20, 0x5b, 0xcc, 0x08, 0xd6,
- 0x85, 0xb0, 0x01, 0x0d, 0xd2, 0xe9, 0xf4, 0xa5, 0x4b, 0x97, 0x6e, 0xda, 0xb4, 0x69, 0xaf, 0x9e,
- 0x9e, 0xb5, 0xa9, 0xb1, 0xab, 0xe5, 0xbe, 0x3b, 0x36, 0xba, 0x41, 0xb6, 0x1b, 0xa2, 0x0f, 0xab,
- 0x24, 0x58, 0x12, 0x51, 0x7f, 0x8a, 0x03, 0x3d, 0xcd, 0x91, 0x0e, 0xd9, 0x90, 0xe9, 0x44, 0xcb,
- 0xfc, 0x89, 0x4e, 0xa5, 0x8c, 0x13, 0x74, 0xc8, 0x00, 0x00, 0x1b, 0xe7, 0x44, 0x9b, 0x29, 0x3e,
- 0xb6, 0x58, 0xe5, 0x66, 0xa5, 0x7f, 0xc0, 0x40, 0x1f, 0xec, 0xbd, 0x60, 0xc1, 0x02, 0xe4, 0x15,
- 0x15, 0x28, 0x51, 0xa3, 0xe2, 0xc9, 0x95, 0x1e, 0xc7, 0x81, 0xde, 0x11, 0x76, 0x9d, 0x3c, 0x79,
- 0x2a, 0x3a, 0x26, 0x36, 0x2e, 0x2e, 0x7e, 0xcc, 0x45, 0xc6, 0x60, 0xd1, 0xd1, 0xd1, 0x00, 0x2a,
- 0xa8, 0x15, 0x09, 0xb8, 0xad, 0xaa, 0x62, 0x48, 0x4f, 0xc1, 0xfe, 0xcb, 0xde, 0xc6, 0xe0, 0x61,
- 0xc1, 0x4b, 0x0f, 0x1f, 0x3e, 0x2c, 0x2c, 0x2a, 0x86, 0x9f, 0x42, 0xce, 0x23, 0x0a, 0xa3, 0xd1,
- 0xe9, 0xd0, 0x06, 0xff, 0xb6, 0x34, 0x2b, 0x6d, 0x62, 0xe8, 0x7e, 0x42, 0x3a, 0x0e, 0x54, 0x37,
- 0x04, 0x6b, 0xd0, 0xba, 0x40, 0x05, 0x34, 0xe7, 0xaa, 0x55, 0xab, 0xb4, 0xb4, 0xb4, 0x0e, 0xec,
- 0x37, 0x70, 0xb0, 0x30, 0x76, 0xb3, 0x36, 0xf4, 0xb1, 0xdf, 0xf5, 0xd4, 0x7a, 0x5d, 0xa4, 0xb9,
- 0x4a, 0x8c, 0x19, 0xd1, 0xb8, 0x1a, 0x6f, 0x29, 0x4e, 0xd0, 0x00, 0xe0, 0x55, 0x5a, 0xb4, 0x29,
- 0x3d, 0xd4, 0x6c, 0xb1, 0x97, 0x95, 0xf6, 0x09, 0x73, 0x83, 0xdd, 0x3b, 0x77, 0x2c, 0x5f, 0xbe,
- 0x7c, 0xde, 0xbc, 0x79, 0x5f, 0x7f, 0xfd, 0xf5, 0x3f, 0xfe, 0xf1, 0x4f, 0xf1, 0x80, 0xb7, 0x91,
- 0x79, 0x19, 0x5f, 0xc9, 0xc9, 0x13, 0x9b, 0xf3, 0x9e, 0x3b, 0xe7, 0x9c, 0xf0, 0xfc, 0xf9, 0xed,
- 0x3b, 0x77, 0xc6, 0xec, 0x0e, 0x00, 0x2d, 0xe7, 0xe4, 0xe6, 0xf6, 0x0f, 0x0c, 0x40, 0xc4, 0x22,
- 0xf8, 0x1a, 0x20, 0x86, 0xfa, 0x7b, 0xfe, 0xd5, 0x71, 0xf0, 0xde, 0x86, 0x22, 0x06, 0x1d, 0x3d,
- 0x09, 0x0e, 0x4e, 0x4d, 0x4d, 0xbb, 0x79, 0xeb, 0x96, 0x91, 0x91, 0xd1, 0xf7, 0xdf, 0x2f, 0x9d,
- 0x3e, 0x7d, 0xfa, 0x47, 0x59, 0xb0, 0xeb, 0x77, 0x36, 0xf1, 0x60, 0x06, 0x71, 0xff, 0x1a, 0xd4,
- 0xc2, 0xac, 0x59, 0xb3, 0xe4, 0xe5, 0xe5, 0xd5, 0xd5, 0xd5, 0xd7, 0xad, 0x5b, 0xa7, 0xbb, 0x5d,
- 0xf7, 0xe0, 0x81, 0xfd, 0x76, 0x16, 0x07, 0xcf, 0xda, 0x98, 0x5c, 0xb3, 0x3b, 0xe0, 0x6b, 0xb7,
- 0xeb, 0xb1, 0xcd, 0xe6, 0x10, 0x8b, 0x15, 0xa1, 0x16, 0x1a, 0xa1, 0x16, 0xcb, 0x42, 0x8e, 0xac,
- 0x0e, 0xb0, 0xd9, 0x7a, 0xcb, 0x4e, 0xdf, 0xe9, 0x88, 0x91, 0xf1, 0x7e, 0xfd, 0x2d, 0x5b, 0xb6,
- 0xa8, 0xaa, 0xaa, 0xc1, 0xef, 0x83, 0xba, 0x25, 0xb4, 0xbd, 0x78, 0x26, 0x91, 0xac, 0xac, 0x2c,
- 0xb9, 0x25, 0xc4, 0xa9, 0xe0, 0xa7, 0x21, 0xe6, 0xe6, 0xe6, 0xe3, 0xc7, 0x8f, 0x97, 0x9e, 0xe9,
- 0x86, 0xe8, 0x20, 0x27, 0x37, 0xaf, 0xb1, 0xa9, 0xa9, 0xba, 0xa6, 0xb6, 0xa6, 0xb6, 0xae, 0xbe,
- 0xbe, 0x01, 0x92, 0x00, 0x75, 0xea, 0x2d, 0x26, 0xc9, 0xbd, 0xd6, 0x50, 0x2b, 0x3f, 0xd6, 0x90,
- 0xd4, 0x3f, 0xa3, 0xa1, 0x70, 0x21, 0xc6, 0x1e, 0x3f, 0x0e, 0xba, 0x7f, 0xff, 0x81, 0xc5, 0xe1,
- 0xc3, 0x2b, 0x57, 0xae, 0x9a, 0x3d, 0x7b, 0x36, 0x25, 0x0c, 0xfe, 0x58, 0x04, 0xbe, 0xb7, 0x89,
- 0x1b, 0xca, 0x00, 0x5d, 0x54, 0x3d, 0x4a, 0xe8, 0x02, 0xba, 0xa4, 0xd0, 0x55, 0x83, 0xef, 0x26,
- 0x7a, 0xd6, 0xb4, 0x75, 0xf4, 0xf6, 0xec, 0x3e, 0x60, 0xb8, 0xdf, 0xe4, 0xa0, 0xb1, 0xb9, 0xe9,
- 0x21, 0x73, 0x93, 0x43, 0x26, 0x07, 0x8d, 0x0c, 0x0d, 0xf6, 0xed, 0xd0, 0xd5, 0x85, 0x9e, 0x5f,
- 0xbc, 0x78, 0x31, 0x94, 0x00, 0x34, 0x06, 0xf2, 0x81, 0xea, 0x10, 0x94, 0xd0, 0x48, 0xd4, 0x62,
- 0x8f, 0x73, 0xe7, 0xcd, 0xfb, 0xe1, 0x87, 0x35, 0x87, 0x8f, 0x1c, 0xb9, 0x77, 0xcf, 0x3b, 0x2e,
- 0x3e, 0x3e, 0x2b, 0x2b, 0x3b, 0xbf, 0xa0, 0xb0, 0xb0, 0xa8, 0x08, 0x3e, 0x8b, 0x48, 0x85, 0x45,
- 0x05, 0x05, 0x85, 0x79, 0x79, 0xf9, 0x59, 0xd9, 0x39, 0xf1, 0x09, 0xcf, 0xa3, 0xa0, 0xbd, 0x62,
- 0x62, 0x93, 0x93, 0x53, 0x10, 0xa3, 0xe1, 0x4b, 0x1c, 0x7d, 0x71, 0xda, 0xfb, 0xa4, 0x22, 0xc8,
- 0x66, 0x89, 0x84, 0x2f, 0x8b, 0x8a, 0x8a, 0x8b, 0x8a, 0x4b, 0x88, 0xcd, 0xf3, 0xca, 0xca, 0xc9,
- 0x7e, 0x0c, 0x08, 0x90, 0xea, 0xea, 0xea, 0x1a, 0xd4, 0x14, 0xd4, 0x95, 0xba, 0xfa, 0x06, 0xa4,
- 0xfa, 0x86, 0x17, 0x89, 0xf8, 0x58, 0x57, 0x5f, 0x43, 0xae, 0x96, 0x80, 0xb3, 0xaa, 0x18, 0x8c,
- 0x8a, 0xca, 0xca, 0xb2, 0xf2, 0x8a, 0xd2, 0xd2, 0xb2, 0xe2, 0x92, 0x52, 0xdc, 0xa7, 0xe8, 0x35,
- 0x3f, 0xf4, 0x1e, 0x09, 0x5e, 0x26, 0x35, 0x2d, 0x8d, 0x1a, 0x43, 0xf8, 0xa1, 0x29, 0x25, 0x35,
- 0x31, 0x31, 0x09, 0x1a, 0x2c, 0x3c, 0x22, 0xe2, 0x86, 0xa7, 0xe7, 0xc1, 0x43, 0x87, 0x96, 0x2d,
- 0x5b, 0x8e, 0x28, 0xe6, 0xf3, 0xcf, 0x3f, 0xff, 0xd3, 0x71, 0xac, 0x84, 0x8d, 0x16, 0xba, 0x20,
- 0x49, 0xbc, 0x11, 0xfc, 0x38, 0xa0, 0x0b, 0x0f, 0x02, 0x47, 0x0f, 0xe2, 0x5d, 0xb8, 0x70, 0x21,
- 0x00, 0x8c, 0x60, 0x7f, 0xe9, 0x52, 0x0d, 0x38, 0x1a, 0xfc, 0xa1, 0xa2, 0xa2, 0x02, 0x4a, 0x84,
- 0x12, 0x46, 0x90, 0x05, 0x2a, 0x43, 0x5d, 0xa6, 0xd6, 0x27, 0x91, 0x96, 0xf4, 0xd4, 0x82, 0xba,
- 0x38, 0x0d, 0xc2, 0x43, 0x5b, 0x5b, 0xdb, 0xf6, 0xe8, 0x51, 0x77, 0x77, 0x8f, 0xdb, 0xb7, 0x6f,
- 0x7b, 0xfb, 0xf8, 0xf8, 0xfa, 0xfa, 0x51, 0xe6, 0xeb, 0xeb, 0x8b, 0x4f, 0x77, 0xef, 0x7a, 0x5d,
- 0xbf, 0x71, 0x03, 0x61, 0xc2, 0x79, 0x17, 0x57, 0xd7, 0x0b, 0x6e, 0x97, 0x2e, 0x5f, 0xf6, 0xf4,
- 0xbc, 0x79, 0xd7, 0xcb, 0x0b, 0xe7, 0x8d, 0x9c, 0xf8, 0xf1, 0xec, 0x3e, 0x58, 0xe7, 0xc1, 0x03,
- 0x7f, 0xff, 0x87, 0x8f, 0x1e, 0x05, 0x04, 0x06, 0x3e, 0x46, 0x40, 0x18, 0x1c, 0x1c, 0xf2, 0xec,
- 0x59, 0x58, 0x58, 0x18, 0xca, 0x37, 0x22, 0x32, 0x32, 0x32, 0x8a, 0xa8, 0x37, 0x54, 0xc2, 0x47,
- 0x7c, 0x19, 0x16, 0x1e, 0x8e, 0x13, 0x82, 0x9f, 0x3e, 0x85, 0x2c, 0xa4, 0x36, 0x32, 0xf3, 0x7f,
- 0xf8, 0x10, 0x37, 0xc1, 0xad, 0x3e, 0xfa, 0xd3, 0x7d, 0x14, 0x43, 0xae, 0x79, 0x7b, 0x7b, 0x43,
- 0x0f, 0x20, 0x33, 0xad, 0x6d, 0x6c, 0x7e, 0xd4, 0xd4, 0x54, 0x5a, 0xb8, 0x90, 0x6a, 0x98, 0xfd,
- 0xb3, 0xe8, 0xd8, 0x37, 0x1b, 0xd5, 0x3d, 0x41, 0x75, 0xae, 0x7d, 0x32, 0xd2, 0xb3, 0x46, 0x36,
- 0xed, 0x7e, 0x05, 0xd7, 0x3c, 0x71, 0x22, 0x31, 0x89, 0x60, 0x2a, 0x69, 0x93, 0x27, 0x4f, 0x01,
- 0x9e, 0xc9, 0xb1, 0xca, 0x5f, 0x50, 0x23, 0x00, 0xdf, 0xd0, 0xca, 0x47, 0x8d, 0xd7, 0x42, 0x15,
- 0x80, 0x3f, 0x02, 0xec, 0x37, 0x6f, 0xd9, 0xb2, 0x67, 0x8f, 0x9e, 0x91, 0x91, 0xb1, 0x89, 0x89,
- 0xa9, 0xa9, 0xa9, 0x99, 0xa9, 0x19, 0x99, 0x4c, 0xcd, 0xf0, 0xd1, 0xc8, 0xd8, 0xd8, 0xc0, 0x60,
- 0xff, 0x1e, 0x3d, 0xbd, 0x9d, 0xbb, 0x76, 0xed, 0xda, 0xbd, 0x5b, 0x6f, 0xef, 0xde, 0xfd, 0x86,
- 0x86, 0x07, 0x0f, 0x1e, 0x7a, 0x79, 0xda, 0xc7, 0x4b, 0x66, 0x66, 0xc4, 0x06, 0x6a, 0xe6, 0x16,
- 0xb0, 0xc3, 0x87, 0x41, 0xfd, 0x96, 0x96, 0xd6, 0xd6, 0x36, 0xb6, 0xb6, 0xc4, 0xdc, 0x5e, 0x7b,
- 0x87, 0x63, 0xc7, 0x8e, 0x39, 0x3a, 0x3a, 0x1e, 0x3f, 0x7e, 0xfc, 0x04, 0x12, 0xfe, 0x8f, 0x4f,
- 0xf8, 0x0e, 0x07, 0x50, 0xdd, 0x50, 0xf4, 0x96, 0x56, 0x56, 0x38, 0x1f, 0xd7, 0xe1, 0x62, 0xdc,
- 0x02, 0xb7, 0xfa, 0xe8, 0x8f, 0xf7, 0x71, 0x12, 0x95, 0xab, 0x46, 0x46, 0x7b, 0xf6, 0xec, 0xd9,
- 0xbc, 0x79, 0xb3, 0xaa, 0x9a, 0x1a, 0x8a, 0x00, 0x6e, 0xf4, 0xf7, 0x19, 0x66, 0xf0, 0x7b, 0x9a,
- 0x44, 0xcf, 0x1a, 0xd5, 0xb4, 0x4b, 0x2d, 0x88, 0xfa, 0x0f, 0xd2, 0xf0, 0x07, 0x25, 0x0e, 0x71,
- 0x14, 0xe7, 0x8c, 0x49, 0xad, 0xa3, 0xef, 0x06, 0x3c, 0xe3, 0xaa, 0xaf, 0xc6, 0x8f, 0x9f, 0x3e,
- 0x7d, 0x06, 0xf4, 0x06, 0xc8, 0x56, 0x5d, 0x7d, 0x09, 0xa2, 0x00, 0x98, 0x86, 0x86, 0x06, 0xc5,
- 0xdb, 0xf8, 0xa8, 0xbe, 0x64, 0x89, 0xaa, 0xaa, 0xaa, 0xb2, 0xb2, 0xb2, 0xa2, 0x12, 0x61, 0xca,
- 0x8b, 0x16, 0x8d, 0x10, 0x3b, 0x75, 0xe2, 0x6f, 0x67, 0xcb, 0x60, 0xcb, 0x97, 0xaf, 0xa0, 0xa6,
- 0xe3, 0xad, 0x26, 0xec, 0x07, 0x68, 0x18, 0xca, 0xf0, 0x07, 0x3e, 0xe0, 0x2b, 0x44, 0xa6, 0x38,
- 0x8c, 0x93, 0x70, 0x2e, 0xce, 0xc7, 0x55, 0xbf, 0xe9, 0x33, 0x7d, 0xb8, 0xbd, 0xc8, 0x55, 0xf5,
- 0x25, 0xc8, 0x70, 0x64, 0x3b, 0x32, 0xff, 0xab, 0xaf, 0xc6, 0x7f, 0xac, 0x45, 0x11, 0xff, 0x9d,
- 0x4d, 0x0c, 0x60, 0xf1, 0x94, 0x0a, 0xea, 0x6f, 0xea, 0xfb, 0xb7, 0xbc, 0x83, 0x78, 0xaa, 0xc5,
- 0xf8, 0xf1, 0x5f, 0x4f, 0x98, 0x30, 0x11, 0xbe, 0x09, 0x84, 0x3d, 0xc2, 0xd9, 0x53, 0xa9, 0xbf,
- 0xf1, 0x25, 0x98, 0xfc, 0xdb, 0x09, 0x13, 0xbe, 0x21, 0x6d, 0x02, 0xce, 0x23, 0x89, 0x7d, 0xf4,
- 0x99, 0xbf, 0xa9, 0x4d, 0x23, 0x6d, 0xfa, 0x88, 0x8d, 0xcc, 0xce, 0x9b, 0x41, 0x7d, 0x9c, 0x36,
- 0x62, 0xbf, 0xc7, 0xa3, 0x7c, 0x0c, 0x13, 0xe7, 0x2a, 0x32, 0x12, 0xd9, 0x8e, 0xcc, 0x47, 0x11,
- 0xfc, 0xfb, 0x37, 0xc6, 0xfe, 0x9b, 0x18, 0xa5, 0x37, 0xa8, 0x0e, 0x05, 0x8a, 0xae, 0xc7, 0x34,
- 0x1c, 0xfa, 0x9f, 0x51, 0xf6, 0x86, 0x33, 0x7f, 0x07, 0x13, 0x3b, 0x94, 0x3f, 0xbb, 0x8d, 0x76,
- 0x88, 0xa3, 0xe1, 0xfa, 0xff, 0x01, 0x00, 0x07, 0xdb, 0x50, 0xec, 0x6b, 0x02, 0x00
-};
-
-fastimage_t bfin_logo = {
-		DEF_BFIN_LOGO_DATA,
-		DEF_BFIN_LOGO_WIDTH,
-		DEF_BFIN_LOGO_HEIGHT,
-		DEF_BFIN_LOGO_BPP,
-		DEF_BFIN_LOGO_PIXEL_SIZE,
-		DEF_BFIN_LOGO_SIZE
-};

+ 0 - 1819
arch/blackfin/include/asm/bfin_logo_230x230_lzma.h

@@ -1,1819 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where:	'screen'	is the pointer to the frame buffer
- *		'width'	is the screen width
- *		'x'		is the horizontal position
- *		'y'		is the vertical position
- */
-
-#define EASYLOGO_ENABLE_LZMA 28532
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[158700];
-
-#include <video_easylogo.h>
-
-#define	DEF_BFIN_LOGO_WIDTH		230
-#define	DEF_BFIN_LOGO_HEIGHT		230
-#define	DEF_BFIN_LOGO_PIXELS		52900
-#define	DEF_BFIN_LOGO_BPP		24
-#define	DEF_BFIN_LOGO_PIXEL_SIZE	3
-#define	DEF_BFIN_LOGO_SIZE		158700
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x6f,
- 0xfd, 0xf8, 0xb8, 0x51, 0x47, 0x76, 0x83, 0x1a, 0x36, 0xff, 0xdf, 0x25, 0x3b, 0x9e, 0x1e, 0xfc,
- 0x17, 0x17, 0x7c, 0x3f, 0x4c, 0x3f, 0x42, 0x00, 0x19, 0xe1, 0x7c, 0x13, 0xce, 0xa1, 0xb5, 0xdf,
- 0x06, 0x70, 0x2e, 0xb6, 0x6c, 0xe0, 0xcb, 0x11, 0xf6, 0x92, 0x94, 0x8a, 0x99, 0x3e, 0x21, 0xb2,
- 0x27, 0xe8, 0x4c, 0x5d, 0x4c, 0x45, 0x6d, 0xfa, 0x0d, 0x07, 0x51, 0x9c, 0xc1, 0xf2, 0x53, 0x6d,
- 0x9e, 0x57, 0xb5, 0x3a, 0x93, 0x8c, 0x7e, 0x3d, 0x18, 0x78, 0x1a, 0x13, 0x72, 0x7a, 0xa6, 0x0f,
- 0x90, 0x31, 0x39, 0xfe, 0xe1, 0x4c, 0x12, 0xda, 0x4f, 0xe8, 0xe7, 0x3f, 0x68, 0xe5, 0xc3, 0x2e,
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- 0x78, 0x62, 0x7f, 0x37, 0x0f, 0xe9, 0x8c, 0xec, 0xf1, 0x43, 0x4d, 0x40, 0x6c, 0x4f, 0xa1, 0xff,
- 0xe7, 0x1c, 0xb2, 0xe4, 0xde, 0x7b, 0x34, 0xb1, 0x4b, 0x16, 0x3d, 0x7f, 0xba, 0xac, 0x99, 0xd8,
- 0xa8, 0xa1, 0x7f, 0xf5, 0xfc, 0x08, 0x14, 0xb6, 0x5c, 0x62, 0x1a, 0x53, 0x7b, 0x76, 0x00, 0x32,
- 0xbe, 0xba, 0xbb, 0x50, 0xb9, 0xa2, 0x4c, 0xf2, 0x4a, 0x00, 0xc5, 0xc6, 0x7c, 0x91, 0xb9, 0xa6,
- 0x86, 0x72, 0x35, 0x2d, 0xe1, 0x7a, 0xb9, 0xd2, 0xd0, 0x62, 0x22, 0xf0, 0x87, 0xe4, 0xbc, 0x89,
- 0x3b, 0xb8, 0xac, 0xb2, 0x91, 0xa1, 0xdc, 0x4c, 0xdd, 0xab, 0x2b, 0xcd, 0x0e, 0x94, 0xb4, 0x17,
- 0x4b, 0x01, 0xcf, 0xec, 0x76, 0xe9, 0x2f, 0x0f, 0x56, 0xc4, 0x75, 0x76, 0x9d, 0xfe, 0x44, 0x5c,
- 0x63, 0x5d, 0x5d, 0xd9, 0x9a, 0x59, 0x6f, 0xba, 0xf4, 0x96, 0xa1, 0x47, 0xee, 0x94, 0xe9, 0xe6,
- 0x0a, 0x55, 0x00, 0x89, 0x8d, 0x2d, 0x69, 0x1b, 0x34, 0x4a, 0xd2, 0x3f, 0xa8, 0x3c, 0x9c, 0x1a,
- 0x66, 0x25, 0x68, 0x4b, 0xdc, 0x84, 0xe2, 0xe1, 0xc1, 0xbf, 0xc2, 0xe3, 0x5d, 0xc5, 0xd7, 0x34,
- 0x03, 0xd1, 0x8f, 0xf0, 0xae, 0x1b, 0x25, 0x13, 0x45, 0xc1, 0x64, 0x18, 0x55, 0x27, 0x2d, 0xac,
- 0xd3, 0x5d, 0x94, 0xab, 0x66, 0xb4, 0xef, 0x1c, 0xca, 0x95, 0x44, 0xb1, 0x95, 0xd2, 0x73, 0x66,
- 0x3e, 0x7c, 0xc7, 0x5f, 0x86, 0x0e, 0xb4, 0x81, 0x15, 0xa8, 0x0f, 0xba, 0x0c, 0x0e, 0xf1, 0x1b,
- 0xec, 0x3f, 0x2f, 0x08, 0x26, 0xef, 0x2b, 0x13, 0x96, 0x98, 0xec, 0x16, 0x88, 0xe8, 0x30, 0x49,
- 0xe8, 0xa7, 0x69, 0x3c, 0x10, 0x7d, 0x3c, 0x5c, 0x73, 0xd2, 0x9d, 0xf3, 0xd6, 0x3e, 0x8a, 0xcb,
- 0x05, 0xb0, 0x24, 0x3b, 0x99, 0xa7, 0x2b, 0x05, 0x96, 0x9a, 0x7d, 0x1e, 0xbd, 0x93, 0x0a, 0x2d,
- 0x79, 0xdf, 0x4f, 0xb3, 0x43, 0xf0, 0x44, 0x4f, 0xe0, 0xac, 0x78, 0x9c, 0x64, 0x85, 0x9b, 0x5e,
- 0x11, 0x0e, 0xea, 0x78, 0x59, 0xf1, 0xaf, 0x80, 0x10, 0xf4, 0xd9, 0x74, 0x0b, 0x18, 0x56, 0x58,
- 0xaa, 0xd7, 0xea, 0xc6, 0xd7, 0x8d, 0x72, 0x0b, 0x82, 0x44, 0x1e, 0x41, 0x9a, 0xbe, 0x41, 0x9b,
- 0xe4, 0x36, 0x27, 0x02, 0x5d, 0xd3, 0x00, 0x60, 0xaa, 0xa1, 0x16, 0x5c, 0xa7, 0x22, 0x2b, 0x2a,
- 0xcb, 0xe0, 0xed, 0xd2, 0xfb, 0xfd, 0x7a, 0x82, 0x21, 0xc0, 0x5d, 0xa6, 0x68, 0x5c, 0x81, 0xe0,
- 0xa4, 0xf8, 0xb5, 0x25, 0x7f, 0xfc, 0x72, 0x8a, 0x91, 0x1f, 0xad, 0x86, 0xcc, 0xa9, 0xe8, 0x67,
- 0x60, 0xfa, 0xdc, 0x07, 0x0e, 0x38, 0x4c, 0x6e, 0x6e, 0x2f, 0xad, 0xcc, 0x43, 0x92, 0x73, 0xe4,
- 0xa7, 0x05, 0x96, 0x43, 0x44, 0x30, 0x75, 0x8c, 0x18, 0xd0, 0x78, 0x04, 0xcb, 0x03, 0xf3, 0x2c,
- 0xce, 0x19, 0xc6, 0x15, 0xd1, 0x9c, 0x14, 0xd5, 0xf5, 0x3e, 0x57, 0x16, 0x15, 0xa8, 0xeb, 0xa7,
- 0xac, 0x18, 0x86, 0x41, 0x16, 0x55, 0x48, 0x3d, 0xa9, 0xb2, 0xdf, 0xc7, 0x6b, 0xef, 0xbf, 0x6c,
- 0xa1, 0x59, 0x59, 0x2c, 0xa7, 0x57, 0xad, 0x35, 0xe8, 0x75, 0x3e, 0xe3, 0x7b, 0xae, 0x48, 0xf4,
- 0x41, 0x1b, 0x84, 0xae, 0x7c, 0xeb, 0x85, 0x07, 0x2f, 0x65, 0xef, 0x55, 0x4d, 0x82, 0x9c, 0xef,
- 0xaa, 0xcc, 0x66, 0x6e, 0xc4, 0xdb, 0x15, 0xf7, 0x7b, 0x62, 0x42, 0x0b, 0x3a, 0x1d, 0xd3, 0x18,
- 0x12, 0xdb, 0x08, 0x50, 0xb2, 0x37, 0xd8, 0x2c, 0x55, 0x47, 0xb6, 0xf6, 0xc1, 0x3a, 0x9b, 0x59,
- 0x00, 0xe4, 0x25, 0x6e, 0x40, 0xdf, 0xb4, 0x38, 0x1f, 0x00, 0x17, 0x6c, 0x20, 0x59, 0x97, 0x46,
- 0xb9, 0xff, 0xea, 0x9e, 0x57, 0x34, 0x19, 0x54, 0xdd, 0x7f, 0xa0, 0x5f, 0x74, 0x72, 0x1b, 0xf2,
- 0xc1, 0x93, 0xed, 0x91, 0xa8, 0x15, 0x5e, 0x10, 0xfc, 0x24, 0xe1, 0xe6, 0x9b, 0xdb, 0x52, 0x2c,
- 0x44, 0x5c, 0xef, 0xdb, 0x6e, 0xc4, 0x50, 0x3f, 0x11, 0xd6, 0x7b, 0x36, 0xfc, 0x05, 0xb2, 0x55,
- 0x53, 0x2e, 0xb5, 0x43, 0x50, 0xd7, 0x56, 0x95, 0xc4, 0x5c, 0xe1, 0x26, 0xe3, 0x82, 0x63, 0x4f,
- 0xb3, 0x9e, 0x4c, 0x87, 0x3e, 0xab, 0x89, 0x33, 0x77, 0xab, 0xb9, 0xcf, 0xba, 0x1e, 0x7c, 0xc3,
- 0x41, 0x2f, 0xe2, 0x2b, 0x14, 0xd6, 0xd3, 0x55, 0x7f, 0x68, 0x37, 0x0c, 0x42, 0x2d, 0xbf, 0x9a,
- 0x51, 0x6c, 0xfe, 0x70, 0x45, 0xc2, 0x4f, 0x5d, 0xf4, 0x0a, 0x08, 0x2a, 0xd8, 0x89, 0xf1, 0x08,
- 0x2e, 0xbd, 0x70, 0x5b, 0xf5, 0x53, 0xf8, 0x5e, 0xc6, 0xec, 0x5c, 0x7b, 0xdc, 0x81, 0x16, 0xba,
- 0xc7, 0x52, 0x64, 0x7b, 0x0f, 0x2d, 0x41, 0x22, 0x60, 0x15, 0x58, 0x3d, 0xa0, 0x45, 0x16, 0x7d,
- 0xdd, 0xcc, 0xe5, 0x00, 0xc5, 0xd8, 0x0e, 0x9b, 0x88, 0x99, 0xde, 0xa4, 0xcd, 0x8b, 0x3c, 0xeb,
- 0x6c, 0x3f, 0x98, 0xec, 0xf9, 0x9a, 0x21, 0xb0, 0xd4, 0xd1, 0x42, 0x0c, 0xe0, 0x09, 0x79, 0x2a,
- 0x28, 0xf9, 0x2e, 0x25, 0x6e, 0xf4, 0x5d, 0xc5, 0xd5, 0xba, 0x0d, 0x94, 0xd5, 0x02, 0xfa, 0xa3,
- 0xab, 0xcf, 0xb6, 0xf5, 0xab, 0x1d, 0x32, 0xc3, 0x98, 0xc8, 0x54, 0x4c, 0xd1, 0xff, 0xfe, 0x4d,
- 0x5e, 0xc8, 0xeb, 0x18, 0x7e, 0xa7, 0x09, 0x54, 0xf5, 0x20, 0x39, 0x36, 0xee, 0x6c, 0x67, 0x9c,
- 0x88, 0x08, 0xf4, 0xdf, 0xae, 0x77, 0x4a, 0x14, 0x29, 0x5e, 0x13, 0xc4, 0x18, 0x55, 0x8e, 0xdf,
- 0x1b, 0x91, 0xb7, 0x6f, 0x43, 0x92, 0x00, 0x0d, 0xd0, 0xcf, 0xdb, 0x32, 0x70, 0xc0, 0xf3, 0x51,
- 0xea, 0xa8, 0xf8, 0xb9, 0x97, 0x16, 0x68, 0xa6, 0xf3, 0xc1, 0xbf, 0xdb, 0x59, 0x71, 0xb2, 0xb0,
- 0x94, 0xbc, 0x2f, 0xdf, 0xf9, 0xa3, 0x4d, 0x29, 0x04, 0xfe, 0xf6, 0xf0, 0x2f, 0x51, 0x58, 0xe9,
- 0xa2, 0x5b, 0x2a, 0xc0, 0xcf, 0x35, 0xba, 0x35, 0x5a, 0x4f, 0x66, 0x7f, 0x4d, 0xa5, 0x25, 0x75,
- 0x5d, 0xff, 0x53, 0x02, 0x8b, 0x0b, 0x4d, 0x50, 0x7a, 0x9e, 0xf2, 0x94, 0xb8, 0x61, 0x35, 0x87,
- 0xc5, 0x7f, 0x89, 0x4f, 0xeb, 0xc6, 0x2a, 0x48, 0x22, 0xe4, 0x2f, 0x78, 0x7e, 0xa0, 0x2d, 0x98,
- 0x21, 0x62, 0xd8, 0xf7, 0xbd, 0x2b, 0xde, 0x77, 0x07, 0xde, 0x55, 0xa2, 0xb2, 0xb9, 0x4a, 0x68,
- 0x5e, 0x4a, 0x0a, 0x0b, 0xc9, 0x49, 0x8e, 0xce, 0x57, 0x83, 0xb5, 0xca, 0xa0, 0x1c, 0x9b, 0xbb,
- 0x5f, 0x6a, 0xf1, 0x92, 0xac, 0x04, 0x8c, 0x1b, 0x46, 0x15, 0x99, 0x14, 0xe6, 0x06, 0xd1, 0x46,
- 0x77, 0x76, 0x3f, 0x2e, 0x37, 0x5b, 0x39, 0xdd, 0x3d, 0x96, 0x95, 0xd9, 0xe5, 0x8c, 0x03, 0x86,
- 0xc6, 0x02, 0x17, 0x95, 0x9a, 0x1c, 0x8c, 0x77, 0xe4, 0x47, 0xfe, 0xe3, 0x87, 0xe5, 0x28, 0xd5,
- 0xcf, 0x48, 0xce, 0x1c, 0x2f, 0xda, 0x23, 0x6c, 0xbc, 0xdf, 0xa7, 0x3f, 0x24, 0x82, 0x65, 0xb7,
- 0xe1, 0x49, 0x07, 0x0f, 0x67, 0x5d, 0x25, 0x05, 0x23, 0xb3, 0x5f, 0xe1, 0xf3, 0xb2, 0x5d, 0xf2,
- 0x22, 0x0b, 0xa3, 0x16, 0xc3, 0xdc, 0xa0, 0xa8, 0x29, 0xb3, 0xf2, 0xc6, 0xdc, 0x98, 0x98, 0xd0,
- 0x78, 0x83, 0xda, 0xea, 0x5e, 0x17, 0x37, 0x30, 0xcf, 0xb0, 0x5c, 0xec, 0xa1, 0xee, 0x70, 0xd5,
- 0x19, 0x0d, 0x86, 0x07, 0x2f, 0x4a, 0x97, 0x5e, 0xa2, 0xf4, 0x53, 0x4b, 0x38, 0x15, 0x53, 0x5b,
- 0xe5, 0xa1, 0x08, 0x43, 0xf8, 0x44, 0x04, 0x5e, 0xe4, 0xf7, 0x68, 0xcf, 0x85, 0xca, 0x25, 0x10,
- 0xed, 0xcc, 0xfa, 0x69, 0x1a, 0x39, 0x51, 0x1f, 0x92, 0xbd, 0xbe, 0xc7, 0x90, 0x1e, 0xb8, 0xde,
- 0x26, 0x2b, 0xc7, 0x5e, 0xb9, 0x2c, 0x36, 0x51, 0xe2, 0x6e, 0x1c, 0xe0, 0xd6, 0x4c, 0x0c, 0x11,
- 0x0d, 0x8f, 0x47, 0x6d, 0xb5, 0xc2, 0xb1, 0xfb, 0x0a, 0xef, 0xec, 0x0e, 0x2b, 0x00, 0xef, 0x1f,
- 0x0d, 0x5b, 0xd8, 0x6a, 0xba, 0xdb, 0x09, 0x3c, 0x6c, 0x50, 0x7a, 0x80, 0xda, 0xd1, 0xbc, 0x11,
- 0x91, 0xd6, 0x6c, 0xf5, 0x04, 0x9b, 0x0c, 0xbc, 0xc9, 0x15, 0x7e, 0x03, 0xbe, 0xe6, 0x6a, 0x31,
- 0x23, 0xef, 0x02, 0xfb, 0xb6, 0xc4, 0xfa, 0xf7, 0xe0, 0xf7, 0x29, 0x7f, 0x75, 0x71, 0x4d, 0x07,
- 0xea, 0x81, 0xea, 0x16, 0x70, 0xd6, 0xea, 0xb1, 0x6b, 0x44, 0x7d, 0xe8, 0xeb, 0x14, 0xfb, 0x7e,
- 0xd8, 0x68, 0xb4, 0x41, 0x60, 0x47, 0xa9, 0x93, 0xc5, 0x78, 0xc2, 0xc7, 0xb5, 0xcd, 0xe7, 0x6f,
- 0x11, 0x9c, 0x72, 0x6b, 0x99, 0x9f, 0xc0, 0x9c, 0x32, 0x01, 0x64, 0x1b, 0x7f, 0x0d, 0x00, 0xbf,
- 0x1d, 0xa1, 0x81, 0x51, 0x0f, 0x96, 0x2e, 0x02, 0x80, 0x26, 0xc1, 0x90, 0x70, 0x81, 0xfd, 0x20,
- 0x79, 0xd1, 0x61, 0x06, 0x0a, 0xab, 0x43, 0x02, 0xc1, 0x80, 0x0e, 0xbb, 0x1a, 0xb1, 0xfa, 0x98,
- 0x64, 0xcc, 0xbb, 0xe3, 0xf3, 0x58, 0x23, 0x7e, 0xfa, 0x91, 0x22, 0x5e, 0x61, 0x11, 0xe5, 0xff,
- 0xfa, 0xe5, 0x64, 0xa4
-};
-
-fastimage_t bfin_logo = {
-		DEF_BFIN_LOGO_DATA,
-		DEF_BFIN_LOGO_WIDTH,
-		DEF_BFIN_LOGO_HEIGHT,
-		DEF_BFIN_LOGO_BPP,
-		DEF_BFIN_LOGO_PIXEL_SIZE,
-		DEF_BFIN_LOGO_SIZE
-};

+ 0 - 1242
arch/blackfin/include/asm/bfin_logo_rgb565_230x230_gzip.h

@@ -1,1242 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where:	'screen'	is the pointer to the frame buffer
- *		'width'	is the screen width
- *		'x'		is the horizontal position
- *		'y'		is the vertical position
- */
-
-#define EASYLOGO_ENABLE_GZIP 19303
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[105800];
-
-#include <video_easylogo.h>
-
-#define	DEF_BFIN_LOGO_WIDTH		230
-#define	DEF_BFIN_LOGO_HEIGHT		230
-#define	DEF_BFIN_LOGO_PIXELS		52900
-#define	DEF_BFIN_LOGO_BPP		16
-#define	DEF_BFIN_LOGO_PIXEL_SIZE	2
-#define	DEF_BFIN_LOGO_SIZE		105800
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x1f, 0x8b, 0x08, 0x00, 0x9d, 0x56, 0x26, 0x4b, 0x00, 0x03, 0xec, 0x5d, 0x7f, 0x4c, 0x1b, 0x77,
- 0x96, 0xb7, 0x2e, 0xe8, 0x3a, 0x52, 0xb8, 0xd3, 0x64, 0xc3, 0x36, 0xd3, 0x14, 0xac, 0xf1, 0xc6,
- 0xa6, 0x36, 0x0c, 0xbd, 0x3a, 0xb8, 0x5a, 0x66, 0x01, 0x29, 0xb6, 0x82, 0x14, 0x5c, 0xb8, 0xdb,
- 0xb8, 0xa1, 0x5b, 0x9c, 0x3a, 0x77, 0xc4, 0x41, 0x2a, 0x72, 0xd1, 0x2a, 0x75, 0x68, 0xeb, 0x38,
- 0x20, 0x85, 0x23, 0x48, 0x45, 0x24, 0x77, 0x65, 0x09, 0x55, 0x59, 0x97, 0x53, 0x2d, 0x99, 0x53,
- 0x39, 0x99, 0x3f, 0xd2, 0x42, 0x6e, 0x49, 0xcc, 0x4a, 0x41, 0x35, 0x52, 0x90, 0x1c, 0xa9, 0xd9,
- 0x9a, 0xdb, 0x90, 0x18, 0xa9, 0xd6, 0xc5, 0x52, 0xb9, 0x3b, 0x77, 0xc5, 0xea, 0x9c, 0x86, 0xe6,
- 0x72, 0xdf, 0x37, 0x5f, 0x0f, 0xe3, 0xdf, 0x36, 0xb6, 0x93, 0xb4, 0x61, 0x3e, 0x5f, 0x85, 0xc4,
- 0x63, 0x67, 0xfc, 0xb5, 0x3f, 0xbc, 0xf7, 0x7d, 0xdf, 0xf7, 0xde, 0xf7, 0x3d, 0x89, 0x44, 0x84,
- 0x88, 0x1f, 0x32, 0xe8, 0x34, 0x43, 0xc4, 0x8f, 0x05, 0x98, 0x2f, 0x2d, 0xa1, 0x25, 0x3a, 0x88,
- 0x7e, 0xb2, 0x9f, 0x74, 0xc6, 0x0c, 0x78, 0xdc, 0x81, 0xae, 0xc3, 0xb3, 0x22, 0xab, 0x3f, 0x64,
- 0x60, 0x0e, 0x81, 0x41, 0x27, 0xb9, 0x40, 0x05, 0xa9, 0x12, 0x99, 0x5c, 0xd6, 0xa4, 0xea, 0x54,
- 0x0f, 0x6e, 0x8e, 0x4e, 0x55, 0x93, 0x4a, 0x2e, 0x2b, 0x91, 0x05, 0x29, 0x27, 0xc7, 0x2a, 0xe6,
- 0x54, 0xc4, 0x0f, 0x0b, 0x3c, 0x8b, 0x0b, 0x88, 0xc1, 0x26, 0xd5, 0xa0, 0x7a, 0x91, 0x0d, 0xb1,
- 0x4a, 0x5d, 0x97, 0x7e, 0xc8, 0xb0, 0x64, 0x14, 0xc6, 0x94, 0x61, 0xc8, 0xd0, 0xac, 0x27, 0x74,
- 0x8b, 0xec, 0xa0, 0xba, 0x49, 0x85, 0x39, 0xed, 0x10, 0xf9, 0xfc, 0xc1, 0x00, 0x4b, 0x23, 0x66,
- 0xb1, 0x53, 0x35, 0xc9, 0x12, 0x88, 0xc1, 0x25, 0x63, 0xa9, 0xb9, 0xd5, 0xd2, 0x6a, 0x29, 0x35,
- 0x4f, 0x19, 0xba, 0xf4, 0xc0, 0x1e, 0xcf, 0xec, 0x9a, 0xb1, 0xd5, 0xd2, 0x6d, 0x61, 0xcc, 0x4b,
- 0xc6, 0x21, 0x83, 0x12, 0x71, 0xda, 0x89, 0x18, 0x5d, 0xa0, 0xfa, 0x49, 0x51, 0xe7, 0x3e, 0x69,
- 0x60, 0x69, 0x74, 0x92, 0x41, 0xaa, 0x49, 0xb5, 0x88, 0xd8, 0x9a, 0x42, 0x5c, 0x95, 0x9a, 0x4b,
- 0xcd, 0xcd, 0xfa, 0x41, 0xb5, 0x93, 0x4c, 0xf7, 0xbf, 0x3a, 0x08, 0xb9, 0x4c, 0xa9, 0x83, 0x57,
- 0xae, 0x21, 0x59, 0x6d, 0xd6, 0x2f, 0xb2, 0x20, 0xa3, 0x58, 0x42, 0x1f, 0xe7, 0xec, 0x45, 0x08,
- 0xa0, 0x25, 0xc0, 0x23, 0x48, 0x63, 0x88, 0xed, 0xd2, 0xaf, 0x19, 0xd7, 0x90, 0x0e, 0x25, 0x74,
- 0x72, 0x19, 0x9d, 0xe3, 0xff, 0x5e, 0xa0, 0x16, 0x59, 0x90, 0xd4, 0x35, 0x63, 0x97, 0x3e, 0x84,
- 0x24, 0x34, 0x18, 0x95, 0x4f, 0x11, 0x8f, 0x17, 0x58, 0xaf, 0x06, 0x29, 0xe0, 0x71, 0xc8, 0x00,
- 0x12, 0xa6, 0xd4, 0x35, 0xa9, 0x3a, 0xb6, 0x2c, 0x57, 0x5a, 0x24, 0xa3, 0x84, 0x0e, 0x74, 0xf2,
- 0x90, 0x21, 0x84, 0xe4, 0x73, 0x41, 0xe4, 0xf3, 0x31, 0x03, 0x4b, 0xa4, 0x5c, 0xb6, 0x88, 0xe4,
- 0x91, 0x31, 0xaf, 0x1d, 0x0f, 0xb1, 0x25, 0x32, 0xba, 0x80, 0xbb, 0x05, 0xa9, 0x10, 0x8b, 0x75,
- 0xf3, 0xa4, 0x1a, 0x6b, 0xdb, 0xfc, 0xef, 0x26, 0x62, 0x2b, 0x00, 0x26, 0x17, 0xd0, 0x0a, 0x49,
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- 0x5e, 0x6b, 0x67, 0x1e, 0x51, 0xfd, 0x78, 0x60, 0x64, 0x22, 0x0e, 0x01, 0xed, 0x8d, 0x70, 0xc2,
- 0xee, 0x11, 0xf3, 0x05, 0xfa, 0x0e, 0xc6, 0x08, 0xd8, 0x5f, 0xe9, 0xb8, 0x19, 0xc8, 0x25, 0xd0,
- 0x41, 0x9c, 0xe4, 0xfe, 0x2e, 0x54, 0x82, 0x72, 0x93, 0x6d, 0x66, 0xca, 0xa9, 0xca, 0x65, 0xd8,
- 0x46, 0x6b, 0xa2, 0x34, 0xeb, 0x0e, 0x68, 0x43, 0xee, 0x10, 0x57, 0x1b, 0x3e, 0x1a, 0x7e, 0x14,
- 0x76, 0x6a, 0x01, 0x3d, 0x2e, 0x32, 0xe2, 0x1d, 0x2f, 0x31, 0x89, 0x4c, 0xb9, 0xed, 0x3a, 0x7c,
- 0xbe, 0xcb, 0xd8, 0xe5, 0xa9, 0x04, 0xbb, 0x89, 0xeb, 0x14, 0xad, 0xcf, 0x7d, 0x4d, 0xab, 0xb5,
- 0x76, 0x06, 0x54, 0xa7, 0xc8, 0xa7, 0x54, 0xa6, 0xca, 0xdf, 0x27, 0x1d, 0x9f, 0x0b, 0x37, 0x22,
- 0x49, 0x43, 0xdf, 0x47, 0xe9, 0xa8, 0x1d, 0xed, 0x50, 0x8c, 0xc2, 0x97, 0x96, 0x5c, 0x85, 0x6a,
- 0x76, 0x7b, 0xcd, 0x5a, 0x6b, 0x03, 0xc7, 0x45, 0x89, 0x5a, 0x39, 0xeb, 0x2e, 0x71, 0xb4, 0x6b,
- 0x62, 0x89, 0x8e, 0xc1, 0x4b, 0x7a, 0xab, 0x83, 0x22, 0x5d, 0x89, 0xc7, 0xdc, 0x4d, 0x1c, 0xea,
- 0xb0, 0x67, 0xd3, 0xee, 0x5a, 0x41, 0xaf, 0xa4, 0xec, 0x08, 0x4a, 0x2e, 0xfe, 0x4d, 0xf9, 0xe8,
- 0xb4, 0x01, 0xf9, 0x09, 0xd6, 0x0f, 0x9a, 0x63, 0xe7, 0x7b, 0xe1, 0x35, 0x8f, 0x46, 0xe3, 0x6d,
- 0x2f, 0x46, 0x65, 0x74, 0x24, 0xeb, 0x47, 0x51, 0x9a, 0x73, 0x3b, 0x88, 0xd1, 0x05, 0xcf, 0x70,
- 0xad, 0x8f, 0x78, 0x43, 0xb4, 0xab, 0xd0, 0x45, 0x3e, 0xd2, 0xe7, 0x1c, 0x72, 0x77, 0x08, 0xe8,
- 0xa6, 0x5b, 0xf5, 0xce, 0xf0, 0x4e, 0xb2, 0x7f, 0xb0, 0xac, 0x17, 0xde, 0xc3, 0x5e, 0x09, 0xe8,
- 0x29, 0x68, 0x99, 0x83, 0xb7, 0xf4, 0xaf, 0x8f, 0xa5, 0xe2, 0xa1, 0xd3, 0x5d, 0x25, 0xd8, 0x9d,
- 0x4d, 0x74, 0xd0, 0x17, 0xce, 0xcc, 0x47, 0x8e, 0xcb, 0x32, 0xad, 0x8c, 0xda, 0xe7, 0x5c, 0xac,
- 0x3c, 0x96, 0x52, 0x5c, 0xf4, 0x56, 0x9b, 0x17, 0x53, 0x64, 0xa5, 0xde, 0x6a, 0x9f, 0xd3, 0xe7,
- 0x1c, 0xae, 0x9e, 0x72, 0xc7, 0xc5, 0x0b, 0xb2, 0xc8, 0xf6, 0x9a, 0xd9, 0x2a, 0x3b, 0x93, 0x79,
- 0x79, 0x6a, 0x87, 0x05, 0x44, 0x3e, 0x0f, 0x35, 0x7b, 0x6f, 0x52, 0x5f, 0x39, 0xd6, 0xb8, 0xd0,
- 0x0d, 0x84, 0x1e, 0xde, 0xbd, 0x3a, 0x98, 0x76, 0xa2, 0x67, 0x1f, 0xeb, 0x1e, 0x27, 0x03, 0xb8,
- 0xc3, 0x10, 0xfb, 0x81, 0x61, 0x3f, 0xb1, 0xa3, 0x53, 0x45, 0xdd, 0x7b, 0xa4, 0x33, 0xaa, 0x6a,
- 0x47, 0x0e, 0x51, 0x2f, 0x50, 0x05, 0xa8, 0x27, 0x16, 0xa1, 0x77, 0x0e, 0xdd, 0x5b, 0xe9, 0x25,
- 0xed, 0xaf, 0x66, 0x7f, 0x79, 0xbb, 0x5f, 0xdf, 0x88, 0x7c, 0x9f, 0xc6, 0x5a, 0x88, 0x09, 0xca,
- 0x35, 0x79, 0x05, 0xfa, 0xfd, 0x34, 0xd6, 0xbb, 0x5a, 0xe6, 0xba, 0xb3, 0x07, 0xf7, 0xda, 0xa3,
- 0xa6, 0x9b, 0xe4, 0x6b, 0x03, 0x57, 0x87, 0xc2, 0xb2, 0x81, 0x1f, 0x5c, 0xf3, 0xc5, 0xf3, 0xa0,
- 0x17, 0x94, 0xf9, 0x67, 0x58, 0x15, 0x55, 0xf6, 0x8b, 0x14, 0xef, 0x4b, 0x8a, 0xfe, 0xf6, 0xb3,
- 0x87, 0xae, 0x0a, 0xb6, 0xdf, 0x51, 0x6c, 0x63, 0x14, 0xd9, 0xcb, 0x78, 0xf9, 0x6c, 0xd5, 0xaa,
- 0x01, 0x28, 0x52, 0x23, 0xfb, 0xe8, 0x29, 0xd8, 0xf9, 0xd7, 0x2a, 0x05, 0xdc, 0x68, 0xd3, 0x84,
- 0xde, 0x19, 0x58, 0x88, 0x6c, 0xbc, 0xc2, 0x1e, 0x1c, 0x00, 0xee, 0x4e, 0x87, 0xb6, 0xd8, 0xdd,
- 0x40, 0x63, 0x20, 0x18, 0x42, 0x4f, 0xd0, 0xc5, 0xd7, 0x97, 0xb2, 0x46, 0x25, 0xe1, 0x5e, 0xac,
- 0x99, 0xfb, 0x89, 0xc2, 0x09, 0x74, 0x0e, 0x99, 0xc0, 0xe3, 0xe1, 0x84, 0x97, 0xce, 0x36, 0xc7,
- 0x2a, 0xf9, 0x99, 0xd9, 0x7f, 0x4e, 0x66, 0xd8, 0x88, 0xcc, 0x47, 0x1a, 0x03, 0x66, 0xcd, 0xe0,
- 0x38, 0xb8, 0xdb, 0x7d, 0x98, 0x8c, 0xbe, 0x34, 0xaa, 0x47, 0x12, 0x52, 0x11, 0x56, 0x56, 0x00,
- 0x76, 0x0e, 0xb9, 0xd2, 0x35, 0xcb, 0x31, 0x94, 0x83, 0x2d, 0x19, 0xbb, 0x10, 0xc9, 0xba, 0x1e,
- 0xea, 0x09, 0x52, 0xe7, 0xda, 0x21, 0xea, 0x34, 0x75, 0x2e, 0x5b, 0x3c, 0xd7, 0xfb, 0x75, 0x6b,
- 0x27, 0xd4, 0x3a, 0x03, 0xbf, 0xcd, 0x3d, 0x9e, 0xe0, 0x73, 0xfd, 0xfa, 0x41, 0xde, 0x3f, 0x53,
- 0xc8, 0xef, 0xb8, 0xd6, 0x2a, 0x7d, 0x4f, 0xee, 0x2a, 0xb3, 0xb9, 0x1c, 0x92, 0x53, 0x3b, 0x8a,
- 0xff, 0xf0, 0x6c, 0x17, 0xaf, 0xc1, 0xd9, 0x6d, 0x59, 0x62, 0x96, 0x6d, 0x1a, 0xfa, 0xf3, 0xe9,
- 0x67, 0xb2, 0x82, 0xcb, 0xd2, 0xff, 0x94, 0x06, 0x79, 0x7c, 0xd5, 0x95, 0x83, 0x4f, 0xc9, 0x08,
- 0xf8, 0x86, 0xe8, 0x13, 0xb4, 0x47, 0x11, 0xa7, 0x77, 0xa8, 0x98, 0xd8, 0xb4, 0x64, 0xd3, 0xa2,
- 0x61, 0xd3, 0x38, 0xb3, 0xf3, 0xdc, 0x41, 0x90, 0xde, 0x0b, 0x95, 0xcb, 0xf7, 0xce, 0x14, 0xf8,
- 0x86, 0x4f, 0xff, 0x11, 0x26, 0xe5, 0xd8, 0xcd, 0x96, 0xff, 0x17, 0xd8, 0x7d, 0xcf, 0x6f, 0x5c,
- 0xec, 0xa7, 0xa1, 0x48, 0x9d, 0x01, 0x00
-};
-
-fastimage_t bfin_logo = {
-		DEF_BFIN_LOGO_DATA,
-		DEF_BFIN_LOGO_WIDTH,
-		DEF_BFIN_LOGO_HEIGHT,
-		DEF_BFIN_LOGO_BPP,
-		DEF_BFIN_LOGO_PIXEL_SIZE,
-		DEF_BFIN_LOGO_SIZE
-};

+ 0 - 1079
arch/blackfin/include/asm/bfin_logo_rgb565_230x230_lzma.h

@@ -1,1079 +0,0 @@
-/*
- * Generated by EasyLogo, (C) 2000 by Paolo Scaffardi
- *
- * To use this, include it and call: easylogo_plot(screen,&bfin_logo, width,x,y)
- *
- * Where:	'screen'	is the pointer to the frame buffer
- *		'width'	is the screen width
- *		'x'		is the horizontal position
- *		'y'		is the vertical position
- */
-
-#define EASYLOGO_ENABLE_LZMA 16703
-
-static unsigned char EASYLOGO_DECOMP_BUFFER[105800];
-
-#include <video_easylogo.h>
-
-#define	DEF_BFIN_LOGO_WIDTH		230
-#define	DEF_BFIN_LOGO_HEIGHT		230
-#define	DEF_BFIN_LOGO_PIXELS		52900
-#define	DEF_BFIN_LOGO_BPP		16
-#define	DEF_BFIN_LOGO_PIXEL_SIZE	2
-#define	DEF_BFIN_LOGO_SIZE		105800
-
-unsigned char DEF_BFIN_LOGO_DATA[] = {
- 0x5d, 0x00, 0x00, 0x80, 0x00, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0x00, 0x00, 0x6f,
- 0xfd, 0xff, 0xff, 0x86, 0x51, 0xd0, 0x3c, 0xfc, 0x65, 0xea, 0x02, 0x56, 0x77, 0x71, 0xde, 0xb1,
- 0x96, 0x62, 0x13, 0xa4, 0x11, 0xbb, 0x19, 0xd3, 0x9a, 0xab, 0x0c, 0x4c, 0x38, 0xa6, 0xe4, 0x24,
- 0x50, 0x2c, 0xfd, 0x3f, 0xd2, 0xc8, 0x41, 0x4b, 0xb3, 0x73, 0x7a, 0xdd, 0x22, 0x8d, 0x88, 0xd2,
- 0x32, 0x18, 0x2e, 0x8a, 0x93, 0x47, 0xf5, 0x99, 0xc7, 0x3f, 0x9c, 0xf5, 0xe7, 0x24, 0xbe, 0xe2,
- 0xbd, 0x73, 0xa7, 0x5a, 0xa6, 0x8d, 0x39, 0xa0, 0x0b, 0xfc, 0x62, 0x94, 0x5d, 0x17, 0xa1, 0x97,
- 0x72, 0xa9, 0xd4, 0xc5, 0xe3, 0x2e, 0x63, 0x86, 0x09, 0x55, 0x3c, 0xd5, 0xc2, 0xe4, 0x56, 0x1d,
- 0x05, 0xc5, 0x76, 0xe7, 0x35, 0x0c, 0x83, 0xbd, 0x33, 0x9b, 0x9f, 0xed, 0x10, 0xb2, 0x96, 0x1a,
- 0xe3, 0x9f, 0x16, 0x88, 0x0b, 0x5b, 0x7e, 0x9c, 0x8e, 0xd4, 0xd1, 0xc0, 0x1b, 0x36, 0xee, 0x23,
- 0xf3, 0xf9, 0xd7, 0x6e, 0xe0, 0x42, 0xe2, 0x99, 0xbe, 0x90, 0xb0, 0x6c, 0xc7, 0x2c, 0xa3, 0x75,
- 0xf6, 0xb6, 0x9d, 0x30, 0x18, 0x87, 0x9c, 0x49, 0x07, 0xf7, 0x78, 0x49, 0x72, 0xa3, 0x62, 0x28,
- 0x7d, 0xa1, 0xc9, 0x15, 0x76, 0x75, 0x63, 0xf7, 0xdf, 0xf4, 0x99, 0x81, 0xa7, 0x1f, 0xfd, 0x93,
- 0xfa, 0x71, 0x91, 0x1b, 0xbe, 0x3e, 0x38, 0xcf, 0x84, 0x51, 0x34, 0x43, 0x23, 0xa7, 0x31, 0x61,
- 0x44, 0x1b, 0x4d, 0x5c, 0x17, 0xcb, 0x39, 0xc6, 0x81, 0x8f, 0x10, 0xb1, 0x73, 0xa0, 0x51, 0x3e,
- 0xba, 0x38, 0xd1, 0x0f, 0x9a, 0x84, 0xc3, 0xa6, 0x30, 0x30, 0x27, 0x4a, 0x01, 0xf8, 0xca, 0xbf,
- 0xea, 0x0e, 0x6f, 0xe3, 0xeb, 0x7d, 0x8a, 0x59, 0x22, 0x07, 0x15, 0xe0, 0xcf, 0x04, 0xb6, 0x03,
- 0xdd, 0x71, 0xef, 0x6a, 0x25, 0xc2, 0x9d, 0x8f, 0xc1, 0x63, 0x2a, 0xec, 0xb8, 0x3e, 0x32, 0xee,
- 0xda, 0x98, 0x28, 0xc0, 0x60, 0x42, 0xe7, 0x0d, 0x38, 0x1b, 0xd0, 0xaa, 0x4c, 0xc4, 0x93, 0x19,
- 0x7a, 0x42, 0x41, 0xe5, 0xf8, 0xa8, 0x42, 0xbc, 0x9c, 0xb4, 0xd8, 0xd2, 0x85, 0xe6, 0x2d, 0xd6,
- 0xad, 0x5c, 0x6d, 0xaa, 0xf8, 0xa5, 0x81, 0xf8, 0x38, 0x05, 0xd9, 0x7c, 0xe2, 0x37, 0x5a, 0x47,
- 0x9d, 0xe7, 0x60, 0x1c, 0xbc, 0x02, 0x2b, 0x66, 0x3a, 0x49, 0xdb, 0xa0, 0xd3, 0x5d, 0x4c, 0xaf,
- 0x8c, 0x01, 0x4d, 0xe3, 0xce, 0xe7, 0x5a, 0xf1, 0x5e, 0x82, 0xd6, 0xcf, 0x69, 0x0c, 0x74, 0x42,
- 0x0a, 0xb3, 0xa3, 0x5a, 0x30, 0x40, 0xee, 0xf6, 0xea, 0xa6, 0xcc, 0x30, 0x44, 0x8c, 0x0f, 0xbc,
- 0x68, 0x0c, 0x49, 0x76, 0x06, 0x1c, 0x76, 0x91, 0xe2, 0xd4, 0x53, 0xc4, 0x29, 0x74, 0x2d, 0x81,
- 0x2e, 0x1f, 0x55, 0x27, 0x36, 0x73, 0x50, 0x24, 0x75, 0xcb, 0x5b, 0x3a, 0xc8, 0x82, 0x0a, 0xf7,
- 0x93, 0x25, 0x94, 0x3d, 0x4a, 0x85, 0x6c, 0xcc, 0x84, 0x1c, 0x5b, 0x58, 0xa9, 0x61, 0xe0, 0xde,
- 0xc2, 0x9e, 0xc6, 0x35, 0xaa, 0x9f, 0x2c, 0x98, 0x5b, 0xd7, 0x74, 0x10, 0x9f, 0x61, 0x8c, 0x67,
- 0x04, 0x3a, 0x1c, 0x37, 0x69, 0x3d, 0xb0, 0x07, 0x8c, 0xfc, 0x22, 0x65, 0x2d, 0x7c, 0x83, 0x91,
- 0x02, 0xc7, 0x4c, 0x59, 0xd3, 0x9e, 0x63, 0x44, 0x64, 0x3f, 0xb8, 0xc4, 0x24, 0x8e, 0xe4, 0xb9,
- 0x64, 0x11, 0x8a, 0x4e, 0x4f, 0xd7, 0x88, 0xb3, 0x5d, 0xb8, 0xe0, 0x19, 0x04, 0xf7, 0x47, 0xec,
- 0xf9, 0xa8, 0x4f, 0x6a, 0xa6, 0x66, 0x49, 0x1b, 0x34, 0xe9, 0xf9, 0x3c, 0x44, 0x51, 0x05, 0x1d,
- 0xb6, 0x81, 0x82, 0xc8, 0xc1, 0x26, 0x3c, 0x1d, 0x8a, 0xa8, 0x2d, 0x80, 0xc7, 0xc9, 0x47, 0x32,
- 0x67, 0x32, 0x05, 0xc1, 0xb1, 0x0a, 0x7e, 0x9b, 0x1e, 0x62, 0xb6, 0x6c, 0x1a, 0x82, 0xf2, 0x49,
- 0xbf, 0x14, 0x0d, 0x7f, 0x0f, 0x61, 0xf9, 0x6e, 0x9f, 0xfa, 0x6b, 0x63, 0x18, 0xfd, 0x36, 0x46,
- 0x1b, 0xc4, 0x76, 0x0e, 0x30, 0x60, 0x29, 0x31, 0x23, 0x42, 0x95, 0x99, 0xbd, 0x9f, 0x5b, 0xe3,
- 0xc8, 0xbd, 0xa4, 0xf9, 0xae, 0xce, 0xcf, 0x9e, 0x43, 0x8f, 0xe3, 0x9d, 0x5b, 0x3b, 0x4e, 0x87,
- 0xe9, 0x58, 0xda, 0x8d, 0xd7, 0x78, 0x43, 0x78, 0x52, 0x01, 0xf2, 0x31, 0xa4, 0x43, 0xeb, 0x84,
- 0x00, 0xf7, 0x5f, 0x2b, 0x63, 0x9d, 0xb9, 0x34, 0x86, 0x9c, 0x94, 0x33, 0xa4, 0x60, 0x36, 0xe0,
- 0x17, 0xf3, 0x6a, 0x7c, 0x0d, 0x3b, 0xe7, 0x7d, 0x2c, 0xc2, 0x92, 0x83, 0x5f, 0xc7, 0x39, 0x2d,
- 0xc6, 0x48, 0x61, 0xc4, 0xde, 0x32, 0x49, 0x8e, 0xbc, 0x7c, 0xf0, 0x18, 0xda, 0xe7, 0x7c, 0xef,
- 0x49, 0xd1, 0xa7, 0xf9, 0xa9, 0x11, 0x67, 0x33, 0x28, 0xee, 0x65, 0x47, 0x99, 0xa7, 0x83, 0xdf,
- 0x3f, 0x8c, 0x23, 0x2f, 0xb5, 0x55, 0xff, 0x79, 0x0b, 0xc0, 0xc7, 0x3d, 0x1e, 0x2b, 0xf9, 0x20,
- 0x93, 0x6b, 0x05, 0x50, 0x94, 0x0c, 0x5c, 0x3f, 0x94, 0x4b, 0x99, 0x10, 0x25, 0x4b, 0xb7, 0x1a,
- 0x8c, 0xe1, 0xaf, 0xe9, 0x8b, 0xde, 0x89, 0x50, 0xa8, 0x08, 0xbb, 0x1a, 0xec, 0xdf, 0xe8, 0x95,
- 0x06, 0x51, 0xe6, 0xb7, 0x26, 0x07, 0xeb, 0x5b, 0x8e, 0x4b, 0x50, 0x64, 0x5c, 0x8d, 0xb5, 0x52,
- 0x30, 0xf5, 0xc9, 0x07, 0xf2, 0x54, 0x4f, 0x7c, 0xb0, 0xfb, 0xa4, 0x48, 0xfd, 0x3c, 0x50, 0xbb,
- 0xcb, 0x39, 0xbe, 0x9a, 0x74, 0x44, 0x85, 0x01, 0x0f, 0x77, 0x1d, 0x86, 0x1f, 0x9a, 0x35, 0x06,
- 0x14, 0x48, 0x08, 0x6d, 0xc1, 0x89, 0xc6, 0x38, 0x5c, 0x8f, 0x1a, 0xc4, 0x89, 0xe7, 0x29, 0xa2,
- 0x87, 0x8a, 0xf2, 0xf7, 0x13, 0x5c, 0x2b, 0x0c, 0x17, 0x22, 0xc6, 0x02, 0x97, 0x5c, 0xe9, 0x10,
- 0xc4, 0xbd, 0x6b, 0x91, 0x9a, 0x0b, 0x70, 0x85, 0xd3, 0x91, 0xce, 0x12, 0x34, 0xef, 0xe3, 0xf7,
- 0xf6, 0xbf, 0x55, 0x0a, 0x67, 0xdd, 0x42, 0x7c, 0xa0, 0x46, 0xad, 0x30, 0xa1, 0xdf, 0x73, 0x6d,
- 0x93, 0x26, 0x57, 0xae, 0x2a, 0xe6, 0xea, 0x2c, 0xe5, 0xf3, 0x09, 0xaa, 0xdd, 0x09, 0xc7, 0xa0,
- 0x0c, 0xef, 0x86, 0xa8, 0x42, 0x93, 0x5e, 0x61, 0xe4, 0xa4, 0x08, 0xaa, 0x37, 0x4b, 0xd4, 0x94,
- 0x83, 0xe1, 0x42, 0x06, 0x65, 0x11, 0x4e, 0xbf, 0xc3, 0xfb, 0xbf, 0x86, 0x4f, 0x01, 0x69, 0x93,
- 0xd5, 0xc8, 0xb4, 0x5d, 0x23, 0x79, 0x38, 0x8a, 0x6b, 0x9f, 0xfb, 0x56, 0xb0, 0x16, 0x6e, 0x9f,
- 0xdf, 0x40, 0x96, 0x9c, 0x92, 0x17, 0xae, 0xdb, 0xba, 0x4e, 0xd6, 0x88, 0x44, 0x2f, 0xaf, 0x84,
- 0xa3, 0xb6, 0x04, 0xa1, 0x59, 0x42, 0x3f, 0xd4, 0x45, 0x0d, 0x76, 0xb2, 0x67, 0x6f, 0xab, 0xad,
- 0xe8, 0xda, 0x1d, 0x8e, 0x07, 0x96, 0xc5, 0x1c, 0xf9, 0x97, 0xe2, 0x21, 0x97, 0xd9, 0x4c, 0x79,
- 0x02, 0xe5, 0x0c, 0x57, 0x59, 0x1b, 0xcb, 0x09, 0x9a, 0xb3, 0x34, 0xc7, 0x0b, 0x66, 0x8a, 0xc9,
- 0x38, 0xa6, 0x2c, 0x27, 0xac, 0x20, 0xbd, 0x69, 0x54, 0xa1, 0x33, 0x9a, 0x70, 0x4f, 0x9d, 0xe2,
- 0x6e, 0x79, 0x72, 0x17, 0xfc, 0x12, 0xe9, 0x96, 0x0c, 0x12, 0x5d, 0x44, 0xb7, 0x71, 0x87, 0x03,
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- 0x5c, 0xcc, 0x82, 0x50, 0xf7, 0x53, 0x97, 0xda, 0xfc, 0xf0, 0x96, 0xda, 0xec, 0x10, 0x57, 0xc2,
- 0xc4, 0x02, 0x06, 0xdb, 0x2d, 0xe6, 0x96, 0x29, 0x0b, 0x04, 0x56, 0xf9, 0x39, 0x02, 0x37, 0x3c,
- 0x65, 0x9a, 0x76, 0xa1, 0x0b, 0x1c, 0xa3, 0xae, 0x7c, 0xae, 0xb3, 0x68, 0x5c, 0x1b, 0x2f, 0xaf,
- 0xfe, 0x9c, 0xb9, 0x64, 0x3d, 0x35, 0x84, 0x2d, 0x26, 0x48, 0xa8, 0x4d, 0x0a, 0x57, 0xec, 0x15,
- 0x2f, 0x7b, 0x8d, 0x1a, 0x6d, 0xb4, 0x72, 0xb1, 0xf3, 0xfa, 0x97, 0x9f, 0x3a, 0x8a, 0xe6, 0x5e,
- 0xf1, 0xc4, 0xcc, 0x6e, 0x75, 0x25, 0x5b, 0x4d, 0x6b, 0xac, 0x47, 0x30, 0xa5, 0x64, 0x51, 0xf1,
- 0x87, 0xf0, 0x85, 0x54, 0x82, 0x23, 0x3e, 0xf8, 0x32, 0xbd, 0x11, 0x17, 0x8a, 0xb3, 0x49, 0xac,
- 0xec, 0x6f, 0x59, 0x7e, 0x5f, 0xd0, 0xcd, 0x3f, 0xa8, 0x1e, 0xa8, 0xd6, 0xb8, 0xda, 0x92, 0x03,
- 0x4f, 0xc8, 0x12, 0x59, 0x93, 0x8c, 0xb3, 0x48, 0x8a, 0x80, 0xef, 0xbe, 0xb9, 0xd4, 0xfa, 0x90,
- 0xd9, 0xf2, 0x1c, 0x7a, 0x3e, 0x73, 0x99, 0x33, 0xaf, 0x6a, 0x79, 0x03, 0xf2, 0x02, 0x5b, 0x1a,
- 0x4f, 0xf7, 0x09, 0x9a, 0x7a, 0x07, 0xd4, 0xe8, 0x88, 0xc1, 0x5b, 0xf0, 0x05, 0xd0, 0x30, 0xab,
- 0x6c, 0x18, 0x6a, 0x3e, 0x8d, 0x1e, 0xdd, 0x2d, 0xdb, 0x23, 0xa8, 0xdb, 0x7c, 0xaa, 0xd1, 0xd6,
- 0xe3, 0xc6, 0xaa, 0xf7, 0x34, 0xad, 0x09, 0xba, 0xf2, 0xa7, 0x16, 0xed, 0x88, 0x7c, 0xe4, 0xe4,
- 0xcc, 0x99, 0x7e, 0xa1, 0xb4, 0x8f, 0xaf, 0x35, 0x11, 0x01, 0x42, 0xf2, 0x19, 0x37, 0x51, 0x18,
- 0x25, 0xc2, 0x35, 0x43, 0xde, 0x85, 0xd8, 0x43, 0x41, 0x16, 0x59, 0x28, 0x1e, 0xc8, 0x6f, 0xd2,
- 0xba, 0xbf, 0x18, 0x52, 0x9c, 0x13, 0x9c, 0x15, 0xe9, 0xbc, 0xd7, 0x21, 0xfa, 0x59, 0x9a, 0x60,
- 0x1e, 0xec, 0x64, 0xd9, 0x60, 0x8d, 0x31, 0x8c, 0xd6, 0x1e, 0x7d, 0xc4, 0xa8, 0x81, 0x76, 0x41,
- 0xa2, 0x41, 0x37, 0x04, 0xe4, 0x87, 0xc5, 0xe4, 0x58, 0x01, 0x37, 0x93, 0x9a, 0x76, 0xbd, 0x20,
- 0x86, 0xc9, 0xb7, 0x52, 0xb6, 0xd3, 0x59, 0x3f, 0x9f, 0xc8, 0xea, 0xbb, 0x9a, 0x71, 0x34, 0x36,
- 0x26, 0x83, 0xd2, 0xab, 0xb6, 0x6b, 0x45, 0x58, 0x0b, 0x73, 0xfd, 0x8d, 0x50, 0x0d, 0x81, 0x12,
- 0x10, 0x5a, 0xdf, 0x2c, 0x53, 0x6b, 0x48, 0x18, 0x60, 0x10, 0x69, 0xcd, 0x73, 0x52, 0x40, 0xd6,
- 0x14, 0x69, 0x68, 0x68, 0x8e, 0xe3, 0x01, 0x54, 0x3c, 0x8e, 0x8b, 0xe0, 0x77, 0x77, 0xdc, 0x5f,
- 0xca, 0x01, 0xc6, 0x08, 0x0b, 0xbf, 0x16, 0x5d, 0x71, 0x8f, 0x3e, 0xf7, 0x8e, 0x8f, 0x1f, 0x66,
- 0xcf, 0x49, 0xb3, 0xe8, 0x55, 0x00, 0x8d, 0x86, 0xcb, 0x3f, 0x2b, 0x03, 0x61, 0xde, 0x10, 0x4e,
- 0x7b, 0x24, 0xb2, 0x08, 0xec, 0x0f, 0xe6, 0xcd, 0x9c, 0xa1, 0xa4, 0x98, 0xe0, 0x0d, 0xcd, 0x20,
- 0xfa, 0x3a, 0x83, 0xb5, 0xec, 0x4c, 0x69, 0xa6, 0xfa, 0x2d, 0xe6, 0x76, 0xda, 0x8c, 0xc2, 0xe2,
- 0x04, 0x75, 0xfd, 0xb3, 0xdc, 0x8d, 0x93, 0x64, 0xd1, 0xa3, 0xcc, 0xb0, 0xf5, 0xbd, 0x0a, 0xaa,
- 0xbe, 0x0e, 0xe8, 0x19, 0x01, 0xb8, 0xc2, 0x4f, 0x5e, 0x78, 0x2f, 0x1a, 0x30, 0xf0, 0xb3, 0x8a,
- 0x5d, 0x9d, 0xc5, 0xac, 0xf4, 0x7b, 0x0d, 0xe4, 0xd4, 0x96, 0xea, 0xca, 0x4b, 0x85, 0x81, 0x3a,
- 0x0d, 0xe9, 0x0b, 0x37, 0x56, 0x9d, 0x0e, 0xd7, 0x02, 0x67, 0x87, 0x03, 0x09, 0xfd, 0x1b, 0x67,
- 0xd5, 0xe4, 0x69, 0xcc, 0xfc, 0xc3, 0xbf, 0x9a, 0x6d, 0x93, 0xc4, 0x45, 0x9c, 0xf8, 0xd9, 0x03,
- 0xad, 0x65, 0x70, 0x82, 0x49, 0xd3, 0xac, 0xa7, 0x8a, 0xf3, 0xda, 0x01, 0xbd, 0x26, 0xb3, 0xa4,
- 0xd7, 0x8a, 0x91, 0xbf, 0xea, 0x8b, 0x2b, 0xb0, 0x6c, 0xd8, 0x84, 0x7b, 0x4b, 0xf4, 0x2c, 0xbc,
- 0x45, 0x30, 0xe1, 0xf0, 0xbf, 0xfc, 0x4c, 0x81, 0xfc, 0x07, 0xa7, 0xea, 0x34, 0xcb, 0x15, 0x55,
- 0xa9, 0x9e, 0x70, 0x4f, 0xbb, 0xd8, 0x1b, 0xd6, 0x1b, 0x2d, 0x4e, 0x20, 0x72, 0x44, 0x00, 0x36,
- 0x1f, 0x23, 0x06, 0x40, 0x7e, 0xde, 0x3e, 0xd4, 0x61, 0x6f, 0x12, 0x56, 0x04, 0xd7, 0x58, 0x2f,
- 0x8d, 0x66, 0x0b, 0xff, 0xd2, 0x23, 0x5c, 0xf4, 0xd4, 0xa3, 0x58, 0xd0, 0x6d, 0xf6, 0x98, 0xab,
- 0xc5, 0x53, 0xea, 0xc4, 0x37, 0x47, 0xc3, 0x4a, 0x8d, 0xc6, 0x4c, 0x19, 0x5d, 0x17, 0xb4, 0x39,
- 0x71, 0xe9, 0x99, 0x82, 0xe6, 0x5b, 0xc5, 0x90, 0x33, 0xf7, 0x5b, 0x8d, 0x98, 0x4c, 0xcd, 0x7a,
- 0x6b, 0xd8, 0xb9, 0x8c, 0x11, 0x34, 0x8d, 0xc0, 0x9a, 0x57, 0x2a, 0x12, 0xd5, 0x7f, 0x3f, 0x94,
- 0x70, 0x93, 0x1a, 0x11, 0xe9, 0xf3, 0x99, 0x4f, 0x10, 0x38, 0xc7, 0xc2, 0xec, 0x62, 0xac, 0x59,
- 0x90, 0x3a, 0x85, 0x1d, 0xeb, 0xee, 0xa3, 0x90, 0x59, 0xfd, 0x0a, 0x07, 0x0a, 0xc7, 0x32, 0x2d,
- 0x11, 0x18, 0x53, 0x70, 0x80, 0x59, 0x59, 0x51, 0x33, 0xd8, 0x29, 0x85, 0xf4, 0x09, 0xf6, 0x76,
- 0x1e, 0x49, 0xa6, 0x79, 0xc1, 0x2c, 0xae, 0xa6, 0x54, 0xbe, 0xf6, 0x54, 0xb1, 0x95, 0x39, 0x97,
- 0xeb, 0xdc, 0xb2, 0xff, 0x99, 0x19, 0x9a, 0x9b, 0x0e, 0xad, 0x0e, 0x3f, 0xbf, 0xe0, 0x39, 0x8e,
- 0x27, 0x37, 0x1c, 0xdc, 0x86, 0x20, 0x1f, 0x21, 0xd5, 0x0e, 0xd6, 0xbc, 0x45, 0x3e, 0x1d, 0x33,
- 0x3b, 0x15, 0x35, 0xf9, 0x52, 0x98, 0x6f, 0x9a, 0x44, 0x25, 0x01, 0x6b, 0x3d, 0x47, 0x3b, 0x11,
- 0x35, 0x0e, 0x2a, 0xb5, 0x4e, 0xb3, 0xc9, 0x24, 0xe5, 0xae, 0x5b, 0x0e, 0x5f, 0x6a, 0x85, 0x89,
- 0xe5, 0x94, 0xd1, 0x74, 0x08, 0x70, 0x8b, 0xbe, 0x4d, 0xb8, 0x77, 0x4c, 0xa3, 0x14, 0x04, 0x09,
- 0xfe, 0x17, 0x0a, 0xca, 0xb0, 0x9a, 0x5d, 0x63, 0x01, 0xd0, 0xf3, 0xe9, 0x3d, 0xde, 0xaf, 0x0b,
- 0x31, 0x13, 0x61, 0x7a, 0x99, 0xf7, 0x00, 0x17, 0xb0, 0x3a, 0xfc, 0x27, 0x62, 0xfe, 0xd1, 0x36,
- 0x87, 0xb5, 0xfe, 0xd2, 0xad, 0xff, 0xfd, 0xfb, 0xb5, 0x38, 0x8b, 0xca, 0x64, 0xdc, 0x55, 0xb5,
- 0x4e, 0xed, 0x07, 0x07, 0x97, 0x13, 0x6b, 0xa1, 0x33, 0x42, 0x95, 0xb2, 0xaa, 0x0b, 0xf9, 0x1d,
- 0x94, 0x86, 0x37, 0x17, 0xe4, 0x7a, 0x63, 0xe8, 0x99, 0x5b, 0xe9, 0xfc, 0x30, 0x6e, 0x26, 0xed,
- 0x21, 0xd2, 0x0a, 0x28, 0xe5, 0xa0, 0xd7, 0x64, 0x02, 0x5e, 0xb1, 0x3a, 0x40, 0x4d, 0x2c, 0x2b,
- 0x4e, 0xc9, 0xbe, 0xf3, 0xe6, 0x91, 0x34, 0xe6, 0x71, 0xd5, 0xce, 0xdb, 0x47, 0x40, 0xbd, 0x80,
- 0x80, 0x48, 0x9b, 0xaf, 0x81, 0xf4, 0x83, 0x3f, 0x8e, 0x3c, 0x49, 0xf6, 0x29, 0x0c, 0x17, 0x91,
- 0xf2, 0x8f, 0x83, 0xfb, 0xb6, 0x04, 0x57, 0x13, 0x2f, 0x59, 0xa1, 0x7b, 0x72, 0xd4, 0x6c, 0x84,
- 0x41, 0x36, 0x86, 0x9e, 0x56, 0x7a, 0x73, 0x59, 0x54, 0x47, 0x8c, 0x85, 0x3f, 0x8d, 0x3a, 0xcc,
- 0x1b, 0x0b, 0x97, 0x26, 0x7a, 0x53, 0x09, 0x05, 0x37, 0xa1, 0x6d, 0x36, 0x62, 0xe9, 0x43, 0xb1,
- 0xf3, 0xe3, 0xb1, 0xc0, 0x80, 0xf7, 0x2e, 0xae, 0x49, 0x7a, 0xe6, 0xba, 0x1b, 0x42, 0x87, 0x5c,
- 0xc3, 0xae, 0x2c, 0xd0, 0xd2, 0x98, 0x77, 0x43, 0xd1, 0x81, 0x26, 0x9a, 0xe2, 0xbf, 0xf4, 0x6f,
- 0xee, 0x24, 0x52, 0xfb, 0x1f, 0x6a, 0x1f, 0x21, 0xef, 0xf0, 0xc6, 0x02, 0x85, 0xde, 0x1a, 0x4d,
- 0x13, 0xff, 0xa1, 0x58, 0x43, 0x79, 0xb7, 0xc9, 0x45, 0x51, 0x3f, 0x90, 0xb6, 0x76, 0xbb, 0xfb,
- 0x51, 0x8e, 0x37, 0xab, 0x13, 0x36, 0x84, 0x7b, 0xea, 0xea, 0x68, 0x49, 0xd7, 0x5b, 0x42, 0x64,
- 0x09, 0x76, 0x7b, 0x6e, 0xe6, 0x93, 0xd3, 0x27, 0x37, 0xce, 0x2f, 0xd7, 0x3b, 0x1e, 0xf0, 0xd2,
- 0x15, 0xb0, 0xc9, 0xb3, 0x09, 0xef, 0xfe, 0x60, 0xa5, 0x79, 0xb5, 0xb6, 0x30, 0x85, 0x0e, 0xcc,
- 0xbb, 0x23, 0x53, 0x58, 0x28, 0xf5, 0x66, 0xe7, 0xed, 0x2a, 0x0e, 0x8e, 0xdd, 0x23, 0x0d, 0x36,
- 0x84, 0xf3, 0xbe, 0x75, 0xe9, 0xf7, 0x47, 0x07, 0xf4, 0x39, 0x7b, 0x57, 0xe7, 0x1d, 0x94, 0xff,
- 0xe7, 0xe4, 0x9b, 0x91, 0x3d, 0x6e, 0xba, 0x28, 0xca, 0x07, 0xbb, 0xc9, 0xb1, 0x84, 0x7c, 0x6a,
- 0x50, 0x97, 0xf1, 0xf7, 0x22, 0xa7, 0xa3, 0x36, 0x28, 0xe9, 0x3a, 0x60, 0x30, 0x84, 0x73, 0xe8,
- 0x60, 0xbf, 0x26, 0xac, 0x57, 0xa9, 0xab, 0xd2, 0xb1, 0x3f, 0xff, 0xfc, 0x33, 0xe0, 0x8d
-};
-
-fastimage_t bfin_logo = {
-		DEF_BFIN_LOGO_DATA,
-		DEF_BFIN_LOGO_WIDTH,
-		DEF_BFIN_LOGO_HEIGHT,
-		DEF_BFIN_LOGO_BPP,
-		DEF_BFIN_LOGO_PIXEL_SIZE,
-		DEF_BFIN_LOGO_SIZE
-};

+ 0 - 358
arch/blackfin/include/asm/bitops.h

@@ -1,358 +0,0 @@
-/*
- * U-Boot - bitops.h Routines for bit operations
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BLACKFIN_BITOPS_H
-#define _BLACKFIN_BITOPS_H
-
-/*
- * Copyright 1992, Linus Torvalds.
- */
-
-#include <asm/byteorder.h>
-#include <asm/system.h>
-#include <asm-generic/bitops/fls.h>
-#include <asm-generic/bitops/__fls.h>
-#include <asm-generic/bitops/fls64.h>
-#include <asm-generic/bitops/__ffs.h>
-
-#ifdef __KERNEL__
-/*
- * Function prototypes to keep gcc -Wall happy
- */
-
-/*
- * The __ functions are not atomic
- */
-
-/*
- * ffz = Find First Zero in word. Undefined if no zero exists,
- * so code should check against ~0UL first..
- */
-static __inline__ unsigned long ffz(unsigned long word)
-{
-	unsigned long result = 0;
-
-	while (word & 1) {
-		result++;
-		word >>= 1;
-	}
-	return result;
-}
-
-static __inline__ void set_bit(int nr, volatile void *addr)
-{
-	int *a = (int *)addr;
-	int mask;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	*a |= mask;
-	local_irq_restore(flags);
-}
-
-static __inline__ void __set_bit(int nr, volatile void *addr)
-{
-	int *a = (int *)addr;
-	int mask;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	*a |= mask;
-}
-#define PLATFORM__SET_BIT
-
-/*
- * clear_bit() doesn't provide any barrier for the compiler.
- */
-#define smp_mb__before_clear_bit()	barrier()
-#define smp_mb__after_clear_bit()	barrier()
-
-static __inline__ void clear_bit(int nr, volatile void *addr)
-{
-	int *a = (int *)addr;
-	int mask;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	*a &= ~mask;
-	local_irq_restore(flags);
-}
-
-static __inline__ void change_bit(int nr, volatile void *addr)
-{
-	int mask, flags;
-	unsigned long *ADDR = (unsigned long *)addr;
-
-	ADDR += nr >> 5;
-	mask = 1 << (nr & 31);
-	local_irq_save(flags);
-	*ADDR ^= mask;
-	local_irq_restore(flags);
-}
-
-static __inline__ void __change_bit(int nr, volatile void *addr)
-{
-	int mask;
-	unsigned long *ADDR = (unsigned long *)addr;
-
-	ADDR += nr >> 5;
-	mask = 1 << (nr & 31);
-	*ADDR ^= mask;
-}
-
-static __inline__ int test_and_set_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	retval = (mask & *a) != 0;
-	*a |= mask;
-	local_irq_restore(flags);
-
-	return retval;
-}
-
-static __inline__ int __test_and_set_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a |= mask;
-	return retval;
-}
-
-static __inline__ int test_and_clear_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	retval = (mask & *a) != 0;
-	*a &= ~mask;
-	local_irq_restore(flags);
-
-	return retval;
-}
-
-static __inline__ int __test_and_clear_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a &= ~mask;
-	return retval;
-}
-
-static __inline__ int test_and_change_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-	unsigned long flags;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	local_irq_save(flags);
-	retval = (mask & *a) != 0;
-	*a ^= mask;
-	local_irq_restore(flags);
-
-	return retval;
-}
-
-static __inline__ int __test_and_change_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	volatile unsigned int *a = (volatile unsigned int *)addr;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	retval = (mask & *a) != 0;
-	*a ^= mask;
-	return retval;
-}
-
-/*
- * This routine doesn't need to be atomic.
- */
-static __inline__ int __constant_test_bit(int nr, const volatile void *addr)
-{
-	return ((1UL << (nr & 31)) &
-		(((const volatile unsigned int *)addr)[nr >> 5])) != 0;
-}
-
-static __inline__ int __test_bit(int nr, volatile void *addr)
-{
-	int *a = (int *)addr;
-	int mask;
-
-	a += nr >> 5;
-	mask = 1 << (nr & 0x1f);
-	return ((mask & *a) != 0);
-}
-
-#define	test_bit(nr,addr) \
-(__builtin_constant_p(nr) ? \
- __constant_test_bit((nr),(addr)) : \
- __test_bit((nr),(addr)))
-
-#define	find_first_zero_bit(addr, size) \
-	find_next_zero_bit((addr), (size), 0)
-
-static __inline__ int find_next_zero_bit(void *addr, int size, int offset)
-{
-	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
-	unsigned long result = offset & ~31UL;
-	unsigned long tmp;
-
-	if (offset >= size)
-		return size;
-	size -= result;
-	offset &= 31UL;
-	if (offset) {
-		tmp = *(p++);
-		tmp |= ~0UL >> (32 - offset);
-		if (size < 32)
-			goto found_first;
-		if (~tmp)
-			goto found_middle;
-		size -= 32;
-		result += 32;
-	}
-	while (size & ~31UL) {
-		if (~(tmp = *(p++)))
-			goto found_middle;
-		result += 32;
-		size -= 32;
-	}
-	if (!size)
-		return result;
-	tmp = *p;
-
-      found_first:
-	tmp |= ~0UL >> size;
-      found_middle:
-	return result + ffz(tmp);
-}
-
-/*
- * hweightN: returns the hamming weight (i.e. the number
- * of bits set) of a N-bit word
- */
-
-#define hweight32(x)	generic_hweight32(x)
-#define hweight16(x)	generic_hweight16(x)
-#define hweight8(x)	generic_hweight8(x)
-
-static __inline__ int ext2_set_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	unsigned long flags;
-	volatile unsigned char *ADDR = (unsigned char *)addr;
-
-	ADDR += nr >> 3;
-	mask = 1 << (nr & 0x07);
-	local_irq_save(flags);
-	retval = (mask & *ADDR) != 0;
-	*ADDR |= mask;
-	local_irq_restore(flags);
-	return retval;
-}
-
-static __inline__ int ext2_clear_bit(int nr, volatile void *addr)
-{
-	int mask, retval;
-	unsigned long flags;
-	volatile unsigned char *ADDR = (unsigned char *)addr;
-
-	ADDR += nr >> 3;
-	mask = 1 << (nr & 0x07);
-	local_irq_save(flags);
-	retval = (mask & *ADDR) != 0;
-	*ADDR &= ~mask;
-	local_irq_restore(flags);
-	return retval;
-}
-
-static __inline__ int ext2_test_bit(int nr, const volatile void *addr)
-{
-	int mask;
-	const volatile unsigned char *ADDR = (const unsigned char *)addr;
-
-	ADDR += nr >> 3;
-	mask = 1 << (nr & 0x07);
-	return ((mask & *ADDR) != 0);
-}
-
-#define ext2_find_first_zero_bit(addr, size) \
-	ext2_find_next_zero_bit((addr), (size), 0)
-
-static __inline__ unsigned long ext2_find_next_zero_bit(void *addr,
-							unsigned long size,
-							unsigned long offset)
-{
-	unsigned long *p = ((unsigned long *)addr) + (offset >> 5);
-	unsigned long result = offset & ~31UL;
-	unsigned long tmp;
-
-	if (offset >= size)
-		return size;
-	size -= result;
-	offset &= 31UL;
-	if (offset) {
-		tmp = *(p++);
-		tmp |= ~0UL >> (32 - offset);
-		if (size < 32)
-			goto found_first;
-		if (~tmp)
-			goto found_middle;
-		size -= 32;
-		result += 32;
-	}
-	while (size & ~31UL) {
-		if (~(tmp = *(p++)))
-			goto found_middle;
-		result += 32;
-		size -= 32;
-	}
-	if (!size)
-		return result;
-	tmp = *p;
-
-      found_first:
-	tmp |= ~0UL >> size;
-      found_middle:
-	return result + ffz(tmp);
-}
-
-/* Bitmap functions for the minix filesystem. */
-#define minix_test_and_set_bit(nr,addr)		test_and_set_bit(nr,addr)
-#define minix_set_bit(nr,addr)			set_bit(nr,addr)
-#define minix_test_and_clear_bit(nr,addr)	test_and_clear_bit(nr,addr)
-#define minix_test_bit(nr,addr)			test_bit(nr,addr)
-#define minix_find_first_zero_bit(addr,size)	find_first_zero_bit(addr,size)
-
-#endif
-
-#endif

+ 0 - 15
arch/blackfin/include/asm/blackfin.h

@@ -1,15 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __MACH_GLOB_BLACKFIN__
-#define __MACH_GLOB_BLACKFIN__
-
-#include "blackfin_def.h"
-#ifndef __ASSEMBLY__
-#include "blackfin_cdef.h"
-#endif
-#include "blackfin_local.h"
-
-#endif /* __MACH_GLOB_BLACKFIN__ */

+ 0 - 91
arch/blackfin/include/asm/blackfin_cdef.h

@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __MACH_CDEF_BLACKFIN__
-#define __MACH_CDEF_BLACKFIN__
-
-#ifdef __ADSPBF504__
-# include "mach-bf506/BF504_cdef.h"
-#endif
-#ifdef __ADSPBF506__
-# include "mach-bf506/BF506_cdef.h"
-#endif
-#ifdef __ADSPBF512__
-# include "mach-bf518/BF512_cdef.h"
-#endif
-#ifdef __ADSPBF514__
-# include "mach-bf518/BF514_cdef.h"
-#endif
-#ifdef __ADSPBF516__
-# include "mach-bf518/BF516_cdef.h"
-#endif
-#ifdef __ADSPBF518__
-# include "mach-bf518/BF518_cdef.h"
-#endif
-#ifdef __ADSPBF522__
-# include "mach-bf527/BF522_cdef.h"
-#endif
-#ifdef __ADSPBF523__
-# include "mach-bf527/BF523_cdef.h"
-#endif
-#ifdef __ADSPBF524__
-# include "mach-bf527/BF524_cdef.h"
-#endif
-#ifdef __ADSPBF525__
-# include "mach-bf527/BF525_cdef.h"
-#endif
-#ifdef __ADSPBF526__
-# include "mach-bf527/BF526_cdef.h"
-#endif
-#ifdef __ADSPBF527__
-# include "mach-bf527/BF527_cdef.h"
-#endif
-#ifdef __ADSPBF531__
-# include "mach-bf533/BF531_cdef.h"
-#endif
-#ifdef __ADSPBF532__
-# include "mach-bf533/BF532_cdef.h"
-#endif
-#ifdef __ADSPBF533__
-# include "mach-bf533/BF533_cdef.h"
-#endif
-#ifdef __ADSPBF534__
-# include "mach-bf537/BF534_cdef.h"
-#endif
-#ifdef __ADSPBF536__
-# include "mach-bf537/BF536_cdef.h"
-#endif
-#ifdef __ADSPBF537__
-# include "mach-bf537/BF537_cdef.h"
-#endif
-#ifdef __ADSPBF538__
-# include "mach-bf538/BF538_cdef.h"
-#endif
-#ifdef __ADSPBF539__
-# include "mach-bf538/BF539_cdef.h"
-#endif
-#ifdef __ADSPBF542__
-# include "mach-bf548/BF542_cdef.h"
-#endif
-#ifdef __ADSPBF544__
-# include "mach-bf548/BF544_cdef.h"
-#endif
-#ifdef __ADSPBF547__
-# include "mach-bf548/BF547_cdef.h"
-#endif
-#ifdef __ADSPBF548__
-# include "mach-bf548/BF548_cdef.h"
-#endif
-#ifdef __ADSPBF549__
-# include "mach-bf548/BF549_cdef.h"
-#endif
-#ifdef __ADSPBF561__
-# include "mach-bf561/BF561_cdef.h"
-#endif
-#ifdef __ADSPBF609__
-# include "mach-bf609/BF609_cdef.h"
-#endif
-
-#endif /* __MACH_CDEF_BLACKFIN__ */

+ 0 - 145
arch/blackfin/include/asm/blackfin_def.h

@@ -1,145 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by toolchain/trunk/proc-defs/sh/create-arch-headers.sh
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __MACH_DEF_BLACKFIN__
-#define __MACH_DEF_BLACKFIN__
-
-#ifdef __ADSPBF504__
-# include "mach-bf506/BF504_def.h"
-# include "mach-bf506/anomaly.h"
-# include "mach-bf506/def_local.h"
-#endif
-#ifdef __ADSPBF506__
-# include "mach-bf506/BF506_def.h"
-# include "mach-bf506/anomaly.h"
-# include "mach-bf506/def_local.h"
-#endif
-#ifdef __ADSPBF512__
-# include "mach-bf518/BF512_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF514__
-# include "mach-bf518/BF514_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF516__
-# include "mach-bf518/BF516_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF518__
-# include "mach-bf518/BF518_def.h"
-# include "mach-bf518/anomaly.h"
-# include "mach-bf518/def_local.h"
-#endif
-#ifdef __ADSPBF522__
-# include "mach-bf527/BF522_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF523__
-# include "mach-bf527/BF523_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF524__
-# include "mach-bf527/BF524_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF525__
-# include "mach-bf527/BF525_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF526__
-# include "mach-bf527/BF526_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF527__
-# include "mach-bf527/BF527_def.h"
-# include "mach-bf527/anomaly.h"
-# include "mach-bf527/def_local.h"
-#endif
-#ifdef __ADSPBF531__
-# include "mach-bf533/BF531_def.h"
-# include "mach-bf533/anomaly.h"
-# include "mach-bf533/def_local.h"
-#endif
-#ifdef __ADSPBF532__
-# include "mach-bf533/BF532_def.h"
-# include "mach-bf533/anomaly.h"
-# include "mach-bf533/def_local.h"
-#endif
-#ifdef __ADSPBF533__
-# include "mach-bf533/BF533_def.h"
-# include "mach-bf533/anomaly.h"
-# include "mach-bf533/def_local.h"
-#endif
-#ifdef __ADSPBF534__
-# include "mach-bf537/BF534_def.h"
-# include "mach-bf537/anomaly.h"
-# include "mach-bf537/def_local.h"
-#endif
-#ifdef __ADSPBF536__
-# include "mach-bf537/BF536_def.h"
-# include "mach-bf537/anomaly.h"
-# include "mach-bf537/def_local.h"
-#endif
-#ifdef __ADSPBF537__
-# include "mach-bf537/BF537_def.h"
-# include "mach-bf537/anomaly.h"
-# include "mach-bf537/def_local.h"
-#endif
-#ifdef __ADSPBF538__
-# include "mach-bf538/BF538_def.h"
-# include "mach-bf538/anomaly.h"
-# include "mach-bf538/def_local.h"
-#endif
-#ifdef __ADSPBF539__
-# include "mach-bf538/BF539_def.h"
-# include "mach-bf538/anomaly.h"
-# include "mach-bf538/def_local.h"
-#endif
-#ifdef __ADSPBF542__
-# include "mach-bf548/BF542_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF544__
-# include "mach-bf548/BF544_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF547__
-# include "mach-bf548/BF547_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF548__
-# include "mach-bf548/BF548_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF549__
-# include "mach-bf548/BF549_def.h"
-# include "mach-bf548/anomaly.h"
-# include "mach-bf548/def_local.h"
-#endif
-#ifdef __ADSPBF561__
-# include "mach-bf561/BF561_def.h"
-# include "mach-bf561/anomaly.h"
-# include "mach-bf561/def_local.h"
-#endif
-#ifdef __ADSPBF609__
-# include "mach-bf609/BF609_def.h"
-# include "mach-bf609/anomaly.h"
-# include "mach-bf609/def_local.h"
-#endif
-
-#endif /* __MACH_DEF_BLACKFIN__ */

+ 0 - 208
arch/blackfin/include/asm/blackfin_local.h

@@ -1,208 +0,0 @@
-/*
- * U-Boot - blackfin_local.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __BLACKFIN_LOCAL_H__
-#define __BLACKFIN_LOCAL_H__
-
-#include <asm/mem_map.h>
-
-#define LO(con32) ((con32) & 0xFFFF)
-#define lo(con32) ((con32) & 0xFFFF)
-#define HI(con32) (((con32) >> 16) & 0xFFFF)
-#define hi(con32) (((con32) >> 16) & 0xFFFF)
-
-#define OFFSET_(x) (x & 0x0000FFFF)
-#define MK_BMSK_(x) (1 << x)
-
-/* Ideally this should be USEC not MSEC, but the USEC multiplication
- * likes to overflow 32bit quantities which is all our assembler
- * currently supports ;(
- */
-#define USEC_PER_MSEC 1000
-#define MSEC_PER_SEC 1000
-#define BFIN_SCLK (100000000)
-#define SCLK_TO_MSEC(sclk) ((MSEC_PER_SEC * ((sclk) / USEC_PER_MSEC)) / (BFIN_SCLK / USEC_PER_MSEC))
-#define MSEC_TO_SCLK(msec) ((((BFIN_SCLK / USEC_PER_MSEC) * (msec)) / MSEC_PER_SEC) * USEC_PER_MSEC)
-
-#define L1_CACHE_SHIFT 5
-#define L1_CACHE_BYTES (1 << L1_CACHE_SHIFT)
-
-#include <linux/linkage.h>
-#include <asm/cache.h>
-
-#ifndef __ASSEMBLY__
-# ifdef SHARED_RESOURCES
-#  include <asm/shared_resources.h>
-# endif
-
-# include <linux/types.h>
-
-# define bfin_revid() (bfin_read_CHIPID() >> 28)
-
-extern int bfin_os_log_check(void);
-extern void bfin_os_log_dump(void);
-
-extern void blackfin_icache_flush_range(const void *, const void *);
-extern void blackfin_dcache_flush_range(const void *, const void *);
-extern void blackfin_icache_dcache_flush_range(const void *, const void *);
-extern void blackfin_dcache_flush_invalidate_range(const void *, const void *);
-
-/* Use DMA to move data from on chip to external memory.  The L1 instruction
- * regions can only be accessed via DMA, so if the address in question is in
- * that region, make sure we attempt to DMA indirectly.
- */
-# ifdef __ADSPBF561__
-  /* Core B regions all need dma from Core A */
-#  define addr_bfin_on_chip_mem(addr) \
-	((((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000) || \
-	 (((unsigned long)(addr) & 0xFFC00000) == 0xFF400000))
-# else
-#  define addr_bfin_on_chip_mem(addr) \
-	(((unsigned long)(addr) & 0xFFF00000) == 0xFFA00000)
-# endif
-
-# include <asm/system.h>
-
-#if ANOMALY_05000198
-# define NOP_PAD_ANOMALY_05000198 "nop;"
-#else
-# define NOP_PAD_ANOMALY_05000198
-#endif
-
-#define BFIN_BUG() while (1) asm volatile("emuexcpt;");
-
-#define _bfin_readX(addr, size, asm_size, asm_ext) ({ \
-	u32 __v; \
-	__asm__ __volatile__( \
-		NOP_PAD_ANOMALY_05000198 \
-		"%0 = " #asm_size "[%1]" #asm_ext ";" \
-		: "=d" (__v) \
-		: "a" (addr) \
-	); \
-	__v; })
-#define _bfin_writeX(addr, val, size, asm_size) \
-	__asm__ __volatile__( \
-		NOP_PAD_ANOMALY_05000198 \
-		#asm_size "[%0] = %1;" \
-		: \
-		: "a" (addr), "d" ((u##size)(val)) \
-		: "memory" \
-	)
-
-#define bfin_read8(addr)  _bfin_readX(addr,  8, b, (z))
-#define bfin_read16(addr) _bfin_readX(addr, 16, w, (z))
-#define bfin_read32(addr) _bfin_readX(addr, 32,  ,    )
-#define bfin_write8(addr, val)  _bfin_writeX(addr, val,  8, b)
-#define bfin_write16(addr, val) _bfin_writeX(addr, val, 16, w)
-#define bfin_write32(addr, val) _bfin_writeX(addr, val, 32,  )
-
-#define bfin_read(addr) \
-({ \
-	sizeof(*(addr)) == 1 ? bfin_read8(addr)  : \
-	sizeof(*(addr)) == 2 ? bfin_read16(addr) : \
-	sizeof(*(addr)) == 4 ? bfin_read32(addr) : \
-	({ BFIN_BUG(); 0; }); \
-})
-#define bfin_write(addr, val) \
-do { \
-	switch (sizeof(*(addr))) { \
-	case 1: bfin_write8(addr, val);  break; \
-	case 2: bfin_write16(addr, val); break; \
-	case 4: bfin_write32(addr, val); break; \
-	default: \
-		BFIN_BUG(); \
-	} \
-} while (0)
-
-#define bfin_write_or(addr, bits) \
-do { \
-	typeof(addr) __addr = (addr); \
-	bfin_write(__addr, bfin_read(__addr) | (bits)); \
-} while (0)
-
-#define bfin_write_and(addr, bits) \
-do { \
-	typeof(addr) __addr = (addr); \
-	bfin_write(__addr, bfin_read(__addr) & (bits)); \
-} while (0)
-
-#define bfin_readPTR(addr) bfin_read32(addr)
-#define bfin_writePTR(addr, val) bfin_write32(addr, val)
-
-/* SSYNC implementation for C file */
-static inline void SSYNC(void)
-{
-	int _tmp;
-	if (ANOMALY_05000312)
-		__asm__ __volatile__(
-			"cli %0;"
-			"nop;"
-			"nop;"
-			"ssync;"
-			"sti %0;"
-			: "=d" (_tmp)
-		);
-	else if (ANOMALY_05000244)
-		__asm__ __volatile__(
-			"nop;"
-			"nop;"
-			"nop;"
-			"ssync;"
-		);
-	else
-		__asm__ __volatile__("ssync;");
-}
-
-/* CSYNC implementation for C file */
-static inline void CSYNC(void)
-{
-	int _tmp;
-	if (ANOMALY_05000312)
-		__asm__ __volatile__(
-			"cli %0;"
-			"nop;"
-			"nop;"
-			"csync;"
-			"sti %0;"
-			: "=d" (_tmp)
-		);
-	else if (ANOMALY_05000244)
-		__asm__ __volatile__(
-			"nop;"
-			"nop;"
-			"nop;"
-			"csync;"
-		);
-	else
-		__asm__ __volatile__("csync;");
-}
-
-#else  /* __ASSEMBLY__ */
-
-/* SSYNC & CSYNC implementations for assembly files */
-
-#define ssync(x) SSYNC(x)
-#define csync(x) CSYNC(x)
-
-#if ANOMALY_05000312
-#define SSYNC(scratch) cli scratch; nop; nop; SSYNC; sti scratch;
-#define CSYNC(scratch) cli scratch; nop; nop; CSYNC; sti scratch;
-
-#elif ANOMALY_05000244
-#define SSYNC(scratch) nop; nop; nop; SSYNC;
-#define CSYNC(scratch) nop; nop; nop; CSYNC;
-
-#else
-#define SSYNC(scratch) SSYNC;
-#define CSYNC(scratch) CSYNC;
-
-#endif /* ANOMALY_05000312 & ANOMALY_05000244 handling */
-
-#endif /* __ASSEMBLY__ */
-
-#endif

+ 0 - 24
arch/blackfin/include/asm/byteorder.h

@@ -1,24 +0,0 @@
-/*
- * U-Boot -  byteorder.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2004
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BLACKFIN_BYTEORDER_H
-#define _BLACKFIN_BYTEORDER_H
-
-#include <asm/types.h>
-
-#if defined(__GNUC__) && !defined(__STRICT_ANSI__) || defined(__KERNEL__)
-#  define __BYTEORDER_HAS_U64__
-#  define __SWAB_64_THRU_32__
-#endif
-
-#include <linux/byteorder/little_endian.h>
-
-#endif

+ 0 - 70
arch/blackfin/include/asm/cache.h

@@ -1,70 +0,0 @@
-/*
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_CACHE_H
-#define __ARCH_BLACKFIN_CACHE_H
-
-#include <linux/linkage.h>	/* for asmlinkage */
-
-/*
- * Bytes per L1 cache line
- * Blackfin loads 32 bytes for cache
- */
-#define L1_CACHE_SHIFT	5
-#define L1_CACHE_BYTES	(1 << L1_CACHE_SHIFT)
-#define SMP_CACHE_BYTES	L1_CACHE_BYTES
-
-#define ARCH_DMA_MINALIGN	L1_CACHE_BYTES
-
-#ifdef CONFIG_SMP
-#define __cacheline_aligned
-#else
-#define ____cacheline_aligned
-
-/*
- * Put cacheline_aliged data to L1 data memory
- */
-#ifdef CONFIG_CACHELINE_ALIGNED_L1
-#define __cacheline_aligned				\
-	  __attribute__((__aligned__(L1_CACHE_BYTES),	\
-		__section__(".data_l1.cacheline_aligned")))
-#endif
-
-#endif
-
-/*
- * largest L1 which this arch supports
- */
-#define L1_CACHE_SHIFT_MAX	5
-
-#if defined(CONFIG_SMP) && \
-    !defined(CONFIG_BFIN_CACHE_COHERENT)
-# if defined(CONFIG_BFIN_EXTMEM_ICACHEABLE) || defined(CONFIG_BFIN_L2_ICACHEABLE)
-# define __ARCH_SYNC_CORE_ICACHE
-# endif
-# if defined(CONFIG_BFIN_EXTMEM_DCACHEABLE) || defined(CONFIG_BFIN_L2_DCACHEABLE)
-# define __ARCH_SYNC_CORE_DCACHE
-# endif
-#ifndef __ASSEMBLY__
-asmlinkage void __raw_smp_mark_barrier_asm(void);
-asmlinkage void __raw_smp_check_barrier_asm(void);
-
-static inline void smp_mark_barrier(void)
-{
-	__raw_smp_mark_barrier_asm();
-}
-static inline void smp_check_barrier(void)
-{
-	__raw_smp_check_barrier_asm();
-}
-
-void resync_core_dcache(void);
-void resync_core_icache(void);
-#endif
-#endif
-
-
-#endif

+ 0 - 88
arch/blackfin/include/asm/clock.h

@@ -1,88 +0,0 @@
-/*
- * Copyright (C) 2012 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __CLOCK_H__
-#define __CLOCK_H__
-
-#include <asm/blackfin.h>
-#ifdef PLL_CTL
-#include <asm/mach-common/bits/pll.h>
-# define pll_is_bypassed() (bfin_read_PLL_CTL() & BYPASS)
-#else
-#include <asm/mach-common/bits/cgu.h>
-# define pll_is_bypassed() (bfin_read_CGU_STAT() & PLLBP)
-# define bfin_read_PLL_CTL() bfin_read_CGU_CTL()
-# define bfin_read_PLL_DIV() bfin_read_CGU_DIV()
-# define SSEL SYSSEL
-# define SSEL_P SYSSEL_P
-#endif
-
-__attribute__((always_inline))
-static inline uint32_t early_division(uint32_t dividend, uint32_t divisor)
-{
-	uint32_t quotient;
-	uint32_t i, j;
-
-	for (quotient = 1, i = 1; dividend > divisor; ++i) {
-		j = divisor << i;
-		if (j > dividend || (j & 0x80000000)) {
-			--i;
-			quotient += (1 << i);
-			dividend -= (divisor << i);
-			i = 0;
-		}
-	}
-
-	return quotient;
-}
-
-__attribute__((always_inline))
-static inline uint32_t early_get_uart_clk(void)
-{
-	uint32_t msel, pll_ctl, vco;
-	uint32_t div, ssel, sclk, uclk;
-
-	pll_ctl = bfin_read_PLL_CTL();
-	msel = (pll_ctl & MSEL) >> MSEL_P;
-	if (msel == 0)
-		msel = (MSEL >> MSEL_P) + 1;
-
-	vco = (CONFIG_CLKIN_HZ >> (pll_ctl & DF)) * msel;
-	sclk = vco;
-	if (!pll_is_bypassed()) {
-		div = bfin_read_PLL_DIV();
-		ssel = (div & SSEL) >> SSEL_P;
-#if CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_BYPASS
-		sclk = vco/ssel;
-#else
-		sclk = early_division(vco, ssel);
-#endif
-	}
-	uclk = sclk;
-#ifdef CGU_DIV
-	ssel = (div & S0SEL) >> S0SEL_P;
-	uclk = early_division(sclk, ssel);
-#endif
-	return uclk;
-}
-
-extern u_long get_vco(void);
-extern u_long get_cclk(void);
-extern u_long get_sclk(void);
-
-#ifdef CGU_DIV
-extern u_long get_sclk0(void);
-extern u_long get_sclk1(void);
-extern u_long get_dclk(void);
-# define get_uart_clk get_sclk0
-# define get_i2c_clk get_sclk0
-# define get_spi_clk get_sclk1
-#else
-# define get_uart_clk get_sclk
-# define get_i2c_clk get_sclk
-# define get_spi_clk get_sclk
-#endif
-
-#endif

+ 0 - 82
arch/blackfin/include/asm/config-pre.h

@@ -1,82 +0,0 @@
-/*
- * config-pre.h - common defines for Blackfin boards in config.h
- *
- * Copyright (c) 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
-#define __ASM_BLACKFIN_CONFIG_PRE_H__
-
-/* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
- * Depending on your cpu, some of these may not be valid, check your HRM.
- * The actual values here are meaningless as long as they're unique.
- */
-#define BFIN_BOOT_BYPASS      1       /* bypass bootrom */
-#define BFIN_BOOT_PARA        2       /* boot ldr out of parallel flash */
-#define BFIN_BOOT_SPI_MASTER  3       /* boot ldr out of serial flash */
-#define BFIN_BOOT_SPI_SLAVE   4       /* boot ldr as spi slave */
-#define BFIN_BOOT_TWI_MASTER  5       /* boot ldr over twi device */
-#define BFIN_BOOT_TWI_SLAVE   6       /* boot ldr over twi slave */
-#define BFIN_BOOT_UART        7       /* boot ldr over uart */
-#define BFIN_BOOT_IDLE        8       /* do nothing, just idle */
-#define BFIN_BOOT_FIFO        9       /* boot ldr out of FIFO */
-#define BFIN_BOOT_MEM         10      /* boot ldr out of memory (warmboot) */
-#define BFIN_BOOT_16HOST_DMA  11      /* boot ldr from 16-bit host dma */
-#define BFIN_BOOT_8HOST_DMA   12      /* boot ldr from 8-bit host dma */
-#define BFIN_BOOT_NAND        13      /* boot ldr from nand flash */
-#define BFIN_BOOT_RSI_MASTER  14      /* boot ldr from rsi */
-#define BFIN_BOOT_LP_SLAVE    15      /* boot ldr from link port */
-
-#ifndef __ASSEMBLY__
-static inline const char *get_bfin_boot_mode(int bfin_boot)
-{
-	switch (bfin_boot) {
-	case BFIN_BOOT_BYPASS:     return "bypass";
-	case BFIN_BOOT_PARA:       return "parallel flash";
-	case BFIN_BOOT_SPI_MASTER: return "spi flash";
-	case BFIN_BOOT_SPI_SLAVE:  return "spi slave";
-	case BFIN_BOOT_TWI_MASTER: return "i2c flash";
-	case BFIN_BOOT_TWI_SLAVE:  return "i2c slave";
-	case BFIN_BOOT_UART:       return "uart";
-	case BFIN_BOOT_IDLE:       return "idle";
-	case BFIN_BOOT_FIFO:       return "fifo";
-	case BFIN_BOOT_MEM:        return "memory";
-	case BFIN_BOOT_16HOST_DMA: return "16bit dma";
-	case BFIN_BOOT_8HOST_DMA:  return "8bit dma";
-	case BFIN_BOOT_NAND:       return "nand flash";
-	case BFIN_BOOT_RSI_MASTER: return "rsi master";
-	case BFIN_BOOT_LP_SLAVE:   return "link port slave";
-	default:                   return "INVALID";
-	}
-}
-#endif
-
-/* Most bootroms allow for EVT1 redirection */
-#if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \
-     && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__)
-# undef CONFIG_BFIN_BOOTROM_USES_EVT1
-#else
-# define CONFIG_BFIN_BOOTROM_USES_EVT1
-#endif
-
-/* Define the default SPI CS used when booting out of SPI */
-#if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
-    defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
-    defined(__ADSPBF51x__)
-# define BFIN_BOOT_SPI_SSEL 2
-#else
-# define BFIN_BOOT_SPI_SSEL 1
-#endif
-
-/* Define to get a GPIO CS with the Blackfin SPI controller */
-#define MAX_CTRL_CS 8
-
-/* There is no Blackfin/NetBSD port */
-#undef CONFIG_BOOTM_NETBSD
-
-/* We rarely use interrupts, so favor throughput over latency */
-#define CONFIG_BFIN_INS_LOWOVERHEAD
-
-#endif

+ 0 - 176
arch/blackfin/include/asm/config.h

@@ -1,176 +0,0 @@
-/*
- * config.h - setup common defines for Blackfin boards based on config.h
- *
- * Copyright (c) 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CONFIG_POST_H__
-#define __ASM_BLACKFIN_CONFIG_POST_H__
-
-/* Some of our defines use this (like CONFIG_SYS_GBL_DATA_ADDR) */
-#include <asm-offsets.h>
-
-/* Sanity check CONFIG_BFIN_CPU */
-#ifndef CONFIG_BFIN_CPU
-# error CONFIG_BFIN_CPU: your board config needs to define this
-#endif
-
-#ifndef CONFIG_BFIN_SCRATCH_REG
-# define CONFIG_BFIN_SCRATCH_REG retn
-#endif
-
-/* U-Boot wants this config name */
-#define CONFIG_SYS_CACHELINE_SIZE L1_CACHE_BYTES
-
-/* Make sure the structure is properly aligned */
-#if ((CONFIG_SYS_GBL_DATA_ADDR & -4) != CONFIG_SYS_GBL_DATA_ADDR)
-# error CONFIG_SYS_GBL_DATA_ADDR: must be 4 byte aligned
-#endif
-
-/* Set default CONFIG_VCO_HZ if need be */
-#if !defined(CONFIG_VCO_HZ)
-# if (CONFIG_CLKIN_HALF == 0)
-#  define CONFIG_VCO_HZ (CONFIG_CLKIN_HZ * CONFIG_VCO_MULT)
-# else
-#  define CONFIG_VCO_HZ ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / 2)
-# endif
-#endif
-
-/* Set default CONFIG_CCLK_HZ if need be */
-#if !defined(CONFIG_CCLK_HZ)
-# if (CONFIG_PLL_BYPASS == 0)
-#  define CONFIG_CCLK_HZ (CONFIG_VCO_HZ / CONFIG_CCLK_DIV)
-# else
-#  define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
-# endif
-#endif
-
-/* Set default CONFIG_SCLK_HZ if need be */
-#if !defined(CONFIG_SCLK_HZ)
-# if (CONFIG_PLL_BYPASS == 0)
-#  define CONFIG_SCLK_HZ (CONFIG_VCO_HZ / CONFIG_SCLK_DIV)
-# else
-#  define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
-# endif
-#endif
-
-/* Since we use these to program PLL registers directly,
- * make sure the values are sane and won't screw us up.
- */
-#if (CONFIG_VCO_MULT & 0x3F) != CONFIG_VCO_MULT
-# error CONFIG_VCO_MULT: Invalid value: must fit in 6 bits (0 - 63)
-#endif
-#if (CONFIG_CLKIN_HALF & 0x1) != CONFIG_CLKIN_HALF
-# error CONFIG_CLKIN_HALF: Invalid value: must be 0 or 1
-#endif
-#if (CONFIG_PLL_BYPASS & 0x1) != CONFIG_PLL_BYPASS
-# error CONFIG_PLL_BYPASS: Invalid value: must be 0 or 1
-#endif
-
-/* If we are using KGDB, make sure we defer exceptions */
-#ifdef CONFIG_CMD_KGDB
-# define CONFIG_EXCEPTION_DEFER	1
-#endif
-
-/* Using L1 scratch pad makes sense for everyone by default. */
-#ifndef CONFIG_LINUX_CMDLINE_ADDR
-# define CONFIG_LINUX_CMDLINE_ADDR L1_SRAM_SCRATCH
-#endif
-#ifndef CONFIG_LINUX_CMDLINE_SIZE
-# define CONFIG_LINUX_CMDLINE_SIZE L1_SRAM_SCRATCH_SIZE
-#endif
-
-/* Set default SPI flash CS to the one we boot from */
-#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_SPI_CS)
-# define CONFIG_ENV_SPI_CS BFIN_BOOT_SPI_SSEL
-#endif
-
-/* We need envcrc to embed the env into LDRs */
-#ifdef CONFIG_ENV_IS_EMBEDDED_IN_LDR
-# define CONFIG_BUILD_ENVCRC
-#endif
-
-/* Default/common Blackfin memory layout */
-#ifndef CONFIG_SYS_SDRAM_BASE
-# define CONFIG_SYS_SDRAM_BASE 0
-#endif
-#ifndef CONFIG_SYS_MAX_RAM_SIZE
-# define CONFIG_SYS_MAX_RAM_SIZE (CONFIG_MEM_SIZE * 1024 * 1024)
-#endif
-#ifndef CONFIG_SYS_MONITOR_BASE
-# if CONFIG_SYS_MAX_RAM_SIZE
-#  define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_MAX_RAM_SIZE - CONFIG_SYS_MONITOR_LEN)
-# else
-#  define CONFIG_SYS_MONITOR_BASE 0
-# endif
-#endif
-#ifndef CONFIG_SYS_MALLOC_BASE
-# define CONFIG_SYS_MALLOC_BASE (CONFIG_SYS_MONITOR_BASE - CONFIG_SYS_MALLOC_LEN)
-#endif
-#ifndef CONFIG_STACKBASE
-# define CONFIG_STACKBASE (CONFIG_SYS_MALLOC_BASE - 4)
-#endif
-#ifndef CONFIG_SYS_MEMTEST_START
-# define CONFIG_SYS_MEMTEST_START 0
-#endif
-#ifndef CONFIG_SYS_MEMTEST_END
-# define CONFIG_SYS_MEMTEST_END (CONFIG_STACKBASE - 8192 + 4)
-#endif
-#ifndef CONFIG_SYS_POST_WORD_ADDR
-# define CONFIG_SYS_POST_WORD_ADDR (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE - 4)
-#endif
-
-/* Check to make sure everything fits in external RAM */
-#if CONFIG_SYS_MAX_RAM_SIZE && \
-    ((CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) > CONFIG_SYS_MAX_RAM_SIZE)
-# error Memory Map does not fit into configuration
-#endif
-
-/* Default/common Blackfin environment settings */
-#ifndef CONFIG_LOADADDR
-# define CONFIG_LOADADDR 0x1000000
-#endif
-#ifndef CONFIG_SYS_LOAD_ADDR
-# define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
-#endif
-#ifndef CONFIG_SYS_BOOTM_LEN
-# define CONFIG_SYS_BOOTM_LEN 0x4000000
-#endif
-#ifndef CONFIG_SYS_CBSIZE
-# define CONFIG_SYS_CBSIZE 1024
-#elif defined(CONFIG_CMD_KGDB) && CONFIG_SYS_CBSIZE < 1024
-# error "kgdb needs cbsize to be >= 1024"
-#endif
-#ifndef CONFIG_SYS_BARGSIZE
-# define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
-#endif
-#ifndef CONFIG_SYS_PBSIZE
-# define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)
-#endif
-#ifndef CONFIG_SYS_MAXARGS
-# define CONFIG_SYS_MAXARGS 16
-#endif
-
-/* Blackfin POST tests */
-#ifdef CONFIG_POST_BSPEC1_GPIO_LEDS
-# define CONFIG_POST_BSPEC1 \
-	{ \
-		"LED test", "led", "This test verifies LEDs on the board.", \
-		POST_MEM | POST_ALWAYS, &led_post_test, NULL, NULL, \
-		CONFIG_SYS_POST_BSPEC1, \
-	}
-#endif
-#ifdef CONFIG_POST_BSPEC2_GPIO_BUTTONS
-# define CONFIG_POST_BSPEC2 \
-	{ \
-		"Button test", "button", "This test verifies buttons on the board.", \
-		POST_MEM | POST_ALWAYS, &button_post_test, NULL, NULL, \
-		CONFIG_SYS_POST_BSPEC2, \
-	}
-#endif
-
-#define CONFIG_CPU CONFIG_BFIN_CPU
-
-#endif

+ 0 - 99
arch/blackfin/include/asm/cplb.h

@@ -1,99 +0,0 @@
-/*
- * cplb.h - defines for managing CPLB tables
- *
- * Copyright (c) 2002-2007 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ASM_BLACKFIN_CPLB_H__
-#define __ASM_BLACKFIN_CPLB_H__
-
-#include <asm/mach-common/bits/mpu.h>
-
-#define CPLB_ENABLE_ICACHE_P	0
-#define CPLB_ENABLE_DCACHE_P	1
-#define CPLB_ENABLE_DCACHE2_P	2
-#define CPLB_ENABLE_CPLBS_P	3	/* Deprecated! */
-#define CPLB_ENABLE_ICPLBS_P	4
-#define CPLB_ENABLE_DCPLBS_P	5
-
-#define CPLB_ENABLE_ICACHE	(1<<CPLB_ENABLE_ICACHE_P)
-#define CPLB_ENABLE_DCACHE	(1<<CPLB_ENABLE_DCACHE_P)
-#define CPLB_ENABLE_DCACHE2	(1<<CPLB_ENABLE_DCACHE2_P)
-#define CPLB_ENABLE_CPLBS	(1<<CPLB_ENABLE_CPLBS_P)
-#define CPLB_ENABLE_ICPLBS	(1<<CPLB_ENABLE_ICPLBS_P)
-#define CPLB_ENABLE_DCPLBS	(1<<CPLB_ENABLE_DCPLBS_P)
-#define CPLB_ENABLE_ANY_CPLBS	CPLB_ENABLE_CPLBS | \
-				CPLB_ENABLE_ICPLBS | \
-				CPLB_ENABLE_DCPLBS
-
-#define CPLB_RELOADED		0x0000
-#define CPLB_NO_UNLOCKED	0x0001
-#define CPLB_NO_ADDR_MATCH	0x0002
-#define CPLB_PROT_VIOL		0x0003
-
-#define CPLB_DEF_CACHE		CPLB_L1_CHBL | CPLB_WT
-#define CPLB_CACHE_ENABLED	CPLB_L1_CHBL | CPLB_DIRTY
-
-#define CPLB_ALL_ACCESS	CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
-
-#define CPLB_I_PAGE_MGMT	CPLB_LOCK | CPLB_VALID
-#define CPLB_D_PAGE_MGMT	CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DNOCACHE		CPLB_ALL_ACCESS | CPLB_VALID
-#define CPLB_DDOCACHE		CPLB_DNOCACHE | CPLB_DEF_CACHE
-#define CPLB_INOCACHE		CPLB_USER_RD | CPLB_VALID
-#define CPLB_IDOCACHE		CPLB_INOCACHE | CPLB_L1_CHBL
-
-/* Data Attibutes*/
-#if defined(__ADSPBF60x__)
-#define SDRAM_IGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | \
-				CPLB_USER_RD | CPLB_VALID)
-#else
-#define SDRAM_IGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | \
-				CPLB_USER_RD | CPLB_VALID)
-#endif
-#define SDRAM_IKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define L1_IMEMORY              (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
-#define SDRAM_INON_CHBL         (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
-
-#if ANOMALY_05000158
-# define ANOMALY_05000158_WORKAROUND 0x200
-#else
-# define ANOMALY_05000158_WORKAROUND 0
-#endif
-
-#ifdef CONFIG_DCACHE_WB		/*Write Back Policy */
-#if defined(__ADSPBF60x__)
-#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \
-				CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
-				CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#else
-#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \
-				CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
-				CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#endif
-#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
-#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-
-#else				/*Write Through */
-#if defined(__ADSPBF60x__)
-#define SDRAM_DGENERIC          (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \
-				CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
-				CPLB_USER_WR | CPLB_VALID | \
-				ANOMALY_05000158_WORKAROUND)
-#else
-#define SDRAM_DGENERIC          (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \
-				CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
-				CPLB_USER_WR | CPLB_VALID | \
-				ANOMALY_05000158_WORKAROUND)
-#endif
-#define SDRAM_DNON_CHBL         (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_DKERNEL           (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
-#define L1_DMEMORY              (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#define SDRAM_EBIU              (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
-#endif
-
-#endif				/* _CPLB_H */

+ 0 - 20
arch/blackfin/include/asm/deferred.h

@@ -1,20 +0,0 @@
-/*
- * U-Boot - deferred register layout
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DEFER_H
-#define _BLACKFIN_DEFER_H
-
-#define deferred_regs_DCPLB_FAULT_ADDR	0
-#define deferred_regs_ICPLB_FAULT_ADDR	1
-#define deferred_regs_retx		2
-#define deferred_regs_SEQSTAT		3
-#define deferred_regs_SYSCFG		4
-#define deferred_regs_IMASK		5
-#define deferred_regs_last		6
-
-#endif /* _BLACKFIN_DEFER_H */

+ 0 - 39
arch/blackfin/include/asm/delay.h

@@ -1,39 +0,0 @@
-/*
- * U-Boot - delay.h Routines for introducing delays
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef _BLACKFIN_DELAY_H
-#define _BLACKFIN_DELAY_H
-
-/*
- * Changes made by akbar.hussain@Lineo.com, for BLACKFIN
- * Copyright (C) 1994 Hamish Macdonald
- *
- * Delay routines, using a pre-computed "loops_per_second" value.
- */
-
-static __inline__ void __delay(unsigned long loops)
-{
-	__asm__ __volatile__("1:\t%0 += -1;\n\t"
-			     "cc = %0 == 0;\n\t"
-			     "if ! cc jump 1b;\n":"=d"(loops)
-			     :"0"(loops));
-}
-
-/*
- * Use only for very small delays ( < 1 msec).  Should probably use a
- * lookup table, really, as the multiplications take much too long with
- * short delays.  This is a "reasonable" implementation, though (and the
- * first constant multiplications gets optimized away if the delay is
- * a constant)
- */
-static __inline__ void __udelay(unsigned long usecs)
-{
-	__delay(usecs);
-}
-
-#endif

+ 0 - 104
arch/blackfin/include/asm/dma.h

@@ -1,104 +0,0 @@
-/*
- * dma.h - Blackfin DMA defines/structures/etc...
- *
- * Copyright 2004-2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_DMA_H_
-#define _BLACKFIN_DMA_H_
-
-#include <linux/types.h>
-#ifdef __ADSPBF60x__
-#include <asm/mach-common/bits/dde.h>
-#else
-#include <asm/mach-common/bits/dma.h>
-#endif
-
-struct dmasg_large {
-	void *next_desc_addr;
-	u32 start_addr;
-	u16 cfg;
-	u16 x_count;
-	s16 x_modify;
-	u16 y_count;
-	s16 y_modify;
-} __attribute__((packed));
-
-struct dmasg {
-	u32 start_addr;
-	u16 cfg;
-	u16 x_count;
-	s16 x_modify;
-	u16 y_count;
-	s16 y_modify;
-} __attribute__((packed));
-
-struct dma_register {
-#ifdef __ADSPBF60x__
-	void *next_desc_ptr;	/* DMA Next Descriptor Pointer register */
-	u32 start_addr;		/* DMA Start address  register */
-	u32 config;		/* DMA Configuration register */
-
-	u32 x_count;		/* DMA x_count register */
-	s32 x_modify;		/* DMA x_modify register */
-	u32 y_count;		/* DMA y_count register */
-	s32 y_modify;		/* DMA y_modify register */
-	u32 __pad0[2];
-
-	void *curr_desc_ptr;	/* DMA Curr Descriptor Pointer register */
-	void *prev_desc_ptr;	/* DMA Prev Descriptor Pointer register */
-	void *curr_addr;	/* DMA Current Address Pointer register */
-	u32 status;		/* DMA irq status register */
-	u32 curr_x_count;	/* DMA Current x-count register */
-	u32 curr_y_count;	/* DMA Current y-count register */
-	u32 __pad1[2];
-
-	u32 bw_limit;		/* DMA Bandwidth Limit Count */
-	u32 curr_bw_limit;	/* DMA curr Bandwidth Limit Count */
-	u32 bw_monitor;		/* DMA Bandwidth Monitor Count */
-	u32 curr_bw_monitor;	/* DMA curr Bandwidth Monitor Count */
-#else
-	void *next_desc_ptr;	/* DMA Next Descriptor Pointer register */
-	u32 start_addr;		/* DMA Start address  register */
-
-	u16 config;		/* DMA Configuration register */
-	u16 dummy1;		/* DMA Configuration register */
-
-	u32 reserved;
-
-	u16 x_count;		/* DMA x_count register */
-	u16 dummy2;
-
-	s16 x_modify;		/* DMA x_modify register */
-	u16 dummy3;
-
-	u16 y_count;		/* DMA y_count register */
-	u16 dummy4;
-
-	s16 y_modify;		/* DMA y_modify register */
-	u16 dummy5;
-
-	void *curr_desc_ptr;	/* DMA Current Descriptor Pointer register */
-
-	u32 curr_addr_ptr;	/* DMA Current Address Pointer register */
-
-	u16 status;		/* DMA irq status register */
-	u16 dummy6;
-
-	u16 peripheral_map;	/* DMA peripheral map register */
-	u16 dummy7;
-
-	u16 curr_x_count;	/* DMA Current x-count register */
-	u16 dummy8;
-
-	u32 reserved2;
-
-	u16 curr_y_count;	/* DMA Current y-count register */
-	u16 dummy9;
-
-	u32 reserved3;
-#endif
-};
-
-#endif

+ 0 - 243
arch/blackfin/include/asm/entry.h

@@ -1,243 +0,0 @@
-/*
- * entry.h - routines for context saving and restoring (for interrupts/exceptions)
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __BLACKFIN_ENTRY_H
-#define __BLACKFIN_ENTRY_H
-#ifdef __ASSEMBLY__
-
-#define SAVE_ALL_INT		save_context_no_interrupts
-#define SAVE_ALL_SYS		save_context_no_interrupts
-#define SAVE_CONTEXT		save_context_with_interrupts
-
-#define RESTORE_ALL		restore_context_no_interrupts
-#define RESTORE_ALL_SYS		restore_context_no_interrupts
-#define RESTORE_CONTEXT		restore_context_with_interrupts
-
-/*
- * Code to save processor context.
- * We even save the register which are preserved by a function call
- * - r4, r5, r6, r7, p3, p4, p5
- */
-.macro save_context_with_interrupts
-	[--sp] = R0;
-	[--sp] = ( R7:0, P5:0 );
-	[--sp] = fp;
-	[--sp] = usp;
-
-	[--sp] = i0;
-	[--sp] = i1;
-	[--sp] = i2;
-	[--sp] = i3;
-
-	[--sp] = m0;
-	[--sp] = m1;
-	[--sp] = m2;
-	[--sp] = m3;
-
-	[--sp] = l0;
-	[--sp] = l1;
-	[--sp] = l2;
-	[--sp] = l3;
-
-	[--sp] = b0;
-	[--sp] = b1;
-	[--sp] = b2;
-	[--sp] = b3;
-	[--sp] = a0.x;
-	[--sp] = a0.w;
-	[--sp] = a1.x;
-	[--sp] = a1.w;
-
-	[--sp] = LC0;
-	[--sp] = LC1;
-	[--sp] = LT0;
-	[--sp] = LT1;
-	[--sp] = LB0;
-	[--sp] = LB1;
-
-	[--sp] = ASTAT;
-
-	[--sp] = r0;	/* Skip reserved */
-	[--sp] = RETS;
-	[--sp] = RETI;
-	[--sp] = RETX;
-	[--sp] = RETN;
-	[--sp] = RETE;
-	[--sp] = SEQSTAT;
-	[--sp] = SYSCFG;
-#ifdef CONFIG_CMD_KGDB
-	p0.l = lo(IPEND)
-	p0.h = hi(IPEND)
-	r0 = [p0];
-#endif
-	[--sp] = r0;	/* Skip IPEND as well. */
-.endm
-
-.macro save_context_no_interrupts
-	[--sp] = R0;
-	[--sp] = ( R7:0, P5:0 );
-	[--sp] = fp;
-	[--sp] = usp;
-
-	[--sp] = i0;
-	[--sp] = i1;
-	[--sp] = i2;
-	[--sp] = i3;
-
-	[--sp] = m0;
-	[--sp] = m1;
-	[--sp] = m2;
-	[--sp] = m3;
-
-	[--sp] = l0;
-	[--sp] = l1;
-	[--sp] = l2;
-	[--sp] = l3;
-
-	[--sp] = b0;
-	[--sp] = b1;
-	[--sp] = b2;
-	[--sp] = b3;
-	[--sp] = a0.x;
-	[--sp] = a0.w;
-	[--sp] = a1.x;
-	[--sp] = a1.w;
-
-	[--sp] = LC0;
-	[--sp] = LC1;
-	[--sp] = LT0;
-	[--sp] = LT1;
-	[--sp] = LB0;
-	[--sp] = LB1;
-
-	[--sp] = ASTAT;
-
-	[--sp] = r0;	/* Skip reserved */
-	[--sp] = RETS;
-	r0 = RETI;
-	[--sp] = r0;
-	[--sp] = RETX;
-	[--sp] = RETN;
-	[--sp] = RETE;
-	[--sp] = SEQSTAT;
-	[--sp] = SYSCFG;
-#ifdef CONFIG_CMD_KGDB
-	p0.l = lo(IPEND)
-	p0.h = hi(IPEND)
-	r0 = [p0];
-#endif
-	[--sp] = r0;	/* Skip IPEND as well. */
-.endm
-
-.macro restore_context_no_interrupts
-	sp += 4;
-	SYSCFG = [sp++];
-	SEQSTAT = [sp++];
-	RETE = [sp++];
-	RETN = [sp++];
-	RETX = [sp++];
-	r0 = [sp++];
-	RETI = r0;
-	RETS = [sp++];
-
-	sp += 4;
-
-	ASTAT = [sp++];
-
-	LB1 = [sp++];
-	LB0 = [sp++];
-	LT1 = [sp++];
-	LT0 = [sp++];
-	LC1 = [sp++];
-	LC0 = [sp++];
-
-	a1.w = [sp++];
-	a1.x = [sp++];
-	a0.w = [sp++];
-	a0.x = [sp++];
-	b3 = [sp++];
-	b2 = [sp++];
-	b1 = [sp++];
-	b0 = [sp++];
-
-	l3 = [sp++];
-	l2 = [sp++];
-	l1 = [sp++];
-	l0 = [sp++];
-
-	m3 = [sp++];
-	m2 = [sp++];
-	m1 = [sp++];
-	m0 = [sp++];
-
-	i3 = [sp++];
-	i2 = [sp++];
-	i1 = [sp++];
-	i0 = [sp++];
-
-	sp += 4;
-	fp = [sp++];
-
-	( R7 : 0, P5 : 0) = [ SP ++ ];
-	sp += 4;
-.endm
-
-.macro restore_context_with_interrupts
-	sp += 4;
-	SYSCFG = [sp++];
-	SEQSTAT = [sp++];
-	RETE = [sp++];
-	RETN = [sp++];
-	RETX = [sp++];
-	RETI = [sp++];
-	RETS = [sp++];
-
-	sp += 4;
-
-	ASTAT = [sp++];
-
-	LB1 = [sp++];
-	LB0 = [sp++];
-	LT1 = [sp++];
-	LT0 = [sp++];
-	LC1 = [sp++];
-	LC0 = [sp++];
-
-	a1.w = [sp++];
-	a1.x = [sp++];
-	a0.w = [sp++];
-	a0.x = [sp++];
-	b3 = [sp++];
-	b2 = [sp++];
-	b1 = [sp++];
-	b0 = [sp++];
-
-	l3 = [sp++];
-	l2 = [sp++];
-	l1 = [sp++];
-	l0 = [sp++];
-
-	m3 = [sp++];
-	m2 = [sp++];
-	m1 = [sp++];
-	m0 = [sp++];
-
-	i3 = [sp++];
-	i2 = [sp++];
-	i1 = [sp++];
-	i0 = [sp++];
-
-	sp += 4;
-	fp = [sp++];
-
-	( R7 : 0, P5 : 0) = [ SP ++ ];
-	sp += 4;
-.endm
-
-#endif
-#endif

+ 0 - 26
arch/blackfin/include/asm/global_data.h

@@ -1,26 +0,0 @@
-/*
- * U-Boot - global_data.h Declarations for global data of U-Boot
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * (C) Copyright 2000-2010
- * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef	__ASM_GBL_DATA_H
-#define __ASM_GBL_DATA_H
-
-#include <asm/u-boot.h>
-
-/* Architecture-specific global data */
-struct arch_global_data {
-	unsigned long board_type;
-};
-
-#include <asm-generic/global_data.h>
-
-#define DECLARE_GLOBAL_DATA_PTR     register volatile gd_t *gd asm ("P3")
-
-#endif

+ 0 - 167
arch/blackfin/include/asm/gpio.h

@@ -1,167 +0,0 @@
-/*
- * Copyright 2006-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __ARCH_BLACKFIN_GPIO_H__
-#define __ARCH_BLACKFIN_GPIO_H__
-
-#include <asm-generic/gpio.h>
-#include <asm/portmux.h>
-
-#define gpio_bank(x)	((x) >> 4)
-#define gpio_bit(x)	(1<<((x) & 0xF))
-#define gpio_sub_n(x)	((x) & 0xF)
-
-#define GPIO_BANKSIZE	16
-#define GPIO_BANK_NUM	DIV_ROUND_UP(MAX_BLACKFIN_GPIOS, GPIO_BANKSIZE)
-
-#define GPIO_0	0
-#define GPIO_1	1
-#define GPIO_2	2
-#define GPIO_3	3
-#define GPIO_4	4
-#define GPIO_5	5
-#define GPIO_6	6
-#define GPIO_7	7
-#define GPIO_8	8
-#define GPIO_9	9
-#define GPIO_10	10
-#define GPIO_11	11
-#define GPIO_12	12
-#define GPIO_13	13
-#define GPIO_14	14
-#define GPIO_15	15
-#define GPIO_16	16
-#define GPIO_17	17
-#define GPIO_18	18
-#define GPIO_19	19
-#define GPIO_20	20
-#define GPIO_21	21
-#define GPIO_22	22
-#define GPIO_23	23
-#define GPIO_24	24
-#define GPIO_25	25
-#define GPIO_26	26
-#define GPIO_27	27
-#define GPIO_28	28
-#define GPIO_29	29
-#define GPIO_30	30
-#define GPIO_31	31
-#define GPIO_32	32
-#define GPIO_33	33
-#define GPIO_34	34
-#define GPIO_35	35
-#define GPIO_36	36
-#define GPIO_37	37
-#define GPIO_38	38
-#define GPIO_39	39
-#define GPIO_40	40
-#define GPIO_41	41
-#define GPIO_42	42
-#define GPIO_43	43
-#define GPIO_44	44
-#define GPIO_45	45
-#define GPIO_46	46
-#define GPIO_47	47
-
-#define PERIPHERAL_USAGE 1
-#define GPIO_USAGE 0
-#define MAX_GPIOS MAX_BLACKFIN_GPIOS
-
-#ifndef __ASSEMBLY__
-
-#ifndef CONFIG_ADI_GPIO2
-void set_gpio_dir(unsigned, unsigned short);
-void set_gpio_inen(unsigned, unsigned short);
-void set_gpio_polar(unsigned, unsigned short);
-void set_gpio_edge(unsigned, unsigned short);
-void set_gpio_both(unsigned, unsigned short);
-void set_gpio_data(unsigned, unsigned short);
-void set_gpio_maska(unsigned, unsigned short);
-void set_gpio_maskb(unsigned, unsigned short);
-void set_gpio_toggle(unsigned);
-void set_gpiop_dir(unsigned, unsigned short);
-void set_gpiop_inen(unsigned, unsigned short);
-void set_gpiop_polar(unsigned, unsigned short);
-void set_gpiop_edge(unsigned, unsigned short);
-void set_gpiop_both(unsigned, unsigned short);
-void set_gpiop_data(unsigned, unsigned short);
-void set_gpiop_maska(unsigned, unsigned short);
-void set_gpiop_maskb(unsigned, unsigned short);
-unsigned short get_gpio_dir(unsigned);
-unsigned short get_gpio_inen(unsigned);
-unsigned short get_gpio_polar(unsigned);
-unsigned short get_gpio_edge(unsigned);
-unsigned short get_gpio_both(unsigned);
-unsigned short get_gpio_maska(unsigned);
-unsigned short get_gpio_maskb(unsigned);
-unsigned short get_gpio_data(unsigned);
-unsigned short get_gpiop_dir(unsigned);
-unsigned short get_gpiop_inen(unsigned);
-unsigned short get_gpiop_polar(unsigned);
-unsigned short get_gpiop_edge(unsigned);
-unsigned short get_gpiop_both(unsigned);
-unsigned short get_gpiop_maska(unsigned);
-unsigned short get_gpiop_maskb(unsigned);
-unsigned short get_gpiop_data(unsigned);
-
-struct gpio_port_t {
-	unsigned short data;
-	unsigned short dummy1;
-	unsigned short data_clear;
-	unsigned short dummy2;
-	unsigned short data_set;
-	unsigned short dummy3;
-	unsigned short toggle;
-	unsigned short dummy4;
-	unsigned short maska;
-	unsigned short dummy5;
-	unsigned short maska_clear;
-	unsigned short dummy6;
-	unsigned short maska_set;
-	unsigned short dummy7;
-	unsigned short maska_toggle;
-	unsigned short dummy8;
-	unsigned short maskb;
-	unsigned short dummy9;
-	unsigned short maskb_clear;
-	unsigned short dummy10;
-	unsigned short maskb_set;
-	unsigned short dummy11;
-	unsigned short maskb_toggle;
-	unsigned short dummy12;
-	unsigned short dir;
-	unsigned short dummy13;
-	unsigned short polar;
-	unsigned short dummy14;
-	unsigned short edge;
-	unsigned short dummy15;
-	unsigned short both;
-	unsigned short dummy16;
-	unsigned short inen;
-};
-#else
-extern struct gpio_port_t * const gpio_array[];
-#endif
-
-#ifdef ADI_SPECIAL_GPIO_BANKS
-void special_gpio_free(unsigned gpio);
-int special_gpio_request(unsigned gpio, const char *label);
-#endif
-
-void gpio_labels(void);
-
-static inline int gpio_is_valid(int number)
-{
-	return number >= 0 && number < MAX_GPIOS;
-}
-
-#include <linux/ctype.h>
-
-#define gpio_status() gpio_labels()
-
-#endif /* __ASSEMBLY__ */
-
-#endif /* __ARCH_BLACKFIN_GPIO_H__ */

+ 0 - 228
arch/blackfin/include/asm/io.h

@@ -1,228 +0,0 @@
-/*
- * U-Boot - io.h IO routines
- *
- * Copyright 2004-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef _BLACKFIN_IO_H
-#define _BLACKFIN_IO_H
-
-#ifdef __KERNEL__
-
-#include <linux/compiler.h>
-#include <asm/blackfin.h>
-
-static inline void sync(void)
-{
-	SSYNC();
-}
-
-/*
- * Given a physical address and a length, return a virtual address
- * that can be used to access the memory range with the caching
- * properties specified by "flags".
- */
-#define MAP_NOCACHE	(0)
-#define MAP_WRCOMBINE	(0)
-#define MAP_WRBACK	(0)
-#define MAP_WRTHROUGH	(0)
-
-static inline void *
-map_physmem(phys_addr_t paddr, unsigned long len, unsigned long flags)
-{
-	return (void *)paddr;
-}
-
-/*
- * Take down a mapping set up by map_physmem().
- */
-static inline void unmap_physmem(void *vaddr, unsigned long flags)
-{
-
-}
-
-static inline phys_addr_t virt_to_phys(void * vaddr)
-{
-	return (phys_addr_t)(vaddr);
-}
-
-/*
- * These are for ISA/PCI shared memory _only_ and should never be used
- * on any other type of memory, including Zorro memory. They are meant to
- * access the bus in the bus byte order which is little-endian!.
- *
- * readX/writeX() are used to access memory mapped devices. On some
- * architectures the memory mapped IO stuff needs to be accessed
- * differently. On the bfin architecture, we just read/write the
- * memory location directly.
- */
-#ifndef __ASSEMBLY__
-
-static inline unsigned char readb(const volatile void __iomem *addr)
-{
-	unsigned int val;
-	int tmp;
-
-	__asm__ __volatile__ (
-		"cli %1;"
-		"NOP; NOP; SSYNC;"
-		"%0 = b [%2] (z);"
-		"sti %1;"
-		: "=d"(val), "=d"(tmp)
-		: "a"(addr)
-	);
-
-	return (unsigned char) val;
-}
-
-static inline unsigned short readw(const volatile void __iomem *addr)
-{
-	unsigned int val;
-	int tmp;
-
-	__asm__ __volatile__ (
-		"cli %1;"
-		"NOP; NOP; SSYNC;"
-		"%0 = w [%2] (z);"
-		"sti %1;"
-		: "=d"(val), "=d"(tmp)
-		: "a"(addr)
-	);
-
-	return (unsigned short) val;
-}
-
-static inline unsigned int readl(const volatile void __iomem *addr)
-{
-	unsigned int val;
-	int tmp;
-
-	__asm__ __volatile__ (
-		"cli %1;"
-		"NOP; NOP; SSYNC;"
-		"%0 = [%2];"
-		"sti %1;"
-		: "=d"(val), "=d"(tmp)
-		: "a"(addr)
-	);
-
-	return val;
-}
-
-#endif /*  __ASSEMBLY__ */
-
-#define writeb(b, addr) (void)((*(volatile unsigned char *) (addr)) = (b))
-#define writew(b, addr) (void)((*(volatile unsigned short *) (addr)) = (b))
-#define writel(b, addr) (void)((*(volatile unsigned int *) (addr)) = (b))
-
-#define __raw_readb readb
-#define __raw_readw readw
-#define __raw_readl readl
-#define __raw_writeb writeb
-#define __raw_writew writew
-#define __raw_writel writel
-#define memset_io(a, b, c)	memset((void *)(a), (b), (c))
-#define memcpy_fromio(a, b, c)	memcpy((a), (void *)(b), (c))
-#define memcpy_toio(a, b, c)	memcpy((void *)(a), (b), (c))
-
-/* Convert "I/O port addresses" to actual addresses.  i.e. ugly casts. */
-#define __io(port) ((void *)(unsigned long)(port))
-
-#define inb(port)    readb(__io(port))
-#define inw(port)    readw(__io(port))
-#define inl(port)    readl(__io(port))
-#define in_le32(port) inl(port)
-#define outb(x, port) writeb(x, __io(port))
-#define outw(x, port) writew(x, __io(port))
-#define outl(x, port) writel(x, __io(port))
-#define out_le32(x, port) outl(x, port)
-
-#define inb_p(port)    inb(__io(port))
-#define inw_p(port)    inw(__io(port))
-#define inl_p(port)    inl(__io(port))
-#define outb_p(x, port) outb(x, __io(port))
-#define outw_p(x, port) outw(x, __io(port))
-#define outl_p(x, port) outl(x, __io(port))
-
-#define ioread8_rep(a, d, c)	readsb(a, d, c)
-#define ioread16_rep(a, d, c)	readsw(a, d, c)
-#define ioread32_rep(a, d, c)	readsl(a, d, c)
-#define iowrite8_rep(a, s, c)	writesb(a, s, c)
-#define iowrite16_rep(a, s, c)	writesw(a, s, c)
-#define iowrite32_rep(a, s, c)	writesl(a, s, c)
-
-#define ioread8(x)			readb(x)
-#define ioread16(x)			readw(x)
-#define ioread32(x)			readl(x)
-#define iowrite8(val, x)		writeb(val, x)
-#define iowrite16(val, x)		writew(val, x)
-#define iowrite32(val, x)		writel(val, x)
-
-#define mmiowb() wmb()
-
-#ifndef __ASSEMBLY__
-
-extern void outsb(unsigned long port, const void *addr, unsigned long count);
-extern void outsw(unsigned long port, const void *addr, unsigned long count);
-extern void outsw_8(unsigned long port, const void *addr, unsigned long count);
-extern void outsl(unsigned long port, const void *addr, unsigned long count);
-
-extern void insb(unsigned long port, void *addr, unsigned long count);
-extern void insw(unsigned long port, void *addr, unsigned long count);
-extern void insw_8(unsigned long port, void *addr, unsigned long count);
-extern void insl(unsigned long port, void *addr, unsigned long count);
-extern void insl_16(unsigned long port, void *addr, unsigned long count);
-
-static inline void readsl(const void __iomem *addr, void *buf, int len)
-{
-	insl((unsigned long)addr, buf, len);
-}
-
-static inline void readsw(const void __iomem *addr, void *buf, int len)
-{
-	insw((unsigned long)addr, buf, len);
-}
-
-static inline void readsb(const void __iomem *addr, void *buf, int len)
-{
-	insb((unsigned long)addr, buf, len);
-}
-
-static inline void writesl(const void __iomem *addr, const void *buf, int len)
-{
-	outsl((unsigned long)addr, buf, len);
-}
-
-static inline void writesw(const void __iomem *addr, const void *buf, int len)
-{
-	outsw((unsigned long)addr, buf, len);
-}
-
-static inline void writesb(const void __iomem *addr, const void *buf, int len)
-{
-	outsb((unsigned long)addr, buf, len);
-}
-
-#if defined(CONFIG_STAMP_CF) || defined(CONFIG_BFIN_IDE)
-/* This hack for CF/IDE needs to be addressed at some point */
-extern void cf_outsw(unsigned short *addr, unsigned short *sect_buf, int words);
-extern void cf_insw(unsigned short *sect_buf, unsigned short *addr, int words);
-extern unsigned char cf_inb(volatile unsigned char *addr);
-extern void cf_outb(unsigned char val, volatile unsigned char *addr);
-#undef inb
-#undef outb
-#undef insw
-#undef outsw
-#define inb(addr) cf_inb((void *)(addr))
-#define outb(x, addr) cf_outb((unsigned char)(x), (void *)(addr))
-#define insw(port, addr, cnt) cf_insw((void *)(addr), (void *)(port), cnt)
-#define outsw(port, addr, cnt) cf_outsw((void *)(port), (void *)(addr), cnt)
-#endif
-
-#endif
-
-#endif				/* __KERNEL__ */
-
-#endif

+ 0 - 12
arch/blackfin/include/asm/linkage.h

@@ -1,12 +0,0 @@
-/*
- * U-Boot - linkage.h
- *
- * Copyright (c) 2005-2007 Analog Devices Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
- */
-
-#ifndef __ASM_LINKAGE_H
-#define __ASM_LINKAGE_H
-
-#endif

+ 0 - 1782
arch/blackfin/include/asm/mach-bf506/BF504_cdef.h

@@ -1,1782 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF504_proc__
-#define __BFIN_CDEF_ADSP_BF504_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL() bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val) bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV() bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val) bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL() bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val) bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT() bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val) bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT() bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val) bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID() bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val) bfin_write32(CHIPID, val)
-#define bfin_read_SWRST() bfin_read16(SWRST)
-#define bfin_write_SWRST(val) bfin_write16(SWRST, val)
-#define bfin_read_SYSCR() bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val) bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT() bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val) bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0() bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val) bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IAR0() bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val) bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1() bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val) bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2() bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val) bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3() bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val) bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR0() bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val) bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_IWR0() bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val) bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IMASK1() bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val) bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4() bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val) bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5() bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val) bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6() bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val) bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7() bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val) bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1() bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val) bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1() bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val) bfin_write32(SIC_IWR1, val)
-#define bfin_read_WDOG_CTL() bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val) bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT() bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val) bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT() bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val) bfin_write32(WDOG_STAT, val)
-#define bfin_read_UART0_DLL() bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val) bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_DLH() bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val) bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_GCTL() bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val) bfin_write16(UART0_GCTL, val)
-#define bfin_read_UART0_LCR() bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val) bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR() bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val) bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR() bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val) bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR() bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val) bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR() bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val) bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_IER_SET() bfin_read16(UART0_IER_SET)
-#define bfin_write_UART0_IER_SET(val) bfin_write16(UART0_IER_SET, val)
-#define bfin_read_UART0_IER_CLEAR() bfin_read16(UART0_IER_CLEAR)
-#define bfin_write_UART0_IER_CLEAR(val) bfin_write16(UART0_IER_CLEAR, val)
-#define bfin_read_UART0_THR() bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val) bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR() bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val) bfin_write16(UART0_RBR, val)
-#define bfin_read_SPI0_CTL() bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val) bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG() bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val) bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT() bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val) bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR() bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val) bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR() bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val) bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD() bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val) bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW() bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val) bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG() bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val) bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER() bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD() bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val) bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH() bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val) bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG() bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val) bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER() bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD() bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val) bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH() bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val) bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG() bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val) bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER() bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD() bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val) bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH() bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val) bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG() bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val) bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER() bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD() bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val) bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH() bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val) bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG() bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val) bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER() bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD() bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val) bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH() bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val) bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG() bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val) bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER() bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD() bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val) bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH() bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val) bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG() bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val) bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER() bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD() bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val) bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH() bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val) bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG() bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val) bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER() bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD() bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val) bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH() bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val) bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE() bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val) bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE() bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val) bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS() bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val) bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO() bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val) bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR() bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val) bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET() bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val) bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE() bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA() bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val) bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET() bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB() bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val) bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET() bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR() bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val) bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR() bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val) bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE() bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val) bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH() bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val) bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN() bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val) bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1() bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val) bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2() bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val) bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV() bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV() bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val) bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val) bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX() bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val) bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1() bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val) bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2() bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val) bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV() bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV() bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val) bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT() bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val) bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL() bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val) bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1() bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val) bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2() bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val) bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0() bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val) bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1() bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val) bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2() bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val) bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3() bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val) bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0() bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val) bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1() bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val) bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2() bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val) bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3() bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val) bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1() bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val) bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2() bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val) bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV() bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV() bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val) bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val) bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX() bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val) bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1() bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val) bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2() bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val) bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV() bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV() bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val) bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT() bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val) bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL() bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val) bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1() bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val) bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2() bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val) bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0() bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val) bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1() bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val) bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2() bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val) bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3() bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val) bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0() bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val) bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1() bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val) bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2() bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val) bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3() bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val) bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL() bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val) bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0() bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val) bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1() bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val) bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_MODE() bfin_read16(EBIU_MODE)
-#define bfin_write_EBIU_MODE(val) bfin_write16(EBIU_MODE, val)
-#define bfin_read_EBIU_FCTL() bfin_read16(EBIU_FCTL)
-#define bfin_write_EBIU_FCTL(val) bfin_write16(EBIU_FCTL, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR() bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG() bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val) bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT() bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val) bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY() bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val) bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT() bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val) bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY() bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val) bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR() bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS() bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT() bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT() bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR() bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG() bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val) bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT() bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val) bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY() bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val) bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT() bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val) bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY() bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val) bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR() bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS() bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT() bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT() bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR() bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG() bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val) bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT() bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val) bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY() bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val) bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT() bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val) bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY() bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val) bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR() bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS() bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT() bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT() bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR() bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG() bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val) bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT() bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val) bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY() bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val) bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT() bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val) bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY() bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val) bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR() bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS() bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT() bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT() bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR() bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG() bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val) bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT() bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val) bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY() bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val) bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT() bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val) bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY() bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val) bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR() bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS() bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT() bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT() bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR() bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG() bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val) bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT() bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val) bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY() bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val) bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT() bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val) bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY() bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val) bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR() bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS() bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT() bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT() bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR() bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG() bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val) bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT() bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val) bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY() bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val) bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT() bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val) bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY() bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val) bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR() bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS() bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT() bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT() bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR() bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG() bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val) bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT() bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val) bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY() bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val) bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT() bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val) bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY() bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val) bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR() bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS() bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT() bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT() bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR() bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG() bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val) bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT() bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val) bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY() bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val) bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT() bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val) bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY() bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val) bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR() bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS() bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT() bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT() bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR() bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG() bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val) bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT() bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val) bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY() bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val) bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT() bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val) bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY() bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val) bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR() bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS() bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT() bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT() bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR() bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG() bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val) bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT() bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val) bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY() bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT() bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val) bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY() bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR() bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS() bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR() bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG() bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val) bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT() bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val) bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY() bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT() bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val) bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY() bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR() bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS() bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG() bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT() bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY() bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT() bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY() bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR() bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG() bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT() bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY() bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT() bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY() bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR() bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG() bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT() bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY() bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT() bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY() bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR() bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG() bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT() bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY() bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT() bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY() bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR() bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL() bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val) bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS() bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val) bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT() bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val) bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY() bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val) bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME() bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val) bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV() bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val) bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL() bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val) bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL() bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val) bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT() bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR() bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL() bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT() bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR() bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT() bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val) bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK() bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val) bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL() bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val) bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT() bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val) bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8() bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val) bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16() bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8() bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val) bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16() bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO() bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val) bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR() bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val) bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET() bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val) bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE() bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA() bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val) bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET() bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB() bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val) bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET() bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR() bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val) bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR() bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val) bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE() bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val) bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH() bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val) bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN() bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val) bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO() bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val) bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR() bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val) bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET() bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val) bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE() bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA() bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val) bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET() bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB() bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val) bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET() bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR() bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val) bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR() bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val) bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE() bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val) bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH() bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val) bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN() bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val) bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_DLL() bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val) bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_DLH() bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val) bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_GCTL() bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val) bfin_write16(UART1_GCTL, val)
-#define bfin_read_UART1_LCR() bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val) bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR() bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val) bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR() bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val) bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR() bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val) bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR() bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val) bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_IER_SET() bfin_read16(UART1_IER_SET)
-#define bfin_write_UART1_IER_SET(val) bfin_write16(UART1_IER_SET, val)
-#define bfin_read_UART1_IER_CLEAR() bfin_read16(UART1_IER_CLEAR)
-#define bfin_write_UART1_IER_CLEAR(val) bfin_write16(UART1_IER_CLEAR, val)
-#define bfin_read_UART1_THR() bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val) bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR() bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val) bfin_write16(UART1_RBR, val)
-#define bfin_read_CAN_MC1() bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val) bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1() bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val) bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1() bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val) bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1() bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val) bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1() bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val) bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1() bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val) bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1() bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val) bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1() bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val) bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1() bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val) bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1() bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val) bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1() bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val) bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1() bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val) bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1() bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val) bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2() bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val) bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2() bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val) bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2() bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val) bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2() bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val) bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2() bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val) bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2() bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val) bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2() bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val) bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2() bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val) bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2() bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val) bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2() bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val) bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2() bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val) bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2() bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val) bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2() bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val) bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK() bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val) bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING() bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val) bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG() bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val) bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS() bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val) bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC() bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val) bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS() bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val) bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM() bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val) bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF() bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val) bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL() bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val) bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR() bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val) bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION() bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val) bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD() bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val) bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR() bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val) bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR() bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val) bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG() bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val) bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT() bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val) bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC() bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val) bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF() bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val) bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2() bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val) bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L() bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val) bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H() bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val) bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L() bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val) bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H() bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val) bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L() bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val) bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H() bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val) bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L() bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val) bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H() bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val) bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L() bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val) bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H() bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val) bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L() bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val) bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H() bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val) bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L() bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val) bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H() bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val) bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L() bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val) bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H() bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val) bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L() bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val) bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H() bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val) bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L() bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val) bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H() bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val) bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L() bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val) bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H() bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val) bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L() bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val) bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H() bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val) bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L() bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val) bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H() bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val) bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L() bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val) bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H() bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val) bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L() bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val) bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H() bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val) bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L() bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val) bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H() bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val) bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L() bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val) bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H() bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val) bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L() bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val) bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H() bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val) bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L() bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val) bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H() bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val) bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L() bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val) bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H() bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val) bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L() bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val) bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H() bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val) bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L() bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val) bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H() bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val) bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L() bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val) bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H() bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val) bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L() bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val) bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H() bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val) bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L() bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val) bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H() bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val) bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L() bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val) bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H() bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val) bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L() bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val) bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H() bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val) bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L() bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val) bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H() bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val) bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L() bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val) bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H() bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val) bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L() bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val) bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H() bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val) bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L() bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val) bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H() bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val) bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L() bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val) bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H() bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val) bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0() bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1() bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2() bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3() bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH() bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0() bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val) bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1() bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val) bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0() bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1() bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2() bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3() bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH() bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0() bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val) bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1() bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val) bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0() bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1() bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2() bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3() bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH() bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0() bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val) bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1() bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val) bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0() bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1() bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2() bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3() bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH() bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0() bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val) bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1() bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val) bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0() bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1() bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2() bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3() bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH() bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0() bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val) bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1() bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val) bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0() bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1() bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2() bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3() bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH() bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0() bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val) bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1() bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val) bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0() bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1() bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2() bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3() bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH() bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0() bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val) bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1() bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val) bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0() bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1() bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2() bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3() bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH() bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0() bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val) bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1() bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val) bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0() bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1() bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2() bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3() bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH() bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0() bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val) bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1() bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val) bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0() bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1() bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2() bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3() bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH() bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0() bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val) bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1() bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val) bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0() bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1() bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2() bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3() bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH() bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0() bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val) bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1() bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val) bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0() bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1() bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2() bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3() bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH() bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0() bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val) bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1() bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val) bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0() bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1() bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2() bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3() bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH() bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0() bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val) bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1() bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val) bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0() bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1() bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2() bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3() bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH() bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0() bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val) bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1() bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val) bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0() bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1() bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2() bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3() bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH() bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0() bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val) bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1() bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val) bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0() bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1() bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2() bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3() bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH() bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0() bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val) bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1() bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val) bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0() bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1() bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2() bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3() bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH() bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0() bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val) bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1() bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val) bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0() bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1() bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2() bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3() bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH() bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0() bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val) bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1() bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val) bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0() bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1() bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2() bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3() bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH() bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0() bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val) bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1() bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val) bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0() bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1() bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2() bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3() bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH() bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0() bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val) bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1() bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val) bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0() bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1() bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2() bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3() bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH() bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0() bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val) bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1() bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val) bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0() bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1() bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2() bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3() bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH() bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0() bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val) bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1() bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val) bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0() bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1() bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2() bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3() bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH() bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0() bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val) bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1() bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val) bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0() bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1() bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2() bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3() bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH() bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0() bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val) bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1() bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val) bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0() bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1() bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2() bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3() bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH() bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0() bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val) bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1() bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val) bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0() bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1() bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2() bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3() bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH() bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0() bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val) bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1() bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val) bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0() bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1() bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2() bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3() bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH() bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0() bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val) bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1() bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val) bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0() bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1() bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2() bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3() bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH() bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0() bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val) bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1() bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val) bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0() bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1() bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2() bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3() bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH() bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0() bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val) bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1() bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val) bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0() bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1() bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2() bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3() bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH() bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0() bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val) bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1() bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val) bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0() bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1() bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2() bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3() bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH() bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0() bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val) bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1() bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val) bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0() bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1() bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2() bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3() bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH() bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0() bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val) bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1() bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val) bfin_write16(CAN_MB31_ID1, val)
-#define bfin_read_PWM1_CTRL() bfin_read16(PWM1_CTRL)
-#define bfin_write_PWM1_CTRL(val) bfin_write16(PWM1_CTRL, val)
-#define bfin_read_PWM1_STAT() bfin_read16(PWM1_STAT)
-#define bfin_write_PWM1_STAT(val) bfin_write16(PWM1_STAT, val)
-#define bfin_read_PWM1_TM() bfin_read16(PWM1_TM)
-#define bfin_write_PWM1_TM(val) bfin_write16(PWM1_TM, val)
-#define bfin_read_PWM1_DT() bfin_read16(PWM1_DT)
-#define bfin_write_PWM1_DT(val) bfin_write16(PWM1_DT, val)
-#define bfin_read_PWM1_GATE() bfin_read16(PWM1_GATE)
-#define bfin_write_PWM1_GATE(val) bfin_write16(PWM1_GATE, val)
-#define bfin_read_PWM1_CHA() bfin_read16(PWM1_CHA)
-#define bfin_write_PWM1_CHA(val) bfin_write16(PWM1_CHA, val)
-#define bfin_read_PWM1_CHB() bfin_read16(PWM1_CHB)
-#define bfin_write_PWM1_CHB(val) bfin_write16(PWM1_CHB, val)
-#define bfin_read_PWM1_CHC() bfin_read16(PWM1_CHC)
-#define bfin_write_PWM1_CHC(val) bfin_write16(PWM1_CHC, val)
-#define bfin_read_PWM1_SEG() bfin_read16(PWM1_SEG)
-#define bfin_write_PWM1_SEG(val) bfin_write16(PWM1_SEG, val)
-#define bfin_read_PWM1_SYNCWT() bfin_read16(PWM1_SYNCWT)
-#define bfin_write_PWM1_SYNCWT(val) bfin_write16(PWM1_SYNCWT, val)
-#define bfin_read_PWM1_CHAL() bfin_read16(PWM1_CHAL)
-#define bfin_write_PWM1_CHAL(val) bfin_write16(PWM1_CHAL, val)
-#define bfin_read_PWM1_CHBL() bfin_read16(PWM1_CHBL)
-#define bfin_write_PWM1_CHBL(val) bfin_write16(PWM1_CHBL, val)
-#define bfin_read_PWM1_CHCL() bfin_read16(PWM1_CHCL)
-#define bfin_write_PWM1_CHCL(val) bfin_write16(PWM1_CHCL, val)
-#define bfin_read_PWM1_LSI() bfin_read16(PWM1_LSI)
-#define bfin_write_PWM1_LSI(val) bfin_write16(PWM1_LSI, val)
-#define bfin_read_PWM1_STAT2() bfin_read16(PWM1_STAT2)
-#define bfin_write_PWM1_STAT2(val) bfin_write16(PWM1_STAT2, val)
-#define bfin_read_PORTF_FER() bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val) bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER() bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val) bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER() bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val) bfin_write16(PORTH_FER, val)
-#define bfin_read_PORTF_MUX() bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val) bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX() bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val) bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX() bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val) bfin_write16(PORTH_MUX, val)
-#define bfin_read_PORTF_DRIVE() bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val) bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE() bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val) bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE() bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val) bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_HYSTERESIS() bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS() bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS() bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_NONGPIO_DRIVE() bfin_read16(NONGPIO_DRIVE)
-#define bfin_write_NONGPIO_DRIVE(val) bfin_write16(NONGPIO_DRIVE, val)
-#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
-#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define bfin_read_FLASH_CONTROL() bfin_read16(FLASH_CONTROL)
-#define bfin_write_FLASH_CONTROL(val) bfin_write16(FLASH_CONTROL, val)
-#define bfin_read_FLASH_CONTROL_SET() bfin_read16(FLASH_CONTROL_SET)
-#define bfin_write_FLASH_CONTROL_SET(val) bfin_write16(FLASH_CONTROL_SET, val)
-#define bfin_read_FLASH_CONTROL_CLEAR() bfin_read16(FLASH_CONTROL_CLEAR)
-#define bfin_write_FLASH_CONTROL_CLEAR(val) bfin_write16(FLASH_CONTROL_CLEAR, val)
-#define bfin_read_CNT1_CONFIG() bfin_read16(CNT1_CONFIG)
-#define bfin_write_CNT1_CONFIG(val) bfin_write16(CNT1_CONFIG, val)
-#define bfin_read_CNT1_IMASK() bfin_read16(CNT1_IMASK)
-#define bfin_write_CNT1_IMASK(val) bfin_write16(CNT1_IMASK, val)
-#define bfin_read_CNT1_STATUS() bfin_read16(CNT1_STATUS)
-#define bfin_write_CNT1_STATUS(val) bfin_write16(CNT1_STATUS, val)
-#define bfin_read_CNT1_COMMAND() bfin_read16(CNT1_COMMAND)
-#define bfin_write_CNT1_COMMAND(val) bfin_write16(CNT1_COMMAND, val)
-#define bfin_read_CNT1_DEBOUNCE() bfin_read16(CNT1_DEBOUNCE)
-#define bfin_write_CNT1_DEBOUNCE(val) bfin_write16(CNT1_DEBOUNCE, val)
-#define bfin_read_CNT1_COUNTER() bfin_read32(CNT1_COUNTER)
-#define bfin_write_CNT1_COUNTER(val) bfin_write32(CNT1_COUNTER, val)
-#define bfin_read_CNT1_MAX() bfin_read32(CNT1_MAX)
-#define bfin_write_CNT1_MAX(val) bfin_write32(CNT1_MAX, val)
-#define bfin_read_CNT1_MIN() bfin_read32(CNT1_MIN)
-#define bfin_write_CNT1_MIN(val) bfin_write32(CNT1_MIN, val)
-#define bfin_read_SPI1_CTL() bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val) bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG() bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val) bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT() bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val) bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR() bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val) bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR() bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val) bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD() bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val) bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW() bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val) bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_CNT0_CONFIG() bfin_read16(CNT0_CONFIG)
-#define bfin_write_CNT0_CONFIG(val) bfin_write16(CNT0_CONFIG, val)
-#define bfin_read_CNT0_IMASK() bfin_read16(CNT0_IMASK)
-#define bfin_write_CNT0_IMASK(val) bfin_write16(CNT0_IMASK, val)
-#define bfin_read_CNT0_STATUS() bfin_read16(CNT0_STATUS)
-#define bfin_write_CNT0_STATUS(val) bfin_write16(CNT0_STATUS, val)
-#define bfin_read_CNT0_COMMAND() bfin_read16(CNT0_COMMAND)
-#define bfin_write_CNT0_COMMAND(val) bfin_write16(CNT0_COMMAND, val)
-#define bfin_read_CNT0_DEBOUNCE() bfin_read16(CNT0_DEBOUNCE)
-#define bfin_write_CNT0_DEBOUNCE(val) bfin_write16(CNT0_DEBOUNCE, val)
-#define bfin_read_CNT0_COUNTER() bfin_read32(CNT0_COUNTER)
-#define bfin_write_CNT0_COUNTER(val) bfin_write32(CNT0_COUNTER, val)
-#define bfin_read_CNT0_MAX() bfin_read32(CNT0_MAX)
-#define bfin_write_CNT0_MAX(val) bfin_write32(CNT0_MAX, val)
-#define bfin_read_CNT0_MIN() bfin_read32(CNT0_MIN)
-#define bfin_write_CNT0_MIN(val) bfin_write32(CNT0_MIN, val)
-#define bfin_read_PWM0_CTRL() bfin_read16(PWM0_CTRL)
-#define bfin_write_PWM0_CTRL(val) bfin_write16(PWM0_CTRL, val)
-#define bfin_read_PWM0_STAT() bfin_read16(PWM0_STAT)
-#define bfin_write_PWM0_STAT(val) bfin_write16(PWM0_STAT, val)
-#define bfin_read_PWM0_TM() bfin_read16(PWM0_TM)
-#define bfin_write_PWM0_TM(val) bfin_write16(PWM0_TM, val)
-#define bfin_read_PWM0_DT() bfin_read16(PWM0_DT)
-#define bfin_write_PWM0_DT(val) bfin_write16(PWM0_DT, val)
-#define bfin_read_PWM0_GATE() bfin_read16(PWM0_GATE)
-#define bfin_write_PWM0_GATE(val) bfin_write16(PWM0_GATE, val)
-#define bfin_read_PWM0_CHA() bfin_read16(PWM0_CHA)
-#define bfin_write_PWM0_CHA(val) bfin_write16(PWM0_CHA, val)
-#define bfin_read_PWM0_CHB() bfin_read16(PWM0_CHB)
-#define bfin_write_PWM0_CHB(val) bfin_write16(PWM0_CHB, val)
-#define bfin_read_PWM0_CHC() bfin_read16(PWM0_CHC)
-#define bfin_write_PWM0_CHC(val) bfin_write16(PWM0_CHC, val)
-#define bfin_read_PWM0_SEG() bfin_read16(PWM0_SEG)
-#define bfin_write_PWM0_SEG(val) bfin_write16(PWM0_SEG, val)
-#define bfin_read_PWM0_SYNCWT() bfin_read16(PWM0_SYNCWT)
-#define bfin_write_PWM0_SYNCWT(val) bfin_write16(PWM0_SYNCWT, val)
-#define bfin_read_PWM0_CHAL() bfin_read16(PWM0_CHAL)
-#define bfin_write_PWM0_CHAL(val) bfin_write16(PWM0_CHAL, val)
-#define bfin_read_PWM0_CHBL() bfin_read16(PWM0_CHBL)
-#define bfin_write_PWM0_CHBL(val) bfin_write16(PWM0_CHBL, val)
-#define bfin_read_PWM0_CHCL() bfin_read16(PWM0_CHCL)
-#define bfin_write_PWM0_CHCL(val) bfin_write16(PWM0_CHCL, val)
-#define bfin_read_PWM0_LSI() bfin_read16(PWM0_LSI)
-#define bfin_write_PWM0_LSI(val) bfin_write16(PWM0_LSI, val)
-#define bfin_read_PWM0_STAT2() bfin_read16(PWM0_STAT2)
-#define bfin_write_PWM0_STAT2(val) bfin_write16(PWM0_STAT2, val)
-#define bfin_read_RSI_PWR_CONTROL() bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CONTROL() bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT() bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val) bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND() bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val) bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD() bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val) bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0() bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val) bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1() bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val) bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2() bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val) bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3() bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val) bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER() bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH() bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val) bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CONTROL() bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT() bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val) bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS() bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val) bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUSCL() bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUSCL(val) bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0() bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val) bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1() bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val) bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT() bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val) bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL() bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO() bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val) bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_ESTAT() bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_ESTAT(val) bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_EMASK() bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_EMASK(val) bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CONFIG() bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CONFIG(val) bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN() bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0() bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val) bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1() bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val) bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2() bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val) bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3() bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val) bfin_write16(RSI_PID3, val)
-#define bfin_read_DMA_TC_CNT() bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val) bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER() bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val) bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF504_proc__ */

+ 0 - 944
arch/blackfin/include/asm/mach-bf506/BF504_def.h

@@ -1,944 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF504_proc__
-#define __BFIN_DEF_ADSP_BF504_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK0                     0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0                       0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0                       0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1                     0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                       0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5                       0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6                       0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7                       0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1                       0xFFC00160 /* Interrupt Status register */
-#define SIC_IWR1                       0xFFC00164 /* Interrupt Wakeup register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch Low Byte */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch High Byte */
-#define UART0_GCTL                     0xFFC00408 /* Global Control Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* Scratch Register */
-#define UART0_IER_SET                  0xFFC00420 /* Interrupt Enable Register Set */
-#define UART0_IER_CLEAR                0xFFC00424 /* Interrupt Enable Register Clear */
-#define UART0_THR                      0xFFC00428 /* Transmit Hold Register */
-#define UART0_RBR                      0xFFC0042C /* Receive Buffer Register */
-#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT                      0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW                    0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
-#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_MODE                      0xFFC00A20 /* Asynchronous Memory Mode Control Register */
-#define EBIU_FCTL                      0xFFC00A24 /* Asynchronous Memory Parameter Control Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch Low Byte */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch High Byte */
-#define UART1_GCTL                     0xFFC02008 /* Global Control Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* Scratch Register */
-#define UART1_IER_SET                  0xFFC02020 /* Interrupt Enable Register Set */
-#define UART1_IER_CLEAR                0xFFC02024 /* Interrupt Enable Register Clear */
-#define UART1_THR                      0xFFC02028 /* Transmit Hold Register */
-#define UART1_RBR                      0xFFC0202C /* Receive Buffer Register */
-#define CAN_MC1                        0xFFC02A00 /* CAN Controller 0 Mailbox Configuration Register 1 */
-#define CAN_MD1                        0xFFC02A04 /* CAN Controller 0 Mailbox Direction Register 1 */
-#define CAN_TRS1                       0xFFC02A08 /* CAN Controller 0 Transmit Request Set Register 1 */
-#define CAN_TRR1                       0xFFC02A0C /* CAN Controller 0 Transmit Request Reset Register 1 */
-#define CAN_TA1                        0xFFC02A10 /* CAN Controller 0 Transmit Acknowledge Register 1 */
-#define CAN_AA1                        0xFFC02A14 /* CAN Controller 0 Abort Acknowledge Register 1 */
-#define CAN_RMP1                       0xFFC02A18 /* CAN Controller 0 Receive Message Pending Register 1 */
-#define CAN_RML1                       0xFFC02A1C /* CAN Controller 0 Receive Message Lost Register 1 */
-#define CAN_MBTIF1                     0xFFC02A20 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 1 */
-#define CAN_MBRIF1                     0xFFC02A24 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 1 */
-#define CAN_MBIM1                      0xFFC02A28 /* CAN Controller 0 Mailbox Interrupt Mask Register 1 */
-#define CAN_RFH1                       0xFFC02A2C /* CAN Controller 0 Remote Frame Handling Enable Register 1 */
-#define CAN_OPSS1                      0xFFC02A30 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 1 */
-#define CAN_MC2                        0xFFC02A40 /* CAN Controller 0 Mailbox Configuration Register 2 */
-#define CAN_MD2                        0xFFC02A44 /* CAN Controller 0 Mailbox Direction Register 2 */
-#define CAN_TRS2                       0xFFC02A48 /* CAN Controller 0 Transmit Request Set Register 2 */
-#define CAN_TRR2                       0xFFC02A4C /* CAN Controller 0 Transmit Request Reset Register 2 */
-#define CAN_TA2                        0xFFC02A50 /* CAN Controller 0 Transmit Acknowledge Register 2 */
-#define CAN_AA2                        0xFFC02A54 /* CAN Controller 0 Abort Acknowledge Register 2 */
-#define CAN_RMP2                       0xFFC02A58 /* CAN Controller 0 Receive Message Pending Register 2 */
-#define CAN_RML2                       0xFFC02A5C /* CAN Controller 0 Receive Message Lost Register 2 */
-#define CAN_MBTIF2                     0xFFC02A60 /* CAN Controller 0 Mailbox Transmit Interrupt Flag Register 2 */
-#define CAN_MBRIF2                     0xFFC02A64 /* CAN Controller 0 Mailbox Receive Interrupt Flag Register 2 */
-#define CAN_MBIM2                      0xFFC02A68 /* CAN Controller 0 Mailbox Interrupt Mask Register 2 */
-#define CAN_RFH2                       0xFFC02A6C /* CAN Controller 0 Remote Frame Handling Enable Register 2 */
-#define CAN_OPSS2                      0xFFC02A70 /* CAN Controller 0 Overwrite Protection Single Shot Transmit Register 2 */
-#define CAN_CLOCK                      0xFFC02A80 /* CAN Controller 0 Clock Register */
-#define CAN_TIMING                     0xFFC02A84 /* CAN Controller 0 Timing Register */
-#define CAN_DEBUG                      0xFFC02A88 /* CAN Controller 0 Debug Register */
-#define CAN_STATUS                     0xFFC02A8C /* CAN Controller 0 Global Status Register */
-#define CAN_CEC                        0xFFC02A90 /* CAN Controller 0 Error Counter Register */
-#define CAN_GIS                        0xFFC02A94 /* CAN Controller 0 Global Interrupt Status Register */
-#define CAN_GIM                        0xFFC02A98 /* CAN Controller 0 Global Interrupt Mask Register */
-#define CAN_GIF                        0xFFC02A9C /* CAN Controller 0 Global Interrupt Flag Register */
-#define CAN_CONTROL                    0xFFC02AA0 /* CAN Controller 0 Master Control Register */
-#define CAN_INTR                       0xFFC02AA4 /* CAN Controller 0 Interrupt Pending Register */
-#define CAN_MBTD                       0xFFC02AAC /* CAN Controller 0 Mailbox Temporary Disable Register */
-#define CAN_EWR                        0xFFC02AB0 /* CAN Controller 0 Programmable Warning Level Register */
-#define CAN_ESR                        0xFFC02AB4 /* CAN Controller 0 Error Status Register */
-#define CAN_UCCNT                      0xFFC02AC4 /* CAN Controller 0 Universal Counter Register */
-#define CAN_UCRC                       0xFFC02AC8 /* CAN Controller 0 Universal Counter Force Reload Register */
-#define CAN_UCCNF                      0xFFC02ACC /* CAN Controller 0 Universal Counter Configuration Register */
-#define CAN_AM00L                      0xFFC02B00 /* CAN Controller 0 Mailbox 0 Acceptance Mask High Register */
-#define CAN_AM00H                      0xFFC02B04 /* CAN Controller 0 Mailbox 0 Acceptance Mask Low Register */
-#define CAN_AM01L                      0xFFC02B08 /* CAN Controller 0 Mailbox 1 Acceptance Mask High Register */
-#define CAN_AM01H                      0xFFC02B0C /* CAN Controller 0 Mailbox 1 Acceptance Mask Low Register */
-#define CAN_AM02L                      0xFFC02B10 /* CAN Controller 0 Mailbox 2 Acceptance Mask High Register */
-#define CAN_AM02H                      0xFFC02B14 /* CAN Controller 0 Mailbox 2 Acceptance Mask Low Register */
-#define CAN_AM03L                      0xFFC02B18 /* CAN Controller 0 Mailbox 3 Acceptance Mask High Register */
-#define CAN_AM03H                      0xFFC02B1C /* CAN Controller 0 Mailbox 3 Acceptance Mask Low Register */
-#define CAN_AM04L                      0xFFC02B20 /* CAN Controller 0 Mailbox 4 Acceptance Mask High Register */
-#define CAN_AM04H                      0xFFC02B24 /* CAN Controller 0 Mailbox 4 Acceptance Mask Low Register */
-#define CAN_AM05L                      0xFFC02B28 /* CAN Controller 0 Mailbox 5 Acceptance Mask High Register */
-#define CAN_AM05H                      0xFFC02B2C /* CAN Controller 0 Mailbox 5 Acceptance Mask Low Register */
-#define CAN_AM06L                      0xFFC02B30 /* CAN Controller 0 Mailbox 6 Acceptance Mask High Register */
-#define CAN_AM06H                      0xFFC02B34 /* CAN Controller 0 Mailbox 6 Acceptance Mask Low Register */
-#define CAN_AM07L                      0xFFC02B38 /* CAN Controller 0 Mailbox 7 Acceptance Mask High Register */
-#define CAN_AM07H                      0xFFC02B3C /* CAN Controller 0 Mailbox 7 Acceptance Mask Low Register */
-#define CAN_AM08L                      0xFFC02B40 /* CAN Controller 0 Mailbox 8 Acceptance Mask High Register */
-#define CAN_AM08H                      0xFFC02B44 /* CAN Controller 0 Mailbox 8 Acceptance Mask Low Register */
-#define CAN_AM09L                      0xFFC02B48 /* CAN Controller 0 Mailbox 9 Acceptance Mask High Register */
-#define CAN_AM09H                      0xFFC02B4C /* CAN Controller 0 Mailbox 9 Acceptance Mask Low Register */
-#define CAN_AM10L                      0xFFC02B50 /* CAN Controller 0 Mailbox 10 Acceptance Mask High Register */
-#define CAN_AM10H                      0xFFC02B54 /* CAN Controller 0 Mailbox 10 Acceptance Mask Low Register */
-#define CAN_AM11L                      0xFFC02B58 /* CAN Controller 0 Mailbox 11 Acceptance Mask High Register */
-#define CAN_AM11H                      0xFFC02B5C /* CAN Controller 0 Mailbox 11 Acceptance Mask Low Register */
-#define CAN_AM12L                      0xFFC02B60 /* CAN Controller 0 Mailbox 12 Acceptance Mask High Register */
-#define CAN_AM12H                      0xFFC02B64 /* CAN Controller 0 Mailbox 12 Acceptance Mask Low Register */
-#define CAN_AM13L                      0xFFC02B68 /* CAN Controller 0 Mailbox 13 Acceptance Mask High Register */
-#define CAN_AM13H                      0xFFC02B6C /* CAN Controller 0 Mailbox 13 Acceptance Mask Low Register */
-#define CAN_AM14L                      0xFFC02B70 /* CAN Controller 0 Mailbox 14 Acceptance Mask High Register */
-#define CAN_AM14H                      0xFFC02B74 /* CAN Controller 0 Mailbox 14 Acceptance Mask Low Register */
-#define CAN_AM15L                      0xFFC02B78 /* CAN Controller 0 Mailbox 15 Acceptance Mask High Register */
-#define CAN_AM15H                      0xFFC02B7C /* CAN Controller 0 Mailbox 15 Acceptance Mask Low Register */
-#define CAN_AM16L                      0xFFC02B80 /* CAN Controller 0 Mailbox 16 Acceptance Mask High Register */
-#define CAN_AM16H                      0xFFC02B84 /* CAN Controller 0 Mailbox 16 Acceptance Mask Low Register */
-#define CAN_AM17L                      0xFFC02B88 /* CAN Controller 0 Mailbox 17 Acceptance Mask High Register */
-#define CAN_AM17H                      0xFFC02B8C /* CAN Controller 0 Mailbox 17 Acceptance Mask Low Register */
-#define CAN_AM18L                      0xFFC02B90 /* CAN Controller 0 Mailbox 18 Acceptance Mask High Register */
-#define CAN_AM18H                      0xFFC02B94 /* CAN Controller 0 Mailbox 18 Acceptance Mask Low Register */
-#define CAN_AM19L                      0xFFC02B98 /* CAN Controller 0 Mailbox 19 Acceptance Mask High Register */
-#define CAN_AM19H                      0xFFC02B9C /* CAN Controller 0 Mailbox 19 Acceptance Mask Low Register */
-#define CAN_AM20L                      0xFFC02BA0 /* CAN Controller 0 Mailbox 20 Acceptance Mask High Register */
-#define CAN_AM20H                      0xFFC02BA4 /* CAN Controller 0 Mailbox 20 Acceptance Mask Low Register */
-#define CAN_AM21L                      0xFFC02BA8 /* CAN Controller 0 Mailbox 21 Acceptance Mask High Register */
-#define CAN_AM21H                      0xFFC02BAC /* CAN Controller 0 Mailbox 21 Acceptance Mask Low Register */
-#define CAN_AM22L                      0xFFC02BB0 /* CAN Controller 0 Mailbox 22 Acceptance Mask High Register */
-#define CAN_AM22H                      0xFFC02BB4 /* CAN Controller 0 Mailbox 22 Acceptance Mask Low Register */
-#define CAN_AM23L                      0xFFC02BB8 /* CAN Controller 0 Mailbox 23 Acceptance Mask High Register */
-#define CAN_AM23H                      0xFFC02BBC /* CAN Controller 0 Mailbox 23 Acceptance Mask Low Register */
-#define CAN_AM24L                      0xFFC02BC0 /* CAN Controller 0 Mailbox 24 Acceptance Mask High Register */
-#define CAN_AM24H                      0xFFC02BC4 /* CAN Controller 0 Mailbox 24 Acceptance Mask Low Register */
-#define CAN_AM25L                      0xFFC02BC8 /* CAN Controller 0 Mailbox 25 Acceptance Mask High Register */
-#define CAN_AM25H                      0xFFC02BCC /* CAN Controller 0 Mailbox 25 Acceptance Mask Low Register */
-#define CAN_AM26L                      0xFFC02BD0 /* CAN Controller 0 Mailbox 26 Acceptance Mask High Register */
-#define CAN_AM26H                      0xFFC02BD4 /* CAN Controller 0 Mailbox 26 Acceptance Mask Low Register */
-#define CAN_AM27L                      0xFFC02BD8 /* CAN Controller 0 Mailbox 27 Acceptance Mask High Register */
-#define CAN_AM27H                      0xFFC02BDC /* CAN Controller 0 Mailbox 27 Acceptance Mask Low Register */
-#define CAN_AM28L                      0xFFC02BE0 /* CAN Controller 0 Mailbox 28 Acceptance Mask High Register */
-#define CAN_AM28H                      0xFFC02BE4 /* CAN Controller 0 Mailbox 28 Acceptance Mask Low Register */
-#define CAN_AM29L                      0xFFC02BE8 /* CAN Controller 0 Mailbox 29 Acceptance Mask High Register */
-#define CAN_AM29H                      0xFFC02BEC /* CAN Controller 0 Mailbox 29 Acceptance Mask Low Register */
-#define CAN_AM30L                      0xFFC02BF0 /* CAN Controller 0 Mailbox 30 Acceptance Mask High Register */
-#define CAN_AM30H                      0xFFC02BF4 /* CAN Controller 0 Mailbox 30 Acceptance Mask Low Register */
-#define CAN_AM31L                      0xFFC02BF8 /* CAN Controller 0 Mailbox 31 Acceptance Mask High Register */
-#define CAN_AM31H                      0xFFC02BFC /* CAN Controller 0 Mailbox 31 Acceptance Mask Low Register */
-#define CAN_MB00_DATA0                 0xFFC02C00 /* CAN Controller 0 Mailbox 0 Data 0 Register */
-#define CAN_MB00_DATA1                 0xFFC02C04 /* CAN Controller 0 Mailbox 0 Data 1 Register */
-#define CAN_MB00_DATA2                 0xFFC02C08 /* CAN Controller 0 Mailbox 0 Data 2 Register */
-#define CAN_MB00_DATA3                 0xFFC02C0C /* CAN Controller 0 Mailbox 0 Data 3 Register */
-#define CAN_MB00_LENGTH                0xFFC02C10 /* CAN Controller 0 Mailbox 0 Length Register */
-#define CAN_MB00_TIMESTAMP             0xFFC02C14 /* CAN Controller 0 Mailbox 0 Timestamp Register */
-#define CAN_MB00_ID0                   0xFFC02C18 /* CAN Controller 0 Mailbox 0 ID0 Register */
-#define CAN_MB00_ID1                   0xFFC02C1C /* CAN Controller 0 Mailbox 0 ID1 Register */
-#define CAN_MB01_DATA0                 0xFFC02C20 /* CAN Controller 0 Mailbox 1 Data 0 Register */
-#define CAN_MB01_DATA1                 0xFFC02C24 /* CAN Controller 0 Mailbox 1 Data 1 Register */
-#define CAN_MB01_DATA2                 0xFFC02C28 /* CAN Controller 0 Mailbox 1 Data 2 Register */
-#define CAN_MB01_DATA3                 0xFFC02C2C /* CAN Controller 0 Mailbox 1 Data 3 Register */
-#define CAN_MB01_LENGTH                0xFFC02C30 /* CAN Controller 0 Mailbox 1 Length Register */
-#define CAN_MB01_TIMESTAMP             0xFFC02C34 /* CAN Controller 0 Mailbox 1 Timestamp Register */
-#define CAN_MB01_ID0                   0xFFC02C38 /* CAN Controller 0 Mailbox 1 ID0 Register */
-#define CAN_MB01_ID1                   0xFFC02C3C /* CAN Controller 0 Mailbox 1 ID1 Register */
-#define CAN_MB02_DATA0                 0xFFC02C40 /* CAN Controller 0 Mailbox 2 Data 0 Register */
-#define CAN_MB02_DATA1                 0xFFC02C44 /* CAN Controller 0 Mailbox 2 Data 1 Register */
-#define CAN_MB02_DATA2                 0xFFC02C48 /* CAN Controller 0 Mailbox 2 Data 2 Register */
-#define CAN_MB02_DATA3                 0xFFC02C4C /* CAN Controller 0 Mailbox 2 Data 3 Register */
-#define CAN_MB02_LENGTH                0xFFC02C50 /* CAN Controller 0 Mailbox 2 Length Register */
-#define CAN_MB02_TIMESTAMP             0xFFC02C54 /* CAN Controller 0 Mailbox 2 Timestamp Register */
-#define CAN_MB02_ID0                   0xFFC02C58 /* CAN Controller 0 Mailbox 2 ID0 Register */
-#define CAN_MB02_ID1                   0xFFC02C5C /* CAN Controller 0 Mailbox 2 ID1 Register */
-#define CAN_MB03_DATA0                 0xFFC02C60 /* CAN Controller 0 Mailbox 3 Data 0 Register */
-#define CAN_MB03_DATA1                 0xFFC02C64 /* CAN Controller 0 Mailbox 3 Data 1 Register */
-#define CAN_MB03_DATA2                 0xFFC02C68 /* CAN Controller 0 Mailbox 3 Data 2 Register */
-#define CAN_MB03_DATA3                 0xFFC02C6C /* CAN Controller 0 Mailbox 3 Data 3 Register */
-#define CAN_MB03_LENGTH                0xFFC02C70 /* CAN Controller 0 Mailbox 3 Length Register */
-#define CAN_MB03_TIMESTAMP             0xFFC02C74 /* CAN Controller 0 Mailbox 3 Timestamp Register */
-#define CAN_MB03_ID0                   0xFFC02C78 /* CAN Controller 0 Mailbox 3 ID0 Register */
-#define CAN_MB03_ID1                   0xFFC02C7C /* CAN Controller 0 Mailbox 3 ID1 Register */
-#define CAN_MB04_DATA0                 0xFFC02C80 /* CAN Controller 0 Mailbox 4 Data 0 Register */
-#define CAN_MB04_DATA1                 0xFFC02C84 /* CAN Controller 0 Mailbox 4 Data 1 Register */
-#define CAN_MB04_DATA2                 0xFFC02C88 /* CAN Controller 0 Mailbox 4 Data 2 Register */
-#define CAN_MB04_DATA3                 0xFFC02C8C /* CAN Controller 0 Mailbox 4 Data 3 Register */
-#define CAN_MB04_LENGTH                0xFFC02C90 /* CAN Controller 0 Mailbox 4 Length Register */
-#define CAN_MB04_TIMESTAMP             0xFFC02C94 /* CAN Controller 0 Mailbox 4 Timestamp Register */
-#define CAN_MB04_ID0                   0xFFC02C98 /* CAN Controller 0 Mailbox 4 ID0 Register */
-#define CAN_MB04_ID1                   0xFFC02C9C /* CAN Controller 0 Mailbox 4 ID1 Register */
-#define CAN_MB05_DATA0                 0xFFC02CA0 /* CAN Controller 0 Mailbox 5 Data 0 Register */
-#define CAN_MB05_DATA1                 0xFFC02CA4 /* CAN Controller 0 Mailbox 5 Data 1 Register */
-#define CAN_MB05_DATA2                 0xFFC02CA8 /* CAN Controller 0 Mailbox 5 Data 2 Register */
-#define CAN_MB05_DATA3                 0xFFC02CAC /* CAN Controller 0 Mailbox 5 Data 3 Register */
-#define CAN_MB05_LENGTH                0xFFC02CB0 /* CAN Controller 0 Mailbox 5 Length Register */
-#define CAN_MB05_TIMESTAMP             0xFFC02CB4 /* CAN Controller 0 Mailbox 5 Timestamp Register */
-#define CAN_MB05_ID0                   0xFFC02CB8 /* CAN Controller 0 Mailbox 5 ID0 Register */
-#define CAN_MB05_ID1                   0xFFC02CBC /* CAN Controller 0 Mailbox 5 ID1 Register */
-#define CAN_MB06_DATA0                 0xFFC02CC0 /* CAN Controller 0 Mailbox 6 Data 0 Register */
-#define CAN_MB06_DATA1                 0xFFC02CC4 /* CAN Controller 0 Mailbox 6 Data 1 Register */
-#define CAN_MB06_DATA2                 0xFFC02CC8 /* CAN Controller 0 Mailbox 6 Data 2 Register */
-#define CAN_MB06_DATA3                 0xFFC02CCC /* CAN Controller 0 Mailbox 6 Data 3 Register */
-#define CAN_MB06_LENGTH                0xFFC02CD0 /* CAN Controller 0 Mailbox 6 Length Register */
-#define CAN_MB06_TIMESTAMP             0xFFC02CD4 /* CAN Controller 0 Mailbox 6 Timestamp Register */
-#define CAN_MB06_ID0                   0xFFC02CD8 /* CAN Controller 0 Mailbox 6 ID0 Register */
-#define CAN_MB06_ID1                   0xFFC02CDC /* CAN Controller 0 Mailbox 6 ID1 Register */
-#define CAN_MB07_DATA0                 0xFFC02CE0 /* CAN Controller 0 Mailbox 7 Data 0 Register */
-#define CAN_MB07_DATA1                 0xFFC02CE4 /* CAN Controller 0 Mailbox 7 Data 1 Register */
-#define CAN_MB07_DATA2                 0xFFC02CE8 /* CAN Controller 0 Mailbox 7 Data 2 Register */
-#define CAN_MB07_DATA3                 0xFFC02CEC /* CAN Controller 0 Mailbox 7 Data 3 Register */
-#define CAN_MB07_LENGTH                0xFFC02CF0 /* CAN Controller 0 Mailbox 7 Length Register */
-#define CAN_MB07_TIMESTAMP             0xFFC02CF4 /* CAN Controller 0 Mailbox 7 Timestamp Register */
-#define CAN_MB07_ID0                   0xFFC02CF8 /* CAN Controller 0 Mailbox 7 ID0 Register */
-#define CAN_MB07_ID1                   0xFFC02CFC /* CAN Controller 0 Mailbox 7 ID1 Register */
-#define CAN_MB08_DATA0                 0xFFC02D00 /* CAN Controller 0 Mailbox 8 Data 0 Register */
-#define CAN_MB08_DATA1                 0xFFC02D04 /* CAN Controller 0 Mailbox 8 Data 1 Register */
-#define CAN_MB08_DATA2                 0xFFC02D08 /* CAN Controller 0 Mailbox 8 Data 2 Register */
-#define CAN_MB08_DATA3                 0xFFC02D0C /* CAN Controller 0 Mailbox 8 Data 3 Register */
-#define CAN_MB08_LENGTH                0xFFC02D10 /* CAN Controller 0 Mailbox 8 Length Register */
-#define CAN_MB08_TIMESTAMP             0xFFC02D14 /* CAN Controller 0 Mailbox 8 Timestamp Register */
-#define CAN_MB08_ID0                   0xFFC02D18 /* CAN Controller 0 Mailbox 8 ID0 Register */
-#define CAN_MB08_ID1                   0xFFC02D1C /* CAN Controller 0 Mailbox 8 ID1 Register */
-#define CAN_MB09_DATA0                 0xFFC02D20 /* CAN Controller 0 Mailbox 9 Data 0 Register */
-#define CAN_MB09_DATA1                 0xFFC02D24 /* CAN Controller 0 Mailbox 9 Data 1 Register */
-#define CAN_MB09_DATA2                 0xFFC02D28 /* CAN Controller 0 Mailbox 9 Data 2 Register */
-#define CAN_MB09_DATA3                 0xFFC02D2C /* CAN Controller 0 Mailbox 9 Data 3 Register */
-#define CAN_MB09_LENGTH                0xFFC02D30 /* CAN Controller 0 Mailbox 9 Length Register */
-#define CAN_MB09_TIMESTAMP             0xFFC02D34 /* CAN Controller 0 Mailbox 9 Timestamp Register */
-#define CAN_MB09_ID0                   0xFFC02D38 /* CAN Controller 0 Mailbox 9 ID0 Register */
-#define CAN_MB09_ID1                   0xFFC02D3C /* CAN Controller 0 Mailbox 9 ID1 Register */
-#define CAN_MB10_DATA0                 0xFFC02D40 /* CAN Controller 0 Mailbox 10 Data 0 Register */
-#define CAN_MB10_DATA1                 0xFFC02D44 /* CAN Controller 0 Mailbox 10 Data 1 Register */
-#define CAN_MB10_DATA2                 0xFFC02D48 /* CAN Controller 0 Mailbox 10 Data 2 Register */
-#define CAN_MB10_DATA3                 0xFFC02D4C /* CAN Controller 0 Mailbox 10 Data 3 Register */
-#define CAN_MB10_LENGTH                0xFFC02D50 /* CAN Controller 0 Mailbox 10 Length Register */
-#define CAN_MB10_TIMESTAMP             0xFFC02D54 /* CAN Controller 0 Mailbox 10 Timestamp Register */
-#define CAN_MB10_ID0                   0xFFC02D58 /* CAN Controller 0 Mailbox 10 ID0 Register */
-#define CAN_MB10_ID1                   0xFFC02D5C /* CAN Controller 0 Mailbox 10 ID1 Register */
-#define CAN_MB11_DATA0                 0xFFC02D60 /* CAN Controller 0 Mailbox 11 Data 0 Register */
-#define CAN_MB11_DATA1                 0xFFC02D64 /* CAN Controller 0 Mailbox 11 Data 1 Register */
-#define CAN_MB11_DATA2                 0xFFC02D68 /* CAN Controller 0 Mailbox 11 Data 2 Register */
-#define CAN_MB11_DATA3                 0xFFC02D6C /* CAN Controller 0 Mailbox 11 Data 3 Register */
-#define CAN_MB11_LENGTH                0xFFC02D70 /* CAN Controller 0 Mailbox 11 Length Register */
-#define CAN_MB11_TIMESTAMP             0xFFC02D74 /* CAN Controller 0 Mailbox 11 Timestamp Register */
-#define CAN_MB11_ID0                   0xFFC02D78 /* CAN Controller 0 Mailbox 11 ID0 Register */
-#define CAN_MB11_ID1                   0xFFC02D7C /* CAN Controller 0 Mailbox 11 ID1 Register */
-#define CAN_MB12_DATA0                 0xFFC02D80 /* CAN Controller 0 Mailbox 12 Data 0 Register */
-#define CAN_MB12_DATA1                 0xFFC02D84 /* CAN Controller 0 Mailbox 12 Data 1 Register */
-#define CAN_MB12_DATA2                 0xFFC02D88 /* CAN Controller 0 Mailbox 12 Data 2 Register */
-#define CAN_MB12_DATA3                 0xFFC02D8C /* CAN Controller 0 Mailbox 12 Data 3 Register */
-#define CAN_MB12_LENGTH                0xFFC02D90 /* CAN Controller 0 Mailbox 12 Length Register */
-#define CAN_MB12_TIMESTAMP             0xFFC02D94 /* CAN Controller 0 Mailbox 12 Timestamp Register */
-#define CAN_MB12_ID0                   0xFFC02D98 /* CAN Controller 0 Mailbox 12 ID0 Register */
-#define CAN_MB12_ID1                   0xFFC02D9C /* CAN Controller 0 Mailbox 12 ID1 Register */
-#define CAN_MB13_DATA0                 0xFFC02DA0 /* CAN Controller 0 Mailbox 13 Data 0 Register */
-#define CAN_MB13_DATA1                 0xFFC02DA4 /* CAN Controller 0 Mailbox 13 Data 1 Register */
-#define CAN_MB13_DATA2                 0xFFC02DA8 /* CAN Controller 0 Mailbox 13 Data 2 Register */
-#define CAN_MB13_DATA3                 0xFFC02DAC /* CAN Controller 0 Mailbox 13 Data 3 Register */
-#define CAN_MB13_LENGTH                0xFFC02DB0 /* CAN Controller 0 Mailbox 13 Length Register */
-#define CAN_MB13_TIMESTAMP             0xFFC02DB4 /* CAN Controller 0 Mailbox 13 Timestamp Register */
-#define CAN_MB13_ID0                   0xFFC02DB8 /* CAN Controller 0 Mailbox 13 ID0 Register */
-#define CAN_MB13_ID1                   0xFFC02DBC /* CAN Controller 0 Mailbox 13 ID1 Register */
-#define CAN_MB14_DATA0                 0xFFC02DC0 /* CAN Controller 0 Mailbox 14 Data 0 Register */
-#define CAN_MB14_DATA1                 0xFFC02DC4 /* CAN Controller 0 Mailbox 14 Data 1 Register */
-#define CAN_MB14_DATA2                 0xFFC02DC8 /* CAN Controller 0 Mailbox 14 Data 2 Register */
-#define CAN_MB14_DATA3                 0xFFC02DCC /* CAN Controller 0 Mailbox 14 Data 3 Register */
-#define CAN_MB14_LENGTH                0xFFC02DD0 /* CAN Controller 0 Mailbox 14 Length Register */
-#define CAN_MB14_TIMESTAMP             0xFFC02DD4 /* CAN Controller 0 Mailbox 14 Timestamp Register */
-#define CAN_MB14_ID0                   0xFFC02DD8 /* CAN Controller 0 Mailbox 14 ID0 Register */
-#define CAN_MB14_ID1                   0xFFC02DDC /* CAN Controller 0 Mailbox 14 ID1 Register */
-#define CAN_MB15_DATA0                 0xFFC02DE0 /* CAN Controller 0 Mailbox 15 Data 0 Register */
-#define CAN_MB15_DATA1                 0xFFC02DE4 /* CAN Controller 0 Mailbox 15 Data 1 Register */
-#define CAN_MB15_DATA2                 0xFFC02DE8 /* CAN Controller 0 Mailbox 15 Data 2 Register */
-#define CAN_MB15_DATA3                 0xFFC02DEC /* CAN Controller 0 Mailbox 15 Data 3 Register */
-#define CAN_MB15_LENGTH                0xFFC02DF0 /* CAN Controller 0 Mailbox 15 Length Register */
-#define CAN_MB15_TIMESTAMP             0xFFC02DF4 /* CAN Controller 0 Mailbox 15 Timestamp Register */
-#define CAN_MB15_ID0                   0xFFC02DF8 /* CAN Controller 0 Mailbox 15 ID0 Register */
-#define CAN_MB15_ID1                   0xFFC02DFC /* CAN Controller 0 Mailbox 15 ID1 Register */
-#define CAN_MB16_DATA0                 0xFFC02E00 /* CAN Controller 0 Mailbox 16 Data 0 Register */
-#define CAN_MB16_DATA1                 0xFFC02E04 /* CAN Controller 0 Mailbox 16 Data 1 Register */
-#define CAN_MB16_DATA2                 0xFFC02E08 /* CAN Controller 0 Mailbox 16 Data 2 Register */
-#define CAN_MB16_DATA3                 0xFFC02E0C /* CAN Controller 0 Mailbox 16 Data 3 Register */
-#define CAN_MB16_LENGTH                0xFFC02E10 /* CAN Controller 0 Mailbox 16 Length Register */
-#define CAN_MB16_TIMESTAMP             0xFFC02E14 /* CAN Controller 0 Mailbox 16 Timestamp Register */
-#define CAN_MB16_ID0                   0xFFC02E18 /* CAN Controller 0 Mailbox 16 ID0 Register */
-#define CAN_MB16_ID1                   0xFFC02E1C /* CAN Controller 0 Mailbox 16 ID1 Register */
-#define CAN_MB17_DATA0                 0xFFC02E20 /* CAN Controller 0 Mailbox 17 Data 0 Register */
-#define CAN_MB17_DATA1                 0xFFC02E24 /* CAN Controller 0 Mailbox 17 Data 1 Register */
-#define CAN_MB17_DATA2                 0xFFC02E28 /* CAN Controller 0 Mailbox 17 Data 2 Register */
-#define CAN_MB17_DATA3                 0xFFC02E2C /* CAN Controller 0 Mailbox 17 Data 3 Register */
-#define CAN_MB17_LENGTH                0xFFC02E30 /* CAN Controller 0 Mailbox 17 Length Register */
-#define CAN_MB17_TIMESTAMP             0xFFC02E34 /* CAN Controller 0 Mailbox 17 Timestamp Register */
-#define CAN_MB17_ID0                   0xFFC02E38 /* CAN Controller 0 Mailbox 17 ID0 Register */
-#define CAN_MB17_ID1                   0xFFC02E3C /* CAN Controller 0 Mailbox 17 ID1 Register */
-#define CAN_MB18_DATA0                 0xFFC02E40 /* CAN Controller 0 Mailbox 18 Data 0 Register */
-#define CAN_MB18_DATA1                 0xFFC02E44 /* CAN Controller 0 Mailbox 18 Data 1 Register */
-#define CAN_MB18_DATA2                 0xFFC02E48 /* CAN Controller 0 Mailbox 18 Data 2 Register */
-#define CAN_MB18_DATA3                 0xFFC02E4C /* CAN Controller 0 Mailbox 18 Data 3 Register */
-#define CAN_MB18_LENGTH                0xFFC02E50 /* CAN Controller 0 Mailbox 18 Length Register */
-#define CAN_MB18_TIMESTAMP             0xFFC02E54 /* CAN Controller 0 Mailbox 18 Timestamp Register */
-#define CAN_MB18_ID0                   0xFFC02E58 /* CAN Controller 0 Mailbox 18 ID0 Register */
-#define CAN_MB18_ID1                   0xFFC02E5C /* CAN Controller 0 Mailbox 18 ID1 Register */
-#define CAN_MB19_DATA0                 0xFFC02E60 /* CAN Controller 0 Mailbox 19 Data 0 Register */
-#define CAN_MB19_DATA1                 0xFFC02E64 /* CAN Controller 0 Mailbox 19 Data 1 Register */
-#define CAN_MB19_DATA2                 0xFFC02E68 /* CAN Controller 0 Mailbox 19 Data 2 Register */
-#define CAN_MB19_DATA3                 0xFFC02E6C /* CAN Controller 0 Mailbox 19 Data 3 Register */
-#define CAN_MB19_LENGTH                0xFFC02E70 /* CAN Controller 0 Mailbox 19 Length Register */
-#define CAN_MB19_TIMESTAMP             0xFFC02E74 /* CAN Controller 0 Mailbox 19 Timestamp Register */
-#define CAN_MB19_ID0                   0xFFC02E78 /* CAN Controller 0 Mailbox 19 ID0 Register */
-#define CAN_MB19_ID1                   0xFFC02E7C /* CAN Controller 0 Mailbox 19 ID1 Register */
-#define CAN_MB20_DATA0                 0xFFC02E80 /* CAN Controller 0 Mailbox 20 Data 0 Register */
-#define CAN_MB20_DATA1                 0xFFC02E84 /* CAN Controller 0 Mailbox 20 Data 1 Register */
-#define CAN_MB20_DATA2                 0xFFC02E88 /* CAN Controller 0 Mailbox 20 Data 2 Register */
-#define CAN_MB20_DATA3                 0xFFC02E8C /* CAN Controller 0 Mailbox 20 Data 3 Register */
-#define CAN_MB20_LENGTH                0xFFC02E90 /* CAN Controller 0 Mailbox 20 Length Register */
-#define CAN_MB20_TIMESTAMP             0xFFC02E94 /* CAN Controller 0 Mailbox 20 Timestamp Register */
-#define CAN_MB20_ID0                   0xFFC02E98 /* CAN Controller 0 Mailbox 20 ID0 Register */
-#define CAN_MB20_ID1                   0xFFC02E9C /* CAN Controller 0 Mailbox 20 ID1 Register */
-#define CAN_MB21_DATA0                 0xFFC02EA0 /* CAN Controller 0 Mailbox 21 Data 0 Register */
-#define CAN_MB21_DATA1                 0xFFC02EA4 /* CAN Controller 0 Mailbox 21 Data 1 Register */
-#define CAN_MB21_DATA2                 0xFFC02EA8 /* CAN Controller 0 Mailbox 21 Data 2 Register */
-#define CAN_MB21_DATA3                 0xFFC02EAC /* CAN Controller 0 Mailbox 21 Data 3 Register */
-#define CAN_MB21_LENGTH                0xFFC02EB0 /* CAN Controller 0 Mailbox 21 Length Register */
-#define CAN_MB21_TIMESTAMP             0xFFC02EB4 /* CAN Controller 0 Mailbox 21 Timestamp Register */
-#define CAN_MB21_ID0                   0xFFC02EB8 /* CAN Controller 0 Mailbox 21 ID0 Register */
-#define CAN_MB21_ID1                   0xFFC02EBC /* CAN Controller 0 Mailbox 21 ID1 Register */
-#define CAN_MB22_DATA0                 0xFFC02EC0 /* CAN Controller 0 Mailbox 22 Data 0 Register */
-#define CAN_MB22_DATA1                 0xFFC02EC4 /* CAN Controller 0 Mailbox 22 Data 1 Register */
-#define CAN_MB22_DATA2                 0xFFC02EC8 /* CAN Controller 0 Mailbox 22 Data 2 Register */
-#define CAN_MB22_DATA3                 0xFFC02ECC /* CAN Controller 0 Mailbox 22 Data 3 Register */
-#define CAN_MB22_LENGTH                0xFFC02ED0 /* CAN Controller 0 Mailbox 22 Length Register */
-#define CAN_MB22_TIMESTAMP             0xFFC02ED4 /* CAN Controller 0 Mailbox 22 Timestamp Register */
-#define CAN_MB22_ID0                   0xFFC02ED8 /* CAN Controller 0 Mailbox 22 ID0 Register */
-#define CAN_MB22_ID1                   0xFFC02EDC /* CAN Controller 0 Mailbox 22 ID1 Register */
-#define CAN_MB23_DATA0                 0xFFC02EE0 /* CAN Controller 0 Mailbox 23 Data 0 Register */
-#define CAN_MB23_DATA1                 0xFFC02EE4 /* CAN Controller 0 Mailbox 23 Data 1 Register */
-#define CAN_MB23_DATA2                 0xFFC02EE8 /* CAN Controller 0 Mailbox 23 Data 2 Register */
-#define CAN_MB23_DATA3                 0xFFC02EEC /* CAN Controller 0 Mailbox 23 Data 3 Register */
-#define CAN_MB23_LENGTH                0xFFC02EF0 /* CAN Controller 0 Mailbox 23 Length Register */
-#define CAN_MB23_TIMESTAMP             0xFFC02EF4 /* CAN Controller 0 Mailbox 23 Timestamp Register */
-#define CAN_MB23_ID0                   0xFFC02EF8 /* CAN Controller 0 Mailbox 23 ID0 Register */
-#define CAN_MB23_ID1                   0xFFC02EFC /* CAN Controller 0 Mailbox 23 ID1 Register */
-#define CAN_MB24_DATA0                 0xFFC02F00 /* CAN Controller 0 Mailbox 24 Data 0 Register */
-#define CAN_MB24_DATA1                 0xFFC02F04 /* CAN Controller 0 Mailbox 24 Data 1 Register */
-#define CAN_MB24_DATA2                 0xFFC02F08 /* CAN Controller 0 Mailbox 24 Data 2 Register */
-#define CAN_MB24_DATA3                 0xFFC02F0C /* CAN Controller 0 Mailbox 24 Data 3 Register */
-#define CAN_MB24_LENGTH                0xFFC02F10 /* CAN Controller 0 Mailbox 24 Length Register */
-#define CAN_MB24_TIMESTAMP             0xFFC02F14 /* CAN Controller 0 Mailbox 24 Timestamp Register */
-#define CAN_MB24_ID0                   0xFFC02F18 /* CAN Controller 0 Mailbox 24 ID0 Register */
-#define CAN_MB24_ID1                   0xFFC02F1C /* CAN Controller 0 Mailbox 24 ID1 Register */
-#define CAN_MB25_DATA0                 0xFFC02F20 /* CAN Controller 0 Mailbox 25 Data 0 Register */
-#define CAN_MB25_DATA1                 0xFFC02F24 /* CAN Controller 0 Mailbox 25 Data 1 Register */
-#define CAN_MB25_DATA2                 0xFFC02F28 /* CAN Controller 0 Mailbox 25 Data 2 Register */
-#define CAN_MB25_DATA3                 0xFFC02F2C /* CAN Controller 0 Mailbox 25 Data 3 Register */
-#define CAN_MB25_LENGTH                0xFFC02F30 /* CAN Controller 0 Mailbox 25 Length Register */
-#define CAN_MB25_TIMESTAMP             0xFFC02F34 /* CAN Controller 0 Mailbox 25 Timestamp Register */
-#define CAN_MB25_ID0                   0xFFC02F38 /* CAN Controller 0 Mailbox 25 ID0 Register */
-#define CAN_MB25_ID1                   0xFFC02F3C /* CAN Controller 0 Mailbox 25 ID1 Register */
-#define CAN_MB26_DATA0                 0xFFC02F40 /* CAN Controller 0 Mailbox 26 Data 0 Register */
-#define CAN_MB26_DATA1                 0xFFC02F44 /* CAN Controller 0 Mailbox 26 Data 1 Register */
-#define CAN_MB26_DATA2                 0xFFC02F48 /* CAN Controller 0 Mailbox 26 Data 2 Register */
-#define CAN_MB26_DATA3                 0xFFC02F4C /* CAN Controller 0 Mailbox 26 Data 3 Register */
-#define CAN_MB26_LENGTH                0xFFC02F50 /* CAN Controller 0 Mailbox 26 Length Register */
-#define CAN_MB26_TIMESTAMP             0xFFC02F54 /* CAN Controller 0 Mailbox 26 Timestamp Register */
-#define CAN_MB26_ID0                   0xFFC02F58 /* CAN Controller 0 Mailbox 26 ID0 Register */
-#define CAN_MB26_ID1                   0xFFC02F5C /* CAN Controller 0 Mailbox 26 ID1 Register */
-#define CAN_MB27_DATA0                 0xFFC02F60 /* CAN Controller 0 Mailbox 27 Data 0 Register */
-#define CAN_MB27_DATA1                 0xFFC02F64 /* CAN Controller 0 Mailbox 27 Data 1 Register */
-#define CAN_MB27_DATA2                 0xFFC02F68 /* CAN Controller 0 Mailbox 27 Data 2 Register */
-#define CAN_MB27_DATA3                 0xFFC02F6C /* CAN Controller 0 Mailbox 27 Data 3 Register */
-#define CAN_MB27_LENGTH                0xFFC02F70 /* CAN Controller 0 Mailbox 27 Length Register */
-#define CAN_MB27_TIMESTAMP             0xFFC02F74 /* CAN Controller 0 Mailbox 27 Timestamp Register */
-#define CAN_MB27_ID0                   0xFFC02F78 /* CAN Controller 0 Mailbox 27 ID0 Register */
-#define CAN_MB27_ID1                   0xFFC02F7C /* CAN Controller 0 Mailbox 27 ID1 Register */
-#define CAN_MB28_DATA0                 0xFFC02F80 /* CAN Controller 0 Mailbox 28 Data 0 Register */
-#define CAN_MB28_DATA1                 0xFFC02F84 /* CAN Controller 0 Mailbox 28 Data 1 Register */
-#define CAN_MB28_DATA2                 0xFFC02F88 /* CAN Controller 0 Mailbox 28 Data 2 Register */
-#define CAN_MB28_DATA3                 0xFFC02F8C /* CAN Controller 0 Mailbox 28 Data 3 Register */
-#define CAN_MB28_LENGTH                0xFFC02F90 /* CAN Controller 0 Mailbox 28 Length Register */
-#define CAN_MB28_TIMESTAMP             0xFFC02F94 /* CAN Controller 0 Mailbox 28 Timestamp Register */
-#define CAN_MB28_ID0                   0xFFC02F98 /* CAN Controller 0 Mailbox 28 ID0 Register */
-#define CAN_MB28_ID1                   0xFFC02F9C /* CAN Controller 0 Mailbox 28 ID1 Register */
-#define CAN_MB29_DATA0                 0xFFC02FA0 /* CAN Controller 0 Mailbox 29 Data 0 Register */
-#define CAN_MB29_DATA1                 0xFFC02FA4 /* CAN Controller 0 Mailbox 29 Data 1 Register */
-#define CAN_MB29_DATA2                 0xFFC02FA8 /* CAN Controller 0 Mailbox 29 Data 2 Register */
-#define CAN_MB29_DATA3                 0xFFC02FAC /* CAN Controller 0 Mailbox 29 Data 3 Register */
-#define CAN_MB29_LENGTH                0xFFC02FB0 /* CAN Controller 0 Mailbox 29 Length Register */
-#define CAN_MB29_TIMESTAMP             0xFFC02FB4 /* CAN Controller 0 Mailbox 29 Timestamp Register */
-#define CAN_MB29_ID0                   0xFFC02FB8 /* CAN Controller 0 Mailbox 29 ID0 Register */
-#define CAN_MB29_ID1                   0xFFC02FBC /* CAN Controller 0 Mailbox 29 ID1 Register */
-#define CAN_MB30_DATA0                 0xFFC02FC0 /* CAN Controller 0 Mailbox 30 Data 0 Register */
-#define CAN_MB30_DATA1                 0xFFC02FC4 /* CAN Controller 0 Mailbox 30 Data 1 Register */
-#define CAN_MB30_DATA2                 0xFFC02FC8 /* CAN Controller 0 Mailbox 30 Data 2 Register */
-#define CAN_MB30_DATA3                 0xFFC02FCC /* CAN Controller 0 Mailbox 30 Data 3 Register */
-#define CAN_MB30_LENGTH                0xFFC02FD0 /* CAN Controller 0 Mailbox 30 Length Register */
-#define CAN_MB30_TIMESTAMP             0xFFC02FD4 /* CAN Controller 0 Mailbox 30 Timestamp Register */
-#define CAN_MB30_ID0                   0xFFC02FD8 /* CAN Controller 0 Mailbox 30 ID0 Register */
-#define CAN_MB30_ID1                   0xFFC02FDC /* CAN Controller 0 Mailbox 30 ID1 Register */
-#define CAN_MB31_DATA0                 0xFFC02FE0 /* CAN Controller 0 Mailbox 31 Data 0 Register */
-#define CAN_MB31_DATA1                 0xFFC02FE4 /* CAN Controller 0 Mailbox 31 Data 1 Register */
-#define CAN_MB31_DATA2                 0xFFC02FE8 /* CAN Controller 0 Mailbox 31 Data 2 Register */
-#define CAN_MB31_DATA3                 0xFFC02FEC /* CAN Controller 0 Mailbox 31 Data 3 Register */
-#define CAN_MB31_LENGTH                0xFFC02FF0 /* CAN Controller 0 Mailbox 31 Length Register */
-#define CAN_MB31_TIMESTAMP             0xFFC02FF4 /* CAN Controller 0 Mailbox 31 Timestamp Register */
-#define CAN_MB31_ID0                   0xFFC02FF8 /* CAN Controller 0 Mailbox 31 ID0 Register */
-#define CAN_MB31_ID1                   0xFFC02FFC /* CAN Controller 0 Mailbox 31 ID1 Register */
-#define PWM1_CTRL                      0xFFC03000 /* PWM1 Control Register */
-#define PWM1_STAT                      0xFFC03004 /* PWM1 Status Register */
-#define PWM1_TM                        0xFFC03008 /* PWM1 Period Register */
-#define PWM1_DT                        0xFFC0300C /* PWM1 Dead Time Register */
-#define PWM1_GATE                      0xFFC03010 /* PWM1 Chopping Control */
-#define PWM1_CHA                       0xFFC03014 /* PWM1 Channel A Duty Control */
-#define PWM1_CHB                       0xFFC03018 /* PWM1 Channel B Duty Control */
-#define PWM1_CHC                       0xFFC0301C /* PWM1 Channel C Duty Control */
-#define PWM1_SEG                       0xFFC03020 /* PWM1 Crossover and Output Enable */
-#define PWM1_SYNCWT                    0xFFC03024 /* PWM1 Sync pulse width control */
-#define PWM1_CHAL                      0xFFC03028 /* PWM1 Channel AL Duty Control (SR mode only) */
-#define PWM1_CHBL                      0xFFC0302C /* PWM1 Channel BL Duty Control (SR mode only) */
-#define PWM1_CHCL                      0xFFC03030 /* PWM1 Channel CL Duty Control (SR mode only) */
-#define PWM1_LSI                       0xFFC03034 /* Low Side Invert (SR mode only) */
-#define PWM1_STAT2                     0xFFC03038 /* PWM1 Status Register */
-#define ACM_CTL                        0xFFC03100 /* ACM Control Register */
-#define ACM_TC0                        0xFFC03104 /* ACM Timing Configuration 0 Register */
-#define ACM_TC1                        0xFFC03108 /* ACM Timing Configuration 1 Register */
-#define ACM_STAT                       0xFFC0310C /* ACM Status Register */
-#define ACM_ES                         0xFFC03110 /* ACM Event Status Register */
-#define ACM_IMSK                       0xFFC03114 /* ACM Interrupt Mask Register */
-#define ACM_MS                         0xFFC03118 /* ACM Missed Event Status Register */
-#define ACM_EMSK                       0xFFC0311C /* ACM Missed Event Interrupt Mask Register */
-#define ACM_ER0                        0xFFC03120 /* ACM Event 0 Control Register */
-#define ACM_ER1                        0xFFC03124 /* ACM Event 1 Control Register */
-#define ACM_ER2                        0xFFC03128 /* ACM Event 2 Control Register */
-#define ACM_ER3                        0xFFC0312C /* ACM Event 3 Control Register */
-#define ACM_ER4                        0xFFC03130 /* ACM Event 4 Control Register */
-#define ACM_ER5                        0xFFC03134 /* ACM Event 5 Control Register */
-#define ACM_ER6                        0xFFC03138 /* ACM Event 6 Control Register */
-#define ACM_ER7                        0xFFC0313C /* ACM Event 7 Control Register */
-#define ACM_ER8                        0xFFC03140 /* ACM Event 8 Control Register */
-#define ACM_ER9                        0xFFC03144 /* ACM Event 9 Control Register */
-#define ACM_ER10                       0xFFC03148 /* ACM Event 10 Control Register */
-#define ACM_ER11                       0xFFC0314C /* ACM Event 11 Control Register */
-#define ACM_ER12                       0xFFC03150 /* ACM Event 12 Control Register */
-#define ACM_ER13                       0xFFC03154 /* ACM Event 13 Control Register */
-#define ACM_ER14                       0xFFC03158 /* ACM Event 14 Control Register */
-#define ACM_ER15                       0xFFC0315C /* ACM Event 15 Control Register */
-#define ACM_ET0                        0xFFC03180 /* ACM Event 0 Time Register */
-#define ACM_ET1                        0xFFC03184 /* ACM Event 1 Time Register */
-#define ACM_ET2                        0xFFC03188 /* ACM Event 2 Time Register */
-#define ACM_ET3                        0xFFC0318C /* ACM Event 3 Time Register */
-#define ACM_ET4                        0xFFC03190 /* ACM Event 4 Time Register */
-#define ACM_ET5                        0xFFC03194 /* ACM Event 5 Time Register */
-#define ACM_ET6                        0xFFC03198 /* ACM Event 6 Time Register */
-#define ACM_ET7                        0xFFC0319C /* ACM Event 7 Time Register */
-#define ACM_ET8                        0xFFC031A0 /* ACM Event 8 Time Register */
-#define ACM_ET9                        0xFFC031A4 /* ACM Event 9 Time Register */
-#define ACM_ET10                       0xFFC031A8 /* ACM Event 10 Time Register */
-#define ACM_ET11                       0xFFC031AC /* ACM Event 11 Time Register */
-#define ACM_ET12                       0xFFC031B0 /* ACM Event 12 Time Register */
-#define ACM_ET13                       0xFFC031B4 /* ACM Event 13 Time Register */
-#define ACM_ET14                       0xFFC031B8 /* ACM Event 14 Time Register */
-#define ACM_ET15                       0xFFC031BC /* ACM Event 15 Time Register */
-#define ACM_TMR0                       0xFFC031C0 /* ACM Timer 0 Registers */
-#define ACM_TMR1                       0xFFC031C4 /* ACM Timer 1 Registers */
-#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define PORTF_MUX                      0xFFC03210 /* Port F mux control */
-#define PORTG_MUX                      0xFFC03214 /* Port G mux control */
-#define PORTH_MUX                      0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE                    0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE                    0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE                    0xFFC03228 /* Port H drive strength control */
-#define PORTF_HYSTERESIS               0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS               0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS               0xFFC03248 /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE                  0xFFC03280 /* Non-GPIO Port drive strength control */
-#define NONGPIO_HYSTERESIS             0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
-#define FLASH_CONTROL                  0xFFC0328C /* Stacked flash control register */
-#define FLASH_CONTROL_SET              0xFFC03290 /* Stacked flash control set register */
-#define FLASH_CONTROL_CLEAR            0xFFC03294 /* Stacked flash control clear register */
-#define CNT1_CONFIG                    0xFFC03300 /* Counter 1 Configuration Register */
-#define CNT1_IMASK                     0xFFC03304 /* Counter 1 Interrupt Mask Register */
-#define CNT1_STATUS                    0xFFC03308 /* Counter 1 Status Register */
-#define CNT1_COMMAND                   0xFFC0330C /* Counter 1 Command Register */
-#define CNT1_DEBOUNCE                  0xFFC03310 /* Counter 1 Debounce Register */
-#define CNT1_COUNTER                   0xFFC03314 /* Counter 1 Counter Register */
-#define CNT1_MAX                       0xFFC03318 /* Counter 1 Boundry Value Register - max count */
-#define CNT1_MIN                       0xFFC0331C /* Counter 1 Boundry Value Register - min count */
-#define SPI1_CTL                       0xFFC03400 /* SPI1 Control */
-#define SPI1_FLG                       0xFFC03404 /* SPI1 Flag Register */
-#define SPI1_STAT                      0xFFC03408 /* SPI1 Status Register */
-#define SPI1_TDBR                      0xFFC0340C /* SPI1 Transmit Data Buffer */
-#define SPI1_RDBR                      0xFFC03410 /* SPI1 Receive Data Buffer */
-#define SPI1_BAUD                      0xFFC03414 /* SPI1 Baud Rate */
-#define SPI1_SHADOW                    0xFFC03418 /* SPI1_RDBR Shadow Register */
-#define CNT0_CONFIG                    0xFFC03500 /* Configuration/Control Register */
-#define CNT0_IMASK                     0xFFC03504 /* Interrupt Mask Register */
-#define CNT0_STATUS                    0xFFC03508 /* Status Register */
-#define CNT0_COMMAND                   0xFFC0350C /* Command Register */
-#define CNT0_DEBOUNCE                  0xFFC03510 /* Debounce Prescaler Register */
-#define CNT0_COUNTER                   0xFFC03514 /* Counter Register */
-#define CNT0_MAX                       0xFFC03518 /* Maximal Count Boundary Value Register */
-#define CNT0_MIN                       0xFFC0351C /* Minimal Count Boundary Value Register */
-#define PWM0_CTRL                      0xFFC03700 /* PWM Control Register */
-#define PWM0_STAT                      0xFFC03704 /* PWM Status Register */
-#define PWM0_TM                        0xFFC03708 /* PWM Period Register */
-#define PWM0_DT                        0xFFC0370C /* PWM Dead Time Register */
-#define PWM0_GATE                      0xFFC03710 /* PWM Chopping Control */
-#define PWM0_CHA                       0xFFC03714 /* PWM Channel A Duty Control */
-#define PWM0_CHB                       0xFFC03718 /* PWM Channel B Duty Control */
-#define PWM0_CHC                       0xFFC0371C /* PWM Channel C Duty Control */
-#define PWM0_SEG                       0xFFC03720 /* PWM Crossover and Output Enable */
-#define PWM0_SYNCWT                    0xFFC03724 /* PWM Sync pulse width control */
-#define PWM0_CHAL                      0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM0_CHBL                      0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM0_CHCL                      0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM0_LSI                       0xFFC03734 /* Low Side Invert (SR mode only) */
-#define PWM0_STAT2                     0xFFC03738 /* PWM Status Register */
-#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0                       0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1                       0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2                       0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3                       0xFFC038DC /* RSI Peripheral ID Register 3 */
-#define DMA_TC_CNT                     0xFFC00B0C
-#define DMA_TC_PER                     0xFFC00B10
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE 0x8000
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE 0x8000
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF504_proc__ */

+ 0 - 11
arch/blackfin/include/asm/mach-bf506/BF506_cdef.h

@@ -1,11 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF506_proc__
-#define __BFIN_CDEF_ADSP_BF506_proc__
-
-#include "BF504_cdef.h"
-
-#endif /* __BFIN_CDEF_ADSP_BF506_proc__ */

+ 0 - 11
arch/blackfin/include/asm/mach-bf506/BF506_def.h

@@ -1,11 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF506_proc__
-#define __BFIN_DEF_ADSP_BF506_proc__
-
-#include "BF504_def.h"
-
-#endif /* __BFIN_DEF_ADSP_BF506_proc__ */

+ 0 - 145
arch/blackfin/include/asm/mach-bf506/anomaly.h

@@ -1,145 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision A, 02/18/2011; ADSP-BF504/BF504F/BF506F Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF506 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* UART IrDA Receiver Fails on Extended Bit Pulses */
-#define ANOMALY_05000447 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* SPORT0 Data Transmit Error in Multi-Channel Mode with Internal Clock */
-#define ANOMALY_05000476 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Disabling ACM During an Ongoing Transfer Can Lead to Undefined ACM Behavior */
-#define ANOMALY_05000478 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* TWI Vbus Minimum Specification Can Be Violated under Certain Conditions */
-#define ANOMALY_05000486 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* Maximum Idd-deepsleep Specifications Can Be Exceeded under Certain Conditions */
-#define ANOMALY_05000495 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif

+ 0 - 5
arch/blackfin/include/asm/mach-bf506/def_local.h

@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF50x 1	/* Linux glue */

+ 0 - 52
arch/blackfin/include/asm/mach-bf506/gpio.h

@@ -1,52 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 35
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-#define GPIO_PG0	16
-#define GPIO_PG1	17
-#define GPIO_PG2	18
-#define GPIO_PG3	19
-#define GPIO_PG4	20
-#define GPIO_PG5	21
-#define GPIO_PG6	22
-#define GPIO_PG7	23
-#define GPIO_PG8	24
-#define GPIO_PG9	25
-#define GPIO_PG10	26
-#define GPIO_PG11	27
-#define GPIO_PG12	28
-#define GPIO_PG13	29
-#define GPIO_PG14	30
-#define GPIO_PG15	31
-#define GPIO_PH0	32
-#define GPIO_PH1	33
-#define GPIO_PH2	34
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */

+ 0 - 148
arch/blackfin/include/asm/mach-bf506/portmux.h

@@ -1,148 +0,0 @@
-/*
- * Copyright 2008-2010 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-/* PPI Port Mux */
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-
-#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-
-#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF13
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-
-#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-
-/* UART Port Mux */
-#ifdef CONFIG_BF506_UART0_PORTF
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#else
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#endif
-#define P_UART0_RTS	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#define P_UART0_CTS	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-
-#ifdef CONFIG_BF506_UART1_PORTG
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#else
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#endif
-#define P_UART1_RTS	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_UART1_CTS	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-
-/* Timer */
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-
-/* CAN */
-#define P_CAN_TX	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_CAN_RX	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-
-/* PWM */
-#define P_PWM0_AH	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PWM0_AL	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-#define P_PWM0_BH	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PWM0_BL	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PWM0_CH	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PWM0_CL	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PWM0_SYNC	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PWM0_TRIP	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-
-#define P_PWM1_AH	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_PWM1_AL	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_PWM1_BH	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_PWM1_BL	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_PWM1_CH	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(2))
-#define P_PWM1_CL	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_PWM1_SYNC	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_PWM1_TRIP	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-
-/* RSI */
-#define P_RSI_DATA0	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_RSI_DATA1	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_RSI_DATA2	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_DATA3	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_RSI_DATA5	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_RSI_DATA6	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RSI_DATA7	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_RSI_CMD	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#define P_RSI_CLK	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-
-/* ACM */
-#define P_ACM_SE_DIFF	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_ACM_RANGE	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_ACM_A0	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_ACM_A1	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_ACM_A2	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-
-#endif				/* _MACH_PORTMUX_H_ */

+ 0 - 59
arch/blackfin/include/asm/mach-bf506/ports.h

@@ -1,59 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK	0x0003
-#define PORT_x_MUX_1_MASK	0x000C
-#define PORT_x_MUX_2_MASK	0x0030
-#define PORT_x_MUX_3_MASK	0x00C0
-#define PORT_x_MUX_4_MASK	0x0300
-#define PORT_x_MUX_5_MASK	0x0C00
-#define PORT_x_MUX_6_MASK	0x3000
-#define PORT_x_MUX_7_MASK	0xC000
-
-#define PORT_x_MUX_FUNC_1	(0x0)
-#define PORT_x_MUX_FUNC_2	(0x1)
-#define PORT_x_MUX_FUNC_3	(0x2)
-#define PORT_x_MUX_FUNC_4	(0x3)
-#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-
-#endif

+ 0 - 1000
arch/blackfin/include/asm/mach-bf518/BF512_cdef.h

@@ -1,1000 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF512_proc__
-#define __BFIN_CDEF_ADSP_BF512_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_SPI0_CTL()           bfin_read16(SPI0_CTL)
-#define bfin_write_SPI0_CTL(val)       bfin_write16(SPI0_CTL, val)
-#define bfin_read_SPI0_FLG()           bfin_read16(SPI0_FLG)
-#define bfin_write_SPI0_FLG(val)       bfin_write16(SPI0_FLG, val)
-#define bfin_read_SPI0_STAT()          bfin_read16(SPI0_STAT)
-#define bfin_write_SPI0_STAT(val)      bfin_write16(SPI0_STAT, val)
-#define bfin_read_SPI0_TDBR()          bfin_read16(SPI0_TDBR)
-#define bfin_write_SPI0_TDBR(val)      bfin_write16(SPI0_TDBR, val)
-#define bfin_read_SPI0_RDBR()          bfin_read16(SPI0_RDBR)
-#define bfin_write_SPI0_RDBR(val)      bfin_write16(SPI0_RDBR, val)
-#define bfin_read_SPI0_BAUD()          bfin_read16(SPI0_BAUD)
-#define bfin_write_SPI0_BAUD(val)      bfin_write16(SPI0_BAUD, val)
-#define bfin_read_SPI0_SHADOW()        bfin_read16(SPI0_SHADOW)
-#define bfin_write_SPI0_SHADOW(val)    bfin_write16(SPI0_SHADOW, val)
-#define bfin_read_SPI1_CTL()           bfin_read16(SPI1_CTL)
-#define bfin_write_SPI1_CTL(val)       bfin_write16(SPI1_CTL, val)
-#define bfin_read_SPI1_FLG()           bfin_read16(SPI1_FLG)
-#define bfin_write_SPI1_FLG(val)       bfin_write16(SPI1_FLG, val)
-#define bfin_read_SPI1_STAT()          bfin_read16(SPI1_STAT)
-#define bfin_write_SPI1_STAT(val)      bfin_write16(SPI1_STAT, val)
-#define bfin_read_SPI1_TDBR()          bfin_read16(SPI1_TDBR)
-#define bfin_write_SPI1_TDBR(val)      bfin_write16(SPI1_TDBR, val)
-#define bfin_read_SPI1_RDBR()          bfin_read16(SPI1_RDBR)
-#define bfin_write_SPI1_RDBR(val)      bfin_write16(SPI1_RDBR, val)
-#define bfin_read_SPI1_BAUD()          bfin_read16(SPI1_BAUD)
-#define bfin_write_SPI1_BAUD(val)      bfin_write16(SPI1_BAUD, val)
-#define bfin_read_SPI1_SHADOW()        bfin_read16(SPI1_SHADOW)
-#define bfin_write_SPI1_SHADOW(val)    bfin_write16(SPI1_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_PORTF_MUX()          bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)      bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()          bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)      bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()          bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)      bfin_write16(PORTH_MUX, val)
-#define bfin_read_PORTF_DRIVE()        bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)    bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()        bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)    bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()        bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)    bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_HYSTERESIS()   bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS()   bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS()   bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_NONGPIO_DRIVE()      bfin_read16(NONGPIO_DRIVE)
-#define bfin_write_NONGPIO_DRIVE(val)  bfin_write16(NONGPIO_DRIVE, val)
-#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
-#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define bfin_read_PWM_CTRL()           bfin_read16(PWM_CTRL)
-#define bfin_write_PWM_CTRL(val)       bfin_write16(PWM_CTRL, val)
-#define bfin_read_PWM_STAT()           bfin_read16(PWM_STAT)
-#define bfin_write_PWM_STAT(val)       bfin_write16(PWM_STAT, val)
-#define bfin_read_PWM_TM()             bfin_read16(PWM_TM)
-#define bfin_write_PWM_TM(val)         bfin_write16(PWM_TM, val)
-#define bfin_read_PWM_DT()             bfin_read16(PWM_DT)
-#define bfin_write_PWM_DT(val)         bfin_write16(PWM_DT, val)
-#define bfin_read_PWM_GATE()           bfin_read16(PWM_GATE)
-#define bfin_write_PWM_GATE(val)       bfin_write16(PWM_GATE, val)
-#define bfin_read_PWM_CHA()            bfin_read16(PWM_CHA)
-#define bfin_write_PWM_CHA(val)        bfin_write16(PWM_CHA, val)
-#define bfin_read_PWM_CHB()            bfin_read16(PWM_CHB)
-#define bfin_write_PWM_CHB(val)        bfin_write16(PWM_CHB, val)
-#define bfin_read_PWM_CHC()            bfin_read16(PWM_CHC)
-#define bfin_write_PWM_CHC(val)        bfin_write16(PWM_CHC, val)
-#define bfin_read_PWM_SEG()            bfin_read16(PWM_SEG)
-#define bfin_write_PWM_SEG(val)        bfin_write16(PWM_SEG, val)
-#define bfin_read_PWM_SYNCWT()         bfin_read16(PWM_SYNCWT)
-#define bfin_write_PWM_SYNCWT(val)     bfin_write16(PWM_SYNCWT, val)
-#define bfin_read_PWM_CHAL()           bfin_read16(PWM_CHAL)
-#define bfin_write_PWM_CHAL(val)       bfin_write16(PWM_CHAL, val)
-#define bfin_read_PWM_CHBL()           bfin_read16(PWM_CHBL)
-#define bfin_write_PWM_CHBL(val)       bfin_write16(PWM_CHBL, val)
-#define bfin_read_PWM_CHCL()           bfin_read16(PWM_CHCL)
-#define bfin_write_PWM_CHCL(val)       bfin_write16(PWM_CHCL, val)
-#define bfin_read_PWM_LSI()            bfin_read16(PWM_LSI)
-#define bfin_write_PWM_LSI(val)        bfin_write16(PWM_LSI, val)
-#define bfin_read_PWM_STAT2()          bfin_read16(PWM_STAT2)
-#define bfin_write_PWM_STAT2(val)      bfin_write16(PWM_STAT2, val)
-#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF512_proc__ */

+ 0 - 517
arch/blackfin/include/asm/mach-bf518/BF512_def.h

@@ -1,517 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF512_proc__
-#define __BFIN_DEF_ADSP_BF512_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SIC_IMASK0                     0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0                       0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0                       0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1                     0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                       0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5                       0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6                       0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7                       0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1                       0xFFC00160 /* Interrupt Status register */
-#define SIC_IWR1                       0xFFC00164 /* Interrupt Wakeup register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define UART0_THR                      0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR                      0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER                      0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR                      0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL                     0xFFC00424 /* Global Control Register */
-#define SPI0_CTL                       0xFFC00500 /* SPI0 Control Register */
-#define SPI0_FLG                       0xFFC00504 /* SPI0 Flag register */
-#define SPI0_STAT                      0xFFC00508 /* SPI0 Status register */
-#define SPI0_TDBR                      0xFFC0050C /* SPI0 Transmit Data Buffer Register */
-#define SPI0_RDBR                      0xFFC00510 /* SPI0 Receive Data Buffer Register */
-#define SPI0_BAUD                      0xFFC00514 /* SPI0 Baud rate Register */
-#define SPI0_SHADOW                    0xFFC00518 /* SPI0_RDBR Shadow Register */
-#define SPI1_CTL                       0xFFC03400 /* SPI1 Control */
-#define SPI1_FLG                       0xFFC03404 /* SPI1 Flag Register */
-#define SPI1_STAT                      0xFFC03408 /* SPI1 Status Register */
-#define SPI1_TDBR                      0xFFC0340C /* SPI1 Transmit Data Buffer */
-#define SPI1_RDBR                      0xFFC03410 /* SPI1 Receive Data Buffer */
-#define SPI1_BAUD                      0xFFC03414 /* SPI1 Baud Rate */
-#define SPI1_SHADOW                    0xFFC03418 /* SPI1_RDBR Shadow Register */
-#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
-#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL                    0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                    0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDSTAT                    0xFFC00A1C /* SDRAM Status Register */
-#define EBIU_SDRRC                     0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_THR                      0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR                      0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER                      0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR                      0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL                     0xFFC02024 /* Global Control Register */
-#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define HMDMA0_CONTROL                 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT                  0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC03318 /* HMDMA0 Current Block Count Register */
-#define HMDMA1_CONTROL                 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC03358 /* HMDMA1 Current Block Count Register */
-#define PORTF_MUX                      0xFFC03210 /* Port F mux control */
-#define PORTG_MUX                      0xFFC03214 /* Port G mux control */
-#define PORTH_MUX                      0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE                    0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE                    0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE                    0xFFC03228 /* Port H drive strength control */
-#define PORTF_HYSTERESIS               0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS               0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS               0xFFC03248 /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE                  0xFFC03280 /* Non-GPIO Port drive strength control */
-#define NONGPIO_HYSTERESIS             0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
-#define CNT_CONFIG                     0xFFC03500 /* Configuration/Control Register */
-#define CNT_IMASK                      0xFFC03504 /* Interrupt Mask Register */
-#define CNT_STATUS                     0xFFC03508 /* Status Register */
-#define CNT_COMMAND                    0xFFC0350C /* Command Register */
-#define CNT_DEBOUNCE                   0xFFC03510 /* Debounce Prescaler Register */
-#define CNT_COUNTER                    0xFFC03514 /* Counter Register */
-#define CNT_MAX                        0xFFC03518 /* Maximal Count Boundary Value Register */
-#define CNT_MIN                        0xFFC0351C /* Minimal Count Boundary Value Register */
-#define SECURE_SYSSWT                  0xFFC03620 /* Secure System Switches */
-#define SECURE_CONTROL                 0xFFC03624 /* Secure Control */
-#define SECURE_STATUS                  0xFFC03628 /* Secure Status */
-#define OTP_DATA0                      0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1                      0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2                      0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3                      0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define PWM_CTRL                       0xFFC03700 /* PWM Control Register */
-#define PWM_STAT                       0xFFC03704 /* PWM Status Register */
-#define PWM_TM                         0xFFC03708 /* PWM Period Register */
-#define PWM_DT                         0xFFC0370C /* PWM Dead Time Register */
-#define PWM_GATE                       0xFFC03710 /* PWM Chopping Control */
-#define PWM_CHA                        0xFFC03714 /* PWM Channel A Duty Control */
-#define PWM_CHB                        0xFFC03718 /* PWM Channel B Duty Control */
-#define PWM_CHC                        0xFFC0371C /* PWM Channel C Duty Control */
-#define PWM_SEG                        0xFFC03720 /* PWM Crossover and Output Enable */
-#define PWM_SYNCWT                     0xFFC03724 /* PWM Sync pulse width control */
-#define PWM_CHAL                       0xFFC03728 /* PWM Channel AL Duty Control (SR mode only) */
-#define PWM_CHBL                       0xFFC0372C /* PWM Channel BL Duty Control (SR mode only) */
-#define PWM_CHCL                       0xFFC03730 /* PWM Channel CL Duty Control (SR mode only) */
-#define PWM_LSI                        0xFFC03734 /* Low Side Invert (SR mode only) */
-#define PWM_STAT2                      0xFFC03738 /* PWM Status Register */
-#define DMA_TC_CNT                     0xFFC00B0C
-#define DMA_TC_PER                     0xFFC00B10
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF512_proc__ */

+ 0 - 68
arch/blackfin/include/asm/mach-bf518/BF514_cdef.h

@@ -1,68 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF514_proc__
-#define __BFIN_CDEF_ADSP_BF514_proc__
-
-#include "BF512_cdef.h"
-
-#define bfin_read_RSI_PWR_CONTROL()    bfin_read16(RSI_PWR_CONTROL)
-#define bfin_write_RSI_PWR_CONTROL(val) bfin_write16(RSI_PWR_CONTROL, val)
-#define bfin_read_RSI_CLK_CONTROL()    bfin_read16(RSI_CLK_CONTROL)
-#define bfin_write_RSI_CLK_CONTROL(val) bfin_write16(RSI_CLK_CONTROL, val)
-#define bfin_read_RSI_ARGUMENT()       bfin_read32(RSI_ARGUMENT)
-#define bfin_write_RSI_ARGUMENT(val)   bfin_write32(RSI_ARGUMENT, val)
-#define bfin_read_RSI_COMMAND()        bfin_read16(RSI_COMMAND)
-#define bfin_write_RSI_COMMAND(val)    bfin_write16(RSI_COMMAND, val)
-#define bfin_read_RSI_RESP_CMD()       bfin_read16(RSI_RESP_CMD)
-#define bfin_write_RSI_RESP_CMD(val)   bfin_write16(RSI_RESP_CMD, val)
-#define bfin_read_RSI_RESPONSE0()      bfin_read32(RSI_RESPONSE0)
-#define bfin_write_RSI_RESPONSE0(val)  bfin_write32(RSI_RESPONSE0, val)
-#define bfin_read_RSI_RESPONSE1()      bfin_read32(RSI_RESPONSE1)
-#define bfin_write_RSI_RESPONSE1(val)  bfin_write32(RSI_RESPONSE1, val)
-#define bfin_read_RSI_RESPONSE2()      bfin_read32(RSI_RESPONSE2)
-#define bfin_write_RSI_RESPONSE2(val)  bfin_write32(RSI_RESPONSE2, val)
-#define bfin_read_RSI_RESPONSE3()      bfin_read32(RSI_RESPONSE3)
-#define bfin_write_RSI_RESPONSE3(val)  bfin_write32(RSI_RESPONSE3, val)
-#define bfin_read_RSI_DATA_TIMER()     bfin_read32(RSI_DATA_TIMER)
-#define bfin_write_RSI_DATA_TIMER(val) bfin_write32(RSI_DATA_TIMER, val)
-#define bfin_read_RSI_DATA_LGTH()      bfin_read16(RSI_DATA_LGTH)
-#define bfin_write_RSI_DATA_LGTH(val)  bfin_write16(RSI_DATA_LGTH, val)
-#define bfin_read_RSI_DATA_CONTROL()   bfin_read16(RSI_DATA_CONTROL)
-#define bfin_write_RSI_DATA_CONTROL(val) bfin_write16(RSI_DATA_CONTROL, val)
-#define bfin_read_RSI_DATA_CNT()       bfin_read16(RSI_DATA_CNT)
-#define bfin_write_RSI_DATA_CNT(val)   bfin_write16(RSI_DATA_CNT, val)
-#define bfin_read_RSI_STATUS()         bfin_read32(RSI_STATUS)
-#define bfin_write_RSI_STATUS(val)     bfin_write32(RSI_STATUS, val)
-#define bfin_read_RSI_STATUSCL()       bfin_read16(RSI_STATUSCL)
-#define bfin_write_RSI_STATUSCL(val)   bfin_write16(RSI_STATUSCL, val)
-#define bfin_read_RSI_MASK0()          bfin_read32(RSI_MASK0)
-#define bfin_write_RSI_MASK0(val)      bfin_write32(RSI_MASK0, val)
-#define bfin_read_RSI_MASK1()          bfin_read32(RSI_MASK1)
-#define bfin_write_RSI_MASK1(val)      bfin_write32(RSI_MASK1, val)
-#define bfin_read_RSI_FIFO_CNT()       bfin_read16(RSI_FIFO_CNT)
-#define bfin_write_RSI_FIFO_CNT(val)   bfin_write16(RSI_FIFO_CNT, val)
-#define bfin_read_RSI_CEATA_CONTROL()  bfin_read16(RSI_CEATA_CONTROL)
-#define bfin_write_RSI_CEATA_CONTROL(val) bfin_write16(RSI_CEATA_CONTROL, val)
-#define bfin_read_RSI_FIFO()           bfin_read32(RSI_FIFO)
-#define bfin_write_RSI_FIFO(val)       bfin_write32(RSI_FIFO, val)
-#define bfin_read_RSI_ESTAT()          bfin_read16(RSI_ESTAT)
-#define bfin_write_RSI_ESTAT(val)      bfin_write16(RSI_ESTAT, val)
-#define bfin_read_RSI_EMASK()          bfin_read16(RSI_EMASK)
-#define bfin_write_RSI_EMASK(val)      bfin_write16(RSI_EMASK, val)
-#define bfin_read_RSI_CONFIG()         bfin_read16(RSI_CONFIG)
-#define bfin_write_RSI_CONFIG(val)     bfin_write16(RSI_CONFIG, val)
-#define bfin_read_RSI_RD_WAIT_EN()     bfin_read16(RSI_RD_WAIT_EN)
-#define bfin_write_RSI_RD_WAIT_EN(val) bfin_write16(RSI_RD_WAIT_EN, val)
-#define bfin_read_RSI_PID0()           bfin_read16(RSI_PID0)
-#define bfin_write_RSI_PID0(val)       bfin_write16(RSI_PID0, val)
-#define bfin_read_RSI_PID1()           bfin_read16(RSI_PID1)
-#define bfin_write_RSI_PID1(val)       bfin_write16(RSI_PID1, val)
-#define bfin_read_RSI_PID2()           bfin_read16(RSI_PID2)
-#define bfin_write_RSI_PID2(val)       bfin_write16(RSI_PID2, val)
-#define bfin_read_RSI_PID3()           bfin_read16(RSI_PID3)
-#define bfin_write_RSI_PID3(val)       bfin_write16(RSI_PID3, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF514_proc__ */

+ 0 - 40
arch/blackfin/include/asm/mach-bf518/BF514_def.h

@@ -1,40 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF514_proc__
-#define __BFIN_DEF_ADSP_BF514_proc__
-
-#include "BF512_def.h"
-
-#define RSI_PWR_CONTROL                0xFFC03800 /* RSI Power Control Register */
-#define RSI_CLK_CONTROL                0xFFC03804 /* RSI Clock Control Register */
-#define RSI_ARGUMENT                   0xFFC03808 /* RSI Argument Register */
-#define RSI_COMMAND                    0xFFC0380C /* RSI Command Register */
-#define RSI_RESP_CMD                   0xFFC03810 /* RSI Response Command Register */
-#define RSI_RESPONSE0                  0xFFC03814 /* RSI Response Register */
-#define RSI_RESPONSE1                  0xFFC03818 /* RSI Response Register */
-#define RSI_RESPONSE2                  0xFFC0381C /* RSI Response Register */
-#define RSI_RESPONSE3                  0xFFC03820 /* RSI Response Register */
-#define RSI_DATA_TIMER                 0xFFC03824 /* RSI Data Timer Register */
-#define RSI_DATA_LGTH                  0xFFC03828 /* RSI Data Length Register */
-#define RSI_DATA_CONTROL               0xFFC0382C /* RSI Data Control Register */
-#define RSI_DATA_CNT                   0xFFC03830 /* RSI Data Counter Register */
-#define RSI_STATUS                     0xFFC03834 /* RSI Status Register */
-#define RSI_STATUSCL                   0xFFC03838 /* RSI Status Clear Register */
-#define RSI_MASK0                      0xFFC0383C /* RSI Interrupt 0 Mask Register */
-#define RSI_MASK1                      0xFFC03840 /* RSI Interrupt 1 Mask Register */
-#define RSI_FIFO_CNT                   0xFFC03848 /* RSI FIFO Counter Register */
-#define RSI_CEATA_CONTROL              0xFFC0384C /* RSI CEATA Register */
-#define RSI_FIFO                       0xFFC03880 /* RSI Data FIFO Register */
-#define RSI_ESTAT                      0xFFC038C0 /* RSI Exception Status Register */
-#define RSI_EMASK                      0xFFC038C4 /* RSI Exception Mask Register */
-#define RSI_CONFIG                     0xFFC038C8 /* RSI Configuration Register */
-#define RSI_RD_WAIT_EN                 0xFFC038CC /* RSI Read Wait Enable Register */
-#define RSI_PID0                       0xFFC038D0 /* RSI Peripheral ID Register 0 */
-#define RSI_PID1                       0xFFC038D4 /* RSI Peripheral ID Register 1 */
-#define RSI_PID2                       0xFFC038D8 /* RSI Peripheral ID Register 2 */
-#define RSI_PID3                       0xFFC038DC /* RSI Peripheral ID Register 3 */
-
-#endif /* __BFIN_DEF_ADSP_BF514_proc__ */

+ 0 - 170
arch/blackfin/include/asm/mach-bf518/BF516_cdef.h

@@ -1,170 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF516_proc__
-#define __BFIN_CDEF_ADSP_BF516_proc__
-
-#include "BF514_cdef.h"
-
-#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF516_proc__ */

+ 0 - 91
arch/blackfin/include/asm/mach-bf518/BF516_def.h

@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF516_proc__
-#define __BFIN_DEF_ADSP_BF516_proc__
-
-#include "BF514_def.h"
-
-#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
-#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-#endif /* __BFIN_DEF_ADSP_BF516_proc__ */

+ 0 - 58
arch/blackfin/include/asm/mach-bf518/BF518_cdef.h

@@ -1,58 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF518_proc__
-#define __BFIN_CDEF_ADSP_BF518_proc__
-
-#include "BF516_cdef.h"
-
-#define bfin_read_EMAC_PTP_CTL()       bfin_read16(EMAC_PTP_CTL)
-#define bfin_write_EMAC_PTP_CTL(val)   bfin_write16(EMAC_PTP_CTL, val)
-#define bfin_read_EMAC_PTP_IE()        bfin_read16(EMAC_PTP_IE)
-#define bfin_write_EMAC_PTP_IE(val)    bfin_write16(EMAC_PTP_IE, val)
-#define bfin_read_EMAC_PTP_ISTAT()     bfin_read16(EMAC_PTP_ISTAT)
-#define bfin_write_EMAC_PTP_ISTAT(val) bfin_write16(EMAC_PTP_ISTAT, val)
-#define bfin_read_EMAC_PTP_FOFF()      bfin_read32(EMAC_PTP_FOFF)
-#define bfin_write_EMAC_PTP_FOFF(val)  bfin_write32(EMAC_PTP_FOFF, val)
-#define bfin_read_EMAC_PTP_FV1()       bfin_read32(EMAC_PTP_FV1)
-#define bfin_write_EMAC_PTP_FV1(val)   bfin_write32(EMAC_PTP_FV1, val)
-#define bfin_read_EMAC_PTP_FV2()       bfin_read32(EMAC_PTP_FV2)
-#define bfin_write_EMAC_PTP_FV2(val)   bfin_write32(EMAC_PTP_FV2, val)
-#define bfin_read_EMAC_PTP_FV3()       bfin_read32(EMAC_PTP_FV3)
-#define bfin_write_EMAC_PTP_FV3(val)   bfin_write32(EMAC_PTP_FV3, val)
-#define bfin_read_EMAC_PTP_ADDEND()    bfin_read32(EMAC_PTP_ADDEND)
-#define bfin_write_EMAC_PTP_ADDEND(val) bfin_write32(EMAC_PTP_ADDEND, val)
-#define bfin_read_EMAC_PTP_ACCR()      bfin_read32(EMAC_PTP_ACCR)
-#define bfin_write_EMAC_PTP_ACCR(val)  bfin_write32(EMAC_PTP_ACCR, val)
-#define bfin_read_EMAC_PTP_OFFSET()    bfin_read32(EMAC_PTP_OFFSET)
-#define bfin_write_EMAC_PTP_OFFSET(val) bfin_write32(EMAC_PTP_OFFSET, val)
-#define bfin_read_EMAC_PTP_TIMELO()    bfin_read32(EMAC_PTP_TIMELO)
-#define bfin_write_EMAC_PTP_TIMELO(val) bfin_write32(EMAC_PTP_TIMELO, val)
-#define bfin_read_EMAC_PTP_TIMEHI()    bfin_read32(EMAC_PTP_TIMEHI)
-#define bfin_write_EMAC_PTP_TIMEHI(val) bfin_write32(EMAC_PTP_TIMEHI, val)
-#define bfin_read_EMAC_PTP_RXSNAPLO()  bfin_read32(EMAC_PTP_RXSNAPLO)
-#define bfin_write_EMAC_PTP_RXSNAPLO(val) bfin_write32(EMAC_PTP_RXSNAPLO, val)
-#define bfin_read_EMAC_PTP_RXSNAPHI()  bfin_read32(EMAC_PTP_RXSNAPHI)
-#define bfin_write_EMAC_PTP_RXSNAPHI(val) bfin_write32(EMAC_PTP_RXSNAPHI, val)
-#define bfin_read_EMAC_PTP_TXSNAPLO()  bfin_read32(EMAC_PTP_TXSNAPLO)
-#define bfin_write_EMAC_PTP_TXSNAPLO(val) bfin_write32(EMAC_PTP_TXSNAPLO, val)
-#define bfin_read_EMAC_PTP_TXSNAPHI()  bfin_read32(EMAC_PTP_TXSNAPHI)
-#define bfin_write_EMAC_PTP_TXSNAPHI(val) bfin_write32(EMAC_PTP_TXSNAPHI, val)
-#define bfin_read_EMAC_PTP_ALARMLO()   bfin_read32(EMAC_PTP_ALARMLO)
-#define bfin_write_EMAC_PTP_ALARMLO(val) bfin_write32(EMAC_PTP_ALARMLO, val)
-#define bfin_read_EMAC_PTP_ALARMHI()   bfin_read32(EMAC_PTP_ALARMHI)
-#define bfin_write_EMAC_PTP_ALARMHI(val) bfin_write32(EMAC_PTP_ALARMHI, val)
-#define bfin_read_EMAC_PTP_ID_OFF()    bfin_read16(EMAC_PTP_ID_OFF)
-#define bfin_write_EMAC_PTP_ID_OFF(val) bfin_write16(EMAC_PTP_ID_OFF, val)
-#define bfin_read_EMAC_PTP_ID_SNAP()   bfin_read32(EMAC_PTP_ID_SNAP)
-#define bfin_write_EMAC_PTP_ID_SNAP(val) bfin_write32(EMAC_PTP_ID_SNAP, val)
-#define bfin_read_EMAC_PTP_PPS_STARTLO() bfin_read32(EMAC_PTP_PPS_STARTLO)
-#define bfin_write_EMAC_PTP_PPS_STARTLO(val) bfin_write32(EMAC_PTP_PPS_STARTLO, val)
-#define bfin_read_EMAC_PTP_PPS_STARTHI() bfin_read32(EMAC_PTP_PPS_STARTHI)
-#define bfin_write_EMAC_PTP_PPS_STARTHI(val) bfin_write32(EMAC_PTP_PPS_STARTHI, val)
-#define bfin_read_EMAC_PTP_PPS_PERIOD() bfin_read32(EMAC_PTP_PPS_PERIOD)
-#define bfin_write_EMAC_PTP_PPS_PERIOD(val) bfin_write32(EMAC_PTP_PPS_PERIOD, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF518_proc__ */

+ 0 - 35
arch/blackfin/include/asm/mach-bf518/BF518_def.h

@@ -1,35 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF518_proc__
-#define __BFIN_DEF_ADSP_BF518_proc__
-
-#include "BF516_def.h"
-
-#define EMAC_PTP_CTL                   0xFFC030A0 /* PTP Block Control */
-#define EMAC_PTP_IE                    0xFFC030A4 /* PTP Block Interrupt Enable */
-#define EMAC_PTP_ISTAT                 0xFFC030A8 /* PTP Block Interrupt Status */
-#define EMAC_PTP_FOFF                  0xFFC030AC /* PTP Filter offset Register */
-#define EMAC_PTP_FV1                   0xFFC030B0 /* PTP Filter Value Register 1 */
-#define EMAC_PTP_FV2                   0xFFC030B4 /* PTP Filter Value Register 2 */
-#define EMAC_PTP_FV3                   0xFFC030B8 /* PTP Filter Value Register 3 */
-#define EMAC_PTP_ADDEND                0xFFC030BC /* PTP Addend for Frequency Compensation */
-#define EMAC_PTP_ACCR                  0xFFC030C0 /* PTP Accumulator for Frequency Compensation */
-#define EMAC_PTP_OFFSET                0xFFC030C4 /* PTP Time Offset Register */
-#define EMAC_PTP_TIMELO                0xFFC030C8 /* PTP Precision Clock Time Low */
-#define EMAC_PTP_TIMEHI                0xFFC030CC /* PTP Precision Clock Time High */
-#define EMAC_PTP_RXSNAPLO              0xFFC030D0 /* PTP Receive Snapshot Register Low */
-#define EMAC_PTP_RXSNAPHI              0xFFC030D4 /* PTP Receive Snapshot Register High */
-#define EMAC_PTP_TXSNAPLO              0xFFC030D8 /* PTP Transmit Snapshot Register Low */
-#define EMAC_PTP_TXSNAPHI              0xFFC030DC /* PTP Transmit Snapshot Register High */
-#define EMAC_PTP_ALARMLO               0xFFC030E0 /* PTP Alarm time Low */
-#define EMAC_PTP_ALARMHI               0xFFC030E4 /* PTP Alarm time High */
-#define EMAC_PTP_ID_OFF                0xFFC030E8 /* PTP Capture ID offset register */
-#define EMAC_PTP_ID_SNAP               0xFFC030EC /* PTP Capture ID register */
-#define EMAC_PTP_PPS_STARTLO           0xFFC030F0 /* PPS Start Time Low */
-#define EMAC_PTP_PPS_STARTHI           0xFFC030F4 /* PPS Start Time High */
-#define EMAC_PTP_PPS_PERIOD            0xFFC030F8 /* PPS Count Register */
-
-#endif /* __BFIN_DEF_ADSP_BF518_proc__ */

+ 0 - 170
arch/blackfin/include/asm/mach-bf518/anomaly.h

@@ -1,170 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
- */
-
-#if __SILICON_REVISION__ < 0
-# error will not work on BF518 silicon version
-#endif
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
-/* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
-#define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* Incorrect L1 Instruction Bank B Memory Map Location */
-#define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
-/* PWM_TRIPB Signal Not Available on PG10 */
-#define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
-/* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
-#define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (0)
-#define ANOMALY_05000357 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000371 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (0)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000475 (0)
-#define ANOMALY_05000480 (0)
-
-#endif

+ 0 - 5
arch/blackfin/include/asm/mach-bf518/def_local.h

@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF51x 1	/* Linux glue */

+ 0 - 58
arch/blackfin/include/asm/mach-bf518/gpio.h

@@ -1,58 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 41
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-#define GPIO_PG0	16
-#define GPIO_PG1	17
-#define GPIO_PG2	18
-#define GPIO_PG3	19
-#define GPIO_PG4	20
-#define GPIO_PG5	21
-#define GPIO_PG6	22
-#define GPIO_PG7	23
-#define GPIO_PG8	24
-#define GPIO_PG9	25
-#define GPIO_PG10	26
-#define GPIO_PG11	27
-#define GPIO_PG12	28
-#define GPIO_PG13	29
-#define GPIO_PG14	30
-#define GPIO_PG15	31
-#define GPIO_PH0	32
-#define GPIO_PH1	33
-#define GPIO_PH2	34
-#define GPIO_PH3	35
-#define GPIO_PH4	36
-#define GPIO_PH5	37
-#define GPIO_PH6	38
-#define GPIO_PH7	39
-#define GPIO_PH8	40
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */

+ 0 - 201
arch/blackfin/include/asm/mach-bf518/portmux.h

@@ -1,201 +0,0 @@
-/*
- * Copyright 2008-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-/* EMAC MII/RMII Port Mux */
-#define P_MII0_ETxD2	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_MII0_ERxD2	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_MII0_ETxD3	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_MII0_ERxD3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_MII0_ERxCLK	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_MII0_ERxDV	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_MII0_COL	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-
-#define P_MII0_MDC	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_MII0_MDIO	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(0))
-#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(0))
-
-#define P_MII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxD2, \
-	P_MII0_ETxD3, \
-	P_MII0_ETxEN, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_COL, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxD2, \
-	P_MII0_ERxD3, \
-	P_MII0_ERxDV, \
-	P_MII0_ERxCLK, \
-	P_MII0_ERxER, \
-	P_MII0_CRS, \
-	P_MII0_MDC, \
-	P_MII0_MDIO, 0}
-
-#define P_RMII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxEN, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxER, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_CRS, \
-	P_MII0_MDC, \
-	P_MII0_MDIO, 0}
-
-/* PPI Port Mux */
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_PPI0_CLK	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_PPI0_FS1	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-/* SPI Port Mux */
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0))
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-
-#define P_SPI1_SS	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_SPI1_SCK	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_SPI1_MISO	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-#define P_SPI1_MOSI	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-
-#define P_SPI1_SSEL1	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_SPI1_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_SPI1_SSEL3	(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(2))
-#define P_SPI1_SSEL4	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(2))
-#define P_SPI1_SSEL5	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG15
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-/* SPORT Port Mux */
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(0))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(0))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-
-#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-
-/* UART Port Mux */
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-
-/* Timer */
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(2))
-#define P_TMR0		(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(2))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-
-/* DMA */
-#define P_DMAR1		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(1))
-#define P_DMAR0		(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(1))
-
-/* TWI */
-#define P_TWI0_SCL	(P_DONTCARE)
-#define P_TWI0_SDA	(P_DONTCARE)
-
-/* PWM */
-#define P_PWM0_AH		(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_PWM0_AL		(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_PWM0_BH		(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_PWM0_BL		(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_PWM0_CH		(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_PWM0_CL		(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_PWM0_SYNC		(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-
-#define P_PWM1_AH		(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(2))
-#define P_PWM1_AL		(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_PWM1_BH		(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-#define P_PWM1_BL		(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_PWM1_CH		(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_PWM1_CL		(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_PWM1_SYNC		(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-
-#define P_PWM_TRIPB		(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-
-/* RSI */
-#define P_RSI_DATA0		(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_RSI_DATA1		(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_RSI_DATA2		(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(1))
-#define P_RSI_DATA3		(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_RSI_DATA4		(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_RSI_DATA5		(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_RSI_DATA6		(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_RSI_DATA7		(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_RSI_CMD		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_RSI_CLK		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-
-/* PTP */
-#define P_PTP_PPS		(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_PTP_CLKOUT		(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-
-/* AMS */
-#define P_AMS2			(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_AMS3			(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#define P_HWAIT			(P_DEFINED | P_IDENT(GPIO_PG0) | P_FUNCT(1))
-
-#endif				/* _MACH_PORTMUX_H_ */

+ 0 - 59
arch/blackfin/include/asm/mach-bf518/ports.h

@@ -1,59 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK	0x0003
-#define PORT_x_MUX_1_MASK	0x000C
-#define PORT_x_MUX_2_MASK	0x0030
-#define PORT_x_MUX_3_MASK	0x00C0
-#define PORT_x_MUX_4_MASK	0x0300
-#define PORT_x_MUX_5_MASK	0x0C00
-#define PORT_x_MUX_6_MASK	0x3000
-#define PORT_x_MUX_7_MASK	0xC000
-
-#define PORT_x_MUX_FUNC_1	(0x0)
-#define PORT_x_MUX_FUNC_2	(0x1)
-#define PORT_x_MUX_FUNC_3	(0x2)
-#define PORT_x_MUX_FUNC_4	(0x3)
-#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-
-#endif

+ 0 - 1012
arch/blackfin/include/asm/mach-bf527/BF522_cdef.h

@@ -1,1012 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF522_proc__
-#define __BFIN_CDEF_ADSP_BF522_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK0()         bfin_read32(SIC_IMASK0)
-#define bfin_write_SIC_IMASK0(val)     bfin_write32(SIC_IMASK0, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR0()           bfin_read32(SIC_ISR0)
-#define bfin_write_SIC_ISR0(val)       bfin_write32(SIC_ISR0, val)
-#define bfin_read_SIC_IWR0()           bfin_read32(SIC_IWR0)
-#define bfin_write_SIC_IWR0(val)       bfin_write32(SIC_IWR0, val)
-#define bfin_read_SIC_IMASK1()         bfin_read32(SIC_IMASK1)
-#define bfin_write_SIC_IMASK1(val)     bfin_write32(SIC_IMASK1, val)
-#define bfin_read_SIC_IAR4()           bfin_read32(SIC_IAR4)
-#define bfin_write_SIC_IAR4(val)       bfin_write32(SIC_IAR4, val)
-#define bfin_read_SIC_IAR5()           bfin_read32(SIC_IAR5)
-#define bfin_write_SIC_IAR5(val)       bfin_write32(SIC_IAR5, val)
-#define bfin_read_SIC_IAR6()           bfin_read32(SIC_IAR6)
-#define bfin_write_SIC_IAR6(val)       bfin_write32(SIC_IAR6, val)
-#define bfin_read_SIC_IAR7()           bfin_read32(SIC_IAR7)
-#define bfin_write_SIC_IAR7(val)       bfin_write32(SIC_IAR7, val)
-#define bfin_read_SIC_ISR1()           bfin_read32(SIC_ISR1)
-#define bfin_write_SIC_ISR1(val)       bfin_write32(SIC_ISR1, val)
-#define bfin_read_SIC_IWR1()           bfin_read32(SIC_IWR1)
-#define bfin_write_SIC_IWR1(val)       bfin_write32(SIC_IWR1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_PORTF_MUX()          bfin_read16(PORTF_MUX)
-#define bfin_write_PORTF_MUX(val)      bfin_write16(PORTF_MUX, val)
-#define bfin_read_PORTG_MUX()          bfin_read16(PORTG_MUX)
-#define bfin_write_PORTG_MUX(val)      bfin_write16(PORTG_MUX, val)
-#define bfin_read_PORTH_MUX()          bfin_read16(PORTH_MUX)
-#define bfin_write_PORTH_MUX(val)      bfin_write16(PORTH_MUX, val)
-#define bfin_read_PORTF_DRIVE()        bfin_read16(PORTF_DRIVE)
-#define bfin_write_PORTF_DRIVE(val)    bfin_write16(PORTF_DRIVE, val)
-#define bfin_read_PORTG_DRIVE()        bfin_read16(PORTG_DRIVE)
-#define bfin_write_PORTG_DRIVE(val)    bfin_write16(PORTG_DRIVE, val)
-#define bfin_read_PORTH_DRIVE()        bfin_read16(PORTH_DRIVE)
-#define bfin_write_PORTH_DRIVE(val)    bfin_write16(PORTH_DRIVE, val)
-#define bfin_read_PORTF_SLEW()         bfin_read16(PORTF_SLEW)
-#define bfin_write_PORTF_SLEW(val)     bfin_write16(PORTF_SLEW, val)
-#define bfin_read_PORTG_SLEW()         bfin_read16(PORTG_SLEW)
-#define bfin_write_PORTG_SLEW(val)     bfin_write16(PORTG_SLEW, val)
-#define bfin_read_PORTH_SLEW()         bfin_read16(PORTH_SLEW)
-#define bfin_write_PORTH_SLEW(val)     bfin_write16(PORTH_SLEW, val)
-#define bfin_read_PORTF_HYSTERESIS()   bfin_read16(PORTF_HYSTERESIS)
-#define bfin_write_PORTF_HYSTERESIS(val) bfin_write16(PORTF_HYSTERESIS, val)
-#define bfin_read_PORTG_HYSTERESIS()   bfin_read16(PORTG_HYSTERESIS)
-#define bfin_write_PORTG_HYSTERESIS(val) bfin_write16(PORTG_HYSTERESIS, val)
-#define bfin_read_PORTH_HYSTERESIS()   bfin_read16(PORTH_HYSTERESIS)
-#define bfin_write_PORTH_HYSTERESIS(val) bfin_write16(PORTH_HYSTERESIS, val)
-#define bfin_read_NONGPIO_DRIVE()      bfin_read16(NONGPIO_DRIVE)
-#define bfin_write_NONGPIO_DRIVE(val)  bfin_write16(NONGPIO_DRIVE, val)
-#define bfin_read_NONGPIO_SLEW()       bfin_read16(NONGPIO_SLEW)
-#define bfin_write_NONGPIO_SLEW(val)   bfin_write16(NONGPIO_SLEW, val)
-#define bfin_read_NONGPIO_HYSTERESIS() bfin_read16(NONGPIO_HYSTERESIS)
-#define bfin_write_NONGPIO_HYSTERESIS(val) bfin_write16(NONGPIO_HYSTERESIS, val)
-#define bfin_read_HOST_CONTROL()       bfin_read16(HOST_CONTROL)
-#define bfin_write_HOST_CONTROL(val)   bfin_write16(HOST_CONTROL, val)
-#define bfin_read_HOST_STATUS()        bfin_read16(HOST_STATUS)
-#define bfin_write_HOST_STATUS(val)    bfin_write16(HOST_STATUS, val)
-#define bfin_read_HOST_TIMEOUT()       bfin_read16(HOST_TIMEOUT)
-#define bfin_write_HOST_TIMEOUT(val)   bfin_write16(HOST_TIMEOUT, val)
-#define bfin_read_CNT_CONFIG()         bfin_read16(CNT_CONFIG)
-#define bfin_write_CNT_CONFIG(val)     bfin_write16(CNT_CONFIG, val)
-#define bfin_read_CNT_IMASK()          bfin_read16(CNT_IMASK)
-#define bfin_write_CNT_IMASK(val)      bfin_write16(CNT_IMASK, val)
-#define bfin_read_CNT_STATUS()         bfin_read16(CNT_STATUS)
-#define bfin_write_CNT_STATUS(val)     bfin_write16(CNT_STATUS, val)
-#define bfin_read_CNT_COMMAND()        bfin_read16(CNT_COMMAND)
-#define bfin_write_CNT_COMMAND(val)    bfin_write16(CNT_COMMAND, val)
-#define bfin_read_CNT_DEBOUNCE()       bfin_read16(CNT_DEBOUNCE)
-#define bfin_write_CNT_DEBOUNCE(val)   bfin_write16(CNT_DEBOUNCE, val)
-#define bfin_read_CNT_COUNTER()        bfin_read32(CNT_COUNTER)
-#define bfin_write_CNT_COUNTER(val)    bfin_write32(CNT_COUNTER, val)
-#define bfin_read_CNT_MAX()            bfin_read32(CNT_MAX)
-#define bfin_write_CNT_MAX(val)        bfin_write32(CNT_MAX, val)
-#define bfin_read_CNT_MIN()            bfin_read32(CNT_MIN)
-#define bfin_write_CNT_MIN(val)        bfin_write32(CNT_MIN, val)
-#define bfin_read_OTP_CONTROL()        bfin_read16(OTP_CONTROL)
-#define bfin_write_OTP_CONTROL(val)    bfin_write16(OTP_CONTROL, val)
-#define bfin_read_OTP_BEN()            bfin_read16(OTP_BEN)
-#define bfin_write_OTP_BEN(val)        bfin_write16(OTP_BEN, val)
-#define bfin_read_OTP_STATUS()         bfin_read16(OTP_STATUS)
-#define bfin_write_OTP_STATUS(val)     bfin_write16(OTP_STATUS, val)
-#define bfin_read_OTP_TIMING()         bfin_read32(OTP_TIMING)
-#define bfin_write_OTP_TIMING(val)     bfin_write32(OTP_TIMING, val)
-#define bfin_read_SECURE_SYSSWT()      bfin_read32(SECURE_SYSSWT)
-#define bfin_write_SECURE_SYSSWT(val)  bfin_write32(SECURE_SYSSWT, val)
-#define bfin_read_SECURE_CONTROL()     bfin_read16(SECURE_CONTROL)
-#define bfin_write_SECURE_CONTROL(val) bfin_write16(SECURE_CONTROL, val)
-#define bfin_read_SECURE_STATUS()      bfin_read16(SECURE_STATUS)
-#define bfin_write_SECURE_STATUS(val)  bfin_write16(SECURE_STATUS, val)
-#define bfin_read_OTP_DATA0()          bfin_read32(OTP_DATA0)
-#define bfin_write_OTP_DATA0(val)      bfin_write32(OTP_DATA0, val)
-#define bfin_read_OTP_DATA1()          bfin_read32(OTP_DATA1)
-#define bfin_write_OTP_DATA1(val)      bfin_write32(OTP_DATA1, val)
-#define bfin_read_OTP_DATA2()          bfin_read32(OTP_DATA2)
-#define bfin_write_OTP_DATA2(val)      bfin_write32(OTP_DATA2, val)
-#define bfin_read_OTP_DATA3()          bfin_read32(OTP_DATA3)
-#define bfin_write_OTP_DATA3(val)      bfin_write32(OTP_DATA3, val)
-#define bfin_read_NFC_CTL()            bfin_read16(NFC_CTL)
-#define bfin_write_NFC_CTL(val)        bfin_write16(NFC_CTL, val)
-#define bfin_read_NFC_STAT()           bfin_read16(NFC_STAT)
-#define bfin_write_NFC_STAT(val)       bfin_write16(NFC_STAT, val)
-#define bfin_read_NFC_IRQSTAT()        bfin_read16(NFC_IRQSTAT)
-#define bfin_write_NFC_IRQSTAT(val)    bfin_write16(NFC_IRQSTAT, val)
-#define bfin_read_NFC_IRQMASK()        bfin_read16(NFC_IRQMASK)
-#define bfin_write_NFC_IRQMASK(val)    bfin_write16(NFC_IRQMASK, val)
-#define bfin_read_NFC_ECC0()           bfin_read16(NFC_ECC0)
-#define bfin_write_NFC_ECC0(val)       bfin_write16(NFC_ECC0, val)
-#define bfin_read_NFC_ECC1()           bfin_read16(NFC_ECC1)
-#define bfin_write_NFC_ECC1(val)       bfin_write16(NFC_ECC1, val)
-#define bfin_read_NFC_ECC2()           bfin_read16(NFC_ECC2)
-#define bfin_write_NFC_ECC2(val)       bfin_write16(NFC_ECC2, val)
-#define bfin_read_NFC_ECC3()           bfin_read16(NFC_ECC3)
-#define bfin_write_NFC_ECC3(val)       bfin_write16(NFC_ECC3, val)
-#define bfin_read_NFC_COUNT()          bfin_read16(NFC_COUNT)
-#define bfin_write_NFC_COUNT(val)      bfin_write16(NFC_COUNT, val)
-#define bfin_read_NFC_RST()            bfin_read16(NFC_RST)
-#define bfin_write_NFC_RST(val)        bfin_write16(NFC_RST, val)
-#define bfin_read_NFC_PGCTL()          bfin_read16(NFC_PGCTL)
-#define bfin_write_NFC_PGCTL(val)      bfin_write16(NFC_PGCTL, val)
-#define bfin_read_NFC_READ()           bfin_read16(NFC_READ)
-#define bfin_write_NFC_READ(val)       bfin_write16(NFC_READ, val)
-#define bfin_read_NFC_ADDR()           bfin_read16(NFC_ADDR)
-#define bfin_write_NFC_ADDR(val)       bfin_write16(NFC_ADDR, val)
-#define bfin_read_NFC_CMD()            bfin_read16(NFC_CMD)
-#define bfin_write_NFC_CMD(val)        bfin_write16(NFC_CMD, val)
-#define bfin_read_NFC_DATA_WR()        bfin_read16(NFC_DATA_WR)
-#define bfin_write_NFC_DATA_WR(val)    bfin_write16(NFC_DATA_WR, val)
-#define bfin_read_NFC_DATA_RD()        bfin_read16(NFC_DATA_RD)
-#define bfin_write_NFC_DATA_RD(val)    bfin_write16(NFC_DATA_RD, val)
-#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF522_proc__ */

+ 0 - 513
arch/blackfin/include/asm/mach-bf527/BF522_def.h

@@ -1,513 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF522_proc__
-#define __BFIN_DEF_ADSP_BF522_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define PLL_CTL                        0xFFC00000 /* PLL Control Register */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register */
-#define PLL_STAT                       0xFFC0000C /* PLL Status Register */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count Register */
-#define CHIPID                         0xFFC00014
-#define SWRST                          0xFFC00100 /* Software Reset Register */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK0                     0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR0                       0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR0                       0xFFC00124 /* Interrupt Wakeup Register */
-#define SIC_IMASK1                     0xFFC0014C /* Interrupt Mask register of SIC2 */
-#define SIC_IAR4                       0xFFC00150 /* Interrupt Assignment register4 */
-#define SIC_IAR5                       0xFFC00154 /* Interrupt Assignment register5 */
-#define SIC_IAR6                       0xFFC00158 /* Interrupt Assignment register6 */
-#define SIC_IAR7                       0xFFC0015C /* Interrupt Assignment register7 */
-#define SIC_ISR1                       0xFFC00160 /* Interrupt Status register */
-#define SIC_IWR1                       0xFFC00164 /* Interrupt Wakeup register */
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT                       0xFFC00300 /* RTC Status Register */
-#define RTC_ICTL                       0xFFC00304 /* RTC Interrupt Control Register */
-#define RTC_ISTAT                      0xFFC00308 /* RTC Interrupt Status Register */
-#define RTC_SWCNT                      0xFFC0030C /* RTC Stopwatch Count Register */
-#define RTC_ALARM                      0xFFC00310 /* RTC Alarm Time Register */
-#define RTC_PREN                       0xFFC00314 /* RTC Prescaler Enable Register */
-#define UART0_THR                      0xFFC00400 /* Transmit Holding register */
-#define UART0_RBR                      0xFFC00400 /* Receive Buffer register */
-#define UART0_DLL                      0xFFC00400 /* Divisor Latch (Low-Byte) */
-#define UART0_IER                      0xFFC00404 /* Interrupt Enable Register */
-#define UART0_DLH                      0xFFC00404 /* Divisor Latch (High-Byte) */
-#define UART0_IIR                      0xFFC00408 /* Interrupt Identification Register */
-#define UART0_LCR                      0xFFC0040C /* Line Control Register */
-#define UART0_MCR                      0xFFC00410 /* Modem Control Register */
-#define UART0_LSR                      0xFFC00414 /* Line Status Register */
-#define UART0_MSR                      0xFFC00418 /* Modem Status Register */
-#define UART0_SCR                      0xFFC0041C /* SCR Scratch Register */
-#define UART0_GCTL                     0xFFC00424 /* Global Control Register */
-#define SPI_CTL                        0xFFC00500 /* SPI Control Register */
-#define SPI_FLG                        0xFFC00504 /* SPI Flag register */
-#define SPI_STAT                       0xFFC00508 /* SPI Status register */
-#define SPI_TDBR                       0xFFC0050C /* SPI Transmit Data Buffer Register */
-#define SPI_RDBR                       0xFFC00510 /* SPI Receive Data Buffer Register */
-#define SPI_BAUD                       0xFFC00514 /* SPI Baud rate Register */
-#define SPI_SHADOW                     0xFFC00518 /* SPI_RDBR Shadow Register */
-#define TIMER0_CONFIG                  0xFFC00600 /* Timer 0 Configuration Register */
-#define TIMER0_COUNTER                 0xFFC00604 /* Timer 0 Counter Register */
-#define TIMER0_PERIOD                  0xFFC00608 /* Timer 0 Period Register */
-#define TIMER0_WIDTH                   0xFFC0060C /* Timer 0 Width Register */
-#define TIMER1_CONFIG                  0xFFC00610 /* Timer 1 Configuration Register */
-#define TIMER1_COUNTER                 0xFFC00614 /* Timer 1 Counter Register */
-#define TIMER1_PERIOD                  0xFFC00618 /* Timer 1 Period Register */
-#define TIMER1_WIDTH                   0xFFC0061C /* Timer 1 Width Register */
-#define TIMER2_CONFIG                  0xFFC00620 /* Timer 2 Configuration Register */
-#define TIMER2_COUNTER                 0xFFC00624 /* Timer 2 Counter Register */
-#define TIMER2_PERIOD                  0xFFC00628 /* Timer 2 Period Register */
-#define TIMER2_WIDTH                   0xFFC0062C /* Timer 2 Width Register */
-#define TIMER3_CONFIG                  0xFFC00630 /* Timer 3 Configuration Register */
-#define TIMER3_COUNTER                 0xFFC00634 /* Timer 3 Counter Register */
-#define TIMER3_PERIOD                  0xFFC00638 /* Timer 3 Period Register */
-#define TIMER3_WIDTH                   0xFFC0063C /* Timer 3 Width Register */
-#define TIMER4_CONFIG                  0xFFC00640 /* Timer 4 Configuration Register */
-#define TIMER4_COUNTER                 0xFFC00644 /* Timer 4 Counter Register */
-#define TIMER4_PERIOD                  0xFFC00648 /* Timer 4 Period Register */
-#define TIMER4_WIDTH                   0xFFC0064C /* Timer 4 Width Register */
-#define TIMER5_CONFIG                  0xFFC00650 /* Timer 5 Configuration Register */
-#define TIMER5_COUNTER                 0xFFC00654 /* Timer 5 Counter Register */
-#define TIMER5_PERIOD                  0xFFC00658 /* Timer 5 Period Register */
-#define TIMER5_WIDTH                   0xFFC0065C /* Timer 5 Width Register */
-#define TIMER6_CONFIG                  0xFFC00660 /* Timer 6 Configuration Register */
-#define TIMER6_COUNTER                 0xFFC00664 /* Timer 6 Counter Register */
-#define TIMER6_PERIOD                  0xFFC00668 /* Timer 6 Period Register */
-#define TIMER6_WIDTH                   0xFFC0066C /* Timer 6 Width Register\n */
-#define TIMER7_CONFIG                  0xFFC00670 /* Timer 7 Configuration Register */
-#define TIMER7_COUNTER                 0xFFC00674 /* Timer 7 Counter Register */
-#define TIMER7_PERIOD                  0xFFC00678 /* Timer 7 Period Register */
-#define TIMER7_WIDTH                   0xFFC0067C /* Timer 7 Width Register */
-#define TIMER_ENABLE                   0xFFC00680 /* Timer Enable Register */
-#define TIMER_DISABLE                  0xFFC00684 /* Timer Disable Register */
-#define TIMER_STATUS                   0xFFC00688 /* Timer Status Register */
-#define PORTFIO                        0xFFC00700 /* Port F I/O Pin State Specify Register */
-#define PORTFIO_CLEAR                  0xFFC00704 /* Port F I/O Peripheral Interrupt Clear Register */
-#define PORTFIO_SET                    0xFFC00708 /* Port F I/O Peripheral Interrupt Set Register */
-#define PORTFIO_TOGGLE                 0xFFC0070C /* Port F I/O Pin State Toggle Register */
-#define PORTFIO_MASKA                  0xFFC00710 /* Port F I/O Mask State Specify Interrupt A Register */
-#define PORTFIO_MASKA_CLEAR            0xFFC00714 /* Port F I/O Mask Disable Interrupt A Register */
-#define PORTFIO_MASKA_SET              0xFFC00718 /* Port F I/O Mask Enable Interrupt A Register */
-#define PORTFIO_MASKA_TOGGLE           0xFFC0071C /* Port F I/O Mask Toggle Enable Interrupt A Register */
-#define PORTFIO_MASKB                  0xFFC00720 /* Port F I/O Mask State Specify Interrupt B Register */
-#define PORTFIO_MASKB_CLEAR            0xFFC00724 /* Port F I/O Mask Disable Interrupt B Register */
-#define PORTFIO_MASKB_SET              0xFFC00728 /* Port F I/O Mask Enable Interrupt B Register */
-#define PORTFIO_MASKB_TOGGLE           0xFFC0072C /* Port F I/O Mask Toggle Enable Interrupt B Register */
-#define PORTFIO_DIR                    0xFFC00730 /* Port F I/O Direction Register */
-#define PORTFIO_POLAR                  0xFFC00734 /* Port F I/O Source Polarity Register */
-#define PORTFIO_EDGE                   0xFFC00738 /* Port F I/O Source Sensitivity Register */
-#define PORTFIO_BOTH                   0xFFC0073C /* Port F I/O Set on BOTH Edges Register */
-#define PORTFIO_INEN                   0xFFC00740 /* Port F I/O Input Enable Register  */
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT0_MTCS0                   0xFFC00840 /* SPORT0 Multi-Channel Transmit Select Register 0 */
-#define SPORT0_MTCS1                   0xFFC00844 /* SPORT0 Multi-Channel Transmit Select Register 1 */
-#define SPORT0_MTCS2                   0xFFC00848 /* SPORT0 Multi-Channel Transmit Select Register 2 */
-#define SPORT0_MTCS3                   0xFFC0084C /* SPORT0 Multi-Channel Transmit Select Register 3 */
-#define SPORT0_MRCS0                   0xFFC00850 /* SPORT0 Multi-Channel Receive Select Register 0 */
-#define SPORT0_MRCS1                   0xFFC00854 /* SPORT0 Multi-Channel Receive Select Register 1 */
-#define SPORT0_MRCS2                   0xFFC00858 /* SPORT0 Multi-Channel Receive Select Register 2 */
-#define SPORT0_MRCS3                   0xFFC0085C /* SPORT0 Multi-Channel Receive Select Register 3 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define SPORT1_MTCS0                   0xFFC00940 /* SPORT1 Multi-Channel Transmit Select Register 0 */
-#define SPORT1_MTCS1                   0xFFC00944 /* SPORT1 Multi-Channel Transmit Select Register 1 */
-#define SPORT1_MTCS2                   0xFFC00948 /* SPORT1 Multi-Channel Transmit Select Register 2 */
-#define SPORT1_MTCS3                   0xFFC0094C /* SPORT1 Multi-Channel Transmit Select Register 3 */
-#define SPORT1_MRCS0                   0xFFC00950 /* SPORT1 Multi-Channel Receive Select Register 0 */
-#define SPORT1_MRCS1                   0xFFC00954 /* SPORT1 Multi-Channel Receive Select Register 1 */
-#define SPORT1_MRCS2                   0xFFC00958 /* SPORT1 Multi-Channel Receive Select Register 2 */
-#define SPORT1_MRCS3                   0xFFC0095C /* SPORT1 Multi-Channel Receive Select Register 3 */
-#define EBIU_AMGCTL                    0xFFC00A00 /* Asynchronous Memory Global Control Register */
-#define EBIU_AMBCTL0                   0xFFC00A04 /* Asynchronous Memory Bank Control Register 0 */
-#define EBIU_AMBCTL1                   0xFFC00A08 /* Asynchronous Memory Bank Control Register 1 */
-#define EBIU_SDGCTL                    0xFFC00A10 /* SDRAM Global Control Register */
-#define EBIU_SDBCTL                    0xFFC00A14 /* SDRAM Bank Control Register */
-#define EBIU_SDRRC                     0xFFC00A18 /* SDRAM Refresh Rate Control Register */
-#define EBIU_SDSTAT                    0xFFC00A1C /* SDRAM Status Register */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00 /* DMA Channel 0 Next Descriptor Pointer Register */
-#define DMA0_START_ADDR                0xFFC00C04 /* DMA Channel 0 Start Address Register */
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10 /* DMA Channel 0 X Count Register */
-#define DMA0_X_MODIFY                  0xFFC00C14 /* DMA Channel 0 X Modify Register */
-#define DMA0_Y_COUNT                   0xFFC00C18 /* DMA Channel 0 Y Count Register */
-#define DMA0_Y_MODIFY                  0xFFC00C1C /* DMA Channel 0 Y Modify Register */
-#define DMA0_CURR_DESC_PTR             0xFFC00C20 /* DMA Channel 0 Current Descriptor Pointer Register */
-#define DMA0_CURR_ADDR                 0xFFC00C24 /* DMA Channel 0 Current Address Register */
-#define DMA0_IRQ_STATUS                0xFFC00C28 /* DMA Channel 0 Interrupt/Status Register */
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C /* DMA Channel 0 Peripheral Map Register */
-#define DMA0_CURR_X_COUNT              0xFFC00C30 /* DMA Channel 0 Current X Count Register */
-#define DMA0_CURR_Y_COUNT              0xFFC00C38 /* DMA Channel 0 Current Y Count Register */
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40 /* DMA Channel 1 Next Descriptor Pointer Register */
-#define DMA1_START_ADDR                0xFFC00C44 /* DMA Channel 1 Start Address Register */
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50 /* DMA Channel 1 X Count Register */
-#define DMA1_X_MODIFY                  0xFFC00C54 /* DMA Channel 1 X Modify Register */
-#define DMA1_Y_COUNT                   0xFFC00C58 /* DMA Channel 1 Y Count Register */
-#define DMA1_Y_MODIFY                  0xFFC00C5C /* DMA Channel 1 Y Modify Register */
-#define DMA1_CURR_DESC_PTR             0xFFC00C60 /* DMA Channel 1 Current Descriptor Pointer Register */
-#define DMA1_CURR_ADDR                 0xFFC00C64 /* DMA Channel 1 Current Address Register */
-#define DMA1_IRQ_STATUS                0xFFC00C68 /* DMA Channel 1 Interrupt/Status Register */
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C /* DMA Channel 1 Peripheral Map Register */
-#define DMA1_CURR_X_COUNT              0xFFC00C70 /* DMA Channel 1 Current X Count Register */
-#define DMA1_CURR_Y_COUNT              0xFFC00C78 /* DMA Channel 1 Current Y Count Register */
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80 /* DMA Channel 2 Next Descriptor Pointer Register */
-#define DMA2_START_ADDR                0xFFC00C84 /* DMA Channel 2 Start Address Register */
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90 /* DMA Channel 2 X Count Register */
-#define DMA2_X_MODIFY                  0xFFC00C94 /* DMA Channel 2 X Modify Register */
-#define DMA2_Y_COUNT                   0xFFC00C98 /* DMA Channel 2 Y Count Register */
-#define DMA2_Y_MODIFY                  0xFFC00C9C /* DMA Channel 2 Y Modify Register */
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0 /* DMA Channel 2 Current Descriptor Pointer Register */
-#define DMA2_CURR_ADDR                 0xFFC00CA4 /* DMA Channel 2 Current Address Register */
-#define DMA2_IRQ_STATUS                0xFFC00CA8 /* DMA Channel 2 Interrupt/Status Register */
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC /* DMA Channel 2 Peripheral Map Register */
-#define DMA2_CURR_X_COUNT              0xFFC00CB0 /* DMA Channel 2 Current X Count Register */
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8 /* DMA Channel 2 Current Y Count Register */
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0 /* DMA Channel 3 Next Descriptor Pointer Register */
-#define DMA3_START_ADDR                0xFFC00CC4 /* DMA Channel 3 Start Address Register */
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0 /* DMA Channel 3 X Count Register */
-#define DMA3_X_MODIFY                  0xFFC00CD4 /* DMA Channel 3 X Modify Register */
-#define DMA3_Y_COUNT                   0xFFC00CD8 /* DMA Channel 3 Y Count Register */
-#define DMA3_Y_MODIFY                  0xFFC00CDC /* DMA Channel 3 Y Modify Register */
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0 /* DMA Channel 3 Current Descriptor Pointer Register */
-#define DMA3_CURR_ADDR                 0xFFC00CE4 /* DMA Channel 3 Current Address Register */
-#define DMA3_IRQ_STATUS                0xFFC00CE8 /* DMA Channel 3 Interrupt/Status Register */
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC /* DMA Channel 3 Peripheral Map Register */
-#define DMA3_CURR_X_COUNT              0xFFC00CF0 /* DMA Channel 3 Current X Count Register */
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8 /* DMA Channel 3 Current Y Count Register */
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00 /* DMA Channel 4 Next Descriptor Pointer Register */
-#define DMA4_START_ADDR                0xFFC00D04 /* DMA Channel 4 Start Address Register */
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10 /* DMA Channel 4 X Count Register */
-#define DMA4_X_MODIFY                  0xFFC00D14 /* DMA Channel 4 X Modify Register */
-#define DMA4_Y_COUNT                   0xFFC00D18 /* DMA Channel 4 Y Count Register */
-#define DMA4_Y_MODIFY                  0xFFC00D1C /* DMA Channel 4 Y Modify Register */
-#define DMA4_CURR_DESC_PTR             0xFFC00D20 /* DMA Channel 4 Current Descriptor Pointer Register */
-#define DMA4_CURR_ADDR                 0xFFC00D24 /* DMA Channel 4 Current Address Register */
-#define DMA4_IRQ_STATUS                0xFFC00D28 /* DMA Channel 4 Interrupt/Status Register */
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C /* DMA Channel 4 Peripheral Map Register */
-#define DMA4_CURR_X_COUNT              0xFFC00D30 /* DMA Channel 4 Current X Count Register */
-#define DMA4_CURR_Y_COUNT              0xFFC00D38 /* DMA Channel 4 Current Y Count Register */
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40 /* DMA Channel 5 Next Descriptor Pointer Register */
-#define DMA5_START_ADDR                0xFFC00D44 /* DMA Channel 5 Start Address Register */
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50 /* DMA Channel 5 X Count Register */
-#define DMA5_X_MODIFY                  0xFFC00D54 /* DMA Channel 5 X Modify Register */
-#define DMA5_Y_COUNT                   0xFFC00D58 /* DMA Channel 5 Y Count Register */
-#define DMA5_Y_MODIFY                  0xFFC00D5C /* DMA Channel 5 Y Modify Register */
-#define DMA5_CURR_DESC_PTR             0xFFC00D60 /* DMA Channel 5 Current Descriptor Pointer Register */
-#define DMA5_CURR_ADDR                 0xFFC00D64 /* DMA Channel 5 Current Address Register */
-#define DMA5_IRQ_STATUS                0xFFC00D68 /* DMA Channel 5 Interrupt/Status Register */
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C /* DMA Channel 5 Peripheral Map Register */
-#define DMA5_CURR_X_COUNT              0xFFC00D70 /* DMA Channel 5 Current X Count Register */
-#define DMA5_CURR_Y_COUNT              0xFFC00D78 /* DMA Channel 5 Current Y Count Register */
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80 /* DMA Channel 6 Next Descriptor Pointer Register */
-#define DMA6_START_ADDR                0xFFC00D84 /* DMA Channel 6 Start Address Register */
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90 /* DMA Channel 6 X Count Register */
-#define DMA6_X_MODIFY                  0xFFC00D94 /* DMA Channel 6 X Modify Register */
-#define DMA6_Y_COUNT                   0xFFC00D98 /* DMA Channel 6 Y Count Register */
-#define DMA6_Y_MODIFY                  0xFFC00D9C /* DMA Channel 6 Y Modify Register */
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0 /* DMA Channel 6 Current Descriptor Pointer Register */
-#define DMA6_CURR_ADDR                 0xFFC00DA4 /* DMA Channel 6 Current Address Register */
-#define DMA6_IRQ_STATUS                0xFFC00DA8 /* DMA Channel 6 Interrupt/Status Register */
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC /* DMA Channel 6 Peripheral Map Register */
-#define DMA6_CURR_X_COUNT              0xFFC00DB0 /* DMA Channel 6 Current X Count Register */
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8 /* DMA Channel 6 Current Y Count Register */
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0 /* DMA Channel 7 Next Descriptor Pointer Register */
-#define DMA7_START_ADDR                0xFFC00DC4 /* DMA Channel 7 Start Address Register */
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0 /* DMA Channel 7 X Count Register */
-#define DMA7_X_MODIFY                  0xFFC00DD4 /* DMA Channel 7 X Modify Register */
-#define DMA7_Y_COUNT                   0xFFC00DD8 /* DMA Channel 7 Y Count Register */
-#define DMA7_Y_MODIFY                  0xFFC00DDC /* DMA Channel 7 Y Modify Register */
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0 /* DMA Channel 7 Current Descriptor Pointer Register */
-#define DMA7_CURR_ADDR                 0xFFC00DE4 /* DMA Channel 7 Current Address Register */
-#define DMA7_IRQ_STATUS                0xFFC00DE8 /* DMA Channel 7 Interrupt/Status Register */
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC /* DMA Channel 7 Peripheral Map Register */
-#define DMA7_CURR_X_COUNT              0xFFC00DF0 /* DMA Channel 7 Current X Count Register */
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8 /* DMA Channel 7 Current Y Count Register */
-#define DMA8_NEXT_DESC_PTR             0xFFC00E00 /* DMA Channel 8 Next Descriptor Pointer Register */
-#define DMA8_START_ADDR                0xFFC00E04 /* DMA Channel 8 Start Address Register */
-#define DMA8_CONFIG                    0xFFC00E08 /* DMA Channel 8 Configuration Register */
-#define DMA8_X_COUNT                   0xFFC00E10 /* DMA Channel 8 X Count Register */
-#define DMA8_X_MODIFY                  0xFFC00E14 /* DMA Channel 8 X Modify Register */
-#define DMA8_Y_COUNT                   0xFFC00E18 /* DMA Channel 8 Y Count Register */
-#define DMA8_Y_MODIFY                  0xFFC00E1C /* DMA Channel 8 Y Modify Register */
-#define DMA8_CURR_DESC_PTR             0xFFC00E20 /* DMA Channel 8 Current Descriptor Pointer Register */
-#define DMA8_CURR_ADDR                 0xFFC00E24 /* DMA Channel 8 Current Address Register */
-#define DMA8_IRQ_STATUS                0xFFC00E28 /* DMA Channel 8 Interrupt/Status Register */
-#define DMA8_PERIPHERAL_MAP            0xFFC00E2C /* DMA Channel 8 Peripheral Map Register */
-#define DMA8_CURR_X_COUNT              0xFFC00E30 /* DMA Channel 8 Current X Count Register */
-#define DMA8_CURR_Y_COUNT              0xFFC00E38 /* DMA Channel 8 Current Y Count Register */
-#define DMA9_NEXT_DESC_PTR             0xFFC00E40 /* DMA Channel 9 Next Descriptor Pointer Register */
-#define DMA9_START_ADDR                0xFFC00E44 /* DMA Channel 9 Start Address Register */
-#define DMA9_CONFIG                    0xFFC00E48 /* DMA Channel 9 Configuration Register */
-#define DMA9_X_COUNT                   0xFFC00E50 /* DMA Channel 9 X Count Register */
-#define DMA9_X_MODIFY                  0xFFC00E54 /* DMA Channel 9 X Modify Register */
-#define DMA9_Y_COUNT                   0xFFC00E58 /* DMA Channel 9 Y Count Register */
-#define DMA9_Y_MODIFY                  0xFFC00E5C /* DMA Channel 9 Y Modify Register */
-#define DMA9_CURR_DESC_PTR             0xFFC00E60 /* DMA Channel 9 Current Descriptor Pointer Register */
-#define DMA9_CURR_ADDR                 0xFFC00E64 /* DMA Channel 9 Current Address Register */
-#define DMA9_IRQ_STATUS                0xFFC00E68 /* DMA Channel 9 Interrupt/Status Register */
-#define DMA9_PERIPHERAL_MAP            0xFFC00E6C /* DMA Channel 9 Peripheral Map Register */
-#define DMA9_CURR_X_COUNT              0xFFC00E70 /* DMA Channel 9 Current X Count Register */
-#define DMA9_CURR_Y_COUNT              0xFFC00E78 /* DMA Channel 9 Current Y Count Register */
-#define DMA10_NEXT_DESC_PTR            0xFFC00E80 /* DMA Channel 10 Next Descriptor Pointer Register */
-#define DMA10_START_ADDR               0xFFC00E84 /* DMA Channel 10 Start Address Register */
-#define DMA10_CONFIG                   0xFFC00E88 /* DMA Channel 10 Configuration Register */
-#define DMA10_X_COUNT                  0xFFC00E90 /* DMA Channel 10 X Count Register */
-#define DMA10_X_MODIFY                 0xFFC00E94 /* DMA Channel 10 X Modify Register */
-#define DMA10_Y_COUNT                  0xFFC00E98 /* DMA Channel 10 Y Count Register */
-#define DMA10_Y_MODIFY                 0xFFC00E9C /* DMA Channel 10 Y Modify Register */
-#define DMA10_CURR_DESC_PTR            0xFFC00EA0 /* DMA Channel 10 Current Descriptor Pointer Register */
-#define DMA10_CURR_ADDR                0xFFC00EA4 /* DMA Channel 10 Current Address Register */
-#define DMA10_IRQ_STATUS               0xFFC00EA8 /* DMA Channel 10 Interrupt/Status Register */
-#define DMA10_PERIPHERAL_MAP           0xFFC00EAC /* DMA Channel 10 Peripheral Map Register */
-#define DMA10_CURR_X_COUNT             0xFFC00EB0 /* DMA Channel 10 Current X Count Register */
-#define DMA10_CURR_Y_COUNT             0xFFC00EB8 /* DMA Channel 10 Current Y Count Register */
-#define DMA11_NEXT_DESC_PTR            0xFFC00EC0 /* DMA Channel 11 Next Descriptor Pointer Register */
-#define DMA11_START_ADDR               0xFFC00EC4 /* DMA Channel 11 Start Address Register */
-#define DMA11_CONFIG                   0xFFC00EC8 /* DMA Channel 11 Configuration Register */
-#define DMA11_X_COUNT                  0xFFC00ED0 /* DMA Channel 11 X Count Register */
-#define DMA11_X_MODIFY                 0xFFC00ED4 /* DMA Channel 11 X Modify Register */
-#define DMA11_Y_COUNT                  0xFFC00ED8 /* DMA Channel 11 Y Count Register */
-#define DMA11_Y_MODIFY                 0xFFC00EDC /* DMA Channel 11 Y Modify Register */
-#define DMA11_CURR_DESC_PTR            0xFFC00EE0 /* DMA Channel 11 Current Descriptor Pointer Register */
-#define DMA11_CURR_ADDR                0xFFC00EE4 /* DMA Channel 11 Current Address Register */
-#define DMA11_IRQ_STATUS               0xFFC00EE8 /* DMA Channel 11 Interrupt/Status Register */
-#define DMA11_PERIPHERAL_MAP           0xFFC00EEC /* DMA Channel 11 Peripheral Map Register */
-#define DMA11_CURR_X_COUNT             0xFFC00EF0 /* DMA Channel 11 Current X Count Register */
-#define DMA11_CURR_Y_COUNT             0xFFC00EF8 /* DMA Channel 11 Current Y Count Register */
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00F40 /* MemDMA Stream 0 Source Next Descriptor Pointer Register */
-#define MDMA_S0_START_ADDR             0xFFC00F44 /* MemDMA Stream 0 Source Start Address Register */
-#define MDMA_S0_CONFIG                 0xFFC00F48 /* MemDMA Stream 0 Source Configuration Register */
-#define MDMA_S0_X_COUNT                0xFFC00F50 /* MemDMA Stream 0 Source X Count Register */
-#define MDMA_S0_X_MODIFY               0xFFC00F54 /* MemDMA Stream 0 Source X Modify Register */
-#define MDMA_S0_Y_COUNT                0xFFC00F58 /* MemDMA Stream 0 Source Y Count Register */
-#define MDMA_S0_Y_MODIFY               0xFFC00F5C /* MemDMA Stream 0 Source Y Modify Register */
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00F60 /* MemDMA Stream 0 Source Current Descriptor Pointer Register */
-#define MDMA_S0_CURR_ADDR              0xFFC00F64 /* MemDMA Stream 0 Source Current Address Register */
-#define MDMA_S0_IRQ_STATUS             0xFFC00F68 /* MemDMA Stream 0 Source Interrupt/Status Register */
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00F6C /* MemDMA Stream 0 Source Peripheral Map Register */
-#define MDMA_S0_CURR_X_COUNT           0xFFC00F70 /* MemDMA Stream 0 Source Current X Count Register */
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00F78 /* MemDMA Stream 0 Source Current Y Count Register */
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00F00 /* MemDMA Stream 0 Destination Next Descriptor Pointer Register */
-#define MDMA_D0_START_ADDR             0xFFC00F04 /* MemDMA Stream 0 Destination Start Address Register */
-#define MDMA_D0_CONFIG                 0xFFC00F08 /* MemDMA Stream 0 Destination Configuration Register */
-#define MDMA_D0_X_COUNT                0xFFC00F10 /* MemDMA Stream 0 Destination X Count Register */
-#define MDMA_D0_X_MODIFY               0xFFC00F14 /* MemDMA Stream 0 Destination X Modify Register */
-#define MDMA_D0_Y_COUNT                0xFFC00F18 /* MemDMA Stream 0 Destination Y Count Register */
-#define MDMA_D0_Y_MODIFY               0xFFC00F1C /* MemDMA Stream 0 Destination Y Modify Register */
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00F20 /* MemDMA Stream 0 Destination Current Descriptor Pointer Register */
-#define MDMA_D0_CURR_ADDR              0xFFC00F24 /* MemDMA Stream 0 Destination Current Address Register */
-#define MDMA_D0_IRQ_STATUS             0xFFC00F28 /* MemDMA Stream 0 Destination Interrupt/Status Register */
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00F2C /* MemDMA Stream 0 Destination Peripheral Map Register */
-#define MDMA_D0_CURR_X_COUNT           0xFFC00F30 /* MemDMA Stream 0 Destination Current X Count Register */
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00F38 /* MemDMA Stream 0 Destination Current Y Count Register */
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00FC0 /* MemDMA Stream 1 Source Next Descriptor Pointer Register */
-#define MDMA_S1_START_ADDR             0xFFC00FC4 /* MemDMA Stream 1 Source Start Address Register */
-#define MDMA_S1_CONFIG                 0xFFC00FC8 /* MemDMA Stream 1 Source Configuration Register */
-#define MDMA_S1_X_COUNT                0xFFC00FD0 /* MemDMA Stream 1 Source X Count Register */
-#define MDMA_S1_X_MODIFY               0xFFC00FD4 /* MemDMA Stream 1 Source X Modify Register */
-#define MDMA_S1_Y_COUNT                0xFFC00FD8 /* MemDMA Stream 1 Source Y Count Register */
-#define MDMA_S1_Y_MODIFY               0xFFC00FDC /* MemDMA Stream 1 Source Y Modify Register */
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00FE0 /* MemDMA Stream 1 Source Current Descriptor Pointer Register */
-#define MDMA_S1_CURR_ADDR              0xFFC00FE4 /* MemDMA Stream 1 Source Current Address Register */
-#define MDMA_S1_IRQ_STATUS             0xFFC00FE8 /* MemDMA Stream 1 Source Interrupt/Status Register */
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00FEC /* MemDMA Stream 1 Source Peripheral Map Register */
-#define MDMA_S1_CURR_X_COUNT           0xFFC00FF0 /* MemDMA Stream 1 Source Current X Count Register */
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00FF8 /* MemDMA Stream 1 Source Current Y Count Register */
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00F80 /* MemDMA Stream 1 Destination Next Descriptor Pointer Register */
-#define MDMA_D1_START_ADDR             0xFFC00F84 /* MemDMA Stream 1 Destination Start Address Register */
-#define MDMA_D1_CONFIG                 0xFFC00F88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00F90 /* MemDMA Stream 1 Destination X Count Register */
-#define MDMA_D1_X_MODIFY               0xFFC00F94 /* MemDMA Stream 1 Destination X Modify Register */
-#define MDMA_D1_Y_COUNT                0xFFC00F98 /* MemDMA Stream 1 Destination Y Count Register */
-#define MDMA_D1_Y_MODIFY               0xFFC00F9C /* MemDMA Stream 1 Destination Y Modify Register */
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00FA0 /* MemDMA Stream 1 Destination Current Descriptor Pointer Register */
-#define MDMA_D1_CURR_ADDR              0xFFC00FA4 /* MemDMA Stream 1 Destination Current Address Register */
-#define MDMA_D1_IRQ_STATUS             0xFFC00FA8 /* MemDMA Stream 1 Destination Interrupt/Status Register */
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00FAC /* MemDMA Stream 1 Destination Peripheral Map Register */
-#define MDMA_D1_CURR_X_COUNT           0xFFC00FB0 /* MemDMA Stream 1 Destination Current X Count Register */
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00FB8 /* MemDMA Stream 1 Destination Current Y Count Register */
-#define PPI_CONTROL                    0xFFC01000 /* PPI Control Register */
-#define PPI_STATUS                     0xFFC01004 /* PPI Status Register */
-#define PPI_COUNT                      0xFFC01008 /* PPI Transfer Count Register */
-#define PPI_DELAY                      0xFFC0100C /* PPI Delay Count Register */
-#define PPI_FRAME                      0xFFC01010 /* PPI Frame Length Register */
-#define TWI_CLKDIV                     0xFFC01400 /* Serial Clock Divider Register */
-#define TWI_CONTROL                    0xFFC01404 /* TWI Control Register */
-#define TWI_SLAVE_CTL                  0xFFC01408 /* Slave Mode Control Register */
-#define TWI_SLAVE_STAT                 0xFFC0140C /* Slave Mode Status Register */
-#define TWI_SLAVE_ADDR                 0xFFC01410 /* Slave Mode Address Register */
-#define TWI_MASTER_CTL                 0xFFC01414 /* Master Mode Control Register */
-#define TWI_MASTER_STAT                0xFFC01418 /* Master Mode Status Register */
-#define TWI_MASTER_ADDR                0xFFC0141C /* Master Mode Address Register */
-#define TWI_INT_STAT                   0xFFC01420 /* TWI Interrupt Status Register */
-#define TWI_INT_MASK                   0xFFC01424 /* TWI Master Interrupt Mask Register */
-#define TWI_FIFO_CTL                   0xFFC01428 /* FIFO Control Register */
-#define TWI_FIFO_STAT                  0xFFC0142C /* FIFO Status Register */
-#define TWI_XMT_DATA8                  0xFFC01480 /* FIFO Transmit Data Single Byte Register */
-#define TWI_XMT_DATA16                 0xFFC01484 /* FIFO Transmit Data Double Byte Register */
-#define TWI_RCV_DATA8                  0xFFC01488 /* FIFO Receive Data Single Byte Register */
-#define TWI_RCV_DATA16                 0xFFC0148C /* FIFO Receive Data Double Byte Register */
-#define PORTGIO                        0xFFC01500 /* Port G I/O Pin State Specify Register */
-#define PORTGIO_CLEAR                  0xFFC01504 /* Port G I/O Peripheral Interrupt Clear Register */
-#define PORTGIO_SET                    0xFFC01508 /* Port G I/O Peripheral Interrupt Set Register */
-#define PORTGIO_TOGGLE                 0xFFC0150C /* Port G I/O Pin State Toggle Register */
-#define PORTGIO_MASKA                  0xFFC01510 /* Port G I/O Mask State Specify Interrupt A Register */
-#define PORTGIO_MASKA_CLEAR            0xFFC01514 /* Port G I/O Mask Disable Interrupt A Register */
-#define PORTGIO_MASKA_SET              0xFFC01518 /* Port G I/O Mask Enable Interrupt A Register */
-#define PORTGIO_MASKA_TOGGLE           0xFFC0151C /* Port G I/O Mask Toggle Enable Interrupt A Register */
-#define PORTGIO_MASKB                  0xFFC01520 /* Port G I/O Mask State Specify Interrupt B Register */
-#define PORTGIO_MASKB_CLEAR            0xFFC01524 /* Port G I/O Mask Disable Interrupt B Register */
-#define PORTGIO_MASKB_SET              0xFFC01528 /* Port G I/O Mask Enable Interrupt B Register */
-#define PORTGIO_MASKB_TOGGLE           0xFFC0152C /* Port G I/O Mask Toggle Enable Interrupt B Register */
-#define PORTGIO_DIR                    0xFFC01530 /* Port G I/O Direction Register */
-#define PORTGIO_POLAR                  0xFFC01534 /* Port G I/O Source Polarity Register */
-#define PORTGIO_EDGE                   0xFFC01538 /* Port G I/O Source Sensitivity Register */
-#define PORTGIO_BOTH                   0xFFC0153C /* Port G I/O Set on BOTH Edges Register */
-#define PORTGIO_INEN                   0xFFC01540 /* Port G I/O Input Enable Register */
-#define PORTHIO                        0xFFC01700 /* Port H I/O Pin State Specify Register */
-#define PORTHIO_CLEAR                  0xFFC01704 /* Port H I/O Peripheral Interrupt Clear Register */
-#define PORTHIO_SET                    0xFFC01708 /* Port H I/O Peripheral Interrupt Set Register */
-#define PORTHIO_TOGGLE                 0xFFC0170C /* Port H I/O Pin State Toggle Register */
-#define PORTHIO_MASKA                  0xFFC01710 /* Port H I/O Mask State Specify Interrupt A Register */
-#define PORTHIO_MASKA_CLEAR            0xFFC01714 /* Port H I/O Mask Disable Interrupt A Register */
-#define PORTHIO_MASKA_SET              0xFFC01718 /* Port H I/O Mask Enable Interrupt A Register */
-#define PORTHIO_MASKA_TOGGLE           0xFFC0171C /* Port H I/O Mask Toggle Enable Interrupt A Register */
-#define PORTHIO_MASKB                  0xFFC01720 /* Port H I/O Mask State Specify Interrupt B Register */
-#define PORTHIO_MASKB_CLEAR            0xFFC01724 /* Port H I/O Mask Disable Interrupt B Register */
-#define PORTHIO_MASKB_SET              0xFFC01728 /* Port H I/O Mask Enable Interrupt B Register */
-#define PORTHIO_MASKB_TOGGLE           0xFFC0172C /* Port H I/O Mask Toggle Enable Interrupt B Register */
-#define PORTHIO_DIR                    0xFFC01730 /* Port H I/O Direction Register */
-#define PORTHIO_POLAR                  0xFFC01734 /* Port H I/O Source Polarity Register */
-#define PORTHIO_EDGE                   0xFFC01738 /* Port H I/O Source Sensitivity Register */
-#define PORTHIO_BOTH                   0xFFC0173C /* Port H I/O Set on BOTH Edges Register */
-#define PORTHIO_INEN                   0xFFC01740 /* Port H I/O Input Enable Register */
-#define UART1_THR                      0xFFC02000 /* Transmit Holding register */
-#define UART1_RBR                      0xFFC02000 /* Receive Buffer register */
-#define UART1_DLL                      0xFFC02000 /* Divisor Latch (Low-Byte) */
-#define UART1_IER                      0xFFC02004 /* Interrupt Enable Register */
-#define UART1_DLH                      0xFFC02004 /* Divisor Latch (High-Byte) */
-#define UART1_IIR                      0xFFC02008 /* Interrupt Identification Register */
-#define UART1_LCR                      0xFFC0200C /* Line Control Register */
-#define UART1_MCR                      0xFFC02010 /* Modem Control Register */
-#define UART1_LSR                      0xFFC02014 /* Line Status Register */
-#define UART1_MSR                      0xFFC02018 /* Modem Status Register */
-#define UART1_SCR                      0xFFC0201C /* SCR Scratch Register */
-#define UART1_GCTL                     0xFFC02024 /* Global Control Register */
-#define PORTF_FER                      0xFFC03200 /* Port F Function Enable Register (Alternate/Flag*) */
-#define PORTG_FER                      0xFFC03204 /* Port G Function Enable Register (Alternate/Flag*) */
-#define PORTH_FER                      0xFFC03208 /* Port H Function Enable Register (Alternate/Flag*) */
-#define HMDMA0_CONTROL                 0xFFC03300 /* Handshake MDMA0 Control Register */
-#define HMDMA0_ECINIT                  0xFFC03304 /* HMDMA0 Initial Edge Count Register */
-#define HMDMA0_BCINIT                  0xFFC03308 /* HMDMA0 Initial Block Count Register */
-#define HMDMA0_ECURGENT                0xFFC0330C /* HMDMA0 Urgent Edge Count Threshhold Register */
-#define HMDMA0_ECOVERFLOW              0xFFC03310 /* HMDMA0 Edge Count Overflow Interrupt Register */
-#define HMDMA0_ECOUNT                  0xFFC03314 /* HMDMA0 Current Edge Count Register */
-#define HMDMA0_BCOUNT                  0xFFC03318 /* HMDMA0 Current Block Count Register */
-#define HMDMA1_CONTROL                 0xFFC03340 /* Handshake MDMA1 Control Register */
-#define HMDMA1_ECINIT                  0xFFC03344 /* HMDMA1 Initial Edge Count Register */
-#define HMDMA1_BCINIT                  0xFFC03348 /* HMDMA1 Initial Block Count Register */
-#define HMDMA1_ECURGENT                0xFFC0334C /* HMDMA1 Urgent Edge Count Threshhold Register */
-#define HMDMA1_ECOVERFLOW              0xFFC03350 /* HMDMA1 Edge Count Overflow Interrupt Register */
-#define HMDMA1_ECOUNT                  0xFFC03354 /* HMDMA1 Current Edge Count Register */
-#define HMDMA1_BCOUNT                  0xFFC03358 /* HMDMA1 Current Block Count Register */
-#define PORTF_MUX                      0xFFC03210 /* Port F mux control */
-#define PORTG_MUX                      0xFFC03214 /* Port G mux control */
-#define PORTH_MUX                      0xFFC03218 /* Port H mux control */
-#define PORTF_DRIVE                    0xFFC03220 /* Port F drive strength control */
-#define PORTG_DRIVE                    0xFFC03224 /* Port G drive strength control */
-#define PORTH_DRIVE                    0xFFC03228 /* Port H drive strength control */
-#define PORTF_SLEW                     0xFFC03230 /* Port F slew control */
-#define PORTG_SLEW                     0xFFC03234 /* Port G slew control */
-#define PORTH_SLEW                     0xFFC03238 /* Port H slew control */
-#define PORTF_HYSTERESIS               0xFFC03240 /* Port F Schmitt trigger control */
-#define PORTG_HYSTERESIS               0xFFC03244 /* Port G Schmitt trigger control */
-#define PORTH_HYSTERESIS               0xFFC03248 /* Port H Schmitt trigger control */
-#define NONGPIO_DRIVE                  0xFFC03280 /* Non-GPIO Port drive strength control */
-#define NONGPIO_SLEW                   0xFFC03284 /* Non-GPIO Port slew control */
-#define NONGPIO_HYSTERESIS             0xFFC03288 /* Non-GPIO Port Schmitt trigger control */
-#define HOST_CONTROL                   0xFFC03400 /* HOST Control Register */
-#define HOST_STATUS                    0xFFC03404 /* HOST Status Register */
-#define HOST_TIMEOUT                   0xFFC03408 /* HOST Acknowledge Mode Timeout Register */
-#define CNT_CONFIG                     0xFFC03500 /* Configuration/Control Register */
-#define CNT_IMASK                      0xFFC03504 /* Interrupt Mask Register */
-#define CNT_STATUS                     0xFFC03508 /* Status Register */
-#define CNT_COMMAND                    0xFFC0350C /* Command Register */
-#define CNT_DEBOUNCE                   0xFFC03510 /* Debounce Prescaler Register */
-#define CNT_COUNTER                    0xFFC03514 /* Counter Register */
-#define CNT_MAX                        0xFFC03518 /* Maximal Count Boundary Value Register */
-#define CNT_MIN                        0xFFC0351C /* Minimal Count Boundary Value Register */
-#define OTP_CONTROL                    0xFFC03600 /* OTP/Fuse Control Register */
-#define OTP_BEN                        0xFFC03604 /* OTP/Fuse Byte Enable */
-#define OTP_STATUS                     0xFFC03608 /* OTP/Fuse Status */
-#define OTP_TIMING                     0xFFC0360C /* OTP/Fuse Access Timing */
-#define SECURE_SYSSWT                  0xFFC03620 /* Secure System Switches */
-#define SECURE_CONTROL                 0xFFC03624 /* Secure Control */
-#define SECURE_STATUS                  0xFFC03628 /* Secure Status */
-#define OTP_DATA0                      0xFFC03680 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA1                      0xFFC03684 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA2                      0xFFC03688 /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define OTP_DATA3                      0xFFC0368C /* OTP/Fuse Data (OTP_DATA0-3) accesses the fuse read write buffer */
-#define NFC_CTL                        0xFFC03700 /* NAND Control Register */
-#define NFC_STAT                       0xFFC03704 /* NAND Status Register */
-#define NFC_IRQSTAT                    0xFFC03708 /* NAND Interrupt Status Register */
-#define NFC_IRQMASK                    0xFFC0370C /* NAND Interrupt Mask Register */
-#define NFC_ECC0                       0xFFC03710 /* NAND ECC Register 0 */
-#define NFC_ECC1                       0xFFC03714 /* NAND ECC Register 1 */
-#define NFC_ECC2                       0xFFC03718 /* NAND ECC Register 2 */
-#define NFC_ECC3                       0xFFC0371C /* NAND ECC Register 3 */
-#define NFC_COUNT                      0xFFC03720 /* NAND ECC Count Register */
-#define NFC_RST                        0xFFC03724 /* NAND ECC Reset Register */
-#define NFC_PGCTL                      0xFFC03728 /* NAND Page Control Register */
-#define NFC_READ                       0xFFC0372C /* NAND Read Data Register */
-#define NFC_ADDR                       0xFFC03740 /* NAND Address Register */
-#define NFC_CMD                        0xFFC03744 /* NAND Command Register */
-#define NFC_DATA_WR                    0xFFC03748 /* NAND Data Write Register */
-#define NFC_DATA_RD                    0xFFC0374C /* NAND Data Read Register */
-#define DMA_TC_CNT                     0xFFC00B0C
-#define DMA_TC_PER                     0xFFC00B10
-
-#endif /* __BFIN_DEF_ADSP_BF522_proc__ */

+ 0 - 1
arch/blackfin/include/asm/mach-bf527/BF523_cdef.h

@@ -1 +0,0 @@
-#include "BF522_cdef.h"

+ 0 - 1
arch/blackfin/include/asm/mach-bf527/BF523_def.h

@@ -1 +0,0 @@
-#include "BF522_def.h"

+ 0 - 350
arch/blackfin/include/asm/mach-bf527/BF524_cdef.h

@@ -1,350 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF524_proc__
-#define __BFIN_CDEF_ADSP_BF524_proc__
-
-#include "BF522_cdef.h"
-
-#define bfin_read_USB_FADDR()          bfin_read16(USB_FADDR)
-#define bfin_write_USB_FADDR(val)      bfin_write16(USB_FADDR, val)
-#define bfin_read_USB_POWER()          bfin_read16(USB_POWER)
-#define bfin_write_USB_POWER(val)      bfin_write16(USB_POWER, val)
-#define bfin_read_USB_INTRTX()         bfin_read16(USB_INTRTX)
-#define bfin_write_USB_INTRTX(val)     bfin_write16(USB_INTRTX, val)
-#define bfin_read_USB_INTRRX()         bfin_read16(USB_INTRRX)
-#define bfin_write_USB_INTRRX(val)     bfin_write16(USB_INTRRX, val)
-#define bfin_read_USB_INTRTXE()        bfin_read16(USB_INTRTXE)
-#define bfin_write_USB_INTRTXE(val)    bfin_write16(USB_INTRTXE, val)
-#define bfin_read_USB_INTRRXE()        bfin_read16(USB_INTRRXE)
-#define bfin_write_USB_INTRRXE(val)    bfin_write16(USB_INTRRXE, val)
-#define bfin_read_USB_INTRUSB()        bfin_read16(USB_INTRUSB)
-#define bfin_write_USB_INTRUSB(val)    bfin_write16(USB_INTRUSB, val)
-#define bfin_read_USB_INTRUSBE()       bfin_read16(USB_INTRUSBE)
-#define bfin_write_USB_INTRUSBE(val)   bfin_write16(USB_INTRUSBE, val)
-#define bfin_read_USB_FRAME()          bfin_read16(USB_FRAME)
-#define bfin_write_USB_FRAME(val)      bfin_write16(USB_FRAME, val)
-#define bfin_read_USB_INDEX()          bfin_read16(USB_INDEX)
-#define bfin_write_USB_INDEX(val)      bfin_write16(USB_INDEX, val)
-#define bfin_read_USB_TESTMODE()       bfin_read16(USB_TESTMODE)
-#define bfin_write_USB_TESTMODE(val)   bfin_write16(USB_TESTMODE, val)
-#define bfin_read_USB_GLOBINTR()       bfin_read16(USB_GLOBINTR)
-#define bfin_write_USB_GLOBINTR(val)   bfin_write16(USB_GLOBINTR, val)
-#define bfin_read_USB_GLOBAL_CTL()     bfin_read16(USB_GLOBAL_CTL)
-#define bfin_write_USB_GLOBAL_CTL(val) bfin_write16(USB_GLOBAL_CTL, val)
-#define bfin_read_USB_TX_MAX_PACKET()  bfin_read16(USB_TX_MAX_PACKET)
-#define bfin_write_USB_TX_MAX_PACKET(val) bfin_write16(USB_TX_MAX_PACKET, val)
-#define bfin_read_USB_CSR0()           bfin_read16(USB_CSR0)
-#define bfin_write_USB_CSR0(val)       bfin_write16(USB_CSR0, val)
-#define bfin_read_USB_TXCSR()          bfin_read16(USB_TXCSR)
-#define bfin_write_USB_TXCSR(val)      bfin_write16(USB_TXCSR, val)
-#define bfin_read_USB_RX_MAX_PACKET()  bfin_read16(USB_RX_MAX_PACKET)
-#define bfin_write_USB_RX_MAX_PACKET(val) bfin_write16(USB_RX_MAX_PACKET, val)
-#define bfin_read_USB_RXCSR()          bfin_read16(USB_RXCSR)
-#define bfin_write_USB_RXCSR(val)      bfin_write16(USB_RXCSR, val)
-#define bfin_read_USB_COUNT0()         bfin_read16(USB_COUNT0)
-#define bfin_write_USB_COUNT0(val)     bfin_write16(USB_COUNT0, val)
-#define bfin_read_USB_RXCOUNT()        bfin_read16(USB_RXCOUNT)
-#define bfin_write_USB_RXCOUNT(val)    bfin_write16(USB_RXCOUNT, val)
-#define bfin_read_USB_TXTYPE()         bfin_read16(USB_TXTYPE)
-#define bfin_write_USB_TXTYPE(val)     bfin_write16(USB_TXTYPE, val)
-#define bfin_read_USB_NAKLIMIT0()      bfin_read16(USB_NAKLIMIT0)
-#define bfin_write_USB_NAKLIMIT0(val)  bfin_write16(USB_NAKLIMIT0, val)
-#define bfin_read_USB_TXINTERVAL()     bfin_read16(USB_TXINTERVAL)
-#define bfin_write_USB_TXINTERVAL(val) bfin_write16(USB_TXINTERVAL, val)
-#define bfin_read_USB_RXTYPE()         bfin_read16(USB_RXTYPE)
-#define bfin_write_USB_RXTYPE(val)     bfin_write16(USB_RXTYPE, val)
-#define bfin_read_USB_RXINTERVAL()     bfin_read16(USB_RXINTERVAL)
-#define bfin_write_USB_RXINTERVAL(val) bfin_write16(USB_RXINTERVAL, val)
-#define bfin_read_USB_TXCOUNT()        bfin_read16(USB_TXCOUNT)
-#define bfin_write_USB_TXCOUNT(val)    bfin_write16(USB_TXCOUNT, val)
-#define bfin_read_USB_EP0_FIFO()       bfin_read16(USB_EP0_FIFO)
-#define bfin_write_USB_EP0_FIFO(val)   bfin_write16(USB_EP0_FIFO, val)
-#define bfin_read_USB_EP1_FIFO()       bfin_read16(USB_EP1_FIFO)
-#define bfin_write_USB_EP1_FIFO(val)   bfin_write16(USB_EP1_FIFO, val)
-#define bfin_read_USB_EP2_FIFO()       bfin_read16(USB_EP2_FIFO)
-#define bfin_write_USB_EP2_FIFO(val)   bfin_write16(USB_EP2_FIFO, val)
-#define bfin_read_USB_EP3_FIFO()       bfin_read16(USB_EP3_FIFO)
-#define bfin_write_USB_EP3_FIFO(val)   bfin_write16(USB_EP3_FIFO, val)
-#define bfin_read_USB_EP4_FIFO()       bfin_read16(USB_EP4_FIFO)
-#define bfin_write_USB_EP4_FIFO(val)   bfin_write16(USB_EP4_FIFO, val)
-#define bfin_read_USB_EP5_FIFO()       bfin_read16(USB_EP5_FIFO)
-#define bfin_write_USB_EP5_FIFO(val)   bfin_write16(USB_EP5_FIFO, val)
-#define bfin_read_USB_EP6_FIFO()       bfin_read16(USB_EP6_FIFO)
-#define bfin_write_USB_EP6_FIFO(val)   bfin_write16(USB_EP6_FIFO, val)
-#define bfin_read_USB_EP7_FIFO()       bfin_read16(USB_EP7_FIFO)
-#define bfin_write_USB_EP7_FIFO(val)   bfin_write16(USB_EP7_FIFO, val)
-#define bfin_read_USB_OTG_DEV_CTL()    bfin_read16(USB_OTG_DEV_CTL)
-#define bfin_write_USB_OTG_DEV_CTL(val) bfin_write16(USB_OTG_DEV_CTL, val)
-#define bfin_read_USB_OTG_VBUS_IRQ()   bfin_read16(USB_OTG_VBUS_IRQ)
-#define bfin_write_USB_OTG_VBUS_IRQ(val) bfin_write16(USB_OTG_VBUS_IRQ, val)
-#define bfin_read_USB_OTG_VBUS_MASK()  bfin_read16(USB_OTG_VBUS_MASK)
-#define bfin_write_USB_OTG_VBUS_MASK(val) bfin_write16(USB_OTG_VBUS_MASK, val)
-#define bfin_read_USB_LINKINFO()       bfin_read16(USB_LINKINFO)
-#define bfin_write_USB_LINKINFO(val)   bfin_write16(USB_LINKINFO, val)
-#define bfin_read_USB_VPLEN()          bfin_read16(USB_VPLEN)
-#define bfin_write_USB_VPLEN(val)      bfin_write16(USB_VPLEN, val)
-#define bfin_read_USB_HS_EOF1()        bfin_read16(USB_HS_EOF1)
-#define bfin_write_USB_HS_EOF1(val)    bfin_write16(USB_HS_EOF1, val)
-#define bfin_read_USB_FS_EOF1()        bfin_read16(USB_FS_EOF1)
-#define bfin_write_USB_FS_EOF1(val)    bfin_write16(USB_FS_EOF1, val)
-#define bfin_read_USB_LS_EOF1()        bfin_read16(USB_LS_EOF1)
-#define bfin_write_USB_LS_EOF1(val)    bfin_write16(USB_LS_EOF1, val)
-#define bfin_read_USB_APHY_CNTRL()     bfin_read16(USB_APHY_CNTRL)
-#define bfin_write_USB_APHY_CNTRL(val) bfin_write16(USB_APHY_CNTRL, val)
-#define bfin_read_USB_APHY_CALIB()     bfin_read16(USB_APHY_CALIB)
-#define bfin_write_USB_APHY_CALIB(val) bfin_write16(USB_APHY_CALIB, val)
-#define bfin_read_USB_APHY_CNTRL2()    bfin_read16(USB_APHY_CNTRL2)
-#define bfin_write_USB_APHY_CNTRL2(val) bfin_write16(USB_APHY_CNTRL2, val)
-#define bfin_read_USB_PHY_TEST()       bfin_read16(USB_PHY_TEST)
-#define bfin_write_USB_PHY_TEST(val)   bfin_write16(USB_PHY_TEST, val)
-#define bfin_read_USB_PLLOSC_CTRL()    bfin_read16(USB_PLLOSC_CTRL)
-#define bfin_write_USB_PLLOSC_CTRL(val) bfin_write16(USB_PLLOSC_CTRL, val)
-#define bfin_read_USB_SRP_CLKDIV()     bfin_read16(USB_SRP_CLKDIV)
-#define bfin_write_USB_SRP_CLKDIV(val) bfin_write16(USB_SRP_CLKDIV, val)
-#define bfin_read_USB_EP_NI0_TXMAXP()  bfin_read16(USB_EP_NI0_TXMAXP)
-#define bfin_write_USB_EP_NI0_TXMAXP(val) bfin_write16(USB_EP_NI0_TXMAXP, val)
-#define bfin_read_USB_EP_NI0_TXCSR()   bfin_read16(USB_EP_NI0_TXCSR)
-#define bfin_write_USB_EP_NI0_TXCSR(val) bfin_write16(USB_EP_NI0_TXCSR, val)
-#define bfin_read_USB_EP_NI0_RXMAXP()  bfin_read16(USB_EP_NI0_RXMAXP)
-#define bfin_write_USB_EP_NI0_RXMAXP(val) bfin_write16(USB_EP_NI0_RXMAXP, val)
-#define bfin_read_USB_EP_NI0_RXCSR()   bfin_read16(USB_EP_NI0_RXCSR)
-#define bfin_write_USB_EP_NI0_RXCSR(val) bfin_write16(USB_EP_NI0_RXCSR, val)
-#define bfin_read_USB_EP_NI0_RXCOUNT() bfin_read16(USB_EP_NI0_RXCOUNT)
-#define bfin_write_USB_EP_NI0_RXCOUNT(val) bfin_write16(USB_EP_NI0_RXCOUNT, val)
-#define bfin_read_USB_EP_NI0_TXTYPE()  bfin_read16(USB_EP_NI0_TXTYPE)
-#define bfin_write_USB_EP_NI0_TXTYPE(val) bfin_write16(USB_EP_NI0_TXTYPE, val)
-#define bfin_read_USB_EP_NI0_TXINTERVAL() bfin_read16(USB_EP_NI0_TXINTERVAL)
-#define bfin_write_USB_EP_NI0_TXINTERVAL(val) bfin_write16(USB_EP_NI0_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_RXTYPE()  bfin_read16(USB_EP_NI0_RXTYPE)
-#define bfin_write_USB_EP_NI0_RXTYPE(val) bfin_write16(USB_EP_NI0_RXTYPE, val)
-#define bfin_read_USB_EP_NI0_RXINTERVAL() bfin_read16(USB_EP_NI0_RXINTERVAL)
-#define bfin_write_USB_EP_NI0_RXINTERVAL(val) bfin_write16(USB_EP_NI0_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI0_TXCOUNT() bfin_read16(USB_EP_NI0_TXCOUNT)
-#define bfin_write_USB_EP_NI0_TXCOUNT(val) bfin_write16(USB_EP_NI0_TXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXMAXP()  bfin_read16(USB_EP_NI1_TXMAXP)
-#define bfin_write_USB_EP_NI1_TXMAXP(val) bfin_write16(USB_EP_NI1_TXMAXP, val)
-#define bfin_read_USB_EP_NI1_TXCSR()   bfin_read16(USB_EP_NI1_TXCSR)
-#define bfin_write_USB_EP_NI1_TXCSR(val) bfin_write16(USB_EP_NI1_TXCSR, val)
-#define bfin_read_USB_EP_NI1_RXMAXP()  bfin_read16(USB_EP_NI1_RXMAXP)
-#define bfin_write_USB_EP_NI1_RXMAXP(val) bfin_write16(USB_EP_NI1_RXMAXP, val)
-#define bfin_read_USB_EP_NI1_RXCSR()   bfin_read16(USB_EP_NI1_RXCSR)
-#define bfin_write_USB_EP_NI1_RXCSR(val) bfin_write16(USB_EP_NI1_RXCSR, val)
-#define bfin_read_USB_EP_NI1_RXCOUNT() bfin_read16(USB_EP_NI1_RXCOUNT)
-#define bfin_write_USB_EP_NI1_RXCOUNT(val) bfin_write16(USB_EP_NI1_RXCOUNT, val)
-#define bfin_read_USB_EP_NI1_TXTYPE()  bfin_read16(USB_EP_NI1_TXTYPE)
-#define bfin_write_USB_EP_NI1_TXTYPE(val) bfin_write16(USB_EP_NI1_TXTYPE, val)
-#define bfin_read_USB_EP_NI1_TXINTERVAL() bfin_read16(USB_EP_NI1_TXINTERVAL)
-#define bfin_write_USB_EP_NI1_TXINTERVAL(val) bfin_write16(USB_EP_NI1_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_RXTYPE()  bfin_read16(USB_EP_NI1_RXTYPE)
-#define bfin_write_USB_EP_NI1_RXTYPE(val) bfin_write16(USB_EP_NI1_RXTYPE, val)
-#define bfin_read_USB_EP_NI1_RXINTERVAL() bfin_read16(USB_EP_NI1_RXINTERVAL)
-#define bfin_write_USB_EP_NI1_RXINTERVAL(val) bfin_write16(USB_EP_NI1_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI1_TXCOUNT() bfin_read16(USB_EP_NI1_TXCOUNT)
-#define bfin_write_USB_EP_NI1_TXCOUNT(val) bfin_write16(USB_EP_NI1_TXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXMAXP()  bfin_read16(USB_EP_NI2_TXMAXP)
-#define bfin_write_USB_EP_NI2_TXMAXP(val) bfin_write16(USB_EP_NI2_TXMAXP, val)
-#define bfin_read_USB_EP_NI2_TXCSR()   bfin_read16(USB_EP_NI2_TXCSR)
-#define bfin_write_USB_EP_NI2_TXCSR(val) bfin_write16(USB_EP_NI2_TXCSR, val)
-#define bfin_read_USB_EP_NI2_RXMAXP()  bfin_read16(USB_EP_NI2_RXMAXP)
-#define bfin_write_USB_EP_NI2_RXMAXP(val) bfin_write16(USB_EP_NI2_RXMAXP, val)
-#define bfin_read_USB_EP_NI2_RXCSR()   bfin_read16(USB_EP_NI2_RXCSR)
-#define bfin_write_USB_EP_NI2_RXCSR(val) bfin_write16(USB_EP_NI2_RXCSR, val)
-#define bfin_read_USB_EP_NI2_RXCOUNT() bfin_read16(USB_EP_NI2_RXCOUNT)
-#define bfin_write_USB_EP_NI2_RXCOUNT(val) bfin_write16(USB_EP_NI2_RXCOUNT, val)
-#define bfin_read_USB_EP_NI2_TXTYPE()  bfin_read16(USB_EP_NI2_TXTYPE)
-#define bfin_write_USB_EP_NI2_TXTYPE(val) bfin_write16(USB_EP_NI2_TXTYPE, val)
-#define bfin_read_USB_EP_NI2_TXINTERVAL() bfin_read16(USB_EP_NI2_TXINTERVAL)
-#define bfin_write_USB_EP_NI2_TXINTERVAL(val) bfin_write16(USB_EP_NI2_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_RXTYPE()  bfin_read16(USB_EP_NI2_RXTYPE)
-#define bfin_write_USB_EP_NI2_RXTYPE(val) bfin_write16(USB_EP_NI2_RXTYPE, val)
-#define bfin_read_USB_EP_NI2_RXINTERVAL() bfin_read16(USB_EP_NI2_RXINTERVAL)
-#define bfin_write_USB_EP_NI2_RXINTERVAL(val) bfin_write16(USB_EP_NI2_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI2_TXCOUNT() bfin_read16(USB_EP_NI2_TXCOUNT)
-#define bfin_write_USB_EP_NI2_TXCOUNT(val) bfin_write16(USB_EP_NI2_TXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXMAXP()  bfin_read16(USB_EP_NI3_TXMAXP)
-#define bfin_write_USB_EP_NI3_TXMAXP(val) bfin_write16(USB_EP_NI3_TXMAXP, val)
-#define bfin_read_USB_EP_NI3_TXCSR()   bfin_read16(USB_EP_NI3_TXCSR)
-#define bfin_write_USB_EP_NI3_TXCSR(val) bfin_write16(USB_EP_NI3_TXCSR, val)
-#define bfin_read_USB_EP_NI3_RXMAXP()  bfin_read16(USB_EP_NI3_RXMAXP)
-#define bfin_write_USB_EP_NI3_RXMAXP(val) bfin_write16(USB_EP_NI3_RXMAXP, val)
-#define bfin_read_USB_EP_NI3_RXCSR()   bfin_read16(USB_EP_NI3_RXCSR)
-#define bfin_write_USB_EP_NI3_RXCSR(val) bfin_write16(USB_EP_NI3_RXCSR, val)
-#define bfin_read_USB_EP_NI3_RXCOUNT() bfin_read16(USB_EP_NI3_RXCOUNT)
-#define bfin_write_USB_EP_NI3_RXCOUNT(val) bfin_write16(USB_EP_NI3_RXCOUNT, val)
-#define bfin_read_USB_EP_NI3_TXTYPE()  bfin_read16(USB_EP_NI3_TXTYPE)
-#define bfin_write_USB_EP_NI3_TXTYPE(val) bfin_write16(USB_EP_NI3_TXTYPE, val)
-#define bfin_read_USB_EP_NI3_TXINTERVAL() bfin_read16(USB_EP_NI3_TXINTERVAL)
-#define bfin_write_USB_EP_NI3_TXINTERVAL(val) bfin_write16(USB_EP_NI3_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_RXTYPE()  bfin_read16(USB_EP_NI3_RXTYPE)
-#define bfin_write_USB_EP_NI3_RXTYPE(val) bfin_write16(USB_EP_NI3_RXTYPE, val)
-#define bfin_read_USB_EP_NI3_RXINTERVAL() bfin_read16(USB_EP_NI3_RXINTERVAL)
-#define bfin_write_USB_EP_NI3_RXINTERVAL(val) bfin_write16(USB_EP_NI3_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI3_TXCOUNT() bfin_read16(USB_EP_NI3_TXCOUNT)
-#define bfin_write_USB_EP_NI3_TXCOUNT(val) bfin_write16(USB_EP_NI3_TXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXMAXP()  bfin_read16(USB_EP_NI4_TXMAXP)
-#define bfin_write_USB_EP_NI4_TXMAXP(val) bfin_write16(USB_EP_NI4_TXMAXP, val)
-#define bfin_read_USB_EP_NI4_TXCSR()   bfin_read16(USB_EP_NI4_TXCSR)
-#define bfin_write_USB_EP_NI4_TXCSR(val) bfin_write16(USB_EP_NI4_TXCSR, val)
-#define bfin_read_USB_EP_NI4_RXMAXP()  bfin_read16(USB_EP_NI4_RXMAXP)
-#define bfin_write_USB_EP_NI4_RXMAXP(val) bfin_write16(USB_EP_NI4_RXMAXP, val)
-#define bfin_read_USB_EP_NI4_RXCSR()   bfin_read16(USB_EP_NI4_RXCSR)
-#define bfin_write_USB_EP_NI4_RXCSR(val) bfin_write16(USB_EP_NI4_RXCSR, val)
-#define bfin_read_USB_EP_NI4_RXCOUNT() bfin_read16(USB_EP_NI4_RXCOUNT)
-#define bfin_write_USB_EP_NI4_RXCOUNT(val) bfin_write16(USB_EP_NI4_RXCOUNT, val)
-#define bfin_read_USB_EP_NI4_TXTYPE()  bfin_read16(USB_EP_NI4_TXTYPE)
-#define bfin_write_USB_EP_NI4_TXTYPE(val) bfin_write16(USB_EP_NI4_TXTYPE, val)
-#define bfin_read_USB_EP_NI4_TXINTERVAL() bfin_read16(USB_EP_NI4_TXINTERVAL)
-#define bfin_write_USB_EP_NI4_TXINTERVAL(val) bfin_write16(USB_EP_NI4_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_RXTYPE()  bfin_read16(USB_EP_NI4_RXTYPE)
-#define bfin_write_USB_EP_NI4_RXTYPE(val) bfin_write16(USB_EP_NI4_RXTYPE, val)
-#define bfin_read_USB_EP_NI4_RXINTERVAL() bfin_read16(USB_EP_NI4_RXINTERVAL)
-#define bfin_write_USB_EP_NI4_RXINTERVAL(val) bfin_write16(USB_EP_NI4_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI4_TXCOUNT() bfin_read16(USB_EP_NI4_TXCOUNT)
-#define bfin_write_USB_EP_NI4_TXCOUNT(val) bfin_write16(USB_EP_NI4_TXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXMAXP()  bfin_read16(USB_EP_NI5_TXMAXP)
-#define bfin_write_USB_EP_NI5_TXMAXP(val) bfin_write16(USB_EP_NI5_TXMAXP, val)
-#define bfin_read_USB_EP_NI5_TXCSR()   bfin_read16(USB_EP_NI5_TXCSR)
-#define bfin_write_USB_EP_NI5_TXCSR(val) bfin_write16(USB_EP_NI5_TXCSR, val)
-#define bfin_read_USB_EP_NI5_RXMAXP()  bfin_read16(USB_EP_NI5_RXMAXP)
-#define bfin_write_USB_EP_NI5_RXMAXP(val) bfin_write16(USB_EP_NI5_RXMAXP, val)
-#define bfin_read_USB_EP_NI5_RXCSR()   bfin_read16(USB_EP_NI5_RXCSR)
-#define bfin_write_USB_EP_NI5_RXCSR(val) bfin_write16(USB_EP_NI5_RXCSR, val)
-#define bfin_read_USB_EP_NI5_RXCOUNT() bfin_read16(USB_EP_NI5_RXCOUNT)
-#define bfin_write_USB_EP_NI5_RXCOUNT(val) bfin_write16(USB_EP_NI5_RXCOUNT, val)
-#define bfin_read_USB_EP_NI5_TXTYPE()  bfin_read16(USB_EP_NI5_TXTYPE)
-#define bfin_write_USB_EP_NI5_TXTYPE(val) bfin_write16(USB_EP_NI5_TXTYPE, val)
-#define bfin_read_USB_EP_NI5_TXINTERVAL() bfin_read16(USB_EP_NI5_TXINTERVAL)
-#define bfin_write_USB_EP_NI5_TXINTERVAL(val) bfin_write16(USB_EP_NI5_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_RXTYPE()  bfin_read16(USB_EP_NI5_RXTYPE)
-#define bfin_write_USB_EP_NI5_RXTYPE(val) bfin_write16(USB_EP_NI5_RXTYPE, val)
-#define bfin_read_USB_EP_NI5_RXINTERVAL() bfin_read16(USB_EP_NI5_RXINTERVAL)
-#define bfin_write_USB_EP_NI5_RXINTERVAL(val) bfin_write16(USB_EP_NI5_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI5_TXCOUNT() bfin_read16(USB_EP_NI5_TXCOUNT)
-#define bfin_write_USB_EP_NI5_TXCOUNT(val) bfin_write16(USB_EP_NI5_TXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXMAXP()  bfin_read16(USB_EP_NI6_TXMAXP)
-#define bfin_write_USB_EP_NI6_TXMAXP(val) bfin_write16(USB_EP_NI6_TXMAXP, val)
-#define bfin_read_USB_EP_NI6_TXCSR()   bfin_read16(USB_EP_NI6_TXCSR)
-#define bfin_write_USB_EP_NI6_TXCSR(val) bfin_write16(USB_EP_NI6_TXCSR, val)
-#define bfin_read_USB_EP_NI6_RXMAXP()  bfin_read16(USB_EP_NI6_RXMAXP)
-#define bfin_write_USB_EP_NI6_RXMAXP(val) bfin_write16(USB_EP_NI6_RXMAXP, val)
-#define bfin_read_USB_EP_NI6_RXCSR()   bfin_read16(USB_EP_NI6_RXCSR)
-#define bfin_write_USB_EP_NI6_RXCSR(val) bfin_write16(USB_EP_NI6_RXCSR, val)
-#define bfin_read_USB_EP_NI6_RXCOUNT() bfin_read16(USB_EP_NI6_RXCOUNT)
-#define bfin_write_USB_EP_NI6_RXCOUNT(val) bfin_write16(USB_EP_NI6_RXCOUNT, val)
-#define bfin_read_USB_EP_NI6_TXTYPE()  bfin_read16(USB_EP_NI6_TXTYPE)
-#define bfin_write_USB_EP_NI6_TXTYPE(val) bfin_write16(USB_EP_NI6_TXTYPE, val)
-#define bfin_read_USB_EP_NI6_TXINTERVAL() bfin_read16(USB_EP_NI6_TXINTERVAL)
-#define bfin_write_USB_EP_NI6_TXINTERVAL(val) bfin_write16(USB_EP_NI6_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_RXTYPE()  bfin_read16(USB_EP_NI6_RXTYPE)
-#define bfin_write_USB_EP_NI6_RXTYPE(val) bfin_write16(USB_EP_NI6_RXTYPE, val)
-#define bfin_read_USB_EP_NI6_RXINTERVAL() bfin_read16(USB_EP_NI6_RXINTERVAL)
-#define bfin_write_USB_EP_NI6_RXINTERVAL(val) bfin_write16(USB_EP_NI6_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI6_TXCOUNT() bfin_read16(USB_EP_NI6_TXCOUNT)
-#define bfin_write_USB_EP_NI6_TXCOUNT(val) bfin_write16(USB_EP_NI6_TXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXMAXP()  bfin_read16(USB_EP_NI7_TXMAXP)
-#define bfin_write_USB_EP_NI7_TXMAXP(val) bfin_write16(USB_EP_NI7_TXMAXP, val)
-#define bfin_read_USB_EP_NI7_TXCSR()   bfin_read16(USB_EP_NI7_TXCSR)
-#define bfin_write_USB_EP_NI7_TXCSR(val) bfin_write16(USB_EP_NI7_TXCSR, val)
-#define bfin_read_USB_EP_NI7_RXMAXP()  bfin_read16(USB_EP_NI7_RXMAXP)
-#define bfin_write_USB_EP_NI7_RXMAXP(val) bfin_write16(USB_EP_NI7_RXMAXP, val)
-#define bfin_read_USB_EP_NI7_RXCSR()   bfin_read16(USB_EP_NI7_RXCSR)
-#define bfin_write_USB_EP_NI7_RXCSR(val) bfin_write16(USB_EP_NI7_RXCSR, val)
-#define bfin_read_USB_EP_NI7_RXCOUNT() bfin_read16(USB_EP_NI7_RXCOUNT)
-#define bfin_write_USB_EP_NI7_RXCOUNT(val) bfin_write16(USB_EP_NI7_RXCOUNT, val)
-#define bfin_read_USB_EP_NI7_TXTYPE()  bfin_read16(USB_EP_NI7_TXTYPE)
-#define bfin_write_USB_EP_NI7_TXTYPE(val) bfin_write16(USB_EP_NI7_TXTYPE, val)
-#define bfin_read_USB_EP_NI7_TXINTERVAL() bfin_read16(USB_EP_NI7_TXINTERVAL)
-#define bfin_write_USB_EP_NI7_TXINTERVAL(val) bfin_write16(USB_EP_NI7_TXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_RXTYPE()  bfin_read16(USB_EP_NI7_RXTYPE)
-#define bfin_write_USB_EP_NI7_RXTYPE(val) bfin_write16(USB_EP_NI7_RXTYPE, val)
-#define bfin_read_USB_EP_NI7_RXINTERVAL() bfin_read16(USB_EP_NI7_RXINTERVAL)
-#define bfin_write_USB_EP_NI7_RXINTERVAL(val) bfin_write16(USB_EP_NI7_RXINTERVAL, val)
-#define bfin_read_USB_EP_NI7_TXCOUNT() bfin_read16(USB_EP_NI7_TXCOUNT)
-#define bfin_write_USB_EP_NI7_TXCOUNT(val) bfin_write16(USB_EP_NI7_TXCOUNT, val)
-#define bfin_read_USB_DMA_INTERRUPT()  bfin_read16(USB_DMA_INTERRUPT)
-#define bfin_write_USB_DMA_INTERRUPT(val) bfin_write16(USB_DMA_INTERRUPT, val)
-#define bfin_read_USB_DMA0_CONTROL()   bfin_read16(USB_DMA0_CONTROL)
-#define bfin_write_USB_DMA0_CONTROL(val) bfin_write16(USB_DMA0_CONTROL, val)
-#define bfin_read_USB_DMA0_ADDRLOW()   bfin_read16(USB_DMA0_ADDRLOW)
-#define bfin_write_USB_DMA0_ADDRLOW(val) bfin_write16(USB_DMA0_ADDRLOW, val)
-#define bfin_read_USB_DMA0_ADDRHIGH()  bfin_read16(USB_DMA0_ADDRHIGH)
-#define bfin_write_USB_DMA0_ADDRHIGH(val) bfin_write16(USB_DMA0_ADDRHIGH, val)
-#define bfin_read_USB_DMA0_COUNTLOW()  bfin_read16(USB_DMA0_COUNTLOW)
-#define bfin_write_USB_DMA0_COUNTLOW(val) bfin_write16(USB_DMA0_COUNTLOW, val)
-#define bfin_read_USB_DMA0_COUNTHIGH() bfin_read16(USB_DMA0_COUNTHIGH)
-#define bfin_write_USB_DMA0_COUNTHIGH(val) bfin_write16(USB_DMA0_COUNTHIGH, val)
-#define bfin_read_USB_DMA1_CONTROL()   bfin_read16(USB_DMA1_CONTROL)
-#define bfin_write_USB_DMA1_CONTROL(val) bfin_write16(USB_DMA1_CONTROL, val)
-#define bfin_read_USB_DMA1_ADDRLOW()   bfin_read16(USB_DMA1_ADDRLOW)
-#define bfin_write_USB_DMA1_ADDRLOW(val) bfin_write16(USB_DMA1_ADDRLOW, val)
-#define bfin_read_USB_DMA1_ADDRHIGH()  bfin_read16(USB_DMA1_ADDRHIGH)
-#define bfin_write_USB_DMA1_ADDRHIGH(val) bfin_write16(USB_DMA1_ADDRHIGH, val)
-#define bfin_read_USB_DMA1_COUNTLOW()  bfin_read16(USB_DMA1_COUNTLOW)
-#define bfin_write_USB_DMA1_COUNTLOW(val) bfin_write16(USB_DMA1_COUNTLOW, val)
-#define bfin_read_USB_DMA1_COUNTHIGH() bfin_read16(USB_DMA1_COUNTHIGH)
-#define bfin_write_USB_DMA1_COUNTHIGH(val) bfin_write16(USB_DMA1_COUNTHIGH, val)
-#define bfin_read_USB_DMA2_CONTROL()   bfin_read16(USB_DMA2_CONTROL)
-#define bfin_write_USB_DMA2_CONTROL(val) bfin_write16(USB_DMA2_CONTROL, val)
-#define bfin_read_USB_DMA2_ADDRLOW()   bfin_read16(USB_DMA2_ADDRLOW)
-#define bfin_write_USB_DMA2_ADDRLOW(val) bfin_write16(USB_DMA2_ADDRLOW, val)
-#define bfin_read_USB_DMA2_ADDRHIGH()  bfin_read16(USB_DMA2_ADDRHIGH)
-#define bfin_write_USB_DMA2_ADDRHIGH(val) bfin_write16(USB_DMA2_ADDRHIGH, val)
-#define bfin_read_USB_DMA2_COUNTLOW()  bfin_read16(USB_DMA2_COUNTLOW)
-#define bfin_write_USB_DMA2_COUNTLOW(val) bfin_write16(USB_DMA2_COUNTLOW, val)
-#define bfin_read_USB_DMA2_COUNTHIGH() bfin_read16(USB_DMA2_COUNTHIGH)
-#define bfin_write_USB_DMA2_COUNTHIGH(val) bfin_write16(USB_DMA2_COUNTHIGH, val)
-#define bfin_read_USB_DMA3_CONTROL()   bfin_read16(USB_DMA3_CONTROL)
-#define bfin_write_USB_DMA3_CONTROL(val) bfin_write16(USB_DMA3_CONTROL, val)
-#define bfin_read_USB_DMA3_ADDRLOW()   bfin_read16(USB_DMA3_ADDRLOW)
-#define bfin_write_USB_DMA3_ADDRLOW(val) bfin_write16(USB_DMA3_ADDRLOW, val)
-#define bfin_read_USB_DMA3_ADDRHIGH()  bfin_read16(USB_DMA3_ADDRHIGH)
-#define bfin_write_USB_DMA3_ADDRHIGH(val) bfin_write16(USB_DMA3_ADDRHIGH, val)
-#define bfin_read_USB_DMA3_COUNTLOW()  bfin_read16(USB_DMA3_COUNTLOW)
-#define bfin_write_USB_DMA3_COUNTLOW(val) bfin_write16(USB_DMA3_COUNTLOW, val)
-#define bfin_read_USB_DMA3_COUNTHIGH() bfin_read16(USB_DMA3_COUNTHIGH)
-#define bfin_write_USB_DMA3_COUNTHIGH(val) bfin_write16(USB_DMA3_COUNTHIGH, val)
-#define bfin_read_USB_DMA4_CONTROL()   bfin_read16(USB_DMA4_CONTROL)
-#define bfin_write_USB_DMA4_CONTROL(val) bfin_write16(USB_DMA4_CONTROL, val)
-#define bfin_read_USB_DMA4_ADDRLOW()   bfin_read16(USB_DMA4_ADDRLOW)
-#define bfin_write_USB_DMA4_ADDRLOW(val) bfin_write16(USB_DMA4_ADDRLOW, val)
-#define bfin_read_USB_DMA4_ADDRHIGH()  bfin_read16(USB_DMA4_ADDRHIGH)
-#define bfin_write_USB_DMA4_ADDRHIGH(val) bfin_write16(USB_DMA4_ADDRHIGH, val)
-#define bfin_read_USB_DMA4_COUNTLOW()  bfin_read16(USB_DMA4_COUNTLOW)
-#define bfin_write_USB_DMA4_COUNTLOW(val) bfin_write16(USB_DMA4_COUNTLOW, val)
-#define bfin_read_USB_DMA4_COUNTHIGH() bfin_read16(USB_DMA4_COUNTHIGH)
-#define bfin_write_USB_DMA4_COUNTHIGH(val) bfin_write16(USB_DMA4_COUNTHIGH, val)
-#define bfin_read_USB_DMA5_CONTROL()   bfin_read16(USB_DMA5_CONTROL)
-#define bfin_write_USB_DMA5_CONTROL(val) bfin_write16(USB_DMA5_CONTROL, val)
-#define bfin_read_USB_DMA5_ADDRLOW()   bfin_read16(USB_DMA5_ADDRLOW)
-#define bfin_write_USB_DMA5_ADDRLOW(val) bfin_write16(USB_DMA5_ADDRLOW, val)
-#define bfin_read_USB_DMA5_ADDRHIGH()  bfin_read16(USB_DMA5_ADDRHIGH)
-#define bfin_write_USB_DMA5_ADDRHIGH(val) bfin_write16(USB_DMA5_ADDRHIGH, val)
-#define bfin_read_USB_DMA5_COUNTLOW()  bfin_read16(USB_DMA5_COUNTLOW)
-#define bfin_write_USB_DMA5_COUNTLOW(val) bfin_write16(USB_DMA5_COUNTLOW, val)
-#define bfin_read_USB_DMA5_COUNTHIGH() bfin_read16(USB_DMA5_COUNTHIGH)
-#define bfin_write_USB_DMA5_COUNTHIGH(val) bfin_write16(USB_DMA5_COUNTHIGH, val)
-#define bfin_read_USB_DMA6_CONTROL()   bfin_read16(USB_DMA6_CONTROL)
-#define bfin_write_USB_DMA6_CONTROL(val) bfin_write16(USB_DMA6_CONTROL, val)
-#define bfin_read_USB_DMA6_ADDRLOW()   bfin_read16(USB_DMA6_ADDRLOW)
-#define bfin_write_USB_DMA6_ADDRLOW(val) bfin_write16(USB_DMA6_ADDRLOW, val)
-#define bfin_read_USB_DMA6_ADDRHIGH()  bfin_read16(USB_DMA6_ADDRHIGH)
-#define bfin_write_USB_DMA6_ADDRHIGH(val) bfin_write16(USB_DMA6_ADDRHIGH, val)
-#define bfin_read_USB_DMA6_COUNTLOW()  bfin_read16(USB_DMA6_COUNTLOW)
-#define bfin_write_USB_DMA6_COUNTLOW(val) bfin_write16(USB_DMA6_COUNTLOW, val)
-#define bfin_read_USB_DMA6_COUNTHIGH() bfin_read16(USB_DMA6_COUNTHIGH)
-#define bfin_write_USB_DMA6_COUNTHIGH(val) bfin_write16(USB_DMA6_COUNTHIGH, val)
-#define bfin_read_USB_DMA7_CONTROL()   bfin_read16(USB_DMA7_CONTROL)
-#define bfin_write_USB_DMA7_CONTROL(val) bfin_write16(USB_DMA7_CONTROL, val)
-#define bfin_read_USB_DMA7_ADDRLOW()   bfin_read16(USB_DMA7_ADDRLOW)
-#define bfin_write_USB_DMA7_ADDRLOW(val) bfin_write16(USB_DMA7_ADDRLOW, val)
-#define bfin_read_USB_DMA7_ADDRHIGH()  bfin_read16(USB_DMA7_ADDRHIGH)
-#define bfin_write_USB_DMA7_ADDRHIGH(val) bfin_write16(USB_DMA7_ADDRHIGH, val)
-#define bfin_read_USB_DMA7_COUNTLOW()  bfin_read16(USB_DMA7_COUNTLOW)
-#define bfin_write_USB_DMA7_COUNTLOW(val) bfin_write16(USB_DMA7_COUNTLOW, val)
-#define bfin_read_USB_DMA7_COUNTHIGH() bfin_read16(USB_DMA7_COUNTHIGH)
-#define bfin_write_USB_DMA7_COUNTHIGH(val) bfin_write16(USB_DMA7_COUNTHIGH, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF524_proc__ */

+ 0 - 181
arch/blackfin/include/asm/mach-bf527/BF524_def.h

@@ -1,181 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF524_proc__
-#define __BFIN_DEF_ADSP_BF524_proc__
-
-#include "BF522_def.h"
-
-#define USB_FADDR                      0xFFC03800 /* Function address register */
-#define USB_POWER                      0xFFC03804 /* Power management register */
-#define USB_INTRTX                     0xFFC03808 /* Interrupt register for endpoint 0 and Tx endpoint 1 to 7 */
-#define USB_INTRRX                     0xFFC0380C /* Interrupt register for Rx endpoints 1 to 7 */
-#define USB_INTRTXE                    0xFFC03810 /* Interrupt enable register for IntrTx */
-#define USB_INTRRXE                    0xFFC03814 /* Interrupt enable register for IntrRx */
-#define USB_INTRUSB                    0xFFC03818 /* Interrupt register for common USB interrupts */
-#define USB_INTRUSBE                   0xFFC0381C /* Interrupt enable register for IntrUSB */
-#define USB_FRAME                      0xFFC03820 /* USB frame number */
-#define USB_INDEX                      0xFFC03824 /* Index register for selecting the indexed endpoint registers */
-#define USB_TESTMODE                   0xFFC03828 /* Enabled USB 20 test modes */
-#define USB_GLOBINTR                   0xFFC0382C /* Global Interrupt Mask register and Wakeup Exception Interrupt */
-#define USB_GLOBAL_CTL                 0xFFC03830 /* Global Clock Control for the core */
-#define USB_TX_MAX_PACKET              0xFFC03840 /* Maximum packet size for Host Tx endpoint */
-#define USB_CSR0                       0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_TXCSR                      0xFFC03844 /* Control Status register for endpoint 0 and Control Status register for Host Tx endpoint */
-#define USB_RX_MAX_PACKET              0xFFC03848 /* Maximum packet size for Host Rx endpoint */
-#define USB_RXCSR                      0xFFC0384C /* Control Status register for Host Rx endpoint */
-#define USB_COUNT0                     0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_RXCOUNT                    0xFFC03850 /* Number of bytes received in endpoint 0 FIFO and Number of bytes received in Host Tx endpoint */
-#define USB_TXTYPE                     0xFFC03854 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint */
-#define USB_NAKLIMIT0                  0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_TXINTERVAL                 0xFFC03858 /* Sets the NAK response timeout on Endpoint 0 and on Bulk transfers for Host Tx endpoint */
-#define USB_RXTYPE                     0xFFC0385C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint */
-#define USB_RXINTERVAL                 0xFFC03860 /* Sets the polling interval for Interrupt and Isochronous transfers or the NAK response timeout on Bulk transfers */
-#define USB_TXCOUNT                    0xFFC03868 /* Number of bytes to be written to the selected endpoint Tx FIFO */
-#define USB_EP0_FIFO                   0xFFC03880 /* Endpoint 0 FIFO */
-#define USB_EP1_FIFO                   0xFFC03888 /* Endpoint 1 FIFO */
-#define USB_EP2_FIFO                   0xFFC03890 /* Endpoint 2 FIFO */
-#define USB_EP3_FIFO                   0xFFC03898 /* Endpoint 3 FIFO */
-#define USB_EP4_FIFO                   0xFFC038A0 /* Endpoint 4 FIFO */
-#define USB_EP5_FIFO                   0xFFC038A8 /* Endpoint 5 FIFO */
-#define USB_EP6_FIFO                   0xFFC038B0 /* Endpoint 6 FIFO */
-#define USB_EP7_FIFO                   0xFFC038B8 /* Endpoint 7 FIFO */
-#define USB_OTG_DEV_CTL                0xFFC03900 /* OTG Device Control Register */
-#define USB_OTG_VBUS_IRQ               0xFFC03904 /* OTG VBUS Control Interrupts */
-#define USB_OTG_VBUS_MASK              0xFFC03908 /* VBUS Control Interrupt Enable */
-#define USB_LINKINFO                   0xFFC03948 /* Enables programming of some PHY-side delays */
-#define USB_VPLEN                      0xFFC0394C /* Determines duration of VBUS pulse for VBUS charging */
-#define USB_HS_EOF1                    0xFFC03950 /* Time buffer for High-Speed transactions */
-#define USB_FS_EOF1                    0xFFC03954 /* Time buffer for Full-Speed transactions */
-#define USB_LS_EOF1                    0xFFC03958 /* Time buffer for Low-Speed transactions */
-#define USB_APHY_CNTRL                 0xFFC039E0 /* Register that increases visibility of Analog PHY */
-#define USB_APHY_CALIB                 0xFFC039E4 /* Register used to set some calibration values */
-#define USB_APHY_CNTRL2                0xFFC039E8 /* Register used to prevent re-enumeration once Moab goes into hibernate mode */
-#define USB_PHY_TEST                   0xFFC039EC /* Used for reducing simulation time and simplifies FIFO testability */
-#define USB_PLLOSC_CTRL                0xFFC039F0 /* Used to program different parameters for USB PLL and Oscillator */
-#define USB_SRP_CLKDIV                 0xFFC039F4 /* Used to program clock divide value for the clock fed to the SRP detection logic */
-#define USB_EP_NI0_TXMAXP              0xFFC03A00 /* Maximum packet size for Host Tx endpoint0 */
-#define USB_EP_NI0_TXCSR               0xFFC03A04 /* Control Status register for endpoint 0 */
-#define USB_EP_NI0_RXMAXP              0xFFC03A08 /* Maximum packet size for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCSR               0xFFC03A0C /* Control Status register for Host Rx endpoint0 */
-#define USB_EP_NI0_RXCOUNT             0xFFC03A10 /* Number of bytes received in endpoint 0 FIFO */
-#define USB_EP_NI0_TXTYPE              0xFFC03A14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint0 */
-#define USB_EP_NI0_TXINTERVAL          0xFFC03A18 /* Sets the NAK response timeout on Endpoint 0 */
-#define USB_EP_NI0_RXTYPE              0xFFC03A1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint0 */
-#define USB_EP_NI0_RXINTERVAL          0xFFC03A20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint0 */
-#define USB_EP_NI0_TXCOUNT             0xFFC03A28 /* Number of bytes to be written to the endpoint0 Tx FIFO */
-#define USB_EP_NI1_TXMAXP              0xFFC03A40 /* Maximum packet size for Host Tx endpoint1 */
-#define USB_EP_NI1_TXCSR               0xFFC03A44 /* Control Status register for endpoint1 */
-#define USB_EP_NI1_RXMAXP              0xFFC03A48 /* Maximum packet size for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCSR               0xFFC03A4C /* Control Status register for Host Rx endpoint1 */
-#define USB_EP_NI1_RXCOUNT             0xFFC03A50 /* Number of bytes received in endpoint1 FIFO */
-#define USB_EP_NI1_TXTYPE              0xFFC03A54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint1 */
-#define USB_EP_NI1_TXINTERVAL          0xFFC03A58 /* Sets the NAK response timeout on Endpoint1 */
-#define USB_EP_NI1_RXTYPE              0xFFC03A5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint1 */
-#define USB_EP_NI1_RXINTERVAL          0xFFC03A60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint1 */
-#define USB_EP_NI1_TXCOUNT             0xFFC03A68 /* Number of bytes to be written to the+H102 endpoint1 Tx FIFO */
-#define USB_EP_NI2_TXMAXP              0xFFC03A80 /* Maximum packet size for Host Tx endpoint2 */
-#define USB_EP_NI2_TXCSR               0xFFC03A84 /* Control Status register for endpoint2 */
-#define USB_EP_NI2_RXMAXP              0xFFC03A88 /* Maximum packet size for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCSR               0xFFC03A8C /* Control Status register for Host Rx endpoint2 */
-#define USB_EP_NI2_RXCOUNT             0xFFC03A90 /* Number of bytes received in endpoint2 FIFO */
-#define USB_EP_NI2_TXTYPE              0xFFC03A94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint2 */
-#define USB_EP_NI2_TXINTERVAL          0xFFC03A98 /* Sets the NAK response timeout on Endpoint2 */
-#define USB_EP_NI2_RXTYPE              0xFFC03A9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint2 */
-#define USB_EP_NI2_RXINTERVAL          0xFFC03AA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint2 */
-#define USB_EP_NI2_TXCOUNT             0xFFC03AA8 /* Number of bytes to be written to the endpoint2 Tx FIFO */
-#define USB_EP_NI3_TXMAXP              0xFFC03AC0 /* Maximum packet size for Host Tx endpoint3 */
-#define USB_EP_NI3_TXCSR               0xFFC03AC4 /* Control Status register for endpoint3 */
-#define USB_EP_NI3_RXMAXP              0xFFC03AC8 /* Maximum packet size for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCSR               0xFFC03ACC /* Control Status register for Host Rx endpoint3 */
-#define USB_EP_NI3_RXCOUNT             0xFFC03AD0 /* Number of bytes received in endpoint3 FIFO */
-#define USB_EP_NI3_TXTYPE              0xFFC03AD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint3 */
-#define USB_EP_NI3_TXINTERVAL          0xFFC03AD8 /* Sets the NAK response timeout on Endpoint3 */
-#define USB_EP_NI3_RXTYPE              0xFFC03ADC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint3 */
-#define USB_EP_NI3_RXINTERVAL          0xFFC03AE0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint3 */
-#define USB_EP_NI3_TXCOUNT             0xFFC03AE8 /* Number of bytes to be written to the H124endpoint3 Tx FIFO */
-#define USB_EP_NI4_TXMAXP              0xFFC03B00 /* Maximum packet size for Host Tx endpoint4 */
-#define USB_EP_NI4_TXCSR               0xFFC03B04 /* Control Status register for endpoint4 */
-#define USB_EP_NI4_RXMAXP              0xFFC03B08 /* Maximum packet size for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCSR               0xFFC03B0C /* Control Status register for Host Rx endpoint4 */
-#define USB_EP_NI4_RXCOUNT             0xFFC03B10 /* Number of bytes received in endpoint4 FIFO */
-#define USB_EP_NI4_TXTYPE              0xFFC03B14 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint4 */
-#define USB_EP_NI4_TXINTERVAL          0xFFC03B18 /* Sets the NAK response timeout on Endpoint4 */
-#define USB_EP_NI4_RXTYPE              0xFFC03B1C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint4 */
-#define USB_EP_NI4_RXINTERVAL          0xFFC03B20 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint4 */
-#define USB_EP_NI4_TXCOUNT             0xFFC03B28 /* Number of bytes to be written to the endpoint4 Tx FIFO */
-#define USB_EP_NI5_TXMAXP              0xFFC03B40 /* Maximum packet size for Host Tx endpoint5 */
-#define USB_EP_NI5_TXCSR               0xFFC03B44 /* Control Status register for endpoint5 */
-#define USB_EP_NI5_RXMAXP              0xFFC03B48 /* Maximum packet size for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCSR               0xFFC03B4C /* Control Status register for Host Rx endpoint5 */
-#define USB_EP_NI5_RXCOUNT             0xFFC03B50 /* Number of bytes received in endpoint5 FIFO */
-#define USB_EP_NI5_TXTYPE              0xFFC03B54 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint5 */
-#define USB_EP_NI5_TXINTERVAL          0xFFC03B58 /* Sets the NAK response timeout on Endpoint5 */
-#define USB_EP_NI5_RXTYPE              0xFFC03B5C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint5 */
-#define USB_EP_NI5_RXINTERVAL          0xFFC03B60 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint5 */
-#define USB_EP_NI5_TXCOUNT             0xFFC03B68 /* Number of bytes to be written to the endpoint5 Tx FIFO */
-#define USB_EP_NI6_TXMAXP              0xFFC03B80 /* Maximum packet size for Host Tx endpoint6 */
-#define USB_EP_NI6_TXCSR               0xFFC03B84 /* Control Status register for endpoint6 */
-#define USB_EP_NI6_RXMAXP              0xFFC03B88 /* Maximum packet size for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCSR               0xFFC03B8C /* Control Status register for Host Rx endpoint6 */
-#define USB_EP_NI6_RXCOUNT             0xFFC03B90 /* Number of bytes received in endpoint6 FIFO */
-#define USB_EP_NI6_TXTYPE              0xFFC03B94 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint6 */
-#define USB_EP_NI6_TXINTERVAL          0xFFC03B98 /* Sets the NAK response timeout on Endpoint6 */
-#define USB_EP_NI6_RXTYPE              0xFFC03B9C /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint6 */
-#define USB_EP_NI6_RXINTERVAL          0xFFC03BA0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint6 */
-#define USB_EP_NI6_TXCOUNT             0xFFC03BA8 /* Number of bytes to be written to the endpoint6 Tx FIFO */
-#define USB_EP_NI7_TXMAXP              0xFFC03BC0 /* Maximum packet size for Host Tx endpoint7 */
-#define USB_EP_NI7_TXCSR               0xFFC03BC4 /* Control Status register for endpoint7 */
-#define USB_EP_NI7_RXMAXP              0xFFC03BC8 /* Maximum packet size for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCSR               0xFFC03BCC /* Control Status register for Host Rx endpoint7 */
-#define USB_EP_NI7_RXCOUNT             0xFFC03BD0 /* Number of bytes received in endpoint7 FIFO */
-#define USB_EP_NI7_TXTYPE              0xFFC03BD4 /* Sets the transaction protocol and peripheral endpoint number for the Host Tx endpoint7 */
-#define USB_EP_NI7_TXINTERVAL          0xFFC03BD8 /* Sets the NAK response timeout on Endpoint7 */
-#define USB_EP_NI7_RXTYPE              0xFFC03BDC /* Sets the transaction protocol and peripheral endpoint number for the Host Rx endpoint7 */
-#define USB_EP_NI7_RXINTERVAL          0xFFC03BF0 /* Sets the polling interval for Interrupt/Isochronous transfers or the NAK response timeout on Bulk transfers for Host Rx endpoint7 */
-#define USB_EP_NI7_TXCOUNT             0xFFC03BF8 /* Number of bytes to be written to the endpoint7 Tx FIFO */
-#define USB_DMA_INTERRUPT              0xFFC03C00 /* Indicates pending interrupts for the DMA channels */
-#define USB_DMA0_CONTROL               0xFFC03C04 /* DMA master channel 0 configuration */
-#define USB_DMA0_ADDRLOW               0xFFC03C08 /* Lower 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_ADDRHIGH              0xFFC03C0C /* Upper 16-bits of memory source/destination address for DMA master channel 0 */
-#define USB_DMA0_COUNTLOW              0xFFC03C10 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA0_COUNTHIGH             0xFFC03C14 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 0 */
-#define USB_DMA1_CONTROL               0xFFC03C24 /* DMA master channel 1 configuration */
-#define USB_DMA1_ADDRLOW               0xFFC03C28 /* Lower 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_ADDRHIGH              0xFFC03C2C /* Upper 16-bits of memory source/destination address for DMA master channel 1 */
-#define USB_DMA1_COUNTLOW              0xFFC03C30 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA1_COUNTHIGH             0xFFC03C34 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 1 */
-#define USB_DMA2_CONTROL               0xFFC03C44 /* DMA master channel 2 configuration */
-#define USB_DMA2_ADDRLOW               0xFFC03C48 /* Lower 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_ADDRHIGH              0xFFC03C4C /* Upper 16-bits of memory source/destination address for DMA master channel 2 */
-#define USB_DMA2_COUNTLOW              0xFFC03C50 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA2_COUNTHIGH             0xFFC03C54 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 2 */
-#define USB_DMA3_CONTROL               0xFFC03C64 /* DMA master channel 3 configuration */
-#define USB_DMA3_ADDRLOW               0xFFC03C68 /* Lower 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_ADDRHIGH              0xFFC03C6C /* Upper 16-bits of memory source/destination address for DMA master channel 3 */
-#define USB_DMA3_COUNTLOW              0xFFC03C70 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA3_COUNTHIGH             0xFFC03C74 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 3 */
-#define USB_DMA4_CONTROL               0xFFC03C84 /* DMA master channel 4 configuration */
-#define USB_DMA4_ADDRLOW               0xFFC03C88 /* Lower 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_ADDRHIGH              0xFFC03C8C /* Upper 16-bits of memory source/destination address for DMA master channel 4 */
-#define USB_DMA4_COUNTLOW              0xFFC03C90 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA4_COUNTHIGH             0xFFC03C94 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 4 */
-#define USB_DMA5_CONTROL               0xFFC03CA4 /* DMA master channel 5 configuration */
-#define USB_DMA5_ADDRLOW               0xFFC03CA8 /* Lower 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_ADDRHIGH              0xFFC03CAC /* Upper 16-bits of memory source/destination address for DMA master channel 5 */
-#define USB_DMA5_COUNTLOW              0xFFC03CB0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA5_COUNTHIGH             0xFFC03CB4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 5 */
-#define USB_DMA6_CONTROL               0xFFC03CC4 /* DMA master channel 6 configuration */
-#define USB_DMA6_ADDRLOW               0xFFC03CC8 /* Lower 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_ADDRHIGH              0xFFC03CCC /* Upper 16-bits of memory source/destination address for DMA master channel 6 */
-#define USB_DMA6_COUNTLOW              0xFFC03CD0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA6_COUNTHIGH             0xFFC03CD4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 6 */
-#define USB_DMA7_CONTROL               0xFFC03CE4 /* DMA master channel 7 configuration */
-#define USB_DMA7_ADDRLOW               0xFFC03CE8 /* Lower 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_ADDRHIGH              0xFFC03CEC /* Upper 16-bits of memory source/destination address for DMA master channel 7 */
-#define USB_DMA7_COUNTLOW              0xFFC03CF0 /* Lower 16-bits of byte count of DMA transfer for DMA master channel 7 */
-#define USB_DMA7_COUNTHIGH             0xFFC03CF4 /* Upper 16-bits of byte count of DMA transfer for DMA master channel 7 */
-
-#endif /* __BFIN_DEF_ADSP_BF524_proc__ */

+ 0 - 1
arch/blackfin/include/asm/mach-bf527/BF525_cdef.h

@@ -1 +0,0 @@
-#include "BF524_cdef.h"

+ 0 - 1
arch/blackfin/include/asm/mach-bf527/BF525_def.h

@@ -1 +0,0 @@
-#include "BF524_def.h"

+ 0 - 170
arch/blackfin/include/asm/mach-bf527/BF526_cdef.h

@@ -1,170 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF526_proc__
-#define __BFIN_CDEF_ADSP_BF526_proc__
-
-#include "BF524_cdef.h"
-
-#define bfin_read_EMAC_OPMODE()        bfin_read32(EMAC_OPMODE)
-#define bfin_write_EMAC_OPMODE(val)    bfin_write32(EMAC_OPMODE, val)
-#define bfin_read_EMAC_ADDRLO()        bfin_read32(EMAC_ADDRLO)
-#define bfin_write_EMAC_ADDRLO(val)    bfin_write32(EMAC_ADDRLO, val)
-#define bfin_read_EMAC_ADDRHI()        bfin_read32(EMAC_ADDRHI)
-#define bfin_write_EMAC_ADDRHI(val)    bfin_write32(EMAC_ADDRHI, val)
-#define bfin_read_EMAC_HASHLO()        bfin_read32(EMAC_HASHLO)
-#define bfin_write_EMAC_HASHLO(val)    bfin_write32(EMAC_HASHLO, val)
-#define bfin_read_EMAC_HASHHI()        bfin_read32(EMAC_HASHHI)
-#define bfin_write_EMAC_HASHHI(val)    bfin_write32(EMAC_HASHHI, val)
-#define bfin_read_EMAC_STAADD()        bfin_read32(EMAC_STAADD)
-#define bfin_write_EMAC_STAADD(val)    bfin_write32(EMAC_STAADD, val)
-#define bfin_read_EMAC_STADAT()        bfin_read32(EMAC_STADAT)
-#define bfin_write_EMAC_STADAT(val)    bfin_write32(EMAC_STADAT, val)
-#define bfin_read_EMAC_FLC()           bfin_read32(EMAC_FLC)
-#define bfin_write_EMAC_FLC(val)       bfin_write32(EMAC_FLC, val)
-#define bfin_read_EMAC_VLAN1()         bfin_read32(EMAC_VLAN1)
-#define bfin_write_EMAC_VLAN1(val)     bfin_write32(EMAC_VLAN1, val)
-#define bfin_read_EMAC_VLAN2()         bfin_read32(EMAC_VLAN2)
-#define bfin_write_EMAC_VLAN2(val)     bfin_write32(EMAC_VLAN2, val)
-#define bfin_read_EMAC_WKUP_CTL()      bfin_read32(EMAC_WKUP_CTL)
-#define bfin_write_EMAC_WKUP_CTL(val)  bfin_write32(EMAC_WKUP_CTL, val)
-#define bfin_read_EMAC_WKUP_FFMSK0()   bfin_read32(EMAC_WKUP_FFMSK0)
-#define bfin_write_EMAC_WKUP_FFMSK0(val) bfin_write32(EMAC_WKUP_FFMSK0, val)
-#define bfin_read_EMAC_WKUP_FFMSK1()   bfin_read32(EMAC_WKUP_FFMSK1)
-#define bfin_write_EMAC_WKUP_FFMSK1(val) bfin_write32(EMAC_WKUP_FFMSK1, val)
-#define bfin_read_EMAC_WKUP_FFMSK2()   bfin_read32(EMAC_WKUP_FFMSK2)
-#define bfin_write_EMAC_WKUP_FFMSK2(val) bfin_write32(EMAC_WKUP_FFMSK2, val)
-#define bfin_read_EMAC_WKUP_FFMSK3()   bfin_read32(EMAC_WKUP_FFMSK3)
-#define bfin_write_EMAC_WKUP_FFMSK3(val) bfin_write32(EMAC_WKUP_FFMSK3, val)
-#define bfin_read_EMAC_WKUP_FFCMD()    bfin_read32(EMAC_WKUP_FFCMD)
-#define bfin_write_EMAC_WKUP_FFCMD(val) bfin_write32(EMAC_WKUP_FFCMD, val)
-#define bfin_read_EMAC_WKUP_FFOFF()    bfin_read32(EMAC_WKUP_FFOFF)
-#define bfin_write_EMAC_WKUP_FFOFF(val) bfin_write32(EMAC_WKUP_FFOFF, val)
-#define bfin_read_EMAC_WKUP_FFCRC0()   bfin_read32(EMAC_WKUP_FFCRC0)
-#define bfin_write_EMAC_WKUP_FFCRC0(val) bfin_write32(EMAC_WKUP_FFCRC0, val)
-#define bfin_read_EMAC_WKUP_FFCRC1()   bfin_read32(EMAC_WKUP_FFCRC1)
-#define bfin_write_EMAC_WKUP_FFCRC1(val) bfin_write32(EMAC_WKUP_FFCRC1, val)
-#define bfin_read_EMAC_SYSCTL()        bfin_read32(EMAC_SYSCTL)
-#define bfin_write_EMAC_SYSCTL(val)    bfin_write32(EMAC_SYSCTL, val)
-#define bfin_read_EMAC_SYSTAT()        bfin_read32(EMAC_SYSTAT)
-#define bfin_write_EMAC_SYSTAT(val)    bfin_write32(EMAC_SYSTAT, val)
-#define bfin_read_EMAC_RX_STAT()       bfin_read32(EMAC_RX_STAT)
-#define bfin_write_EMAC_RX_STAT(val)   bfin_write32(EMAC_RX_STAT, val)
-#define bfin_read_EMAC_RX_STKY()       bfin_read32(EMAC_RX_STKY)
-#define bfin_write_EMAC_RX_STKY(val)   bfin_write32(EMAC_RX_STKY, val)
-#define bfin_read_EMAC_RX_IRQE()       bfin_read32(EMAC_RX_IRQE)
-#define bfin_write_EMAC_RX_IRQE(val)   bfin_write32(EMAC_RX_IRQE, val)
-#define bfin_read_EMAC_TX_STAT()       bfin_read32(EMAC_TX_STAT)
-#define bfin_write_EMAC_TX_STAT(val)   bfin_write32(EMAC_TX_STAT, val)
-#define bfin_read_EMAC_TX_STKY()       bfin_read32(EMAC_TX_STKY)
-#define bfin_write_EMAC_TX_STKY(val)   bfin_write32(EMAC_TX_STKY, val)
-#define bfin_read_EMAC_TX_IRQE()       bfin_read32(EMAC_TX_IRQE)
-#define bfin_write_EMAC_TX_IRQE(val)   bfin_write32(EMAC_TX_IRQE, val)
-#define bfin_read_EMAC_MMC_CTL()       bfin_read32(EMAC_MMC_CTL)
-#define bfin_write_EMAC_MMC_CTL(val)   bfin_write32(EMAC_MMC_CTL, val)
-#define bfin_read_EMAC_MMC_RIRQS()     bfin_read32(EMAC_MMC_RIRQS)
-#define bfin_write_EMAC_MMC_RIRQS(val) bfin_write32(EMAC_MMC_RIRQS, val)
-#define bfin_read_EMAC_MMC_RIRQE()     bfin_read32(EMAC_MMC_RIRQE)
-#define bfin_write_EMAC_MMC_RIRQE(val) bfin_write32(EMAC_MMC_RIRQE, val)
-#define bfin_read_EMAC_MMC_TIRQS()     bfin_read32(EMAC_MMC_TIRQS)
-#define bfin_write_EMAC_MMC_TIRQS(val) bfin_write32(EMAC_MMC_TIRQS, val)
-#define bfin_read_EMAC_MMC_TIRQE()     bfin_read32(EMAC_MMC_TIRQE)
-#define bfin_write_EMAC_MMC_TIRQE(val) bfin_write32(EMAC_MMC_TIRQE, val)
-#define bfin_read_EMAC_RXC_OK()        bfin_read32(EMAC_RXC_OK)
-#define bfin_write_EMAC_RXC_OK(val)    bfin_write32(EMAC_RXC_OK, val)
-#define bfin_read_EMAC_RXC_FCS()       bfin_read32(EMAC_RXC_FCS)
-#define bfin_write_EMAC_RXC_FCS(val)   bfin_write32(EMAC_RXC_FCS, val)
-#define bfin_read_EMAC_RXC_ALIGN()     bfin_read32(EMAC_RXC_ALIGN)
-#define bfin_write_EMAC_RXC_ALIGN(val) bfin_write32(EMAC_RXC_ALIGN, val)
-#define bfin_read_EMAC_RXC_OCTET()     bfin_read32(EMAC_RXC_OCTET)
-#define bfin_write_EMAC_RXC_OCTET(val) bfin_write32(EMAC_RXC_OCTET, val)
-#define bfin_read_EMAC_RXC_DMAOVF()    bfin_read32(EMAC_RXC_DMAOVF)
-#define bfin_write_EMAC_RXC_DMAOVF(val) bfin_write32(EMAC_RXC_DMAOVF, val)
-#define bfin_read_EMAC_RXC_UNICST()    bfin_read32(EMAC_RXC_UNICST)
-#define bfin_write_EMAC_RXC_UNICST(val) bfin_write32(EMAC_RXC_UNICST, val)
-#define bfin_read_EMAC_RXC_MULTI()     bfin_read32(EMAC_RXC_MULTI)
-#define bfin_write_EMAC_RXC_MULTI(val) bfin_write32(EMAC_RXC_MULTI, val)
-#define bfin_read_EMAC_RXC_BROAD()     bfin_read32(EMAC_RXC_BROAD)
-#define bfin_write_EMAC_RXC_BROAD(val) bfin_write32(EMAC_RXC_BROAD, val)
-#define bfin_read_EMAC_RXC_LNERRI()    bfin_read32(EMAC_RXC_LNERRI)
-#define bfin_write_EMAC_RXC_LNERRI(val) bfin_write32(EMAC_RXC_LNERRI, val)
-#define bfin_read_EMAC_RXC_LNERRO()    bfin_read32(EMAC_RXC_LNERRO)
-#define bfin_write_EMAC_RXC_LNERRO(val) bfin_write32(EMAC_RXC_LNERRO, val)
-#define bfin_read_EMAC_RXC_LONG()      bfin_read32(EMAC_RXC_LONG)
-#define bfin_write_EMAC_RXC_LONG(val)  bfin_write32(EMAC_RXC_LONG, val)
-#define bfin_read_EMAC_RXC_MACCTL()    bfin_read32(EMAC_RXC_MACCTL)
-#define bfin_write_EMAC_RXC_MACCTL(val) bfin_write32(EMAC_RXC_MACCTL, val)
-#define bfin_read_EMAC_RXC_OPCODE()    bfin_read32(EMAC_RXC_OPCODE)
-#define bfin_write_EMAC_RXC_OPCODE(val) bfin_write32(EMAC_RXC_OPCODE, val)
-#define bfin_read_EMAC_RXC_PAUSE()     bfin_read32(EMAC_RXC_PAUSE)
-#define bfin_write_EMAC_RXC_PAUSE(val) bfin_write32(EMAC_RXC_PAUSE, val)
-#define bfin_read_EMAC_RXC_ALLFRM()    bfin_read32(EMAC_RXC_ALLFRM)
-#define bfin_write_EMAC_RXC_ALLFRM(val) bfin_write32(EMAC_RXC_ALLFRM, val)
-#define bfin_read_EMAC_RXC_ALLOCT()    bfin_read32(EMAC_RXC_ALLOCT)
-#define bfin_write_EMAC_RXC_ALLOCT(val) bfin_write32(EMAC_RXC_ALLOCT, val)
-#define bfin_read_EMAC_RXC_TYPED()     bfin_read32(EMAC_RXC_TYPED)
-#define bfin_write_EMAC_RXC_TYPED(val) bfin_write32(EMAC_RXC_TYPED, val)
-#define bfin_read_EMAC_RXC_SHORT()     bfin_read32(EMAC_RXC_SHORT)
-#define bfin_write_EMAC_RXC_SHORT(val) bfin_write32(EMAC_RXC_SHORT, val)
-#define bfin_read_EMAC_RXC_EQ64()      bfin_read32(EMAC_RXC_EQ64)
-#define bfin_write_EMAC_RXC_EQ64(val)  bfin_write32(EMAC_RXC_EQ64, val)
-#define bfin_read_EMAC_RXC_LT128()     bfin_read32(EMAC_RXC_LT128)
-#define bfin_write_EMAC_RXC_LT128(val) bfin_write32(EMAC_RXC_LT128, val)
-#define bfin_read_EMAC_RXC_LT256()     bfin_read32(EMAC_RXC_LT256)
-#define bfin_write_EMAC_RXC_LT256(val) bfin_write32(EMAC_RXC_LT256, val)
-#define bfin_read_EMAC_RXC_LT512()     bfin_read32(EMAC_RXC_LT512)
-#define bfin_write_EMAC_RXC_LT512(val) bfin_write32(EMAC_RXC_LT512, val)
-#define bfin_read_EMAC_RXC_LT1024()    bfin_read32(EMAC_RXC_LT1024)
-#define bfin_write_EMAC_RXC_LT1024(val) bfin_write32(EMAC_RXC_LT1024, val)
-#define bfin_read_EMAC_RXC_GE1024()    bfin_read32(EMAC_RXC_GE1024)
-#define bfin_write_EMAC_RXC_GE1024(val) bfin_write32(EMAC_RXC_GE1024, val)
-#define bfin_read_EMAC_TXC_OK()        bfin_read32(EMAC_TXC_OK)
-#define bfin_write_EMAC_TXC_OK(val)    bfin_write32(EMAC_TXC_OK, val)
-#define bfin_read_EMAC_TXC_1COL()      bfin_read32(EMAC_TXC_1COL)
-#define bfin_write_EMAC_TXC_1COL(val)  bfin_write32(EMAC_TXC_1COL, val)
-#define bfin_read_EMAC_TXC_GT1COL()    bfin_read32(EMAC_TXC_GT1COL)
-#define bfin_write_EMAC_TXC_GT1COL(val) bfin_write32(EMAC_TXC_GT1COL, val)
-#define bfin_read_EMAC_TXC_OCTET()     bfin_read32(EMAC_TXC_OCTET)
-#define bfin_write_EMAC_TXC_OCTET(val) bfin_write32(EMAC_TXC_OCTET, val)
-#define bfin_read_EMAC_TXC_DEFER()     bfin_read32(EMAC_TXC_DEFER)
-#define bfin_write_EMAC_TXC_DEFER(val) bfin_write32(EMAC_TXC_DEFER, val)
-#define bfin_read_EMAC_TXC_LATECL()    bfin_read32(EMAC_TXC_LATECL)
-#define bfin_write_EMAC_TXC_LATECL(val) bfin_write32(EMAC_TXC_LATECL, val)
-#define bfin_read_EMAC_TXC_XS_COL()    bfin_read32(EMAC_TXC_XS_COL)
-#define bfin_write_EMAC_TXC_XS_COL(val) bfin_write32(EMAC_TXC_XS_COL, val)
-#define bfin_read_EMAC_TXC_DMAUND()    bfin_read32(EMAC_TXC_DMAUND)
-#define bfin_write_EMAC_TXC_DMAUND(val) bfin_write32(EMAC_TXC_DMAUND, val)
-#define bfin_read_EMAC_TXC_CRSERR()    bfin_read32(EMAC_TXC_CRSERR)
-#define bfin_write_EMAC_TXC_CRSERR(val) bfin_write32(EMAC_TXC_CRSERR, val)
-#define bfin_read_EMAC_TXC_UNICST()    bfin_read32(EMAC_TXC_UNICST)
-#define bfin_write_EMAC_TXC_UNICST(val) bfin_write32(EMAC_TXC_UNICST, val)
-#define bfin_read_EMAC_TXC_MULTI()     bfin_read32(EMAC_TXC_MULTI)
-#define bfin_write_EMAC_TXC_MULTI(val) bfin_write32(EMAC_TXC_MULTI, val)
-#define bfin_read_EMAC_TXC_BROAD()     bfin_read32(EMAC_TXC_BROAD)
-#define bfin_write_EMAC_TXC_BROAD(val) bfin_write32(EMAC_TXC_BROAD, val)
-#define bfin_read_EMAC_TXC_XS_DFR()    bfin_read32(EMAC_TXC_XS_DFR)
-#define bfin_write_EMAC_TXC_XS_DFR(val) bfin_write32(EMAC_TXC_XS_DFR, val)
-#define bfin_read_EMAC_TXC_MACCTL()    bfin_read32(EMAC_TXC_MACCTL)
-#define bfin_write_EMAC_TXC_MACCTL(val) bfin_write32(EMAC_TXC_MACCTL, val)
-#define bfin_read_EMAC_TXC_ALLFRM()    bfin_read32(EMAC_TXC_ALLFRM)
-#define bfin_write_EMAC_TXC_ALLFRM(val) bfin_write32(EMAC_TXC_ALLFRM, val)
-#define bfin_read_EMAC_TXC_ALLOCT()    bfin_read32(EMAC_TXC_ALLOCT)
-#define bfin_write_EMAC_TXC_ALLOCT(val) bfin_write32(EMAC_TXC_ALLOCT, val)
-#define bfin_read_EMAC_TXC_EQ64()      bfin_read32(EMAC_TXC_EQ64)
-#define bfin_write_EMAC_TXC_EQ64(val)  bfin_write32(EMAC_TXC_EQ64, val)
-#define bfin_read_EMAC_TXC_LT128()     bfin_read32(EMAC_TXC_LT128)
-#define bfin_write_EMAC_TXC_LT128(val) bfin_write32(EMAC_TXC_LT128, val)
-#define bfin_read_EMAC_TXC_LT256()     bfin_read32(EMAC_TXC_LT256)
-#define bfin_write_EMAC_TXC_LT256(val) bfin_write32(EMAC_TXC_LT256, val)
-#define bfin_read_EMAC_TXC_LT512()     bfin_read32(EMAC_TXC_LT512)
-#define bfin_write_EMAC_TXC_LT512(val) bfin_write32(EMAC_TXC_LT512, val)
-#define bfin_read_EMAC_TXC_LT1024()    bfin_read32(EMAC_TXC_LT1024)
-#define bfin_write_EMAC_TXC_LT1024(val) bfin_write32(EMAC_TXC_LT1024, val)
-#define bfin_read_EMAC_TXC_GE1024()    bfin_read32(EMAC_TXC_GE1024)
-#define bfin_write_EMAC_TXC_GE1024(val) bfin_write32(EMAC_TXC_GE1024, val)
-#define bfin_read_EMAC_TXC_ABORT()     bfin_read32(EMAC_TXC_ABORT)
-#define bfin_write_EMAC_TXC_ABORT(val) bfin_write32(EMAC_TXC_ABORT, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF526_proc__ */

+ 0 - 91
arch/blackfin/include/asm/mach-bf527/BF526_def.h

@@ -1,91 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF526_proc__
-#define __BFIN_DEF_ADSP_BF526_proc__
-
-#include "BF524_def.h"
-
-#define EMAC_OPMODE                    0xFFC03000 /* Operating Mode Register */
-#define EMAC_ADDRLO                    0xFFC03004 /* Address Low (32 LSBs) Register */
-#define EMAC_ADDRHI                    0xFFC03008 /* Address High (16 MSBs) Register */
-#define EMAC_HASHLO                    0xFFC0300C /* Multicast Hash Table Low (Bins 31-0) Register */
-#define EMAC_HASHHI                    0xFFC03010 /* Multicast Hash Table High (Bins 63-32) Register */
-#define EMAC_STAADD                    0xFFC03014 /* Station Management Address Register */
-#define EMAC_STADAT                    0xFFC03018 /* Station Management Data Register */
-#define EMAC_FLC                       0xFFC0301C /* Flow Control Register */
-#define EMAC_VLAN1                     0xFFC03020 /* VLAN1 Tag Register */
-#define EMAC_VLAN2                     0xFFC03024 /* VLAN2 Tag Register */
-#define EMAC_WKUP_CTL                  0xFFC0302C /* Wake-Up Control/Status Register */
-#define EMAC_WKUP_FFMSK0               0xFFC03030 /* Wake-Up Frame Filter 0 Byte Mask Register */
-#define EMAC_WKUP_FFMSK1               0xFFC03034 /* Wake-Up Frame Filter 1 Byte Mask Register */
-#define EMAC_WKUP_FFMSK2               0xFFC03038 /* Wake-Up Frame Filter 2 Byte Mask Register */
-#define EMAC_WKUP_FFMSK3               0xFFC0303C /* Wake-Up Frame Filter 3 Byte Mask Register */
-#define EMAC_WKUP_FFCMD                0xFFC03040 /* Wake-Up Frame Filter Commands Register */
-#define EMAC_WKUP_FFOFF                0xFFC03044 /* Wake-Up Frame Filter Offsets Register */
-#define EMAC_WKUP_FFCRC0               0xFFC03048 /* Wake-Up Frame Filter 0,1 CRC-16 Register */
-#define EMAC_WKUP_FFCRC1               0xFFC0304C /* Wake-Up Frame Filter 2,3 CRC-16 Register */
-#define EMAC_SYSCTL                    0xFFC03060 /* EMAC System Control Register */
-#define EMAC_SYSTAT                    0xFFC03064 /* EMAC System Status Register */
-#define EMAC_RX_STAT                   0xFFC03068 /* RX Current Frame Status Register */
-#define EMAC_RX_STKY                   0xFFC0306C /* RX Sticky Frame Status Register */
-#define EMAC_RX_IRQE                   0xFFC03070 /* RX Frame Status Interrupt Enables Register */
-#define EMAC_TX_STAT                   0xFFC03074 /* TX Current Frame Status Register */
-#define EMAC_TX_STKY                   0xFFC03078 /* TX Sticky Frame Status Register */
-#define EMAC_TX_IRQE                   0xFFC0307C /* TX Frame Status Interrupt Enables Register */
-#define EMAC_MMC_CTL                   0xFFC03080 /* MMC Counter Control Register */
-#define EMAC_MMC_RIRQS                 0xFFC03084 /* MMC RX Interrupt Status Register */
-#define EMAC_MMC_RIRQE                 0xFFC03088 /* MMC RX Interrupt Enables Register */
-#define EMAC_MMC_TIRQS                 0xFFC0308C /* MMC TX Interrupt Status Register */
-#define EMAC_MMC_TIRQE                 0xFFC03090 /* MMC TX Interrupt Enables Register */
-#define EMAC_RXC_OK                    0xFFC03100 /* RX Frame Successful Count */
-#define EMAC_RXC_FCS                   0xFFC03104 /* RX Frame FCS Failure Count */
-#define EMAC_RXC_ALIGN                 0xFFC03108 /* RX Alignment Error Count */
-#define EMAC_RXC_OCTET                 0xFFC0310C /* RX Octets Successfully Received Count */
-#define EMAC_RXC_DMAOVF                0xFFC03110 /* Internal MAC Sublayer Error RX Frame Count */
-#define EMAC_RXC_UNICST                0xFFC03114 /* Unicast RX Frame Count */
-#define EMAC_RXC_MULTI                 0xFFC03118 /* Multicast RX Frame Count */
-#define EMAC_RXC_BROAD                 0xFFC0311C /* Broadcast RX Frame Count */
-#define EMAC_RXC_LNERRI                0xFFC03120 /* RX Frame In Range Error Count */
-#define EMAC_RXC_LNERRO                0xFFC03124 /* RX Frame Out Of Range Error Count */
-#define EMAC_RXC_LONG                  0xFFC03128 /* RX Frame Too Long Count */
-#define EMAC_RXC_MACCTL                0xFFC0312C /* MAC Control RX Frame Count */
-#define EMAC_RXC_OPCODE                0xFFC03130 /* Unsupported Op-Code RX Frame Count */
-#define EMAC_RXC_PAUSE                 0xFFC03134 /* MAC Control Pause RX Frame Count */
-#define EMAC_RXC_ALLFRM                0xFFC03138 /* Overall RX Frame Count */
-#define EMAC_RXC_ALLOCT                0xFFC0313C /* Overall RX Octet Count */
-#define EMAC_RXC_TYPED                 0xFFC03140 /* Type/Length Consistent RX Frame Count  */
-#define EMAC_RXC_SHORT                 0xFFC03144 /* RX Frame Fragment Count - Byte Count x < 64 */
-#define EMAC_RXC_EQ64                  0xFFC03148 /* Good RX Frame Count - Byte Count x = 64 */
-#define EMAC_RXC_LT128                 0xFFC0314C /* Good RX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_RXC_LT256                 0xFFC03150 /* Good RX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_RXC_LT512                 0xFFC03154 /* Good RX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_RXC_LT1024                0xFFC03158 /* Good RX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_RXC_GE1024                0xFFC0315C /* Good RX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_OK                    0xFFC03180 /* TX Frame Successful Count */
-#define EMAC_TXC_1COL                  0xFFC03184 /* TX Frames Successful After Single Collision Count */
-#define EMAC_TXC_GT1COL                0xFFC03188 /* TX Frames Successful After Multiple Collisions Count */
-#define EMAC_TXC_OCTET                 0xFFC0318C /* TX Octets Successfully Received Count */
-#define EMAC_TXC_DEFER                 0xFFC03190 /* TX Frame Delayed Due To Busy Count */
-#define EMAC_TXC_LATECL                0xFFC03194 /* Late TX Collisions Count */
-#define EMAC_TXC_XS_COL                0xFFC03198 /* TX Frame Failed Due To Excessive Collisions Count */
-#define EMAC_TXC_DMAUND                0xFFC0319C /* Internal MAC Sublayer Error TX Frame Count */
-#define EMAC_TXC_CRSERR                0xFFC031A0 /* Carrier Sense Deasserted During TX Frame Count */
-#define EMAC_TXC_UNICST                0xFFC031A4 /* Unicast TX Frame Count */
-#define EMAC_TXC_MULTI                 0xFFC031A8 /* Multicast TX Frame Count */
-#define EMAC_TXC_BROAD                 0xFFC031AC /* Broadcast TX Frame Count */
-#define EMAC_TXC_XS_DFR                0xFFC031B0 /* TX Frames With Excessive Deferral Count */
-#define EMAC_TXC_MACCTL                0xFFC031B4 /* MAC Control TX Frame Count */
-#define EMAC_TXC_ALLFRM                0xFFC031B8 /* Overall TX Frame Count */
-#define EMAC_TXC_ALLOCT                0xFFC031BC /* Overall TX Octet Count */
-#define EMAC_TXC_EQ64                  0xFFC031C0 /* Good TX Frame Count - Byte Count x = 64 */
-#define EMAC_TXC_LT128                 0xFFC031C4 /* Good TX Frame Count - Byte Count  64 <= x < 128 */
-#define EMAC_TXC_LT256                 0xFFC031C8 /* Good TX Frame Count - Byte Count 128 <= x < 256 */
-#define EMAC_TXC_LT512                 0xFFC031CC /* Good TX Frame Count - Byte Count 256 <= x < 512 */
-#define EMAC_TXC_LT1024                0xFFC031D0 /* Good TX Frame Count - Byte Count 512 <= x < 1024 */
-#define EMAC_TXC_GE1024                0xFFC031D4 /* Good TX Frame Count - Byte Count x >= 1024 */
-#define EMAC_TXC_ABORT                 0xFFC031D8 /* Total TX Frames Aborted Count */
-
-#endif /* __BFIN_DEF_ADSP_BF526_proc__ */

+ 0 - 1
arch/blackfin/include/asm/mach-bf527/BF527_cdef.h

@@ -1 +0,0 @@
-#include "BF526_cdef.h"

+ 0 - 1
arch/blackfin/include/asm/mach-bf527/BF527_def.h

@@ -1 +0,0 @@
-#include "BF526_def.h"

+ 0 - 290
arch/blackfin/include/asm/mach-bf527/anomaly.h

@@ -1,290 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision F, 05/23/2011; ADSP-BF526 Blackfin Processor Anomaly List
- *  - Revision I, 05/23/2011; ADSP-BF527 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support old silicon - sorry */
-#if __SILICON_REVISION__ < 0
-# error will not work on BF526/BF527 silicon version
-#endif
-
-#if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
-# define ANOMALY_BF526 1
-#else
-# define ANOMALY_BF526 0
-#endif
-#if defined(__ADSPBF523__) || defined(__ADSPBF525__) || defined(__ADSPBF527__)
-# define ANOMALY_BF527 1
-#else
-# define ANOMALY_BF527 0
-#endif
-
-#define _ANOMALY_BF526(rev526) (ANOMALY_BF526 && __SILICON_REVISION__ rev526)
-#define _ANOMALY_BF527(rev527) (ANOMALY_BF527 && __SILICON_REVISION__ rev527)
-#define _ANOMALY_BF526_BF527(rev526, rev527) (_ANOMALY_BF526(rev526) || _ANOMALY_BF527(rev527))
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (1)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Access of OTP_STATUS During otp_write() Function */
-#define ANOMALY_05000328 (_ANOMALY_BF527(< 2))
-/* Host DMA Boot Modes Are Not Functional */
-#define ANOMALY_05000330 (_ANOMALY_BF527(< 2))
-/* Disallowed Configuration Prevents Subsequent Allowed Configuration on Host DMA Port */
-#define ANOMALY_05000337 (_ANOMALY_BF527(< 2))
-/* Ethernet MAC MDIO Reads Do Not Meet IEEE Specification */
-#define ANOMALY_05000341 (_ANOMALY_BF527(< 2))
-/* TWI May Not Operate Correctly Under Certain Signal Termination Conditions */
-#define ANOMALY_05000342 (_ANOMALY_BF527(< 2))
-/* USB Calibration Value Is Not Initialized */
-#define ANOMALY_05000346 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB Calibration Value to use */
-#define ANOMALY_05000346_value 0xE510
-/* Preboot Routine Incorrectly Alters Reset Value of USB Register */
-#define ANOMALY_05000347 (_ANOMALY_BF527(< 2))
-/* Security Features Are Not Functional */
-#define ANOMALY_05000348 (_ANOMALY_BF527(< 1))
-/* bfrom_SysControl() Firmware Function Performs Improper System Reset */
-#define ANOMALY_05000353 (_ANOMALY_BF526(< 1))
-/* Regulator Programming Blocked when Hibernate Wakeup Source Remains Active */
-#define ANOMALY_05000355 (_ANOMALY_BF527(< 2))
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (_ANOMALY_BF527(< 2))
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000364 (_ANOMALY_BF527(== 1))
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Incorrect Default CSEL Value in PLL_DIV */
-#define ANOMALY_05000368 (_ANOMALY_BF527(< 2))
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (_ANOMALY_BF527(< 2))
-/* Authentication Fails To Initiate */
-#define ANOMALY_05000376 (_ANOMALY_BF527(< 2))
-/* Data Read From L3 Memory by USB DMA May be Corrupted */
-#define ANOMALY_05000380 (_ANOMALY_BF527(< 2))
-/* 8-Bit NAND Flash Boot Mode Not Functional */
-#define ANOMALY_05000382 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Boot from OTP Memory Not Functional */
-#define ANOMALY_05000385 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Routine Not Functional */
-#define ANOMALY_05000386 (_ANOMALY_BF527(< 2))
-/* Programmable Preboot Settings Not Functional */
-#define ANOMALY_05000387 (_ANOMALY_BF527(< 2))
-/* CRC32 Checksum Support Not Functional */
-#define ANOMALY_05000388 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Reset Vector Must Not Be in SDRAM Memory Space */
-#define ANOMALY_05000389 (_ANOMALY_BF527(< 2))
-/* pTempCurrent Not Present in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000392 (_ANOMALY_BF527(< 2))
-/* Deprecated Value of dTempByteCount in ADI_BOOT_DATA Structure */
-#define ANOMALY_05000393 (_ANOMALY_BF527(< 2))
-/* Log Buffer Not Functional */
-#define ANOMALY_05000394 (_ANOMALY_BF527(< 2))
-/* Hook Routine Not Functional */
-#define ANOMALY_05000395 (_ANOMALY_BF527(< 2))
-/* Header Indirect Bit Not Functional */
-#define ANOMALY_05000396 (_ANOMALY_BF527(< 2))
-/* BK_ONES, BK_ZEROS, and BK_DATECODE Constants Not Functional */
-#define ANOMALY_05000397 (_ANOMALY_BF527(< 2))
-/* SWRESET, DFRESET and WDRESET Bits in the SYSCR Register Not Functional */
-#define ANOMALY_05000398 (_ANOMALY_BF527(< 2))
-/* BCODE_NOBOOT in BCODE Field of SYSCR Register Not Functional */
-#define ANOMALY_05000399 (_ANOMALY_BF527(< 2))
-/* PPI Data Signals D0 and D8 do not Tristate After Disabling PPI */
-#define ANOMALY_05000401 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Disallows Certain User Interrupts */
-#define ANOMALY_05000404 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox SESR Firmware Does Not Save/Restore Full Context */
-#define ANOMALY_05000405 (1)
-/* Lockbox SESR Firmware Arguments Are Not Retained After First Initialization */
-#define ANOMALY_05000407 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
-#define ANOMALY_05000408 (1)
-/* Lockbox firmware leaves MDMA0 channel enabled */
-#define ANOMALY_05000409 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Incorrect Default Internal Voltage Regulator Setting */
-#define ANOMALY_05000410 (_ANOMALY_BF527(< 2))
-/* bfrom_SysControl() Firmware Function Cannot be Used to Enter Power Saving Modes */
-#define ANOMALY_05000411 (_ANOMALY_BF526(< 1))
-/* OTP_CHECK_FOR_PREV_WRITE Bit is Not Functional in bfrom_OtpWrite() API */
-#define ANOMALY_05000414 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* DEB2_URGENT Bit Not Functional */
-#define ANOMALY_05000415 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* SPORT0 Ignores External TSCLK0 on PG14 When TMR6 is an Output */
-#define ANOMALY_05000417 (_ANOMALY_BF527(< 2))
-/* PPI Timing Requirements tSFSPE and tHFSPE Do Not Meet Data Sheet Specifications */
-#define ANOMALY_05000418 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* USB PLL_STABLE Bit May Not Accurately Reflect the USB PLL's Status */
-#define ANOMALY_05000420 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
-#define ANOMALY_05000421 (1)
-/* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
-#define ANOMALY_05000422 (_ANOMALY_BF526_BF527(> 0, > 1))
-/* Certain Ethernet Frames With Errors are Misclassified in RMII Mode */
-#define ANOMALY_05000423 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Internal Voltage Regulator Not Trimmed */
-#define ANOMALY_05000424 (_ANOMALY_BF527(< 2))
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* WB_EDGE Bit in NFC_IRQSTAT Incorrectly Reflects Buffer Status Instead of IRQ Status */
-#define ANOMALY_05000429 (_ANOMALY_BF526_BF527(< 1, < 2))
-/* Software System Reset Corrupts PLL_LOCKCNT Register */
-#define ANOMALY_05000430 (_ANOMALY_BF527(> 1))
-/* Incorrect Use of Stack in Lockbox Firmware During Authentication */
-#define ANOMALY_05000431 (1)
-/* bfrom_SysControl() Does Not Clear SIC_IWR1 Before Executing PLL Programming Sequence */
-#define ANOMALY_05000432 (_ANOMALY_BF526(< 1))
-/* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
-#define ANOMALY_05000434 (1)
-/* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
-#define ANOMALY_05000435 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* Preboot Cannot be Used to Alter the PLL_DIV Register */
-#define ANOMALY_05000439 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
-#define ANOMALY_05000440 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* OTP Write Accesses Not Supported */
-#define ANOMALY_05000442 (_ANOMALY_BF527(< 1))
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* The WURESET Bit in the SYSCR Register is not Functional */
-#define ANOMALY_05000445 (_ANOMALY_BF527(>= 0))
-/* USB DMA Short Packet Data Corruption */
-#define ANOMALY_05000450 (1)
-/* BCODE_QUICKBOOT, BCODE_ALLBOOT, and BCODE_FULLBOOT Settings in SYSCR Register Not Functional */
-#define ANOMALY_05000451 (_ANOMALY_BF527(>= 0))
-/* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
-#define ANOMALY_05000452 (_ANOMALY_BF526_BF527(< 1, >= 0))
-/* USB Receive Interrupt Is Not Generated in DMA Mode 1 */
-#define ANOMALY_05000456 (1)
-/* Host DMA Port Responds to Certain Bus Activity Without HOST_CE Assertion */
-#define ANOMALY_05000457 (1)
-/* USB DMA Mode 1 Failure When Multiple USB DMA Channels Are Concurrently Enabled */
-#define ANOMALY_05000460 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* USB Rx DMA Hang */
-#define ANOMALY_05000465 (1)
-/* TxPktRdy Bit Not Set for Transmit Endpoint When Core and DMA Access USB Endpoint FIFOs Simultaneously */
-#define ANOMALY_05000466 (1)
-/* Possible USB RX Data Corruption When Control & Data EP FIFOs are Accessed via the Core */
-#define ANOMALY_05000467 (1)
-/* PLL Latches Incorrect Settings During Reset */
-#define ANOMALY_05000469 (1)
-/* Incorrect Default MSEL Value in PLL_CTL */
-#define ANOMALY_05000472 (_ANOMALY_BF526(>= 0))
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* Possible USB Data Corruption When Multiple Endpoints Are Accessed by the Core */
-#define ANOMALY_05000483 (1)
-/* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
-#define ANOMALY_05000485 (_ANOMALY_BF526_BF527(< 2, >= 0))
-/* The CODEC Zero-Cross Detect Feature is not Functional */
-#define ANOMALY_05000487 (1)
-/* SPI Master Boot Can Fail Under Certain Conditions */
-#define ANOMALY_05000490 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
-#define ANOMALY_05000498 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000099 (0)
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000125 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000158 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000179 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000183 (0)
-#define ANOMALY_05000189 (0)
-#define ANOMALY_05000198 (0)
-#define ANOMALY_05000202 (0)
-#define ANOMALY_05000215 (0)
-#define ANOMALY_05000219 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000227 (0)
-#define ANOMALY_05000230 (0)
-#define ANOMALY_05000231 (0)
-#define ANOMALY_05000233 (0)
-#define ANOMALY_05000234 (0)
-#define ANOMALY_05000242 (0)
-#define ANOMALY_05000244 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000250 (0)
-#define ANOMALY_05000257 (0)
-#define ANOMALY_05000261 (0)
-#define ANOMALY_05000263 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000273 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000278 (0)
-#define ANOMALY_05000281 (0)
-#define ANOMALY_05000283 (0)
-#define ANOMALY_05000285 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000301 (0)
-#define ANOMALY_05000305 (0)
-#define ANOMALY_05000307 (0)
-#define ANOMALY_05000311 (0)
-#define ANOMALY_05000312 (0)
-#define ANOMALY_05000315 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000363 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000400 (0)
-#define ANOMALY_05000402 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-
-#endif

+ 0 - 6
arch/blackfin/include/asm/mach-bf527/def_local.h

@@ -1,6 +0,0 @@
-#include "gpio.h"
-#include "mem_map.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define CONFIG_BF52x 1	/* Linux glue */

+ 0 - 65
arch/blackfin/include/asm/mach-bf527/gpio.h

@@ -1,65 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 48
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-#define GPIO_PG0	16
-#define GPIO_PG1	17
-#define GPIO_PG2	18
-#define GPIO_PG3	19
-#define GPIO_PG4	20
-#define GPIO_PG5	21
-#define GPIO_PG6	22
-#define GPIO_PG7	23
-#define GPIO_PG8	24
-#define GPIO_PG9	25
-#define GPIO_PG10	26
-#define GPIO_PG11	27
-#define GPIO_PG12	28
-#define GPIO_PG13	29
-#define GPIO_PG14	30
-#define GPIO_PG15	31
-#define GPIO_PH0	32
-#define GPIO_PH1	33
-#define GPIO_PH2	34
-#define GPIO_PH3	35
-#define GPIO_PH4	36
-#define GPIO_PH5	37
-#define GPIO_PH6	38
-#define GPIO_PH7	39
-#define GPIO_PH8	40
-#define GPIO_PH9	41
-#define GPIO_PH10	42
-#define GPIO_PH11	43
-#define GPIO_PH12	44
-#define GPIO_PH13	45
-#define GPIO_PH14	46
-#define GPIO_PH15	47
-
-#define PORT_F GPIO_PF0
-#define PORT_G GPIO_PG0
-#define PORT_H GPIO_PH0
-
-#endif /* _MACH_GPIO_H_ */

+ 0 - 21
arch/blackfin/include/asm/mach-bf527/mem_map.h

@@ -1,21 +0,0 @@
-/*
- * Common Blackfin memory map
- *
- * Copyright 2004-2009 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-#ifndef __BF52X_MEM_MAP_H__
-#define __BF52X_MEM_MAP_H__
-
-#define L1_DATA_A_SRAM      (0xFF800000)
-#define L1_DATA_A_SRAM_SIZE (0x4000)
-#define L1_DATA_A_SRAM_END  (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM      (0xFF900000)
-#define L1_DATA_B_SRAM_SIZE (0x4000)
-#define L1_DATA_B_SRAM_END  (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM        (0xFFA00000)
-#define L1_INST_SRAM_SIZE   (0xC000)
-#define L1_INST_SRAM_END    (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif

+ 0 - 220
arch/blackfin/include/asm/mach-bf527/portmux.h

@@ -1,220 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(0))
-#define P_PPI0_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(0))
-#define P_PPI0_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(0))
-#define P_PPI0_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(0))
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(0))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(0))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(0))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(0))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(0))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(0))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(0))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(0))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(0))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(0))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(0))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(0))
-
-#if !defined(CONFIG_BF527_SPORT0_PORTG)
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(1))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(1))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(1))
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(1))
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(1))
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(1))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(1))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(1))
-#else
-#define P_SPORT0_DTPRI	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(0))
-#define P_SPORT0_DRSEC	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(1))
-#define P_SPORT0_DTSEC	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(1))
-#define P_SPORT0_DRPRI	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(1))
-#define P_SPORT0_RFS	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(1))
-#define P_SPORT0_RSCLK	(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(1))
-#if !defined(CONFIG_BF527_SPORT0_TSCLK_PG14)
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(1))
-#else
-#define P_SPORT0_TSCLK	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(0))
-#endif
-#define P_SPORT0_TFS	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(0))
-#endif
-
-#define P_SPORT1_DRPRI	(P_DEFINED | P_IDENT(GPIO_PF8) | P_FUNCT(1))
-#define P_SPORT1_RSCLK	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(1))
-#define P_SPORT1_RFS	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(1))
-#define P_SPORT1_TFS	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(1))
-#define P_SPORT1_DTPRI	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(1))
-#define P_SPORT1_TSCLK	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(1))
-#define P_SPORT1_DTSEC	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(1))
-#define P_SPORT1_DRSEC	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(1))
-
-#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF9) | P_FUNCT(2))
-#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PF10) | P_FUNCT(2))
-
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(2))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(2))
-
-#if !defined(CONFIG_BF527_UART1_PORTG)
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PF14) | P_FUNCT(2))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PF15) | P_FUNCT(2))
-#else
-#define P_UART1_TX	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(1))
-#define P_UART1_RX	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(1))
-#endif
-
-#define P_CNT_CZM	(P_DEFINED | P_IDENT(GPIO_PF11) | P_FUNCT(3))
-#define P_CNT_CDG	(P_DEFINED | P_IDENT(GPIO_PF12) | P_FUNCT(3))
-#define P_CNT_CUD	(P_DEFINED | P_IDENT(GPIO_PF13) | P_FUNCT(3))
-
-#define P_HWAIT		(P_DONTCARE)
-
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PG1
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL1
-
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(0))
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PG1) | P_FUNCT(2))
-#define P_SPI0_SCK	(P_DEFINED | P_IDENT(GPIO_PG2) | P_FUNCT(2))
-#define P_SPI0_MISO	(P_DEFINED | P_IDENT(GPIO_PG3) | P_FUNCT(2))
-#define P_SPI0_MOSI	(P_DEFINED | P_IDENT(GPIO_PG4) | P_FUNCT(2))
-#define P_TMR1		(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_PPI0_FS2	(P_DEFINED | P_IDENT(GPIO_PG5) | P_FUNCT(0))
-#define P_TMR3		(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(0))
-#define P_TMR4		(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(0))
-#define P_TMR5		(P_DEFINED | P_IDENT(GPIO_PG9) | P_FUNCT(0))
-#define P_TMR6		(P_DEFINED | P_IDENT(GPIO_PG10) | P_FUNCT(0))
-/* #define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(0)) */
-#define P_DMAR1		(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(0))
-#define P_DMAR0		(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(0))
-#define P_TMR2		(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(1))
-#define P_TMR7		(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(1))
-#define P_MDC		(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(1))
-#define P_RMII0_MDINT	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-#define P_MII0_PHYINT	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(1))
-
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PG6) | P_FUNCT(2))
-#define P_UART0_TX	(P_DEFINED | P_IDENT(GPIO_PG7) | P_FUNCT(2))
-#define P_UART0_RX	(P_DEFINED | P_IDENT(GPIO_PG8) | P_FUNCT(2))
-
-#define P_HOST_WR	(P_DEFINED | P_IDENT(GPIO_PG11) | P_FUNCT(2))
-#define P_HOST_ACK	(P_DEFINED | P_IDENT(GPIO_PG12) | P_FUNCT(2))
-#define P_HOST_ADDR	(P_DEFINED | P_IDENT(GPIO_PG13) | P_FUNCT(2))
-#define P_HOST_RD	(P_DEFINED | P_IDENT(GPIO_PG14) | P_FUNCT(2))
-#define P_HOST_CE	(P_DEFINED | P_IDENT(GPIO_PG15) | P_FUNCT(2))
-
-#if defined(CONFIG_BF527_NAND_D_PORTF)
-#define P_NAND_D0	(P_DEFINED | P_IDENT(GPIO_PF0) | P_FUNCT(2))
-#define P_NAND_D1	(P_DEFINED | P_IDENT(GPIO_PF1) | P_FUNCT(2))
-#define P_NAND_D2	(P_DEFINED | P_IDENT(GPIO_PF2) | P_FUNCT(2))
-#define P_NAND_D3	(P_DEFINED | P_IDENT(GPIO_PF3) | P_FUNCT(2))
-#define P_NAND_D4	(P_DEFINED | P_IDENT(GPIO_PF4) | P_FUNCT(2))
-#define P_NAND_D5	(P_DEFINED | P_IDENT(GPIO_PF5) | P_FUNCT(2))
-#define P_NAND_D6	(P_DEFINED | P_IDENT(GPIO_PF6) | P_FUNCT(2))
-#define P_NAND_D7	(P_DEFINED | P_IDENT(GPIO_PF7) | P_FUNCT(2))
-#else /*if defined(CONFIG_BF527_NAND_D_PORTH)*/
-#define P_NAND_D0	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(0))
-#define P_NAND_D1	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(0))
-#define P_NAND_D2	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(0))
-#define P_NAND_D3	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(0))
-#define P_NAND_D4	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(0))
-#define P_NAND_D5	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(0))
-#define P_NAND_D6	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(0))
-#define P_NAND_D7	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(0))
-#endif
-
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(0))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(0))
-#define P_NAND_CE	(P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(0))
-#define P_NAND_WE	(P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(0))
-#define P_NAND_RE	(P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(0))
-#define P_NAND_RB	(P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(0))
-#define P_NAND_CLE	(P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(0))
-#define P_NAND_ALE	(P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(0))
-
-#define P_HOST_D0	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(2))
-#define P_HOST_D1	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(2))
-#define P_HOST_D2	(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(2))
-#define P_HOST_D3	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(2))
-#define P_HOST_D4	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(2))
-#define P_HOST_D5	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(2))
-#define P_HOST_D6	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(2))
-#define P_HOST_D7	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(2))
-#define P_HOST_D8	(P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(2))
-#define P_HOST_D9	(P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(2))
-#define P_HOST_D10	(P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(2))
-#define P_HOST_D11	(P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(2))
-#define P_HOST_D12	(P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(2))
-#define P_HOST_D13	(P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(2))
-#define P_HOST_D14	(P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(2))
-#define P_HOST_D15	(P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(2))
-
-#define P_MII0_ETxD0	(P_DEFINED | P_IDENT(GPIO_PH5) | P_FUNCT(1))
-#define P_MII0_ETxD1	(P_DEFINED | P_IDENT(GPIO_PH7) | P_FUNCT(1))
-#define P_MII0_ETxD2	(P_DEFINED | P_IDENT(GPIO_PH9) | P_FUNCT(1))
-#define P_MII0_ETxD3	(P_DEFINED | P_IDENT(GPIO_PH11) | P_FUNCT(1))
-#define P_MII0_ETxEN	(P_DEFINED | P_IDENT(GPIO_PH3) | P_FUNCT(1))
-#define P_MII0_TxCLK	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_MII0_COL	(P_DEFINED | P_IDENT(GPIO_PH15) | P_FUNCT(1))
-#define P_MII0_ERxD0	(P_DEFINED | P_IDENT(GPIO_PH6) | P_FUNCT(1))
-#define P_MII0_ERxD1	(P_DEFINED | P_IDENT(GPIO_PH8) | P_FUNCT(1))
-#define P_MII0_ERxD2	(P_DEFINED | P_IDENT(GPIO_PH10) | P_FUNCT(1))
-#define P_MII0_ERxD3	(P_DEFINED | P_IDENT(GPIO_PH12) | P_FUNCT(1))
-#define P_MII0_ERxDV	(P_DEFINED | P_IDENT(GPIO_PH14) | P_FUNCT(1))
-#define P_MII0_ERxCLK	(P_DEFINED | P_IDENT(GPIO_PH13) | P_FUNCT(1))
-#define P_MII0_ERxER	(P_DEFINED | P_IDENT(GPIO_PH1) | P_FUNCT(1))
-#define P_MII0_CRS	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_RMII0_REF_CLK	(P_DEFINED | P_IDENT(GPIO_PH4) | P_FUNCT(1))
-#define P_RMII0_CRS_DV	(P_DEFINED | P_IDENT(GPIO_PH0) | P_FUNCT(1))
-#define P_MDIO		(P_DEFINED | P_IDENT(GPIO_PH2) | P_FUNCT(1))
-
-#define P_TWI0_SCL	(P_DONTCARE)
-#define P_TWI0_SDA	(P_DONTCARE)
-#define P_PPI0_FS1	(P_DONTCARE)
-#define P_TMR0		(P_DONTCARE)
-#define P_TMRCLK	(P_DONTCARE)
-#define P_PPI0_CLK	(P_DONTCARE)
-
-#define P_MII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxD2, \
-	P_MII0_ETxD3, \
-	P_MII0_ETxEN, \
-	P_MII0_TxCLK, \
-	P_MII0_PHYINT, \
-	P_MII0_COL, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxD2, \
-	P_MII0_ERxD3, \
-	P_MII0_ERxDV, \
-	P_MII0_ERxCLK, \
-	P_MII0_ERxER, \
-	P_MII0_CRS, \
-	P_MDC, \
-	P_MDIO, 0}
-
-#define P_RMII0 {\
-	P_MII0_ETxD0, \
-	P_MII0_ETxD1, \
-	P_MII0_ETxEN, \
-	P_MII0_ERxD0, \
-	P_MII0_ERxD1, \
-	P_MII0_ERxER, \
-	P_RMII0_REF_CLK, \
-	P_RMII0_MDINT, \
-	P_RMII0_CRS_DV, \
-	P_MDC, \
-	P_MDIO, 0}
-
-#endif				/* _MACH_PORTMUX_H_ */

+ 0 - 60
arch/blackfin/include/asm/mach-bf527/ports.h

@@ -1,60 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-/* PORTx_MUX Masks */
-#define PORT_x_MUX_0_MASK	0x0003
-#define PORT_x_MUX_1_MASK	0x000C
-#define PORT_x_MUX_2_MASK	0x0030
-#define PORT_x_MUX_3_MASK	0x00C0
-#define PORT_x_MUX_4_MASK	0x0300
-#define PORT_x_MUX_5_MASK	0x0C00
-#define PORT_x_MUX_6_MASK	0x3000
-#define PORT_x_MUX_7_MASK	0xC000
-
-#define PORT_x_MUX_FUNC_1	(0x0)
-#define PORT_x_MUX_FUNC_2	(0x1)
-#define PORT_x_MUX_FUNC_3	(0x2)
-#define PORT_x_MUX_FUNC_4	(0x3)
-#define PORT_x_MUX_0_FUNC_1	(PORT_x_MUX_FUNC_1 << 0)
-#define PORT_x_MUX_0_FUNC_2	(PORT_x_MUX_FUNC_2 << 0)
-#define PORT_x_MUX_0_FUNC_3	(PORT_x_MUX_FUNC_3 << 0)
-#define PORT_x_MUX_0_FUNC_4	(PORT_x_MUX_FUNC_4 << 0)
-#define PORT_x_MUX_1_FUNC_1	(PORT_x_MUX_FUNC_1 << 2)
-#define PORT_x_MUX_1_FUNC_2	(PORT_x_MUX_FUNC_2 << 2)
-#define PORT_x_MUX_1_FUNC_3	(PORT_x_MUX_FUNC_3 << 2)
-#define PORT_x_MUX_1_FUNC_4	(PORT_x_MUX_FUNC_4 << 2)
-#define PORT_x_MUX_2_FUNC_1	(PORT_x_MUX_FUNC_1 << 4)
-#define PORT_x_MUX_2_FUNC_2	(PORT_x_MUX_FUNC_2 << 4)
-#define PORT_x_MUX_2_FUNC_3	(PORT_x_MUX_FUNC_3 << 4)
-#define PORT_x_MUX_2_FUNC_4	(PORT_x_MUX_FUNC_4 << 4)
-#define PORT_x_MUX_3_FUNC_1	(PORT_x_MUX_FUNC_1 << 6)
-#define PORT_x_MUX_3_FUNC_2	(PORT_x_MUX_FUNC_2 << 6)
-#define PORT_x_MUX_3_FUNC_3	(PORT_x_MUX_FUNC_3 << 6)
-#define PORT_x_MUX_3_FUNC_4	(PORT_x_MUX_FUNC_4 << 6)
-#define PORT_x_MUX_4_FUNC_1	(PORT_x_MUX_FUNC_1 << 8)
-#define PORT_x_MUX_4_FUNC_2	(PORT_x_MUX_FUNC_2 << 8)
-#define PORT_x_MUX_4_FUNC_3	(PORT_x_MUX_FUNC_3 << 8)
-#define PORT_x_MUX_4_FUNC_4	(PORT_x_MUX_FUNC_4 << 8)
-#define PORT_x_MUX_5_FUNC_1	(PORT_x_MUX_FUNC_1 << 10)
-#define PORT_x_MUX_5_FUNC_2	(PORT_x_MUX_FUNC_2 << 10)
-#define PORT_x_MUX_5_FUNC_3	(PORT_x_MUX_FUNC_3 << 10)
-#define PORT_x_MUX_5_FUNC_4	(PORT_x_MUX_FUNC_4 << 10)
-#define PORT_x_MUX_6_FUNC_1	(PORT_x_MUX_FUNC_1 << 12)
-#define PORT_x_MUX_6_FUNC_2	(PORT_x_MUX_FUNC_2 << 12)
-#define PORT_x_MUX_6_FUNC_3	(PORT_x_MUX_FUNC_3 << 12)
-#define PORT_x_MUX_6_FUNC_4	(PORT_x_MUX_FUNC_4 << 12)
-#define PORT_x_MUX_7_FUNC_1	(PORT_x_MUX_FUNC_1 << 14)
-#define PORT_x_MUX_7_FUNC_2	(PORT_x_MUX_FUNC_2 << 14)
-#define PORT_x_MUX_7_FUNC_3	(PORT_x_MUX_FUNC_3 << 14)
-#define PORT_x_MUX_7_FUNC_4	(PORT_x_MUX_FUNC_4 << 14)
-
-#include "../mach-common/bits/ports-f.h"
-#include "../mach-common/bits/ports-g.h"
-#include "../mach-common/bits/ports-h.h"
-#include "../mach-common/bits/ports-j.h"
-
-#endif

+ 0 - 872
arch/blackfin/include/asm/mach-bf533/BF531_cdef.h

@@ -1,872 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF531_proc__
-#define __BFIN_CDEF_ADSP_BF531_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_MDMAFLX0_DMACNFG_D() bfin_read16(MDMAFLX0_DMACNFG_D)
-#define bfin_write_MDMAFLX0_DMACNFG_D(val) bfin_write16(MDMAFLX0_DMACNFG_D, val)
-#define bfin_read_MDMAFLX0_XCOUNT_D()  bfin_read16(MDMAFLX0_XCOUNT_D)
-#define bfin_write_MDMAFLX0_XCOUNT_D(val) bfin_write16(MDMAFLX0_XCOUNT_D, val)
-#define bfin_read_MDMAFLX0_XMODIFY_D() bfin_read16(MDMAFLX0_XMODIFY_D)
-#define bfin_write_MDMAFLX0_XMODIFY_D(val) bfin_write16(MDMAFLX0_XMODIFY_D, val)
-#define bfin_read_MDMAFLX0_YCOUNT_D()  bfin_read16(MDMAFLX0_YCOUNT_D)
-#define bfin_write_MDMAFLX0_YCOUNT_D(val) bfin_write16(MDMAFLX0_YCOUNT_D, val)
-#define bfin_read_MDMAFLX0_YMODIFY_D() bfin_read16(MDMAFLX0_YMODIFY_D)
-#define bfin_write_MDMAFLX0_YMODIFY_D(val) bfin_write16(MDMAFLX0_YMODIFY_D, val)
-#define bfin_read_MDMAFLX0_IRQSTAT_D() bfin_read16(MDMAFLX0_IRQSTAT_D)
-#define bfin_write_MDMAFLX0_IRQSTAT_D(val) bfin_write16(MDMAFLX0_IRQSTAT_D, val)
-#define bfin_read_MDMAFLX0_PMAP_D()    bfin_read16(MDMAFLX0_PMAP_D)
-#define bfin_write_MDMAFLX0_PMAP_D(val) bfin_write16(MDMAFLX0_PMAP_D, val)
-#define bfin_read_MDMAFLX0_CURXCOUNT_D() bfin_read16(MDMAFLX0_CURXCOUNT_D)
-#define bfin_write_MDMAFLX0_CURXCOUNT_D(val) bfin_write16(MDMAFLX0_CURXCOUNT_D, val)
-#define bfin_read_MDMAFLX0_CURYCOUNT_D() bfin_read16(MDMAFLX0_CURYCOUNT_D)
-#define bfin_write_MDMAFLX0_CURYCOUNT_D(val) bfin_write16(MDMAFLX0_CURYCOUNT_D, val)
-#define bfin_read_MDMAFLX0_DMACNFG_S() bfin_read16(MDMAFLX0_DMACNFG_S)
-#define bfin_write_MDMAFLX0_DMACNFG_S(val) bfin_write16(MDMAFLX0_DMACNFG_S, val)
-#define bfin_read_MDMAFLX0_XCOUNT_S()  bfin_read16(MDMAFLX0_XCOUNT_S)
-#define bfin_write_MDMAFLX0_XCOUNT_S(val) bfin_write16(MDMAFLX0_XCOUNT_S, val)
-#define bfin_read_MDMAFLX0_XMODIFY_S() bfin_read16(MDMAFLX0_XMODIFY_S)
-#define bfin_write_MDMAFLX0_XMODIFY_S(val) bfin_write16(MDMAFLX0_XMODIFY_S, val)
-#define bfin_read_MDMAFLX0_YCOUNT_S()  bfin_read16(MDMAFLX0_YCOUNT_S)
-#define bfin_write_MDMAFLX0_YCOUNT_S(val) bfin_write16(MDMAFLX0_YCOUNT_S, val)
-#define bfin_read_MDMAFLX0_YMODIFY_S() bfin_read16(MDMAFLX0_YMODIFY_S)
-#define bfin_write_MDMAFLX0_YMODIFY_S(val) bfin_write16(MDMAFLX0_YMODIFY_S, val)
-#define bfin_read_MDMAFLX0_IRQSTAT_S() bfin_read16(MDMAFLX0_IRQSTAT_S)
-#define bfin_write_MDMAFLX0_IRQSTAT_S(val) bfin_write16(MDMAFLX0_IRQSTAT_S, val)
-#define bfin_read_MDMAFLX0_PMAP_S()    bfin_read16(MDMAFLX0_PMAP_S)
-#define bfin_write_MDMAFLX0_PMAP_S(val) bfin_write16(MDMAFLX0_PMAP_S, val)
-#define bfin_read_MDMAFLX0_CURXCOUNT_S() bfin_read16(MDMAFLX0_CURXCOUNT_S)
-#define bfin_write_MDMAFLX0_CURXCOUNT_S(val) bfin_write16(MDMAFLX0_CURXCOUNT_S, val)
-#define bfin_read_MDMAFLX0_CURYCOUNT_S() bfin_read16(MDMAFLX0_CURYCOUNT_S)
-#define bfin_write_MDMAFLX0_CURYCOUNT_S(val) bfin_write16(MDMAFLX0_CURYCOUNT_S, val)
-#define bfin_read_MDMAFLX1_DMACNFG_D() bfin_read16(MDMAFLX1_DMACNFG_D)
-#define bfin_write_MDMAFLX1_DMACNFG_D(val) bfin_write16(MDMAFLX1_DMACNFG_D, val)
-#define bfin_read_MDMAFLX1_XCOUNT_D()  bfin_read16(MDMAFLX1_XCOUNT_D)
-#define bfin_write_MDMAFLX1_XCOUNT_D(val) bfin_write16(MDMAFLX1_XCOUNT_D, val)
-#define bfin_read_MDMAFLX1_XMODIFY_D() bfin_read16(MDMAFLX1_XMODIFY_D)
-#define bfin_write_MDMAFLX1_XMODIFY_D(val) bfin_write16(MDMAFLX1_XMODIFY_D, val)
-#define bfin_read_MDMAFLX1_YCOUNT_D()  bfin_read16(MDMAFLX1_YCOUNT_D)
-#define bfin_write_MDMAFLX1_YCOUNT_D(val) bfin_write16(MDMAFLX1_YCOUNT_D, val)
-#define bfin_read_MDMAFLX1_YMODIFY_D() bfin_read16(MDMAFLX1_YMODIFY_D)
-#define bfin_write_MDMAFLX1_YMODIFY_D(val) bfin_write16(MDMAFLX1_YMODIFY_D, val)
-#define bfin_read_MDMAFLX1_IRQSTAT_D() bfin_read16(MDMAFLX1_IRQSTAT_D)
-#define bfin_write_MDMAFLX1_IRQSTAT_D(val) bfin_write16(MDMAFLX1_IRQSTAT_D, val)
-#define bfin_read_MDMAFLX1_PMAP_D()    bfin_read16(MDMAFLX1_PMAP_D)
-#define bfin_write_MDMAFLX1_PMAP_D(val) bfin_write16(MDMAFLX1_PMAP_D, val)
-#define bfin_read_MDMAFLX1_CURXCOUNT_D() bfin_read16(MDMAFLX1_CURXCOUNT_D)
-#define bfin_write_MDMAFLX1_CURXCOUNT_D(val) bfin_write16(MDMAFLX1_CURXCOUNT_D, val)
-#define bfin_read_MDMAFLX1_CURYCOUNT_D() bfin_read16(MDMAFLX1_CURYCOUNT_D)
-#define bfin_write_MDMAFLX1_CURYCOUNT_D(val) bfin_write16(MDMAFLX1_CURYCOUNT_D, val)
-#define bfin_read_MDMAFLX1_DMACNFG_S() bfin_read16(MDMAFLX1_DMACNFG_S)
-#define bfin_write_MDMAFLX1_DMACNFG_S(val) bfin_write16(MDMAFLX1_DMACNFG_S, val)
-#define bfin_read_MDMAFLX1_XCOUNT_S()  bfin_read16(MDMAFLX1_XCOUNT_S)
-#define bfin_write_MDMAFLX1_XCOUNT_S(val) bfin_write16(MDMAFLX1_XCOUNT_S, val)
-#define bfin_read_MDMAFLX1_XMODIFY_S() bfin_read16(MDMAFLX1_XMODIFY_S)
-#define bfin_write_MDMAFLX1_XMODIFY_S(val) bfin_write16(MDMAFLX1_XMODIFY_S, val)
-#define bfin_read_MDMAFLX1_YCOUNT_S()  bfin_read16(MDMAFLX1_YCOUNT_S)
-#define bfin_write_MDMAFLX1_YCOUNT_S(val) bfin_write16(MDMAFLX1_YCOUNT_S, val)
-#define bfin_read_MDMAFLX1_YMODIFY_S() bfin_read16(MDMAFLX1_YMODIFY_S)
-#define bfin_write_MDMAFLX1_YMODIFY_S(val) bfin_write16(MDMAFLX1_YMODIFY_S, val)
-#define bfin_read_MDMAFLX1_IRQSTAT_S() bfin_read16(MDMAFLX1_IRQSTAT_S)
-#define bfin_write_MDMAFLX1_IRQSTAT_S(val) bfin_write16(MDMAFLX1_IRQSTAT_S, val)
-#define bfin_read_MDMAFLX1_PMAP_S()    bfin_read16(MDMAFLX1_PMAP_S)
-#define bfin_write_MDMAFLX1_PMAP_S(val) bfin_write16(MDMAFLX1_PMAP_S, val)
-#define bfin_read_MDMAFLX1_CURXCOUNT_S() bfin_read16(MDMAFLX1_CURXCOUNT_S)
-#define bfin_write_MDMAFLX1_CURXCOUNT_S(val) bfin_write16(MDMAFLX1_CURXCOUNT_S, val)
-#define bfin_read_MDMAFLX1_CURYCOUNT_S() bfin_read16(MDMAFLX1_CURYCOUNT_S)
-#define bfin_write_MDMAFLX1_CURYCOUNT_S(val) bfin_write16(MDMAFLX1_CURYCOUNT_S, val)
-#define bfin_read_DMAFLX0_DMACNFG()    bfin_read16(DMAFLX0_DMACNFG)
-#define bfin_write_DMAFLX0_DMACNFG(val) bfin_write16(DMAFLX0_DMACNFG, val)
-#define bfin_read_DMAFLX0_XCOUNT()     bfin_read16(DMAFLX0_XCOUNT)
-#define bfin_write_DMAFLX0_XCOUNT(val) bfin_write16(DMAFLX0_XCOUNT, val)
-#define bfin_read_DMAFLX0_XMODIFY()    bfin_read16(DMAFLX0_XMODIFY)
-#define bfin_write_DMAFLX0_XMODIFY(val) bfin_write16(DMAFLX0_XMODIFY, val)
-#define bfin_read_DMAFLX0_YCOUNT()     bfin_read16(DMAFLX0_YCOUNT)
-#define bfin_write_DMAFLX0_YCOUNT(val) bfin_write16(DMAFLX0_YCOUNT, val)
-#define bfin_read_DMAFLX0_YMODIFY()    bfin_read16(DMAFLX0_YMODIFY)
-#define bfin_write_DMAFLX0_YMODIFY(val) bfin_write16(DMAFLX0_YMODIFY, val)
-#define bfin_read_DMAFLX0_IRQSTAT()    bfin_read16(DMAFLX0_IRQSTAT)
-#define bfin_write_DMAFLX0_IRQSTAT(val) bfin_write16(DMAFLX0_IRQSTAT, val)
-#define bfin_read_DMAFLX0_PMAP()       bfin_read16(DMAFLX0_PMAP)
-#define bfin_write_DMAFLX0_PMAP(val)   bfin_write16(DMAFLX0_PMAP, val)
-#define bfin_read_DMAFLX0_CURXCOUNT()  bfin_read16(DMAFLX0_CURXCOUNT)
-#define bfin_write_DMAFLX0_CURXCOUNT(val) bfin_write16(DMAFLX0_CURXCOUNT, val)
-#define bfin_read_DMAFLX0_CURYCOUNT()  bfin_read16(DMAFLX0_CURYCOUNT)
-#define bfin_write_DMAFLX0_CURYCOUNT(val) bfin_write16(DMAFLX0_CURYCOUNT, val)
-#define bfin_read_DMAFLX1_DMACNFG()    bfin_read16(DMAFLX1_DMACNFG)
-#define bfin_write_DMAFLX1_DMACNFG(val) bfin_write16(DMAFLX1_DMACNFG, val)
-#define bfin_read_DMAFLX1_XCOUNT()     bfin_read16(DMAFLX1_XCOUNT)
-#define bfin_write_DMAFLX1_XCOUNT(val) bfin_write16(DMAFLX1_XCOUNT, val)
-#define bfin_read_DMAFLX1_XMODIFY()    bfin_read16(DMAFLX1_XMODIFY)
-#define bfin_write_DMAFLX1_XMODIFY(val) bfin_write16(DMAFLX1_XMODIFY, val)
-#define bfin_read_DMAFLX1_YCOUNT()     bfin_read16(DMAFLX1_YCOUNT)
-#define bfin_write_DMAFLX1_YCOUNT(val) bfin_write16(DMAFLX1_YCOUNT, val)
-#define bfin_read_DMAFLX1_YMODIFY()    bfin_read16(DMAFLX1_YMODIFY)
-#define bfin_write_DMAFLX1_YMODIFY(val) bfin_write16(DMAFLX1_YMODIFY, val)
-#define bfin_read_DMAFLX1_IRQSTAT()    bfin_read16(DMAFLX1_IRQSTAT)
-#define bfin_write_DMAFLX1_IRQSTAT(val) bfin_write16(DMAFLX1_IRQSTAT, val)
-#define bfin_read_DMAFLX1_PMAP()       bfin_read16(DMAFLX1_PMAP)
-#define bfin_write_DMAFLX1_PMAP(val)   bfin_write16(DMAFLX1_PMAP, val)
-#define bfin_read_DMAFLX1_CURXCOUNT()  bfin_read16(DMAFLX1_CURXCOUNT)
-#define bfin_write_DMAFLX1_CURXCOUNT(val) bfin_write16(DMAFLX1_CURXCOUNT, val)
-#define bfin_read_DMAFLX1_CURYCOUNT()  bfin_read16(DMAFLX1_CURYCOUNT)
-#define bfin_write_DMAFLX1_CURYCOUNT(val) bfin_write16(DMAFLX1_CURYCOUNT, val)
-#define bfin_read_DMAFLX2_DMACNFG()    bfin_read16(DMAFLX2_DMACNFG)
-#define bfin_write_DMAFLX2_DMACNFG(val) bfin_write16(DMAFLX2_DMACNFG, val)
-#define bfin_read_DMAFLX2_XCOUNT()     bfin_read16(DMAFLX2_XCOUNT)
-#define bfin_write_DMAFLX2_XCOUNT(val) bfin_write16(DMAFLX2_XCOUNT, val)
-#define bfin_read_DMAFLX2_XMODIFY()    bfin_read16(DMAFLX2_XMODIFY)
-#define bfin_write_DMAFLX2_XMODIFY(val) bfin_write16(DMAFLX2_XMODIFY, val)
-#define bfin_read_DMAFLX2_YCOUNT()     bfin_read16(DMAFLX2_YCOUNT)
-#define bfin_write_DMAFLX2_YCOUNT(val) bfin_write16(DMAFLX2_YCOUNT, val)
-#define bfin_read_DMAFLX2_YMODIFY()    bfin_read16(DMAFLX2_YMODIFY)
-#define bfin_write_DMAFLX2_YMODIFY(val) bfin_write16(DMAFLX2_YMODIFY, val)
-#define bfin_read_DMAFLX2_IRQSTAT()    bfin_read16(DMAFLX2_IRQSTAT)
-#define bfin_write_DMAFLX2_IRQSTAT(val) bfin_write16(DMAFLX2_IRQSTAT, val)
-#define bfin_read_DMAFLX2_PMAP()       bfin_read16(DMAFLX2_PMAP)
-#define bfin_write_DMAFLX2_PMAP(val)   bfin_write16(DMAFLX2_PMAP, val)
-#define bfin_read_DMAFLX2_CURXCOUNT()  bfin_read16(DMAFLX2_CURXCOUNT)
-#define bfin_write_DMAFLX2_CURXCOUNT(val) bfin_write16(DMAFLX2_CURXCOUNT, val)
-#define bfin_read_DMAFLX2_CURYCOUNT()  bfin_read16(DMAFLX2_CURYCOUNT)
-#define bfin_write_DMAFLX2_CURYCOUNT(val) bfin_write16(DMAFLX2_CURYCOUNT, val)
-#define bfin_read_DMAFLX3_DMACNFG()    bfin_read16(DMAFLX3_DMACNFG)
-#define bfin_write_DMAFLX3_DMACNFG(val) bfin_write16(DMAFLX3_DMACNFG, val)
-#define bfin_read_DMAFLX3_XCOUNT()     bfin_read16(DMAFLX3_XCOUNT)
-#define bfin_write_DMAFLX3_XCOUNT(val) bfin_write16(DMAFLX3_XCOUNT, val)
-#define bfin_read_DMAFLX3_XMODIFY()    bfin_read16(DMAFLX3_XMODIFY)
-#define bfin_write_DMAFLX3_XMODIFY(val) bfin_write16(DMAFLX3_XMODIFY, val)
-#define bfin_read_DMAFLX3_YCOUNT()     bfin_read16(DMAFLX3_YCOUNT)
-#define bfin_write_DMAFLX3_YCOUNT(val) bfin_write16(DMAFLX3_YCOUNT, val)
-#define bfin_read_DMAFLX3_YMODIFY()    bfin_read16(DMAFLX3_YMODIFY)
-#define bfin_write_DMAFLX3_YMODIFY(val) bfin_write16(DMAFLX3_YMODIFY, val)
-#define bfin_read_DMAFLX3_IRQSTAT()    bfin_read16(DMAFLX3_IRQSTAT)
-#define bfin_write_DMAFLX3_IRQSTAT(val) bfin_write16(DMAFLX3_IRQSTAT, val)
-#define bfin_read_DMAFLX3_PMAP()       bfin_read16(DMAFLX3_PMAP)
-#define bfin_write_DMAFLX3_PMAP(val)   bfin_write16(DMAFLX3_PMAP, val)
-#define bfin_read_DMAFLX3_CURXCOUNT()  bfin_read16(DMAFLX3_CURXCOUNT)
-#define bfin_write_DMAFLX3_CURXCOUNT(val) bfin_write16(DMAFLX3_CURXCOUNT, val)
-#define bfin_read_DMAFLX3_CURYCOUNT()  bfin_read16(DMAFLX3_CURYCOUNT)
-#define bfin_write_DMAFLX3_CURYCOUNT(val) bfin_write16(DMAFLX3_CURYCOUNT, val)
-#define bfin_read_DMAFLX4_DMACNFG()    bfin_read16(DMAFLX4_DMACNFG)
-#define bfin_write_DMAFLX4_DMACNFG(val) bfin_write16(DMAFLX4_DMACNFG, val)
-#define bfin_read_DMAFLX4_XCOUNT()     bfin_read16(DMAFLX4_XCOUNT)
-#define bfin_write_DMAFLX4_XCOUNT(val) bfin_write16(DMAFLX4_XCOUNT, val)
-#define bfin_read_DMAFLX4_XMODIFY()    bfin_read16(DMAFLX4_XMODIFY)
-#define bfin_write_DMAFLX4_XMODIFY(val) bfin_write16(DMAFLX4_XMODIFY, val)
-#define bfin_read_DMAFLX4_YCOUNT()     bfin_read16(DMAFLX4_YCOUNT)
-#define bfin_write_DMAFLX4_YCOUNT(val) bfin_write16(DMAFLX4_YCOUNT, val)
-#define bfin_read_DMAFLX4_YMODIFY()    bfin_read16(DMAFLX4_YMODIFY)
-#define bfin_write_DMAFLX4_YMODIFY(val) bfin_write16(DMAFLX4_YMODIFY, val)
-#define bfin_read_DMAFLX4_IRQSTAT()    bfin_read16(DMAFLX4_IRQSTAT)
-#define bfin_write_DMAFLX4_IRQSTAT(val) bfin_write16(DMAFLX4_IRQSTAT, val)
-#define bfin_read_DMAFLX4_PMAP()       bfin_read16(DMAFLX4_PMAP)
-#define bfin_write_DMAFLX4_PMAP(val)   bfin_write16(DMAFLX4_PMAP, val)
-#define bfin_read_DMAFLX4_CURXCOUNT()  bfin_read16(DMAFLX4_CURXCOUNT)
-#define bfin_write_DMAFLX4_CURXCOUNT(val) bfin_write16(DMAFLX4_CURXCOUNT, val)
-#define bfin_read_DMAFLX4_CURYCOUNT()  bfin_read16(DMAFLX4_CURYCOUNT)
-#define bfin_write_DMAFLX4_CURYCOUNT(val) bfin_write16(DMAFLX4_CURYCOUNT, val)
-#define bfin_read_DMAFLX5_DMACNFG()    bfin_read16(DMAFLX5_DMACNFG)
-#define bfin_write_DMAFLX5_DMACNFG(val) bfin_write16(DMAFLX5_DMACNFG, val)
-#define bfin_read_DMAFLX5_XCOUNT()     bfin_read16(DMAFLX5_XCOUNT)
-#define bfin_write_DMAFLX5_XCOUNT(val) bfin_write16(DMAFLX5_XCOUNT, val)
-#define bfin_read_DMAFLX5_XMODIFY()    bfin_read16(DMAFLX5_XMODIFY)
-#define bfin_write_DMAFLX5_XMODIFY(val) bfin_write16(DMAFLX5_XMODIFY, val)
-#define bfin_read_DMAFLX5_YCOUNT()     bfin_read16(DMAFLX5_YCOUNT)
-#define bfin_write_DMAFLX5_YCOUNT(val) bfin_write16(DMAFLX5_YCOUNT, val)
-#define bfin_read_DMAFLX5_YMODIFY()    bfin_read16(DMAFLX5_YMODIFY)
-#define bfin_write_DMAFLX5_YMODIFY(val) bfin_write16(DMAFLX5_YMODIFY, val)
-#define bfin_read_DMAFLX5_IRQSTAT()    bfin_read16(DMAFLX5_IRQSTAT)
-#define bfin_write_DMAFLX5_IRQSTAT(val) bfin_write16(DMAFLX5_IRQSTAT, val)
-#define bfin_read_DMAFLX5_PMAP()       bfin_read16(DMAFLX5_PMAP)
-#define bfin_write_DMAFLX5_PMAP(val)   bfin_write16(DMAFLX5_PMAP, val)
-#define bfin_read_DMAFLX5_CURXCOUNT()  bfin_read16(DMAFLX5_CURXCOUNT)
-#define bfin_write_DMAFLX5_CURXCOUNT(val) bfin_write16(DMAFLX5_CURXCOUNT, val)
-#define bfin_read_DMAFLX5_CURYCOUNT()  bfin_read16(DMAFLX5_CURYCOUNT)
-#define bfin_write_DMAFLX5_CURYCOUNT(val) bfin_write16(DMAFLX5_CURYCOUNT, val)
-#define bfin_read_DMAFLX6_DMACNFG()    bfin_read16(DMAFLX6_DMACNFG)
-#define bfin_write_DMAFLX6_DMACNFG(val) bfin_write16(DMAFLX6_DMACNFG, val)
-#define bfin_read_DMAFLX6_XCOUNT()     bfin_read16(DMAFLX6_XCOUNT)
-#define bfin_write_DMAFLX6_XCOUNT(val) bfin_write16(DMAFLX6_XCOUNT, val)
-#define bfin_read_DMAFLX6_XMODIFY()    bfin_read16(DMAFLX6_XMODIFY)
-#define bfin_write_DMAFLX6_XMODIFY(val) bfin_write16(DMAFLX6_XMODIFY, val)
-#define bfin_read_DMAFLX6_YCOUNT()     bfin_read16(DMAFLX6_YCOUNT)
-#define bfin_write_DMAFLX6_YCOUNT(val) bfin_write16(DMAFLX6_YCOUNT, val)
-#define bfin_read_DMAFLX6_YMODIFY()    bfin_read16(DMAFLX6_YMODIFY)
-#define bfin_write_DMAFLX6_YMODIFY(val) bfin_write16(DMAFLX6_YMODIFY, val)
-#define bfin_read_DMAFLX6_IRQSTAT()    bfin_read16(DMAFLX6_IRQSTAT)
-#define bfin_write_DMAFLX6_IRQSTAT(val) bfin_write16(DMAFLX6_IRQSTAT, val)
-#define bfin_read_DMAFLX6_PMAP()       bfin_read16(DMAFLX6_PMAP)
-#define bfin_write_DMAFLX6_PMAP(val)   bfin_write16(DMAFLX6_PMAP, val)
-#define bfin_read_DMAFLX6_CURXCOUNT()  bfin_read16(DMAFLX6_CURXCOUNT)
-#define bfin_write_DMAFLX6_CURXCOUNT(val) bfin_write16(DMAFLX6_CURXCOUNT, val)
-#define bfin_read_DMAFLX6_CURYCOUNT()  bfin_read16(DMAFLX6_CURYCOUNT)
-#define bfin_write_DMAFLX6_CURYCOUNT(val) bfin_write16(DMAFLX6_CURYCOUNT, val)
-#define bfin_read_DMAFLX7_DMACNFG()    bfin_read16(DMAFLX7_DMACNFG)
-#define bfin_write_DMAFLX7_DMACNFG(val) bfin_write16(DMAFLX7_DMACNFG, val)
-#define bfin_read_DMAFLX7_XCOUNT()     bfin_read16(DMAFLX7_XCOUNT)
-#define bfin_write_DMAFLX7_XCOUNT(val) bfin_write16(DMAFLX7_XCOUNT, val)
-#define bfin_read_DMAFLX7_XMODIFY()    bfin_read16(DMAFLX7_XMODIFY)
-#define bfin_write_DMAFLX7_XMODIFY(val) bfin_write16(DMAFLX7_XMODIFY, val)
-#define bfin_read_DMAFLX7_YCOUNT()     bfin_read16(DMAFLX7_YCOUNT)
-#define bfin_write_DMAFLX7_YCOUNT(val) bfin_write16(DMAFLX7_YCOUNT, val)
-#define bfin_read_DMAFLX7_YMODIFY()    bfin_read16(DMAFLX7_YMODIFY)
-#define bfin_write_DMAFLX7_YMODIFY(val) bfin_write16(DMAFLX7_YMODIFY, val)
-#define bfin_read_DMAFLX7_IRQSTAT()    bfin_read16(DMAFLX7_IRQSTAT)
-#define bfin_write_DMAFLX7_IRQSTAT(val) bfin_write16(DMAFLX7_IRQSTAT, val)
-#define bfin_read_DMAFLX7_PMAP()       bfin_read16(DMAFLX7_PMAP)
-#define bfin_write_DMAFLX7_PMAP(val)   bfin_write16(DMAFLX7_PMAP, val)
-#define bfin_read_DMAFLX7_CURXCOUNT()  bfin_read16(DMAFLX7_CURXCOUNT)
-#define bfin_write_DMAFLX7_CURXCOUNT(val) bfin_write16(DMAFLX7_CURXCOUNT, val)
-#define bfin_read_DMAFLX7_CURYCOUNT()  bfin_read16(DMAFLX7_CURYCOUNT)
-#define bfin_write_DMAFLX7_CURYCOUNT(val) bfin_write16(DMAFLX7_CURYCOUNT, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()       bfin_read16(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)   bfin_write16(TIMER_STATUS, val)
-#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK()          bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val)      bfin_write32(SIC_IMASK, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR()            bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val)        bfin_write32(SIC_ISR, val)
-#define bfin_read_SIC_IWR()            bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val)        bfin_write32(SIC_IWR, val)
-#define bfin_read_UART_THR()           bfin_read16(UART_THR)
-#define bfin_write_UART_THR(val)       bfin_write16(UART_THR, val)
-#define bfin_read_UART_DLL()           bfin_read16(UART_DLL)
-#define bfin_write_UART_DLL(val)       bfin_write16(UART_DLL, val)
-#define bfin_read_UART_DLH()           bfin_read16(UART_DLH)
-#define bfin_write_UART_DLH(val)       bfin_write16(UART_DLH, val)
-#define bfin_read_UART_IER()           bfin_read16(UART_IER)
-#define bfin_write_UART_IER(val)       bfin_write16(UART_IER, val)
-#define bfin_read_UART_IIR()           bfin_read16(UART_IIR)
-#define bfin_write_UART_IIR(val)       bfin_write16(UART_IIR, val)
-#define bfin_read_UART_LCR()           bfin_read16(UART_LCR)
-#define bfin_write_UART_LCR(val)       bfin_write16(UART_LCR, val)
-#define bfin_read_UART_MCR()           bfin_read16(UART_MCR)
-#define bfin_write_UART_MCR(val)       bfin_write16(UART_MCR, val)
-#define bfin_read_UART_LSR()           bfin_read16(UART_LSR)
-#define bfin_write_UART_LSR(val)       bfin_write16(UART_LSR, val)
-#define bfin_read_UART_SCR()           bfin_read16(UART_SCR)
-#define bfin_write_UART_SCR(val)       bfin_write16(UART_SCR, val)
-#define bfin_read_UART_RBR()           bfin_read16(UART_RBR)
-#define bfin_write_UART_RBR(val)       bfin_write16(UART_RBR, val)
-#define bfin_read_UART_GCTL()          bfin_read16(UART_GCTL)
-#define bfin_write_UART_GCTL(val)      bfin_write16(UART_GCTL, val)
-#define bfin_read_SPT0_TX_CONFIG0()    bfin_read16(SPT0_TX_CONFIG0)
-#define bfin_write_SPT0_TX_CONFIG0(val) bfin_write16(SPT0_TX_CONFIG0, val)
-#define bfin_read_SPT0_TX_CONFIG1()    bfin_read16(SPT0_TX_CONFIG1)
-#define bfin_write_SPT0_TX_CONFIG1(val) bfin_write16(SPT0_TX_CONFIG1, val)
-#define bfin_read_SPT0_RX_CONFIG0()    bfin_read16(SPT0_RX_CONFIG0)
-#define bfin_write_SPT0_RX_CONFIG0(val) bfin_write16(SPT0_RX_CONFIG0, val)
-#define bfin_read_SPT0_RX_CONFIG1()    bfin_read16(SPT0_RX_CONFIG1)
-#define bfin_write_SPT0_RX_CONFIG1(val) bfin_write16(SPT0_RX_CONFIG1, val)
-#define bfin_read_SPT0_TX()            bfin_read32(SPT0_TX)
-#define bfin_write_SPT0_TX(val)        bfin_write32(SPT0_TX, val)
-#define bfin_read_SPT0_RX()            bfin_read32(SPT0_RX)
-#define bfin_write_SPT0_RX(val)        bfin_write32(SPT0_RX, val)
-#define bfin_read_SPT0_TSCLKDIV()      bfin_read16(SPT0_TSCLKDIV)
-#define bfin_write_SPT0_TSCLKDIV(val)  bfin_write16(SPT0_TSCLKDIV, val)
-#define bfin_read_SPT0_RSCLKDIV()      bfin_read16(SPT0_RSCLKDIV)
-#define bfin_write_SPT0_RSCLKDIV(val)  bfin_write16(SPT0_RSCLKDIV, val)
-#define bfin_read_SPT0_TFSDIV()        bfin_read16(SPT0_TFSDIV)
-#define bfin_write_SPT0_TFSDIV(val)    bfin_write16(SPT0_TFSDIV, val)
-#define bfin_read_SPT0_RFSDIV()        bfin_read16(SPT0_RFSDIV)
-#define bfin_write_SPT0_RFSDIV(val)    bfin_write16(SPT0_RFSDIV, val)
-#define bfin_read_SPT0_STAT()          bfin_read16(SPT0_STAT)
-#define bfin_write_SPT0_STAT(val)      bfin_write16(SPT0_STAT, val)
-#define bfin_read_SPT0_MTCS0()         bfin_read32(SPT0_MTCS0)
-#define bfin_write_SPT0_MTCS0(val)     bfin_write32(SPT0_MTCS0, val)
-#define bfin_read_SPT0_MTCS1()         bfin_read32(SPT0_MTCS1)
-#define bfin_write_SPT0_MTCS1(val)     bfin_write32(SPT0_MTCS1, val)
-#define bfin_read_SPT0_MTCS2()         bfin_read32(SPT0_MTCS2)
-#define bfin_write_SPT0_MTCS2(val)     bfin_write32(SPT0_MTCS2, val)
-#define bfin_read_SPT0_MTCS3()         bfin_read32(SPT0_MTCS3)
-#define bfin_write_SPT0_MTCS3(val)     bfin_write32(SPT0_MTCS3, val)
-#define bfin_read_SPT0_MRCS0()         bfin_read32(SPT0_MRCS0)
-#define bfin_write_SPT0_MRCS0(val)     bfin_write32(SPT0_MRCS0, val)
-#define bfin_read_SPT0_MRCS1()         bfin_read32(SPT0_MRCS1)
-#define bfin_write_SPT0_MRCS1(val)     bfin_write32(SPT0_MRCS1, val)
-#define bfin_read_SPT0_MRCS2()         bfin_read32(SPT0_MRCS2)
-#define bfin_write_SPT0_MRCS2(val)     bfin_write32(SPT0_MRCS2, val)
-#define bfin_read_SPT0_MRCS3()         bfin_read32(SPT0_MRCS3)
-#define bfin_write_SPT0_MRCS3(val)     bfin_write32(SPT0_MRCS3, val)
-#define bfin_read_SPT0_MCMC1()         bfin_read16(SPT0_MCMC1)
-#define bfin_write_SPT0_MCMC1(val)     bfin_write16(SPT0_MCMC1, val)
-#define bfin_read_SPT0_MCMC2()         bfin_read16(SPT0_MCMC2)
-#define bfin_write_SPT0_MCMC2(val)     bfin_write16(SPT0_MCMC2, val)
-#define bfin_read_SPT0_CHNL()          bfin_read16(SPT0_CHNL)
-#define bfin_write_SPT0_CHNL(val)      bfin_write16(SPT0_CHNL, val)
-#define bfin_read_SPT1_TX_CONFIG0()    bfin_read16(SPT1_TX_CONFIG0)
-#define bfin_write_SPT1_TX_CONFIG0(val) bfin_write16(SPT1_TX_CONFIG0, val)
-#define bfin_read_SPT1_TX_CONFIG1()    bfin_read16(SPT1_TX_CONFIG1)
-#define bfin_write_SPT1_TX_CONFIG1(val) bfin_write16(SPT1_TX_CONFIG1, val)
-#define bfin_read_SPT1_RX_CONFIG0()    bfin_read16(SPT1_RX_CONFIG0)
-#define bfin_write_SPT1_RX_CONFIG0(val) bfin_write16(SPT1_RX_CONFIG0, val)
-#define bfin_read_SPT1_RX_CONFIG1()    bfin_read16(SPT1_RX_CONFIG1)
-#define bfin_write_SPT1_RX_CONFIG1(val) bfin_write16(SPT1_RX_CONFIG1, val)
-#define bfin_read_SPT1_TX()            bfin_read16(SPT1_TX)
-#define bfin_write_SPT1_TX(val)        bfin_write16(SPT1_TX, val)
-#define bfin_read_SPT1_RX()            bfin_read16(SPT1_RX)
-#define bfin_write_SPT1_RX(val)        bfin_write16(SPT1_RX, val)
-#define bfin_read_SPT1_TSCLKDIV()      bfin_read16(SPT1_TSCLKDIV)
-#define bfin_write_SPT1_TSCLKDIV(val)  bfin_write16(SPT1_TSCLKDIV, val)
-#define bfin_read_SPT1_RSCLKDIV()      bfin_read16(SPT1_RSCLKDIV)
-#define bfin_write_SPT1_RSCLKDIV(val)  bfin_write16(SPT1_RSCLKDIV, val)
-#define bfin_read_SPT1_TFSDIV()        bfin_read16(SPT1_TFSDIV)
-#define bfin_write_SPT1_TFSDIV(val)    bfin_write16(SPT1_TFSDIV, val)
-#define bfin_read_SPT1_RFSDIV()        bfin_read16(SPT1_RFSDIV)
-#define bfin_write_SPT1_RFSDIV(val)    bfin_write16(SPT1_RFSDIV, val)
-#define bfin_read_SPT1_STAT()          bfin_read16(SPT1_STAT)
-#define bfin_write_SPT1_STAT(val)      bfin_write16(SPT1_STAT, val)
-#define bfin_read_SPT1_MTCS0()         bfin_read32(SPT1_MTCS0)
-#define bfin_write_SPT1_MTCS0(val)     bfin_write32(SPT1_MTCS0, val)
-#define bfin_read_SPT1_MTCS1()         bfin_read32(SPT1_MTCS1)
-#define bfin_write_SPT1_MTCS1(val)     bfin_write32(SPT1_MTCS1, val)
-#define bfin_read_SPT1_MTCS2()         bfin_read32(SPT1_MTCS2)
-#define bfin_write_SPT1_MTCS2(val)     bfin_write32(SPT1_MTCS2, val)
-#define bfin_read_SPT1_MTCS3()         bfin_read32(SPT1_MTCS3)
-#define bfin_write_SPT1_MTCS3(val)     bfin_write32(SPT1_MTCS3, val)
-#define bfin_read_SPT1_MRCS0()         bfin_read32(SPT1_MRCS0)
-#define bfin_write_SPT1_MRCS0(val)     bfin_write32(SPT1_MRCS0, val)
-#define bfin_read_SPT1_MRCS1()         bfin_read32(SPT1_MRCS1)
-#define bfin_write_SPT1_MRCS1(val)     bfin_write32(SPT1_MRCS1, val)
-#define bfin_read_SPT1_MRCS2()         bfin_read32(SPT1_MRCS2)
-#define bfin_write_SPT1_MRCS2(val)     bfin_write32(SPT1_MRCS2, val)
-#define bfin_read_SPT1_MRCS3()         bfin_read32(SPT1_MRCS3)
-#define bfin_write_SPT1_MRCS3(val)     bfin_write32(SPT1_MRCS3, val)
-#define bfin_read_SPT1_MCMC1()         bfin_read16(SPT1_MCMC1)
-#define bfin_write_SPT1_MCMC1(val)     bfin_write16(SPT1_MCMC1, val)
-#define bfin_read_SPT1_MCMC2()         bfin_read16(SPT1_MCMC2)
-#define bfin_write_SPT1_MCMC2(val)     bfin_write16(SPT1_MCMC2, val)
-#define bfin_read_SPT1_CHNL()          bfin_read16(SPT1_CHNL)
-#define bfin_write_SPT1_CHNL(val)      bfin_write16(SPT1_CHNL, val)
-#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_TBUFCTL()            bfin_read32(TBUFCTL)
-#define bfin_write_TBUFCTL(val)        bfin_write32(TBUFCTL, val)
-#define bfin_read_TBUFSTAT()           bfin_read32(TBUFSTAT)
-#define bfin_write_TBUFSTAT(val)       bfin_write32(TBUFSTAT, val)
-#define bfin_read_TBUF()               bfin_readPTR(TBUF)
-#define bfin_write_TBUF(val)           bfin_writePTR(TBUF, val)
-#define bfin_read_PFCTL()              bfin_read32(PFCTL)
-#define bfin_write_PFCTL(val)          bfin_write32(PFCTL, val)
-#define bfin_read_PFCNTR0()            bfin_read32(PFCNTR0)
-#define bfin_write_PFCNTR0(val)        bfin_write32(PFCNTR0, val)
-#define bfin_read_PFCNTR1()            bfin_read32(PFCNTR1)
-#define bfin_write_PFCNTR1(val)        bfin_write32(PFCNTR1, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define bfin_read_FIO_FLAG_D()         bfin_read16(FIO_FLAG_D)
-#define bfin_write_FIO_FLAG_D(val)     bfin_write16(FIO_FLAG_D, val)
-#define bfin_read_FIO_FLAG_C()         bfin_read16(FIO_FLAG_C)
-#define bfin_write_FIO_FLAG_C(val)     bfin_write16(FIO_FLAG_C, val)
-#define bfin_read_FIO_FLAG_S()         bfin_read16(FIO_FLAG_S)
-#define bfin_write_FIO_FLAG_S(val)     bfin_write16(FIO_FLAG_S, val)
-#define bfin_read_FIO_FLAG_T()         bfin_read16(FIO_FLAG_T)
-#define bfin_write_FIO_FLAG_T(val)     bfin_write16(FIO_FLAG_T, val)
-#define bfin_read_FIO_MASKA_D()        bfin_read16(FIO_MASKA_D)
-#define bfin_write_FIO_MASKA_D(val)    bfin_write16(FIO_MASKA_D, val)
-#define bfin_read_FIO_MASKA_C()        bfin_read16(FIO_MASKA_C)
-#define bfin_write_FIO_MASKA_C(val)    bfin_write16(FIO_MASKA_C, val)
-#define bfin_read_FIO_MASKA_S()        bfin_read16(FIO_MASKA_S)
-#define bfin_write_FIO_MASKA_S(val)    bfin_write16(FIO_MASKA_S, val)
-#define bfin_read_FIO_MASKA_T()        bfin_read16(FIO_MASKA_T)
-#define bfin_write_FIO_MASKA_T(val)    bfin_write16(FIO_MASKA_T, val)
-#define bfin_read_FIO_MASKB_D()        bfin_read16(FIO_MASKB_D)
-#define bfin_write_FIO_MASKB_D(val)    bfin_write16(FIO_MASKB_D, val)
-#define bfin_read_FIO_MASKB_C()        bfin_read16(FIO_MASKB_C)
-#define bfin_write_FIO_MASKB_C(val)    bfin_write16(FIO_MASKB_C, val)
-#define bfin_read_FIO_MASKB_S()        bfin_read16(FIO_MASKB_S)
-#define bfin_write_FIO_MASKB_S(val)    bfin_write16(FIO_MASKB_S, val)
-#define bfin_read_FIO_MASKB_T()        bfin_read16(FIO_MASKB_T)
-#define bfin_write_FIO_MASKB_T(val)    bfin_write16(FIO_MASKB_T, val)
-#define bfin_read_FIO_DIR()            bfin_read16(FIO_DIR)
-#define bfin_write_FIO_DIR(val)        bfin_write16(FIO_DIR, val)
-#define bfin_read_FIO_POLAR()          bfin_read16(FIO_POLAR)
-#define bfin_write_FIO_POLAR(val)      bfin_write16(FIO_POLAR, val)
-#define bfin_read_FIO_EDGE()           bfin_read16(FIO_EDGE)
-#define bfin_write_FIO_EDGE(val)       bfin_write16(FIO_EDGE, val)
-#define bfin_read_FIO_BOTH()           bfin_read16(FIO_BOTH)
-#define bfin_write_FIO_BOTH(val)       bfin_write16(FIO_BOTH, val)
-#define bfin_read_FIO_INEN()           bfin_read16(FIO_INEN)
-#define bfin_write_FIO_INEN(val)       bfin_write16(FIO_INEN, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_read32(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_write32(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_read32(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_write32(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_read32(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_write32(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_read32(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_write32(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_read32(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_write32(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_read32(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_write32(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_read32(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_write32(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_read32(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_write32(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_read32(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_write32(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_read32(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_write32(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_read32(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_write32(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_read32(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_write32(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_read32(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_write32(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_read32(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_write32(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_read32(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_write32(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_read32(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_write32(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_read32(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_write32(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_read32(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_write32(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_read32(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_write32(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_read32(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_write32(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_read32(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_write32(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_read32(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_write32(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_read32(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_write32(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_read32(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_write32(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_read32(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_write32(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_read32(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_write32(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_read32(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_write32(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_read32(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_write32(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_read32(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_write32(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_read32(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_write32(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_read32(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_write32(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_read32(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_write32(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_read32(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_write32(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_read32(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_write32(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_read32(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_write32(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_read32(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_write32(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_read32(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_write32(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_read32(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_write32(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_read32(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_write32(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_read32(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_write32(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_read32(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_write32(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_read32(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_write32(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_read32(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_write32(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_read32(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_write32(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_read32(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_write32(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_read32(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_write32(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_read32(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_write32(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF531_proc__ */

+ 0 - 444
arch/blackfin/include/asm/mach-bf533/BF531_def.h

@@ -1,444 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF531_proc__
-#define __BFIN_DEF_ADSP_BF531_proc__
-
-#include "../mach-common/ADSP-EDN-core_def.h"
-
-#define MDMAFLX0_DMACNFG_D             0xFFC00E08
-#define MDMAFLX0_XCOUNT_D              0xFFC00E10
-#define MDMAFLX0_XMODIFY_D             0xFFC00E14
-#define MDMAFLX0_YCOUNT_D              0xFFC00E18
-#define MDMAFLX0_YMODIFY_D             0xFFC00E1C
-#define MDMAFLX0_IRQSTAT_D             0xFFC00E28
-#define MDMAFLX0_PMAP_D                0xFFC00E2C
-#define MDMAFLX0_CURXCOUNT_D           0xFFC00E30
-#define MDMAFLX0_CURYCOUNT_D           0xFFC00E38
-#define MDMAFLX0_DMACNFG_S             0xFFC00E48
-#define MDMAFLX0_XCOUNT_S              0xFFC00E50
-#define MDMAFLX0_XMODIFY_S             0xFFC00E54
-#define MDMAFLX0_YCOUNT_S              0xFFC00E58
-#define MDMAFLX0_YMODIFY_S             0xFFC00E5C
-#define MDMAFLX0_IRQSTAT_S             0xFFC00E68
-#define MDMAFLX0_PMAP_S                0xFFC00E6C
-#define MDMAFLX0_CURXCOUNT_S           0xFFC00E70
-#define MDMAFLX0_CURYCOUNT_S           0xFFC00E78
-#define MDMAFLX1_DMACNFG_D             0xFFC00E88
-#define MDMAFLX1_XCOUNT_D              0xFFC00E90
-#define MDMAFLX1_XMODIFY_D             0xFFC00E94
-#define MDMAFLX1_YCOUNT_D              0xFFC00E98
-#define MDMAFLX1_YMODIFY_D             0xFFC00E9C
-#define MDMAFLX1_IRQSTAT_D             0xFFC00EA8
-#define MDMAFLX1_PMAP_D                0xFFC00EAC
-#define MDMAFLX1_CURXCOUNT_D           0xFFC00EB0
-#define MDMAFLX1_CURYCOUNT_D           0xFFC00EB8
-#define MDMAFLX1_DMACNFG_S             0xFFC00EC8
-#define MDMAFLX1_XCOUNT_S              0xFFC00ED0
-#define MDMAFLX1_XMODIFY_S             0xFFC00ED4
-#define MDMAFLX1_YCOUNT_S              0xFFC00ED8
-#define MDMAFLX1_YMODIFY_S             0xFFC00EDC
-#define MDMAFLX1_IRQSTAT_S             0xFFC00EE8
-#define MDMAFLX1_PMAP_S                0xFFC00EEC
-#define MDMAFLX1_CURXCOUNT_S           0xFFC00EF0
-#define MDMAFLX1_CURYCOUNT_S           0xFFC00EF8
-#define DMAFLX0_DMACNFG                0xFFC00C08
-#define DMAFLX0_XCOUNT                 0xFFC00C10
-#define DMAFLX0_XMODIFY                0xFFC00C14
-#define DMAFLX0_YCOUNT                 0xFFC00C18
-#define DMAFLX0_YMODIFY                0xFFC00C1C
-#define DMAFLX0_IRQSTAT                0xFFC00C28
-#define DMAFLX0_PMAP                   0xFFC00C2C
-#define DMAFLX0_CURXCOUNT              0xFFC00C30
-#define DMAFLX0_CURYCOUNT              0xFFC00C38
-#define DMAFLX1_DMACNFG                0xFFC00C48
-#define DMAFLX1_XCOUNT                 0xFFC00C50
-#define DMAFLX1_XMODIFY                0xFFC00C54
-#define DMAFLX1_YCOUNT                 0xFFC00C58
-#define DMAFLX1_YMODIFY                0xFFC00C5C
-#define DMAFLX1_IRQSTAT                0xFFC00C68
-#define DMAFLX1_PMAP                   0xFFC00C6C
-#define DMAFLX1_CURXCOUNT              0xFFC00C70
-#define DMAFLX1_CURYCOUNT              0xFFC00C78
-#define DMAFLX2_DMACNFG                0xFFC00C88
-#define DMAFLX2_XCOUNT                 0xFFC00C90
-#define DMAFLX2_XMODIFY                0xFFC00C94
-#define DMAFLX2_YCOUNT                 0xFFC00C98
-#define DMAFLX2_YMODIFY                0xFFC00C9C
-#define DMAFLX2_IRQSTAT                0xFFC00CA8
-#define DMAFLX2_PMAP                   0xFFC00CAC
-#define DMAFLX2_CURXCOUNT              0xFFC00CB0
-#define DMAFLX2_CURYCOUNT              0xFFC00CB8
-#define DMAFLX3_DMACNFG                0xFFC00CC8
-#define DMAFLX3_XCOUNT                 0xFFC00CD0
-#define DMAFLX3_XMODIFY                0xFFC00CD4
-#define DMAFLX3_YCOUNT                 0xFFC00CD8
-#define DMAFLX3_YMODIFY                0xFFC00CDC
-#define DMAFLX3_IRQSTAT                0xFFC00CE8
-#define DMAFLX3_PMAP                   0xFFC00CEC
-#define DMAFLX3_CURXCOUNT              0xFFC00CF0
-#define DMAFLX3_CURYCOUNT              0xFFC00CF8
-#define DMAFLX4_DMACNFG                0xFFC00D08
-#define DMAFLX4_XCOUNT                 0xFFC00D10
-#define DMAFLX4_XMODIFY                0xFFC00D14
-#define DMAFLX4_YCOUNT                 0xFFC00D18
-#define DMAFLX4_YMODIFY                0xFFC00D1C
-#define DMAFLX4_IRQSTAT                0xFFC00D28
-#define DMAFLX4_PMAP                   0xFFC00D2C
-#define DMAFLX4_CURXCOUNT              0xFFC00D30
-#define DMAFLX4_CURYCOUNT              0xFFC00D38
-#define DMAFLX5_DMACNFG                0xFFC00D48
-#define DMAFLX5_XCOUNT                 0xFFC00D50
-#define DMAFLX5_XMODIFY                0xFFC00D54
-#define DMAFLX5_YCOUNT                 0xFFC00D58
-#define DMAFLX5_YMODIFY                0xFFC00D5C
-#define DMAFLX5_IRQSTAT                0xFFC00D68
-#define DMAFLX5_PMAP                   0xFFC00D6C
-#define DMAFLX5_CURXCOUNT              0xFFC00D70
-#define DMAFLX5_CURYCOUNT              0xFFC00D78
-#define DMAFLX6_DMACNFG                0xFFC00D88
-#define DMAFLX6_XCOUNT                 0xFFC00D90
-#define DMAFLX6_XMODIFY                0xFFC00D94
-#define DMAFLX6_YCOUNT                 0xFFC00D98
-#define DMAFLX6_YMODIFY                0xFFC00D9C
-#define DMAFLX6_IRQSTAT                0xFFC00DA8
-#define DMAFLX6_PMAP                   0xFFC00DAC
-#define DMAFLX6_CURXCOUNT              0xFFC00DB0
-#define DMAFLX6_CURYCOUNT              0xFFC00DB8
-#define DMAFLX7_DMACNFG                0xFFC00DC8
-#define DMAFLX7_XCOUNT                 0xFFC00DD0
-#define DMAFLX7_XMODIFY                0xFFC00DD4
-#define DMAFLX7_YCOUNT                 0xFFC00DD8
-#define DMAFLX7_YMODIFY                0xFFC00DDC
-#define DMAFLX7_IRQSTAT                0xFFC00DE8
-#define DMAFLX7_PMAP                   0xFFC00DEC
-#define DMAFLX7_CURXCOUNT              0xFFC00DF0
-#define DMAFLX7_CURYCOUNT              0xFFC00DF8
-#define TIMER0_CONFIG                  0xFFC00600
-#define TIMER0_COUNTER                 0xFFC00604
-#define TIMER0_PERIOD                  0xFFC00608
-#define TIMER0_WIDTH                   0xFFC0060C
-#define TIMER1_CONFIG                  0xFFC00610
-#define TIMER1_COUNTER                 0xFFC00614
-#define TIMER1_PERIOD                  0xFFC00618
-#define TIMER1_WIDTH                   0xFFC0061C
-#define TIMER2_CONFIG                  0xFFC00620
-#define TIMER2_COUNTER                 0xFFC00624
-#define TIMER2_PERIOD                  0xFFC00628
-#define TIMER2_WIDTH                   0xFFC0062C
-#define TIMER_ENABLE                   0xFFC00640
-#define TIMER_DISABLE                  0xFFC00644
-#define TIMER_STATUS                   0xFFC00648
-#define SIC_RVECT                      0xFFC00108 /* Interrupt Reset Vector Address Register */
-#define SIC_IMASK                      0xFFC0010C /* Interrupt Mask Register */
-#define SIC_IAR0                       0xFFC00110 /* Interrupt Assignment Register 0 */
-#define SIC_IAR1                       0xFFC00114 /* Interrupt Assignment Register 1 */
-#define SIC_IAR2                       0xFFC00118 /* Interrupt Assignment Register 2 */
-#define SIC_IAR3                       0xFFC0011C /* Interrupt Assignment Register 3 */
-#define SIC_ISR                        0xFFC00120 /* Interrupt Status Register */
-#define SIC_IWR                        0xFFC00124 /* Interrupt Wakeup Register */
-#define UART_THR                       0xFFC00400 /* Transmit Holding */
-#define UART_DLL                       0xFFC00400 /* Divisor Latch Low Byte */
-#define UART_DLH                       0xFFC00404 /* Divisor Latch High Byte */
-#define UART_IER                       0xFFC00404
-#define UART_IIR                       0xFFC00408
-#define UART_LCR                       0xFFC0040C
-#define UART_MCR                       0xFFC00410
-#define UART_LSR                       0xFFC00414
-#define UART_SCR                       0xFFC0041C
-#define UART_RBR                       0xFFC00400 /* Receive Buffer */
-#define UART0_RBR                      UART_RBR
-#define UART_GCTL                      0xFFC00424
-#define SPT0_TX_CONFIG0                0xFFC00800
-#define SPT0_TX_CONFIG1                0xFFC00804
-#define SPT0_RX_CONFIG0                0xFFC00820
-#define SPT0_RX_CONFIG1                0xFFC00824
-#define SPT0_TX                        0xFFC00810
-#define SPT0_RX                        0xFFC00818
-#define SPT0_TSCLKDIV                  0xFFC00808
-#define SPT0_RSCLKDIV                  0xFFC00828
-#define SPT0_TFSDIV                    0xFFC0080C
-#define SPT0_RFSDIV                    0xFFC0082C
-#define SPT0_STAT                      0xFFC00830
-#define SPT0_MTCS0                     0xFFC00840
-#define SPT0_MTCS1                     0xFFC00844
-#define SPT0_MTCS2                     0xFFC00848
-#define SPT0_MTCS3                     0xFFC0084C
-#define SPT0_MRCS0                     0xFFC00850
-#define SPT0_MRCS1                     0xFFC00854
-#define SPT0_MRCS2                     0xFFC00858
-#define SPT0_MRCS3                     0xFFC0085C
-#define SPT0_MCMC1                     0xFFC00838
-#define SPT0_MCMC2                     0xFFC0083C
-#define SPT0_CHNL                      0xFFC00834
-#define SPT1_TX_CONFIG0                0xFFC00900
-#define SPT1_TX_CONFIG1                0xFFC00904
-#define SPT1_RX_CONFIG0                0xFFC00920
-#define SPT1_RX_CONFIG1                0xFFC00924
-#define SPT1_TX                        0xFFC00910
-#define SPT1_RX                        0xFFC00918
-#define SPT1_TSCLKDIV                  0xFFC00908
-#define SPT1_RSCLKDIV                  0xFFC00928
-#define SPT1_TFSDIV                    0xFFC0090C
-#define SPT1_RFSDIV                    0xFFC0092C
-#define SPT1_STAT                      0xFFC00930
-#define SPT1_MTCS0                     0xFFC00940
-#define SPT1_MTCS1                     0xFFC00944
-#define SPT1_MTCS2                     0xFFC00948
-#define SPT1_MTCS3                     0xFFC0094C
-#define SPT1_MRCS0                     0xFFC00950
-#define SPT1_MRCS1                     0xFFC00954
-#define SPT1_MRCS2                     0xFFC00958
-#define SPT1_MRCS3                     0xFFC0095C
-#define SPT1_MCMC1                     0xFFC00938
-#define SPT1_MCMC2                     0xFFC0093C
-#define SPT1_CHNL                      0xFFC00934
-#define PPI_CONTROL                    0xFFC01000
-#define PPI_STATUS                     0xFFC01004
-#define PPI_DELAY                      0xFFC0100C
-#define PPI_COUNT                      0xFFC01008
-#define PPI_FRAME                      0xFFC01010
-#define PLL_CTL                        0xFFC00000 /* PLL Control register (16-bit) */
-#define PLL_DIV                        0xFFC00004 /* PLL Divide Register (16-bit) */
-#define VR_CTL                         0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
-#define PLL_STAT                       0xFFC0000C /* PLL Status register (16-bit) */
-#define PLL_LOCKCNT                    0xFFC00010 /* PLL Lock Count register (16-bit) */
-#define SWRST                          0xFFC00100 /* Software Reset Register (16-bit) */
-#define SYSCR                          0xFFC00104 /* System Configuration register */
-#define CHIPID                         0xFFC00014
-#define WDOG_CTL                       0xFFC00200 /* Watchdog Control Register */
-#define WDOG_CNT                       0xFFC00204 /* Watchdog Count Register */
-#define WDOG_STAT                      0xFFC00208 /* Watchdog Status Register */
-#define RTC_STAT                       0xFFC00300
-#define RTC_ICTL                       0xFFC00304
-#define RTC_ISTAT                      0xFFC00308
-#define RTC_SWCNT                      0xFFC0030C
-#define RTC_ALARM                      0xFFC00310
-#define RTC_PREN                       0xFFC00314
-#define SPI_CTL                        0xFFC00500
-#define SPI_FLG                        0xFFC00504
-#define SPI_STAT                       0xFFC00508
-#define SPI_TDBR                       0xFFC0050C
-#define SPI_RDBR                       0xFFC00510
-#define SPI_BAUD                       0xFFC00514
-#define SPI_SHADOW                     0xFFC00518
-#define FIO_FLAG_D                     0xFFC00700
-#define FIO_FLAG_C                     0xFFC00704
-#define FIO_FLAG_S                     0xFFC00708
-#define FIO_FLAG_T                     0xFFC0070C
-#define FIO_MASKA_D                    0xFFC00710
-#define FIO_MASKA_C                    0xFFC00714
-#define FIO_MASKA_S                    0xFFC00718
-#define FIO_MASKA_T                    0xFFC0071C
-#define FIO_MASKB_D                    0xFFC00720
-#define FIO_MASKB_C                    0xFFC00724
-#define FIO_MASKB_S                    0xFFC00728
-#define FIO_MASKB_T                    0xFFC0072C
-#define FIO_DIR                        0xFFC00730
-#define FIO_POLAR                      0xFFC00734
-#define FIO_EDGE                       0xFFC00738
-#define FIO_BOTH                       0xFFC0073C
-#define FIO_INEN                       0xFFC00740
-#define SPORT0_TCR1                    0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_TCR2                    0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_TCLKDIV                 0xFFC00808 /* SPORT0 Transmit Clock Divider */
-#define SPORT0_TFSDIV                  0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
-#define SPORT0_TX                      0xFFC00810 /* SPORT0 TX Data Register */
-#define SPORT0_RX                      0xFFC00818 /* SPORT0 RX Data Register */
-#define SPORT0_RCR1                    0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
-#define SPORT0_RCR2                    0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
-#define SPORT0_RCLKDIV                 0xFFC00828 /* SPORT0 Receive Clock Divider */
-#define SPORT0_RFSDIV                  0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
-#define SPORT0_STAT                    0xFFC00830 /* SPORT0 Status Register */
-#define SPORT0_CHNL                    0xFFC00834 /* SPORT0 Current Channel Register */
-#define SPORT0_MCMC1                   0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
-#define SPORT0_MCMC2                   0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
-#define SPORT1_TCR1                    0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_TCR2                    0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_TCLKDIV                 0xFFC00908 /* SPORT1 Transmit Clock Divider */
-#define SPORT1_TFSDIV                  0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
-#define SPORT1_TX                      0xFFC00910 /* SPORT1 TX Data Register */
-#define SPORT1_RX                      0xFFC00918 /* SPORT1 RX Data Register */
-#define SPORT1_RCR1                    0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
-#define SPORT1_RCR2                    0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
-#define SPORT1_RCLKDIV                 0xFFC00928 /* SPORT1 Receive Clock Divider */
-#define SPORT1_RFSDIV                  0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
-#define SPORT1_STAT                    0xFFC00930 /* SPORT1 Status Register */
-#define SPORT1_CHNL                    0xFFC00934 /* SPORT1 Current Channel Register */
-#define SPORT1_MCMC1                   0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
-#define SPORT1_MCMC2                   0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
-#define DMA0_NEXT_DESC_PTR             0xFFC00C00
-#define DMA0_START_ADDR                0xFFC00C04
-#define DMA0_CONFIG                    0xFFC00C08 /* DMA Channel 0 Configuration Register */
-#define DMA0_X_COUNT                   0xFFC00C10
-#define DMA0_X_MODIFY                  0xFFC00C14
-#define DMA0_Y_COUNT                   0xFFC00C18
-#define DMA0_Y_MODIFY                  0xFFC00C1C
-#define DMA0_CURR_DESC_PTR             0xFFC00C20
-#define DMA0_CURR_ADDR                 0xFFC00C24
-#define DMA0_IRQ_STATUS                0xFFC00C28
-#define DMA0_PERIPHERAL_MAP            0xFFC00C2C
-#define DMA0_CURR_X_COUNT              0xFFC00C30
-#define DMA0_CURR_Y_COUNT              0xFFC00C38
-#define DMA1_NEXT_DESC_PTR             0xFFC00C40
-#define DMA1_START_ADDR                0xFFC00C44
-#define DMA1_CONFIG                    0xFFC00C48 /* DMA Channel 1 Configuration Register */
-#define DMA1_X_COUNT                   0xFFC00C50
-#define DMA1_X_MODIFY                  0xFFC00C54
-#define DMA1_Y_COUNT                   0xFFC00C58
-#define DMA1_Y_MODIFY                  0xFFC00C5C
-#define DMA1_CURR_DESC_PTR             0xFFC00C60
-#define DMA1_CURR_ADDR                 0xFFC00C64
-#define DMA1_IRQ_STATUS                0xFFC00C68
-#define DMA1_PERIPHERAL_MAP            0xFFC00C6C
-#define DMA1_CURR_X_COUNT              0xFFC00C70
-#define DMA1_CURR_Y_COUNT              0xFFC00C78
-#define DMA2_NEXT_DESC_PTR             0xFFC00C80
-#define DMA2_START_ADDR                0xFFC00C84
-#define DMA2_CONFIG                    0xFFC00C88 /* DMA Channel 2 Configuration Register */
-#define DMA2_X_COUNT                   0xFFC00C90
-#define DMA2_X_MODIFY                  0xFFC00C94
-#define DMA2_Y_COUNT                   0xFFC00C98
-#define DMA2_Y_MODIFY                  0xFFC00C9C
-#define DMA2_CURR_DESC_PTR             0xFFC00CA0
-#define DMA2_CURR_ADDR                 0xFFC00CA4
-#define DMA2_IRQ_STATUS                0xFFC00CA8
-#define DMA2_PERIPHERAL_MAP            0xFFC00CAC
-#define DMA2_CURR_X_COUNT              0xFFC00CB0
-#define DMA2_CURR_Y_COUNT              0xFFC00CB8
-#define DMA3_NEXT_DESC_PTR             0xFFC00CC0
-#define DMA3_START_ADDR                0xFFC00CC4
-#define DMA3_CONFIG                    0xFFC00CC8 /* DMA Channel 3 Configuration Register */
-#define DMA3_X_COUNT                   0xFFC00CD0
-#define DMA3_X_MODIFY                  0xFFC00CD4
-#define DMA3_Y_COUNT                   0xFFC00CD8
-#define DMA3_Y_MODIFY                  0xFFC00CDC
-#define DMA3_CURR_DESC_PTR             0xFFC00CE0
-#define DMA3_CURR_ADDR                 0xFFC00CE4
-#define DMA3_IRQ_STATUS                0xFFC00CE8
-#define DMA3_PERIPHERAL_MAP            0xFFC00CEC
-#define DMA3_CURR_X_COUNT              0xFFC00CF0
-#define DMA3_CURR_Y_COUNT              0xFFC00CF8
-#define DMA4_NEXT_DESC_PTR             0xFFC00D00
-#define DMA4_START_ADDR                0xFFC00D04
-#define DMA4_CONFIG                    0xFFC00D08 /* DMA Channel 4 Configuration Register */
-#define DMA4_X_COUNT                   0xFFC00D10
-#define DMA4_X_MODIFY                  0xFFC00D14
-#define DMA4_Y_COUNT                   0xFFC00D18
-#define DMA4_Y_MODIFY                  0xFFC00D1C
-#define DMA4_CURR_DESC_PTR             0xFFC00D20
-#define DMA4_CURR_ADDR                 0xFFC00D24
-#define DMA4_IRQ_STATUS                0xFFC00D28
-#define DMA4_PERIPHERAL_MAP            0xFFC00D2C
-#define DMA4_CURR_X_COUNT              0xFFC00D30
-#define DMA4_CURR_Y_COUNT              0xFFC00D38
-#define DMA5_NEXT_DESC_PTR             0xFFC00D40
-#define DMA5_START_ADDR                0xFFC00D44
-#define DMA5_CONFIG                    0xFFC00D48 /* DMA Channel 5 Configuration Register */
-#define DMA5_X_COUNT                   0xFFC00D50
-#define DMA5_X_MODIFY                  0xFFC00D54
-#define DMA5_Y_COUNT                   0xFFC00D58
-#define DMA5_Y_MODIFY                  0xFFC00D5C
-#define DMA5_CURR_DESC_PTR             0xFFC00D60
-#define DMA5_CURR_ADDR                 0xFFC00D64
-#define DMA5_IRQ_STATUS                0xFFC00D68
-#define DMA5_PERIPHERAL_MAP            0xFFC00D6C
-#define DMA5_CURR_X_COUNT              0xFFC00D70
-#define DMA5_CURR_Y_COUNT              0xFFC00D78
-#define DMA6_NEXT_DESC_PTR             0xFFC00D80
-#define DMA6_START_ADDR                0xFFC00D84
-#define DMA6_CONFIG                    0xFFC00D88 /* DMA Channel 6 Configuration Register */
-#define DMA6_X_COUNT                   0xFFC00D90
-#define DMA6_X_MODIFY                  0xFFC00D94
-#define DMA6_Y_COUNT                   0xFFC00D98
-#define DMA6_Y_MODIFY                  0xFFC00D9C
-#define DMA6_CURR_DESC_PTR             0xFFC00DA0
-#define DMA6_CURR_ADDR                 0xFFC00DA4
-#define DMA6_IRQ_STATUS                0xFFC00DA8
-#define DMA6_PERIPHERAL_MAP            0xFFC00DAC
-#define DMA6_CURR_X_COUNT              0xFFC00DB0
-#define DMA6_CURR_Y_COUNT              0xFFC00DB8
-#define DMA7_NEXT_DESC_PTR             0xFFC00DC0
-#define DMA7_START_ADDR                0xFFC00DC4
-#define DMA7_CONFIG                    0xFFC00DC8 /* DMA Channel 7 Configuration Register */
-#define DMA7_X_COUNT                   0xFFC00DD0
-#define DMA7_X_MODIFY                  0xFFC00DD4
-#define DMA7_Y_COUNT                   0xFFC00DD8
-#define DMA7_Y_MODIFY                  0xFFC00DDC
-#define DMA7_CURR_DESC_PTR             0xFFC00DE0
-#define DMA7_CURR_ADDR                 0xFFC00DE4
-#define DMA7_IRQ_STATUS                0xFFC00DE8
-#define DMA7_PERIPHERAL_MAP            0xFFC00DEC
-#define DMA7_CURR_X_COUNT              0xFFC00DF0
-#define DMA7_CURR_Y_COUNT              0xFFC00DF8
-#define MDMA_D0_NEXT_DESC_PTR          0xFFC00E00
-#define MDMA_D0_START_ADDR             0xFFC00E04
-#define MDMA_D0_CONFIG                 0xFFC00E08
-#define MDMA_D0_X_COUNT                0xFFC00E10
-#define MDMA_D0_X_MODIFY               0xFFC00E14
-#define MDMA_D0_Y_COUNT                0xFFC00E18
-#define MDMA_D0_Y_MODIFY               0xFFC00E1C
-#define MDMA_D0_CURR_DESC_PTR          0xFFC00E20
-#define MDMA_D0_CURR_ADDR              0xFFC00E24
-#define MDMA_D0_IRQ_STATUS             0xFFC00E28
-#define MDMA_D0_PERIPHERAL_MAP         0xFFC00E2C
-#define MDMA_D0_CURR_X_COUNT           0xFFC00E30
-#define MDMA_D0_CURR_Y_COUNT           0xFFC00E38
-#define MDMA_S0_NEXT_DESC_PTR          0xFFC00E40
-#define MDMA_S0_START_ADDR             0xFFC00E44
-#define MDMA_S0_CONFIG                 0xFFC00E48
-#define MDMA_S0_X_COUNT                0xFFC00E50
-#define MDMA_S0_X_MODIFY               0xFFC00E54
-#define MDMA_S0_Y_COUNT                0xFFC00E58
-#define MDMA_S0_Y_MODIFY               0xFFC00E5C
-#define MDMA_S0_CURR_DESC_PTR          0xFFC00E60
-#define MDMA_S0_CURR_ADDR              0xFFC00E64
-#define MDMA_S0_IRQ_STATUS             0xFFC00E68
-#define MDMA_S0_PERIPHERAL_MAP         0xFFC00E6C
-#define MDMA_S0_CURR_X_COUNT           0xFFC00E70
-#define MDMA_S0_CURR_Y_COUNT           0xFFC00E78
-#define MDMA_D1_NEXT_DESC_PTR          0xFFC00E80
-#define MDMA_D1_START_ADDR             0xFFC00E84
-#define MDMA_D1_CONFIG                 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
-#define MDMA_D1_X_COUNT                0xFFC00E90
-#define MDMA_D1_X_MODIFY               0xFFC00E94
-#define MDMA_D1_Y_COUNT                0xFFC00E98
-#define MDMA_D1_Y_MODIFY               0xFFC00E9C
-#define MDMA_D1_CURR_DESC_PTR          0xFFC00EA0
-#define MDMA_D1_CURR_ADDR              0xFFC00EA4
-#define MDMA_D1_IRQ_STATUS             0xFFC00EA8
-#define MDMA_D1_PERIPHERAL_MAP         0xFFC00EAC
-#define MDMA_D1_CURR_X_COUNT           0xFFC00EB0
-#define MDMA_D1_CURR_Y_COUNT           0xFFC00EB8
-#define MDMA_S1_NEXT_DESC_PTR          0xFFC00EC0
-#define MDMA_S1_START_ADDR             0xFFC00EC4
-#define MDMA_S1_CONFIG                 0xFFC00EC8
-#define MDMA_S1_X_COUNT                0xFFC00ED0
-#define MDMA_S1_X_MODIFY               0xFFC00ED4
-#define MDMA_S1_Y_COUNT                0xFFC00ED8
-#define MDMA_S1_Y_MODIFY               0xFFC00EDC
-#define MDMA_S1_CURR_DESC_PTR          0xFFC00EE0
-#define MDMA_S1_CURR_ADDR              0xFFC00EE4
-#define MDMA_S1_IRQ_STATUS             0xFFC00EE8
-#define MDMA_S1_PERIPHERAL_MAP         0xFFC00EEC
-#define MDMA_S1_CURR_X_COUNT           0xFFC00EF0
-#define MDMA_S1_CURR_Y_COUNT           0xFFC00EF8
-#define EBIU_AMGCTL                    0xFFC00A00
-#define EBIU_AMBCTL0                   0xFFC00A04
-#define EBIU_AMBCTL1                   0xFFC00A08
-#define EBIU_SDGCTL                    0xFFC00A10
-#define EBIU_SDBCTL                    0xFFC00A14
-#define EBIU_SDRRC                     0xFFC00A18
-#define EBIU_SDSTAT                    0xFFC00A1C
-#define DMA_TC_CNT                     0xFFC00B0C
-#define DMA_TC_PER                     0xFFC00B10
-
-#ifndef __BFIN_DEF_ADSP_BF533_proc__
-#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-#endif
-
-#endif /* __BFIN_DEF_ADSP_BF531_proc__ */

+ 0 - 1
arch/blackfin/include/asm/mach-bf533/BF532_cdef.h

@@ -1 +0,0 @@
-#include "BF531_cdef.h"

+ 0 - 17
arch/blackfin/include/asm/mach-bf533/BF532_def.h

@@ -1,17 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF532_proc__
-#define __BFIN_DEF_ADSP_BF532_proc__
-
-#include "BF531_def.h"
-
-#ifndef __BFIN_DEF_ADSP_BF533_proc__
-#define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-#endif
-
-#endif /* __BFIN_DEF_ADSP_BF532_proc__ */

+ 0 - 1
arch/blackfin/include/asm/mach-bf533/BF533_cdef.h

@@ -1 +0,0 @@
-#include "BF532_cdef.h"

+ 0 - 21
arch/blackfin/include/asm/mach-bf533/BF533_def.h

@@ -1,21 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-def-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_DEF_ADSP_BF533_proc__
-#define __BFIN_DEF_ADSP_BF533_proc__
-
-#include "BF532_def.h"
-
-#define L1_DATA_A_SRAM 0xFF800000 /* 0xFF800000 -> 0xFF803FFF Data Bank A SRAM */
-#define L1_DATA_A_SRAM_SIZE (0xFF803FFF - 0xFF800000 + 1)
-#define L1_DATA_A_SRAM_END (L1_DATA_A_SRAM + L1_DATA_A_SRAM_SIZE)
-#define L1_DATA_B_SRAM 0xFF900000 /* 0xFF900000 -> 0xFF903FFF Data Bank B SRAM */
-#define L1_DATA_B_SRAM_SIZE (0xFF903FFF - 0xFF900000 + 1)
-#define L1_DATA_B_SRAM_END (L1_DATA_B_SRAM + L1_DATA_B_SRAM_SIZE)
-#define L1_INST_SRAM 0xFFA00000 /* 0xFFA00000 -> 0xFFA07FFF Instruction Bank A SRAM */
-#define L1_INST_SRAM_SIZE (0xFFA07FFF - 0xFFA00000 + 1)
-#define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
-
-#endif /* __BFIN_DEF_ADSP_BF533_proc__ */

+ 0 - 383
arch/blackfin/include/asm/mach-bf533/anomaly.h

@@ -1,383 +0,0 @@
-/*
- * DO NOT EDIT THIS FILE
- * This file is under version control at
- *   svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
- * and can be replaced with that version at any time
- * DO NOT EDIT THIS FILE
- *
- * Copyright 2004-2011 Analog Devices Inc.
- * Licensed under the ADI BSD license.
- *   https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
- */
-
-/* This file should be up to date with:
- *  - Revision G, 05/23/2011; ADSP-BF531/BF532/BF533 Blackfin Processor Anomaly List
- */
-
-#ifndef _MACH_ANOMALY_H_
-#define _MACH_ANOMALY_H_
-
-/* We do not support 0.1 or 0.2 silicon - sorry */
-#if __SILICON_REVISION__ < 3
-# error will not work on BF533 silicon version 0.0, 0.1, or 0.2
-#endif
-
-#if defined(__ADSPBF531__)
-# define ANOMALY_BF531 1
-#else
-# define ANOMALY_BF531 0
-#endif
-#if defined(__ADSPBF532__)
-# define ANOMALY_BF532 1
-#else
-# define ANOMALY_BF532 0
-#endif
-#if defined(__ADSPBF533__)
-# define ANOMALY_BF533 1
-#else
-# define ANOMALY_BF533 0
-#endif
-
-/* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
-#define ANOMALY_05000074 (1)
-/* UART Line Status Register (UART_LSR) Bits Are Not Updated at the Same Time */
-#define ANOMALY_05000099 (__SILICON_REVISION__ < 5)
-/* Watchpoint Status Register (WPSTAT) Bits Are Set on Every Corresponding Match */
-#define ANOMALY_05000105 (__SILICON_REVISION__ > 2)
-/* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
-#define ANOMALY_05000119 (1)
-/* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
-#define ANOMALY_05000122 (1)
-/* Instruction DMA Can Cause Data Cache Fills to Fail (Boot Implications) */
-#define ANOMALY_05000158 (__SILICON_REVISION__ < 5)
-/* PPI Data Lengths between 8 and 16 Do Not Zero Out Upper Bits */
-#define ANOMALY_05000166 (1)
-/* Turning SPORTs on while External Frame Sync Is Active May Corrupt Data */
-#define ANOMALY_05000167 (1)
-/* PPI_COUNT Cannot Be Programmed to 0 in General Purpose TX or RX Modes */
-#define ANOMALY_05000179 (__SILICON_REVISION__ < 5)
-/* PPI_DELAY Not Functional in PPI Modes with 0 Frame Syncs */
-#define ANOMALY_05000180 (1)
-/* Timer Pin Limitations for PPI TX Modes with External Frame Syncs */
-#define ANOMALY_05000183 (__SILICON_REVISION__ < 4)
-/* False Protection Exceptions when Speculative Fetch Is Cancelled */
-#define ANOMALY_05000189 (__SILICON_REVISION__ < 4)
-/* False I/O Pin Interrupts on Edge-Sensitive Inputs When Polarity Setting Is Changed */
-#define ANOMALY_05000193 (__SILICON_REVISION__ < 4)
-/* Restarting SPORT in Specific Modes May Cause Data Corruption */
-#define ANOMALY_05000194 (__SILICON_REVISION__ < 4)
-/* Failing MMR Accesses when Preceding Memory Read Stalls */
-#define ANOMALY_05000198 (__SILICON_REVISION__ < 5)
-/* Current DMA Address Shows Wrong Value During Carry Fix */
-#define ANOMALY_05000199 (__SILICON_REVISION__ < 4)
-/* SPORT TFS and DT Are Incorrectly Driven During Inactive Channels in Certain Conditions */
-#define ANOMALY_05000200 (__SILICON_REVISION__ == 3 || __SILICON_REVISION__ == 4)
-/* Receive Frame Sync Not Ignored During Active Frames in SPORT Multi-Channel Mode */
-#define ANOMALY_05000201 (__SILICON_REVISION__ == 3)
-/* Possible Infinite Stall with Specific Dual-DAG Situation */
-#define ANOMALY_05000202 (__SILICON_REVISION__ < 5)
-/* Specific Sequence That Can Cause DMA Error or DMA Stopping */
-#define ANOMALY_05000203 (__SILICON_REVISION__ < 4)
-/* Incorrect Data Read with Writethrough "Allocate Cache Lines on Reads Only" Cache Mode */
-#define ANOMALY_05000204 (__SILICON_REVISION__ < 4 && ANOMALY_BF533)
-/* Recovery from "Brown-Out" Condition */
-#define ANOMALY_05000207 (__SILICON_REVISION__ < 4)
-/* VSTAT Status Bit in PLL_STAT Register Is Not Functional */
-#define ANOMALY_05000208 (1)
-/* Speed Path in Computational Unit Affects Certain Instructions */
-#define ANOMALY_05000209 (__SILICON_REVISION__ < 4)
-/* UART TX Interrupt Masked Erroneously */
-#define ANOMALY_05000215 (__SILICON_REVISION__ < 5)
-/* NMI Event at Boot Time Results in Unpredictable State */
-#define ANOMALY_05000219 (1)
-/* Incorrect Pulse-Width of UART Start Bit */
-#define ANOMALY_05000225 (__SILICON_REVISION__ < 5)
-/* Scratchpad Memory Bank Reads May Return Incorrect Data */
-#define ANOMALY_05000227 (__SILICON_REVISION__ < 5)
-/* SPI Slave Boot Mode Modifies Registers from Reset Value */
-#define ANOMALY_05000229 (1)
-/* UART Receiver is Less Robust Against Baudrate Differences in Certain Conditions */
-#define ANOMALY_05000230 (__SILICON_REVISION__ < 5)
-/* UART STB Bit Incorrectly Affects Receiver Setting */
-#define ANOMALY_05000231 (__SILICON_REVISION__ < 5)
-/* PPI_FS3 Is Not Driven in 2 or 3 Internal Frame Sync Transmit Modes */
-#define ANOMALY_05000233 (__SILICON_REVISION__ < 6)
-/* Incorrect Revision Number in DSPID Register */
-#define ANOMALY_05000234 (__SILICON_REVISION__ == 4)
-/* DF Bit in PLL_CTL Register Does Not Respond to Hardware Reset */
-#define ANOMALY_05000242 (__SILICON_REVISION__ < 5)
-/* If I-Cache Is On, CSYNC/SSYNC/IDLE Around Change of Control Causes Failures */
-#define ANOMALY_05000244 (__SILICON_REVISION__ < 5)
-/* False Hardware Error from an Access in the Shadow of a Conditional Branch */
-#define ANOMALY_05000245 (1)
-/* Data CPLBs Should Prevent False Hardware Errors */
-#define ANOMALY_05000246 (__SILICON_REVISION__ < 5)
-/* Incorrect Bit Shift of Data Word in Multichannel (TDM) Mode in Certain Conditions */
-#define ANOMALY_05000250 (__SILICON_REVISION__ == 4)
-/* Maximum External Clock Speed for Timers */
-#define ANOMALY_05000253 (__SILICON_REVISION__ < 5)
-/* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
-#define ANOMALY_05000254 (__SILICON_REVISION__ > 4)
-/* Entering Hibernate State with RTC Seconds Interrupt Not Functional */
-#define ANOMALY_05000255 (__SILICON_REVISION__ < 5)
-/* Interrupt/Exception During Short Hardware Loop May Cause Bad Instruction Fetches */
-#define ANOMALY_05000257 (__SILICON_REVISION__ < 5)
-/* Instruction Cache Is Corrupted When Bits 9 and 12 of the ICPLB Data Registers Differ */
-#define ANOMALY_05000258 (__SILICON_REVISION__ < 5)
-/* ICPLB_STATUS MMR Register May Be Corrupted */
-#define ANOMALY_05000260 (__SILICON_REVISION__ < 5)
-/* DCPLB_FAULT_ADDR MMR Register May Be Corrupted */
-#define ANOMALY_05000261 (__SILICON_REVISION__ < 5)
-/* Stores To Data Cache May Be Lost */
-#define ANOMALY_05000262 (__SILICON_REVISION__ < 5)
-/* Hardware Loop Corrupted When Taking an ICPLB Exception */
-#define ANOMALY_05000263 (__SILICON_REVISION__ < 5)
-/* CSYNC/SSYNC/IDLE Causes Infinite Stall in Penultimate Instruction in Hardware Loop */
-#define ANOMALY_05000264 (__SILICON_REVISION__ < 5)
-/* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
-#define ANOMALY_05000265 (1)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Increase */
-#define ANOMALY_05000269 (__SILICON_REVISION__ < 5)
-/* High I/O Activity Causes Output Voltage of Internal Voltage Regulator (Vddint) to Decrease */
-#define ANOMALY_05000270 (__SILICON_REVISION__ < 5)
-/* Spontaneous Reset of Internal Voltage Regulator */
-#define ANOMALY_05000271 (__SILICON_REVISION__ == 3)
-/* Certain Data Cache Writethrough Modes Fail for Vddint <= 0.9V */
-#define ANOMALY_05000272 (1)
-/* Writes to Synchronous SDRAM Memory May Be Lost */
-#define ANOMALY_05000273 (__SILICON_REVISION__ < 6)
-/* Timing Requirements Change for External Frame Sync PPI Modes with Non-Zero PPI_DELAY */
-#define ANOMALY_05000276 (1)
-/* Writes to an I/O Data Register One SCLK Cycle after an Edge Is Detected May Clear Interrupt */
-#define ANOMALY_05000277 (__SILICON_REVISION__ < 6)
-/* Disabling Peripherals with DMA Running May Cause DMA System Instability */
-#define ANOMALY_05000278 (__SILICON_REVISION__ < 6)
-/* False Hardware Error when ISR Context Is Not Restored */
-#define ANOMALY_05000281 (__SILICON_REVISION__ < 6)
-/* Memory DMA Corruption with 32-Bit Data and Traffic Control */
-#define ANOMALY_05000282 (__SILICON_REVISION__ < 6)
-/* System MMR Write Is Stalled Indefinitely when Killed in a Particular Stage */
-#define ANOMALY_05000283 (__SILICON_REVISION__ < 6)
-/* SPORTs May Receive Bad Data If FIFOs Fill Up */
-#define ANOMALY_05000288 (__SILICON_REVISION__ < 6)
-/* Memory-To-Memory DMA Source/Destination Descriptors Must Be in Same Memory Space */
-#define ANOMALY_05000301 (__SILICON_REVISION__ < 6)
-/* SSYNCs after Writes to DMA MMR Registers May Not Be Handled Correctly */
-#define ANOMALY_05000302 (__SILICON_REVISION__ < 5)
-/* SPORT_HYS Bit in PLL_CTL Register Is Not Functional */
-#define ANOMALY_05000305 (__SILICON_REVISION__ < 5)
-/* ALT_TIMING Bit in PPI_CONTROL Register Is Not Functional */
-#define ANOMALY_05000306 (__SILICON_REVISION__ < 5)
-/* SCKELOW Bit Does Not Maintain State Through Hibernate */
-#define ANOMALY_05000307 (1)	/* note: brokenness is noted in documentation, not anomaly sheet */
-/* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
-#define ANOMALY_05000310 (1)
-/* Erroneous Flag (GPIO) Pin Operations under Specific Sequences */
-#define ANOMALY_05000311 (__SILICON_REVISION__ < 6)
-/* Errors when SSYNC, CSYNC, or Loads to LT, LB and LC Registers Are Interrupted */
-#define ANOMALY_05000312 (__SILICON_REVISION__ < 6)
-/* PPI Is Level-Sensitive on First Transfer In Single Frame Sync Modes */
-#define ANOMALY_05000313 (__SILICON_REVISION__ < 6)
-/* Killed System MMR Write Completes Erroneously on Next System MMR Access */
-#define ANOMALY_05000315 (__SILICON_REVISION__ < 6)
-/* Internal Voltage Regulator Values of 1.05V, 1.10V and 1.15V Not Allowed for LQFP Packages */
-#define ANOMALY_05000319 ((ANOMALY_BF531 || ANOMALY_BF532) && __SILICON_REVISION__ < 6)
-/* Serial Port (SPORT) Multichannel Transmit Failure when Channel 0 Is Disabled */
-#define ANOMALY_05000357 (__SILICON_REVISION__ < 6)
-/* UART Break Signal Issues */
-#define ANOMALY_05000363 (__SILICON_REVISION__ < 5)
-/* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
-#define ANOMALY_05000366 (1)
-/* Possible RETS Register Corruption when Subroutine Is under 5 Cycles in Duration */
-#define ANOMALY_05000371 (__SILICON_REVISION__ < 6)
-/* PPI Does Not Start Properly In Specific Mode */
-#define ANOMALY_05000400 (__SILICON_REVISION__ == 5)
-/* SSYNC Stalls Processor when Executed from Non-Cacheable Memory */
-#define ANOMALY_05000402 (__SILICON_REVISION__ == 5)
-/* Level-Sensitive External GPIO Wakeups May Cause Indefinite Stall */
-#define ANOMALY_05000403 (1)
-/* Speculative Fetches Can Cause Undesired External FIFO Operations */
-#define ANOMALY_05000416 (1)
-/* Multichannel SPORT Channel Misalignment Under Specific Configuration */
-#define ANOMALY_05000425 (1)
-/* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
-#define ANOMALY_05000426 (1)
-/* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
-#define ANOMALY_05000443 (1)
-/* False Hardware Error when RETI Points to Invalid Memory */
-#define ANOMALY_05000461 (1)
-/* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
-#define ANOMALY_05000462 (1)
-/* Boot Failure When SDRAM Control Signals Toggle Coming Out Of Reset */
-#define ANOMALY_05000471 (1)
-/* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
-#define ANOMALY_05000473 (1)
-/* Possible Lockup Condition when Modifying PLL from External Memory */
-#define ANOMALY_05000475 (1)
-/* TESTSET Instruction Cannot Be Interrupted */
-#define ANOMALY_05000477 (1)
-/* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
-#define ANOMALY_05000481 (1)
-/* PLL May Latch Incorrect Values Coming Out of Reset */
-#define ANOMALY_05000489 (1)
-/* Instruction Memory Stalls Can Cause IFLUSH to Fail */
-#define ANOMALY_05000491 (1)
-/* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
-#define ANOMALY_05000494 (1)
-/* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
-#define ANOMALY_05000501 (1)
-
-/*
- * These anomalies have been "phased" out of analog.com anomaly sheets and are
- * here to show running on older silicon just isn't feasible.
- */
-
-/* Internal voltage regulator can't be modified via register writes */
-#define ANOMALY_05000066 (__SILICON_REVISION__ < 2)
-/* Watchpoints (Hardware Breakpoints) are not supported */
-#define ANOMALY_05000067 (__SILICON_REVISION__ < 3)
-/* SDRAM PSSE bit cannot be set again after SDRAM Powerup */
-#define ANOMALY_05000070 (__SILICON_REVISION__ < 2)
-/* Writing FIO_DIR can corrupt a programmable flag's data */
-#define ANOMALY_05000079 (__SILICON_REVISION__ < 2)
-/* Timer Auto-Baud Mode requires the UART clock to be enabled. */
-#define ANOMALY_05000086 (__SILICON_REVISION__ < 2)
-/* Internal Clocking Modes on SPORT0 not supported */
-#define ANOMALY_05000088 (__SILICON_REVISION__ < 2)
-/* Internal voltage regulator does not wake up from an RTC wakeup */
-#define ANOMALY_05000092 (__SILICON_REVISION__ < 2)
-/* The IFLUSH Instruction Must Be Preceded by a CSYNC Instruction */
-#define ANOMALY_05000093 (__SILICON_REVISION__ < 2)
-/* Vectoring to instruction that is being filled into the i-cache may cause erroneous behavior */
-#define ANOMALY_05000095 (__SILICON_REVISION__ < 2)
-/* PREFETCH, FLUSH, and FLUSHINV Instructions Must Be Followed by a CSYNC Instruction */
-#define ANOMALY_05000096 (__SILICON_REVISION__ < 2)
-/* Performance Monitor 0 and 1 are swapped when monitoring memory events */
-#define ANOMALY_05000097 (__SILICON_REVISION__ < 2)
-/* 32-bit SPORT DMA will be word reversed */
-#define ANOMALY_05000098 (__SILICON_REVISION__ < 2)
-/* Incorrect status in the UART_IIR register */
-#define ANOMALY_05000100 (__SILICON_REVISION__ < 2)
-/* Reading X_MODIFY or Y_MODIFY while DMA channel is active */
-#define ANOMALY_05000101 (__SILICON_REVISION__ < 2)
-/* Descriptor MemDMA may lock up with 32-bit transfers or if transfers span 64KB buffers */
-#define ANOMALY_05000102 (__SILICON_REVISION__ < 2)
-/* Incorrect Value Written to the Cycle Counters */
-#define ANOMALY_05000103 (__SILICON_REVISION__ < 2)
-/* Stores to L1 Data Memory Incorrect when a Specific Sequence Is Followed */
-#define ANOMALY_05000104 (__SILICON_REVISION__ < 2)
-/* Programmable Flag (PF3) functionality not supported in all PPI modes */
-#define ANOMALY_05000106 (__SILICON_REVISION__ < 2)
-/* Data store can be lost when targeting a cache line fill */
-#define ANOMALY_05000107 (__SILICON_REVISION__ < 2)
-/* Reserved Bits in SYSCFG Register Not Set at Power-On */
-#define ANOMALY_05000109 (__SILICON_REVISION__ < 3)
-/* Infinite Core Stall */
-#define ANOMALY_05000114 (__SILICON_REVISION__ < 2)
-/* PPI_FSx may glitch when generated by the on chip Timers. */
-#define ANOMALY_05000115 (__SILICON_REVISION__ < 2)
-/* Trace Buffers May Contain Errors in Emulation Mode and/or Exception, NMI, Reset Handlers */
-#define ANOMALY_05000116 (__SILICON_REVISION__ < 3)
-/* DTEST registers allow access to Data Cache when DTEST_COMMAND< 14 >= 0 */
-#define ANOMALY_05000117 (__SILICON_REVISION__ < 2)
-/* Booting from an 8-bit or 24-bit Addressable SPI device is not supported */
-#define ANOMALY_05000118 (__SILICON_REVISION__ < 2)
-/* DTEST_COMMAND Initiated Memory Access May Be Incorrect If Data Cache or DMA Is Active */
-#define ANOMALY_05000123 (__SILICON_REVISION__ < 3)
-/* DMA Lock-up at CCLK to SCLK ratios of 4:1, 2:1, or 1:1 */
-#define ANOMALY_05000124 (__SILICON_REVISION__ < 3)
-/* Erroneous Exception when Enabling Cache */
-#define ANOMALY_05000125 (__SILICON_REVISION__ < 3)
-/* SPI clock polarity and phase bits incorrect during booting */
-#define ANOMALY_05000126 (__SILICON_REVISION__ < 3)
-/* DMEM_CONTROL<12> Is Not Set on Reset */
-#define ANOMALY_05000137 (__SILICON_REVISION__ < 3)
-/* SPI boot will not complete if there is a zero fill block in the loader file */
-#define ANOMALY_05000138 (__SILICON_REVISION__ == 2)
-/* TIMERx_CONFIG[5] must be set for PPI in GP output mode with internal Frame Syncs */
-#define ANOMALY_05000139 (__SILICON_REVISION__ < 2)
-/* Allowing the SPORT RX FIFO to fill will cause an overflow */
-#define ANOMALY_05000140 (__SILICON_REVISION__ < 3)
-/* Infinite Stall may occur with a particular sequence of consecutive dual dag events */
-#define ANOMALY_05000141 (__SILICON_REVISION__ < 3)
-/* Interrupts may be lost when a programmable input flag is configured to be edge sensitive */
-#define ANOMALY_05000142 (__SILICON_REVISION__ < 3)
-/* A read from external memory may return a wrong value with data cache enabled */
-#define ANOMALY_05000143 (__SILICON_REVISION__ < 3)
-/* DMA and TESTSET conflict when both are accessing external memory */
-#define ANOMALY_05000144 (__SILICON_REVISION__ < 3)
-/* In PWM_OUT mode, you must enable the PPI block to generate a waveform from PPI_CLK */
-#define ANOMALY_05000145 (__SILICON_REVISION__ < 3)
-/* MDMA may lose the first few words of a descriptor chain */
-#define ANOMALY_05000146 (__SILICON_REVISION__ < 3)
-/* Source MDMA descriptor may stop with a DMA Error near beginning of descriptor fetch */
-#define ANOMALY_05000147 (__SILICON_REVISION__ < 3)
-/* When booting from 16-bit asynchronous memory, the upper 8 bits of each word must be 0x00 */
-#define ANOMALY_05000148 (__SILICON_REVISION__ < 3)
-/* Frame Delay in SPORT Multichannel Mode */
-#define ANOMALY_05000153 (__SILICON_REVISION__ < 3)
-/* SPORT TFS signal stays active in multichannel mode outside of valid channels */
-#define ANOMALY_05000154 (__SILICON_REVISION__ < 3)
-/* Timer1 can not be used for PWMOUT mode when a certain PPI mode is in use */
-#define ANOMALY_05000155 (__SILICON_REVISION__ < 3)
-/* Killed 32-Bit MMR Write Leads to Next System MMR Access Thinking It Should Be 32-Bit */
-#define ANOMALY_05000157 (__SILICON_REVISION__ < 3)
-/* SPORT Transmit Data Is Not Gated by External Frame Sync in Certain Conditions */
-#define ANOMALY_05000163 (__SILICON_REVISION__ < 3)
-/* Undefined Behavior when Power-Up Sequence Is Issued to SDRAM during Auto-Refresh */
-#define ANOMALY_05000168 (__SILICON_REVISION__ < 3)
-/* DATA CPLB Page Miss Can Result in Lost Write-Through Data Cache Writes */
-#define ANOMALY_05000169 (__SILICON_REVISION__ < 3)
-/* DMA vs Core accesses to external memory */
-#define ANOMALY_05000173 (__SILICON_REVISION__ < 3)
-/* Cache Fill Buffer Data lost */
-#define ANOMALY_05000174 (__SILICON_REVISION__ < 3)
-/* Overlapping Sequencer and Memory Stalls */
-#define ANOMALY_05000175 (__SILICON_REVISION__ < 3)
-/* Overflow Bit Asserted when Multiplication of -1 by -1 Followed by Accumulator Saturation */
-#define ANOMALY_05000176 (__SILICON_REVISION__ < 3)
-/* Disabling the PPI Resets the PPI Configuration Registers */
-#define ANOMALY_05000181 (__SILICON_REVISION__ < 3)
-/* Early PPI Transmit when FS1 Asserts before FS2 in TX Mode with 2 External Frame Syncs */
-#define ANOMALY_05000185 (__SILICON_REVISION__ < 3)
-/* PPI does not invert the Driving PPICLK edge in Transmit Modes */
-#define ANOMALY_05000191 (__SILICON_REVISION__ < 3)
-/* In PPI Transmit Modes with External Frame Syncs POLC bit must be set to 1 */
-#define ANOMALY_05000192 (__SILICON_REVISION__ < 3)
-/* Internal Voltage Regulator may not start up */
-#define ANOMALY_05000206 (__SILICON_REVISION__ < 3)
-
-/* Anomalies that don't exist on this proc */
-#define ANOMALY_05000120 (0)
-#define ANOMALY_05000149 (0)
-#define ANOMALY_05000171 (0)
-#define ANOMALY_05000182 (0)
-#define ANOMALY_05000220 (0)
-#define ANOMALY_05000248 (0)
-#define ANOMALY_05000266 (0)
-#define ANOMALY_05000274 (0)
-#define ANOMALY_05000287 (0)
-#define ANOMALY_05000323 (0)
-#define ANOMALY_05000353 (1)
-#define ANOMALY_05000362 (1)
-#define ANOMALY_05000364 (0)
-#define ANOMALY_05000380 (0)
-#define ANOMALY_05000383 (0)
-#define ANOMALY_05000386 (1)
-#define ANOMALY_05000389 (0)
-#define ANOMALY_05000412 (0)
-#define ANOMALY_05000430 (0)
-#define ANOMALY_05000432 (0)
-#define ANOMALY_05000435 (0)
-#define ANOMALY_05000440 (0)
-#define ANOMALY_05000447 (0)
-#define ANOMALY_05000448 (0)
-#define ANOMALY_05000456 (0)
-#define ANOMALY_05000450 (0)
-#define ANOMALY_05000465 (0)
-#define ANOMALY_05000467 (0)
-#define ANOMALY_05000474 (0)
-#define ANOMALY_05000480 (0)
-#define ANOMALY_05000485 (0)
-
-#endif

+ 0 - 5
arch/blackfin/include/asm/mach-bf533/def_local.h

@@ -1,5 +0,0 @@
-#include "gpio.h"
-#include "portmux.h"
-#include "ports.h"
-
-#define BF533_FAMILY 1	/* Linux glue */

+ 0 - 31
arch/blackfin/include/asm/mach-bf533/gpio.h

@@ -1,31 +0,0 @@
-/*
- * Copyright (C) 2008 Analog Devices Inc.
- * Licensed under the GPL-2 or later.
- */
-
-
-#ifndef _MACH_GPIO_H_
-#define _MACH_GPIO_H_
-
-#define MAX_BLACKFIN_GPIOS 16
-
-#define GPIO_PF0	0
-#define GPIO_PF1	1
-#define GPIO_PF2	2
-#define GPIO_PF3	3
-#define GPIO_PF4	4
-#define GPIO_PF5	5
-#define GPIO_PF6	6
-#define GPIO_PF7	7
-#define GPIO_PF8	8
-#define GPIO_PF9	9
-#define GPIO_PF10	10
-#define GPIO_PF11	11
-#define GPIO_PF12	12
-#define GPIO_PF13	13
-#define GPIO_PF14	14
-#define GPIO_PF15	15
-
-#define PORT_F GPIO_PF0
-
-#endif /* _MACH_GPIO_H_ */

+ 0 - 71
arch/blackfin/include/asm/mach-bf533/portmux.h

@@ -1,71 +0,0 @@
-/*
- * Copyright 2007-2009 Analog Devices Inc.
- *
- * Licensed under the GPL-2 or later
- */
-
-#ifndef _MACH_PORTMUX_H_
-#define _MACH_PORTMUX_H_
-
-#define MAX_RESOURCES	MAX_BLACKFIN_GPIOS
-
-#define P_PPI0_CLK	(P_DONTCARE)
-#define P_PPI0_FS1	(P_DONTCARE)
-#define P_PPI0_FS2	(P_DONTCARE)
-#define P_PPI0_FS3	(P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_PPI0_D15	(P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_PPI0_D14	(P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_PPI0_D13	(P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_PPI0_D12	(P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_PPI0_D11	(P_DEFINED | P_IDENT(GPIO_PF8))
-#define P_PPI0_D10	(P_DEFINED | P_IDENT(GPIO_PF9))
-#define P_PPI0_D9	(P_DEFINED | P_IDENT(GPIO_PF10))
-#define P_PPI0_D8	(P_DEFINED | P_IDENT(GPIO_PF11))
-#define P_PPI0_D0	(P_DONTCARE)
-#define P_PPI0_D1	(P_DONTCARE)
-#define P_PPI0_D2	(P_DONTCARE)
-#define P_PPI0_D3	(P_DONTCARE)
-#define P_PPI0_D4	(P_DEFINED | P_IDENT(GPIO_PF15))
-#define P_PPI0_D5	(P_DEFINED | P_IDENT(GPIO_PF14))
-#define P_PPI0_D6	(P_DEFINED | P_IDENT(GPIO_PF13))
-#define P_PPI0_D7	(P_DEFINED | P_IDENT(GPIO_PF12))
-
-#define P_SPORT1_TSCLK	(P_DONTCARE)
-#define P_SPORT1_RSCLK	(P_DONTCARE)
-#define P_SPORT0_TSCLK	(P_DONTCARE)
-#define P_SPORT0_RSCLK	(P_DONTCARE)
-#define P_UART0_RX	(P_DONTCARE)
-#define P_UART0_TX	(P_DONTCARE)
-#define P_SPORT1_DRSEC	(P_DONTCARE)
-#define P_SPORT1_RFS	(P_DONTCARE)
-#define P_SPORT1_DTPRI	(P_DONTCARE)
-#define P_SPORT1_DTSEC	(P_DONTCARE)
-#define P_SPORT1_TFS	(P_DONTCARE)
-#define P_SPORT1_DRPRI	(P_DONTCARE)
-#define P_SPORT0_DRSEC	(P_DONTCARE)
-#define P_SPORT0_RFS	(P_DONTCARE)
-#define P_SPORT0_DTPRI	(P_DONTCARE)
-#define P_SPORT0_DTSEC	(P_DONTCARE)
-#define P_SPORT0_TFS	(P_DONTCARE)
-#define P_SPORT0_DRPRI	(P_DONTCARE)
-
-#define P_SPI0_MOSI	(P_DONTCARE)
-#define P_SPI0_MISO	(P_DONTCARE)
-#define P_SPI0_SCK	(P_DONTCARE)
-#define P_SPI0_SSEL7	(P_DEFINED | P_IDENT(GPIO_PF7))
-#define P_SPI0_SSEL6	(P_DEFINED | P_IDENT(GPIO_PF6))
-#define P_SPI0_SSEL5	(P_DEFINED | P_IDENT(GPIO_PF5))
-#define P_SPI0_SSEL4	(P_DEFINED | P_IDENT(GPIO_PF4))
-#define P_SPI0_SSEL3	(P_DEFINED | P_IDENT(GPIO_PF3))
-#define P_SPI0_SSEL2	(P_DEFINED | P_IDENT(GPIO_PF2))
-#define P_SPI0_SSEL1	(P_DEFINED | P_IDENT(GPIO_PF1))
-#define P_SPI0_SS	(P_DEFINED | P_IDENT(GPIO_PF0))
-#define GPIO_DEFAULT_BOOT_SPI_CS GPIO_PF2
-#define P_DEFAULT_BOOT_SPI_CS P_SPI0_SSEL2
-
-#define P_TMR2		(P_DONTCARE)
-#define P_TMR1		(P_DONTCARE)
-#define P_TMR0		(P_DONTCARE)
-#define P_TMRCLK	(P_DEFINED | P_IDENT(GPIO_PF1))
-
-#endif /* _MACH_PORTMUX_H_ */

+ 0 - 10
arch/blackfin/include/asm/mach-bf533/ports.h

@@ -1,10 +0,0 @@
-/*
- * Port Masks
- */
-
-#ifndef __BFIN_PERIPHERAL_PORT__
-#define __BFIN_PERIPHERAL_PORT__
-
-#include "../mach-common/bits/ports-f.h"
-
-#endif

+ 0 - 1624
arch/blackfin/include/asm/mach-bf537/BF534_cdef.h

@@ -1,1624 +0,0 @@
-/* DO NOT EDIT THIS FILE
- * Automatically generated by generate-cdef-headers.xsl
- * DO NOT EDIT THIS FILE
- */
-
-#ifndef __BFIN_CDEF_ADSP_BF534_proc__
-#define __BFIN_CDEF_ADSP_BF534_proc__
-
-#include "../mach-common/ADSP-EDN-core_cdef.h"
-
-#define bfin_read_PLL_CTL()            bfin_read16(PLL_CTL)
-#define bfin_write_PLL_CTL(val)        bfin_write16(PLL_CTL, val)
-#define bfin_read_PLL_DIV()            bfin_read16(PLL_DIV)
-#define bfin_write_PLL_DIV(val)        bfin_write16(PLL_DIV, val)
-#define bfin_read_VR_CTL()             bfin_read16(VR_CTL)
-#define bfin_write_VR_CTL(val)         bfin_write16(VR_CTL, val)
-#define bfin_read_PLL_STAT()           bfin_read16(PLL_STAT)
-#define bfin_write_PLL_STAT(val)       bfin_write16(PLL_STAT, val)
-#define bfin_read_PLL_LOCKCNT()        bfin_read16(PLL_LOCKCNT)
-#define bfin_write_PLL_LOCKCNT(val)    bfin_write16(PLL_LOCKCNT, val)
-#define bfin_read_SWRST()              bfin_read16(SWRST)
-#define bfin_write_SWRST(val)          bfin_write16(SWRST, val)
-#define bfin_read_SYSCR()              bfin_read16(SYSCR)
-#define bfin_write_SYSCR(val)          bfin_write16(SYSCR, val)
-#define bfin_read_SIC_RVECT()          bfin_read16(SIC_RVECT)
-#define bfin_write_SIC_RVECT(val)      bfin_write16(SIC_RVECT, val)
-#define bfin_read_SIC_IMASK()          bfin_read32(SIC_IMASK)
-#define bfin_write_SIC_IMASK(val)      bfin_write32(SIC_IMASK, val)
-#define bfin_read_SIC_IAR0()           bfin_read32(SIC_IAR0)
-#define bfin_write_SIC_IAR0(val)       bfin_write32(SIC_IAR0, val)
-#define bfin_read_SIC_IAR1()           bfin_read32(SIC_IAR1)
-#define bfin_write_SIC_IAR1(val)       bfin_write32(SIC_IAR1, val)
-#define bfin_read_SIC_IAR2()           bfin_read32(SIC_IAR2)
-#define bfin_write_SIC_IAR2(val)       bfin_write32(SIC_IAR2, val)
-#define bfin_read_SIC_IAR3()           bfin_read32(SIC_IAR3)
-#define bfin_write_SIC_IAR3(val)       bfin_write32(SIC_IAR3, val)
-#define bfin_read_SIC_ISR()            bfin_read32(SIC_ISR)
-#define bfin_write_SIC_ISR(val)        bfin_write32(SIC_ISR, val)
-#define bfin_read_SIC_IWR()            bfin_read32(SIC_IWR)
-#define bfin_write_SIC_IWR(val)        bfin_write32(SIC_IWR, val)
-#define bfin_read_WDOG_CTL()           bfin_read16(WDOG_CTL)
-#define bfin_write_WDOG_CTL(val)       bfin_write16(WDOG_CTL, val)
-#define bfin_read_WDOG_CNT()           bfin_read32(WDOG_CNT)
-#define bfin_write_WDOG_CNT(val)       bfin_write32(WDOG_CNT, val)
-#define bfin_read_WDOG_STAT()          bfin_read32(WDOG_STAT)
-#define bfin_write_WDOG_STAT(val)      bfin_write32(WDOG_STAT, val)
-#define bfin_read_RTC_STAT()           bfin_read32(RTC_STAT)
-#define bfin_write_RTC_STAT(val)       bfin_write32(RTC_STAT, val)
-#define bfin_read_RTC_ICTL()           bfin_read16(RTC_ICTL)
-#define bfin_write_RTC_ICTL(val)       bfin_write16(RTC_ICTL, val)
-#define bfin_read_RTC_ISTAT()          bfin_read16(RTC_ISTAT)
-#define bfin_write_RTC_ISTAT(val)      bfin_write16(RTC_ISTAT, val)
-#define bfin_read_RTC_SWCNT()          bfin_read16(RTC_SWCNT)
-#define bfin_write_RTC_SWCNT(val)      bfin_write16(RTC_SWCNT, val)
-#define bfin_read_RTC_ALARM()          bfin_read32(RTC_ALARM)
-#define bfin_write_RTC_ALARM(val)      bfin_write32(RTC_ALARM, val)
-#define bfin_read_RTC_PREN()           bfin_read16(RTC_PREN)
-#define bfin_write_RTC_PREN(val)       bfin_write16(RTC_PREN, val)
-#define bfin_read_UART0_THR()          bfin_read16(UART0_THR)
-#define bfin_write_UART0_THR(val)      bfin_write16(UART0_THR, val)
-#define bfin_read_UART0_RBR()          bfin_read16(UART0_RBR)
-#define bfin_write_UART0_RBR(val)      bfin_write16(UART0_RBR, val)
-#define bfin_read_UART0_DLL()          bfin_read16(UART0_DLL)
-#define bfin_write_UART0_DLL(val)      bfin_write16(UART0_DLL, val)
-#define bfin_read_UART0_IER()          bfin_read16(UART0_IER)
-#define bfin_write_UART0_IER(val)      bfin_write16(UART0_IER, val)
-#define bfin_read_UART0_DLH()          bfin_read16(UART0_DLH)
-#define bfin_write_UART0_DLH(val)      bfin_write16(UART0_DLH, val)
-#define bfin_read_UART0_IIR()          bfin_read16(UART0_IIR)
-#define bfin_write_UART0_IIR(val)      bfin_write16(UART0_IIR, val)
-#define bfin_read_UART0_LCR()          bfin_read16(UART0_LCR)
-#define bfin_write_UART0_LCR(val)      bfin_write16(UART0_LCR, val)
-#define bfin_read_UART0_MCR()          bfin_read16(UART0_MCR)
-#define bfin_write_UART0_MCR(val)      bfin_write16(UART0_MCR, val)
-#define bfin_read_UART0_LSR()          bfin_read16(UART0_LSR)
-#define bfin_write_UART0_LSR(val)      bfin_write16(UART0_LSR, val)
-#define bfin_read_UART0_MSR()          bfin_read16(UART0_MSR)
-#define bfin_write_UART0_MSR(val)      bfin_write16(UART0_MSR, val)
-#define bfin_read_UART0_SCR()          bfin_read16(UART0_SCR)
-#define bfin_write_UART0_SCR(val)      bfin_write16(UART0_SCR, val)
-#define bfin_read_UART0_GCTL()         bfin_read16(UART0_GCTL)
-#define bfin_write_UART0_GCTL(val)     bfin_write16(UART0_GCTL, val)
-#define bfin_read_SPI_CTL()            bfin_read16(SPI_CTL)
-#define bfin_write_SPI_CTL(val)        bfin_write16(SPI_CTL, val)
-#define bfin_read_SPI_FLG()            bfin_read16(SPI_FLG)
-#define bfin_write_SPI_FLG(val)        bfin_write16(SPI_FLG, val)
-#define bfin_read_SPI_STAT()           bfin_read16(SPI_STAT)
-#define bfin_write_SPI_STAT(val)       bfin_write16(SPI_STAT, val)
-#define bfin_read_SPI_TDBR()           bfin_read16(SPI_TDBR)
-#define bfin_write_SPI_TDBR(val)       bfin_write16(SPI_TDBR, val)
-#define bfin_read_SPI_RDBR()           bfin_read16(SPI_RDBR)
-#define bfin_write_SPI_RDBR(val)       bfin_write16(SPI_RDBR, val)
-#define bfin_read_SPI_BAUD()           bfin_read16(SPI_BAUD)
-#define bfin_write_SPI_BAUD(val)       bfin_write16(SPI_BAUD, val)
-#define bfin_read_SPI_SHADOW()         bfin_read16(SPI_SHADOW)
-#define bfin_write_SPI_SHADOW(val)     bfin_write16(SPI_SHADOW, val)
-#define bfin_read_TIMER0_CONFIG()      bfin_read16(TIMER0_CONFIG)
-#define bfin_write_TIMER0_CONFIG(val)  bfin_write16(TIMER0_CONFIG, val)
-#define bfin_read_TIMER0_COUNTER()     bfin_read32(TIMER0_COUNTER)
-#define bfin_write_TIMER0_COUNTER(val) bfin_write32(TIMER0_COUNTER, val)
-#define bfin_read_TIMER0_PERIOD()      bfin_read32(TIMER0_PERIOD)
-#define bfin_write_TIMER0_PERIOD(val)  bfin_write32(TIMER0_PERIOD, val)
-#define bfin_read_TIMER0_WIDTH()       bfin_read32(TIMER0_WIDTH)
-#define bfin_write_TIMER0_WIDTH(val)   bfin_write32(TIMER0_WIDTH, val)
-#define bfin_read_TIMER1_CONFIG()      bfin_read16(TIMER1_CONFIG)
-#define bfin_write_TIMER1_CONFIG(val)  bfin_write16(TIMER1_CONFIG, val)
-#define bfin_read_TIMER1_COUNTER()     bfin_read32(TIMER1_COUNTER)
-#define bfin_write_TIMER1_COUNTER(val) bfin_write32(TIMER1_COUNTER, val)
-#define bfin_read_TIMER1_PERIOD()      bfin_read32(TIMER1_PERIOD)
-#define bfin_write_TIMER1_PERIOD(val)  bfin_write32(TIMER1_PERIOD, val)
-#define bfin_read_TIMER1_WIDTH()       bfin_read32(TIMER1_WIDTH)
-#define bfin_write_TIMER1_WIDTH(val)   bfin_write32(TIMER1_WIDTH, val)
-#define bfin_read_TIMER2_CONFIG()      bfin_read16(TIMER2_CONFIG)
-#define bfin_write_TIMER2_CONFIG(val)  bfin_write16(TIMER2_CONFIG, val)
-#define bfin_read_TIMER2_COUNTER()     bfin_read32(TIMER2_COUNTER)
-#define bfin_write_TIMER2_COUNTER(val) bfin_write32(TIMER2_COUNTER, val)
-#define bfin_read_TIMER2_PERIOD()      bfin_read32(TIMER2_PERIOD)
-#define bfin_write_TIMER2_PERIOD(val)  bfin_write32(TIMER2_PERIOD, val)
-#define bfin_read_TIMER2_WIDTH()       bfin_read32(TIMER2_WIDTH)
-#define bfin_write_TIMER2_WIDTH(val)   bfin_write32(TIMER2_WIDTH, val)
-#define bfin_read_TIMER3_CONFIG()      bfin_read16(TIMER3_CONFIG)
-#define bfin_write_TIMER3_CONFIG(val)  bfin_write16(TIMER3_CONFIG, val)
-#define bfin_read_TIMER3_COUNTER()     bfin_read32(TIMER3_COUNTER)
-#define bfin_write_TIMER3_COUNTER(val) bfin_write32(TIMER3_COUNTER, val)
-#define bfin_read_TIMER3_PERIOD()      bfin_read32(TIMER3_PERIOD)
-#define bfin_write_TIMER3_PERIOD(val)  bfin_write32(TIMER3_PERIOD, val)
-#define bfin_read_TIMER3_WIDTH()       bfin_read32(TIMER3_WIDTH)
-#define bfin_write_TIMER3_WIDTH(val)   bfin_write32(TIMER3_WIDTH, val)
-#define bfin_read_TIMER4_CONFIG()      bfin_read16(TIMER4_CONFIG)
-#define bfin_write_TIMER4_CONFIG(val)  bfin_write16(TIMER4_CONFIG, val)
-#define bfin_read_TIMER4_COUNTER()     bfin_read32(TIMER4_COUNTER)
-#define bfin_write_TIMER4_COUNTER(val) bfin_write32(TIMER4_COUNTER, val)
-#define bfin_read_TIMER4_PERIOD()      bfin_read32(TIMER4_PERIOD)
-#define bfin_write_TIMER4_PERIOD(val)  bfin_write32(TIMER4_PERIOD, val)
-#define bfin_read_TIMER4_WIDTH()       bfin_read32(TIMER4_WIDTH)
-#define bfin_write_TIMER4_WIDTH(val)   bfin_write32(TIMER4_WIDTH, val)
-#define bfin_read_TIMER5_CONFIG()      bfin_read16(TIMER5_CONFIG)
-#define bfin_write_TIMER5_CONFIG(val)  bfin_write16(TIMER5_CONFIG, val)
-#define bfin_read_TIMER5_COUNTER()     bfin_read32(TIMER5_COUNTER)
-#define bfin_write_TIMER5_COUNTER(val) bfin_write32(TIMER5_COUNTER, val)
-#define bfin_read_TIMER5_PERIOD()      bfin_read32(TIMER5_PERIOD)
-#define bfin_write_TIMER5_PERIOD(val)  bfin_write32(TIMER5_PERIOD, val)
-#define bfin_read_TIMER5_WIDTH()       bfin_read32(TIMER5_WIDTH)
-#define bfin_write_TIMER5_WIDTH(val)   bfin_write32(TIMER5_WIDTH, val)
-#define bfin_read_TIMER6_CONFIG()      bfin_read16(TIMER6_CONFIG)
-#define bfin_write_TIMER6_CONFIG(val)  bfin_write16(TIMER6_CONFIG, val)
-#define bfin_read_TIMER6_COUNTER()     bfin_read32(TIMER6_COUNTER)
-#define bfin_write_TIMER6_COUNTER(val) bfin_write32(TIMER6_COUNTER, val)
-#define bfin_read_TIMER6_PERIOD()      bfin_read32(TIMER6_PERIOD)
-#define bfin_write_TIMER6_PERIOD(val)  bfin_write32(TIMER6_PERIOD, val)
-#define bfin_read_TIMER6_WIDTH()       bfin_read32(TIMER6_WIDTH)
-#define bfin_write_TIMER6_WIDTH(val)   bfin_write32(TIMER6_WIDTH, val)
-#define bfin_read_TIMER7_CONFIG()      bfin_read16(TIMER7_CONFIG)
-#define bfin_write_TIMER7_CONFIG(val)  bfin_write16(TIMER7_CONFIG, val)
-#define bfin_read_TIMER7_COUNTER()     bfin_read32(TIMER7_COUNTER)
-#define bfin_write_TIMER7_COUNTER(val) bfin_write32(TIMER7_COUNTER, val)
-#define bfin_read_TIMER7_PERIOD()      bfin_read32(TIMER7_PERIOD)
-#define bfin_write_TIMER7_PERIOD(val)  bfin_write32(TIMER7_PERIOD, val)
-#define bfin_read_TIMER7_WIDTH()       bfin_read32(TIMER7_WIDTH)
-#define bfin_write_TIMER7_WIDTH(val)   bfin_write32(TIMER7_WIDTH, val)
-#define bfin_read_TIMER_ENABLE()       bfin_read16(TIMER_ENABLE)
-#define bfin_write_TIMER_ENABLE(val)   bfin_write16(TIMER_ENABLE, val)
-#define bfin_read_TIMER_DISABLE()      bfin_read16(TIMER_DISABLE)
-#define bfin_write_TIMER_DISABLE(val)  bfin_write16(TIMER_DISABLE, val)
-#define bfin_read_TIMER_STATUS()       bfin_read32(TIMER_STATUS)
-#define bfin_write_TIMER_STATUS(val)   bfin_write32(TIMER_STATUS, val)
-#define bfin_read_PORTFIO()            bfin_read16(PORTFIO)
-#define bfin_write_PORTFIO(val)        bfin_write16(PORTFIO, val)
-#define bfin_read_PORTFIO_CLEAR()      bfin_read16(PORTFIO_CLEAR)
-#define bfin_write_PORTFIO_CLEAR(val)  bfin_write16(PORTFIO_CLEAR, val)
-#define bfin_read_PORTFIO_SET()        bfin_read16(PORTFIO_SET)
-#define bfin_write_PORTFIO_SET(val)    bfin_write16(PORTFIO_SET, val)
-#define bfin_read_PORTFIO_TOGGLE()     bfin_read16(PORTFIO_TOGGLE)
-#define bfin_write_PORTFIO_TOGGLE(val) bfin_write16(PORTFIO_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKA()      bfin_read16(PORTFIO_MASKA)
-#define bfin_write_PORTFIO_MASKA(val)  bfin_write16(PORTFIO_MASKA, val)
-#define bfin_read_PORTFIO_MASKA_CLEAR() bfin_read16(PORTFIO_MASKA_CLEAR)
-#define bfin_write_PORTFIO_MASKA_CLEAR(val) bfin_write16(PORTFIO_MASKA_CLEAR, val)
-#define bfin_read_PORTFIO_MASKA_SET()  bfin_read16(PORTFIO_MASKA_SET)
-#define bfin_write_PORTFIO_MASKA_SET(val) bfin_write16(PORTFIO_MASKA_SET, val)
-#define bfin_read_PORTFIO_MASKA_TOGGLE() bfin_read16(PORTFIO_MASKA_TOGGLE)
-#define bfin_write_PORTFIO_MASKA_TOGGLE(val) bfin_write16(PORTFIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTFIO_MASKB()      bfin_read16(PORTFIO_MASKB)
-#define bfin_write_PORTFIO_MASKB(val)  bfin_write16(PORTFIO_MASKB, val)
-#define bfin_read_PORTFIO_MASKB_CLEAR() bfin_read16(PORTFIO_MASKB_CLEAR)
-#define bfin_write_PORTFIO_MASKB_CLEAR(val) bfin_write16(PORTFIO_MASKB_CLEAR, val)
-#define bfin_read_PORTFIO_MASKB_SET()  bfin_read16(PORTFIO_MASKB_SET)
-#define bfin_write_PORTFIO_MASKB_SET(val) bfin_write16(PORTFIO_MASKB_SET, val)
-#define bfin_read_PORTFIO_MASKB_TOGGLE() bfin_read16(PORTFIO_MASKB_TOGGLE)
-#define bfin_write_PORTFIO_MASKB_TOGGLE(val) bfin_write16(PORTFIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTFIO_DIR()        bfin_read16(PORTFIO_DIR)
-#define bfin_write_PORTFIO_DIR(val)    bfin_write16(PORTFIO_DIR, val)
-#define bfin_read_PORTFIO_POLAR()      bfin_read16(PORTFIO_POLAR)
-#define bfin_write_PORTFIO_POLAR(val)  bfin_write16(PORTFIO_POLAR, val)
-#define bfin_read_PORTFIO_EDGE()       bfin_read16(PORTFIO_EDGE)
-#define bfin_write_PORTFIO_EDGE(val)   bfin_write16(PORTFIO_EDGE, val)
-#define bfin_read_PORTFIO_BOTH()       bfin_read16(PORTFIO_BOTH)
-#define bfin_write_PORTFIO_BOTH(val)   bfin_write16(PORTFIO_BOTH, val)
-#define bfin_read_PORTFIO_INEN()       bfin_read16(PORTFIO_INEN)
-#define bfin_write_PORTFIO_INEN(val)   bfin_write16(PORTFIO_INEN, val)
-#define bfin_read_SPORT0_TCR1()        bfin_read16(SPORT0_TCR1)
-#define bfin_write_SPORT0_TCR1(val)    bfin_write16(SPORT0_TCR1, val)
-#define bfin_read_SPORT0_TCR2()        bfin_read16(SPORT0_TCR2)
-#define bfin_write_SPORT0_TCR2(val)    bfin_write16(SPORT0_TCR2, val)
-#define bfin_read_SPORT0_TCLKDIV()     bfin_read16(SPORT0_TCLKDIV)
-#define bfin_write_SPORT0_TCLKDIV(val) bfin_write16(SPORT0_TCLKDIV, val)
-#define bfin_read_SPORT0_TFSDIV()      bfin_read16(SPORT0_TFSDIV)
-#define bfin_write_SPORT0_TFSDIV(val)  bfin_write16(SPORT0_TFSDIV, val)
-#define bfin_write_SPORT0_TX(val)      bfin_write32(SPORT0_TX, val)
-#define bfin_read_SPORT0_RX()          bfin_read32(SPORT0_RX)
-#define bfin_write_SPORT0_RX(val)      bfin_write32(SPORT0_RX, val)
-#define bfin_read_SPORT0_RCR1()        bfin_read16(SPORT0_RCR1)
-#define bfin_write_SPORT0_RCR1(val)    bfin_write16(SPORT0_RCR1, val)
-#define bfin_read_SPORT0_RCR2()        bfin_read16(SPORT0_RCR2)
-#define bfin_write_SPORT0_RCR2(val)    bfin_write16(SPORT0_RCR2, val)
-#define bfin_read_SPORT0_RCLKDIV()     bfin_read16(SPORT0_RCLKDIV)
-#define bfin_write_SPORT0_RCLKDIV(val) bfin_write16(SPORT0_RCLKDIV, val)
-#define bfin_read_SPORT0_RFSDIV()      bfin_read16(SPORT0_RFSDIV)
-#define bfin_write_SPORT0_RFSDIV(val)  bfin_write16(SPORT0_RFSDIV, val)
-#define bfin_read_SPORT0_STAT()        bfin_read16(SPORT0_STAT)
-#define bfin_write_SPORT0_STAT(val)    bfin_write16(SPORT0_STAT, val)
-#define bfin_read_SPORT0_CHNL()        bfin_read16(SPORT0_CHNL)
-#define bfin_write_SPORT0_CHNL(val)    bfin_write16(SPORT0_CHNL, val)
-#define bfin_read_SPORT0_MCMC1()       bfin_read16(SPORT0_MCMC1)
-#define bfin_write_SPORT0_MCMC1(val)   bfin_write16(SPORT0_MCMC1, val)
-#define bfin_read_SPORT0_MCMC2()       bfin_read16(SPORT0_MCMC2)
-#define bfin_write_SPORT0_MCMC2(val)   bfin_write16(SPORT0_MCMC2, val)
-#define bfin_read_SPORT0_MTCS0()       bfin_read32(SPORT0_MTCS0)
-#define bfin_write_SPORT0_MTCS0(val)   bfin_write32(SPORT0_MTCS0, val)
-#define bfin_read_SPORT0_MTCS1()       bfin_read32(SPORT0_MTCS1)
-#define bfin_write_SPORT0_MTCS1(val)   bfin_write32(SPORT0_MTCS1, val)
-#define bfin_read_SPORT0_MTCS2()       bfin_read32(SPORT0_MTCS2)
-#define bfin_write_SPORT0_MTCS2(val)   bfin_write32(SPORT0_MTCS2, val)
-#define bfin_read_SPORT0_MTCS3()       bfin_read32(SPORT0_MTCS3)
-#define bfin_write_SPORT0_MTCS3(val)   bfin_write32(SPORT0_MTCS3, val)
-#define bfin_read_SPORT0_MRCS0()       bfin_read32(SPORT0_MRCS0)
-#define bfin_write_SPORT0_MRCS0(val)   bfin_write32(SPORT0_MRCS0, val)
-#define bfin_read_SPORT0_MRCS1()       bfin_read32(SPORT0_MRCS1)
-#define bfin_write_SPORT0_MRCS1(val)   bfin_write32(SPORT0_MRCS1, val)
-#define bfin_read_SPORT0_MRCS2()       bfin_read32(SPORT0_MRCS2)
-#define bfin_write_SPORT0_MRCS2(val)   bfin_write32(SPORT0_MRCS2, val)
-#define bfin_read_SPORT0_MRCS3()       bfin_read32(SPORT0_MRCS3)
-#define bfin_write_SPORT0_MRCS3(val)   bfin_write32(SPORT0_MRCS3, val)
-#define bfin_read_SPORT1_TCR1()        bfin_read16(SPORT1_TCR1)
-#define bfin_write_SPORT1_TCR1(val)    bfin_write16(SPORT1_TCR1, val)
-#define bfin_read_SPORT1_TCR2()        bfin_read16(SPORT1_TCR2)
-#define bfin_write_SPORT1_TCR2(val)    bfin_write16(SPORT1_TCR2, val)
-#define bfin_read_SPORT1_TCLKDIV()     bfin_read16(SPORT1_TCLKDIV)
-#define bfin_write_SPORT1_TCLKDIV(val) bfin_write16(SPORT1_TCLKDIV, val)
-#define bfin_read_SPORT1_TFSDIV()      bfin_read16(SPORT1_TFSDIV)
-#define bfin_write_SPORT1_TFSDIV(val)  bfin_write16(SPORT1_TFSDIV, val)
-#define bfin_write_SPORT1_TX(val)      bfin_write32(SPORT1_TX, val)
-#define bfin_read_SPORT1_RX()          bfin_read32(SPORT1_RX)
-#define bfin_write_SPORT1_RX(val)      bfin_write32(SPORT1_RX, val)
-#define bfin_read_SPORT1_RCR1()        bfin_read16(SPORT1_RCR1)
-#define bfin_write_SPORT1_RCR1(val)    bfin_write16(SPORT1_RCR1, val)
-#define bfin_read_SPORT1_RCR2()        bfin_read16(SPORT1_RCR2)
-#define bfin_write_SPORT1_RCR2(val)    bfin_write16(SPORT1_RCR2, val)
-#define bfin_read_SPORT1_RCLKDIV()     bfin_read16(SPORT1_RCLKDIV)
-#define bfin_write_SPORT1_RCLKDIV(val) bfin_write16(SPORT1_RCLKDIV, val)
-#define bfin_read_SPORT1_RFSDIV()      bfin_read16(SPORT1_RFSDIV)
-#define bfin_write_SPORT1_RFSDIV(val)  bfin_write16(SPORT1_RFSDIV, val)
-#define bfin_read_SPORT1_STAT()        bfin_read16(SPORT1_STAT)
-#define bfin_write_SPORT1_STAT(val)    bfin_write16(SPORT1_STAT, val)
-#define bfin_read_SPORT1_CHNL()        bfin_read16(SPORT1_CHNL)
-#define bfin_write_SPORT1_CHNL(val)    bfin_write16(SPORT1_CHNL, val)
-#define bfin_read_SPORT1_MCMC1()       bfin_read16(SPORT1_MCMC1)
-#define bfin_write_SPORT1_MCMC1(val)   bfin_write16(SPORT1_MCMC1, val)
-#define bfin_read_SPORT1_MCMC2()       bfin_read16(SPORT1_MCMC2)
-#define bfin_write_SPORT1_MCMC2(val)   bfin_write16(SPORT1_MCMC2, val)
-#define bfin_read_SPORT1_MTCS0()       bfin_read32(SPORT1_MTCS0)
-#define bfin_write_SPORT1_MTCS0(val)   bfin_write32(SPORT1_MTCS0, val)
-#define bfin_read_SPORT1_MTCS1()       bfin_read32(SPORT1_MTCS1)
-#define bfin_write_SPORT1_MTCS1(val)   bfin_write32(SPORT1_MTCS1, val)
-#define bfin_read_SPORT1_MTCS2()       bfin_read32(SPORT1_MTCS2)
-#define bfin_write_SPORT1_MTCS2(val)   bfin_write32(SPORT1_MTCS2, val)
-#define bfin_read_SPORT1_MTCS3()       bfin_read32(SPORT1_MTCS3)
-#define bfin_write_SPORT1_MTCS3(val)   bfin_write32(SPORT1_MTCS3, val)
-#define bfin_read_SPORT1_MRCS0()       bfin_read32(SPORT1_MRCS0)
-#define bfin_write_SPORT1_MRCS0(val)   bfin_write32(SPORT1_MRCS0, val)
-#define bfin_read_SPORT1_MRCS1()       bfin_read32(SPORT1_MRCS1)
-#define bfin_write_SPORT1_MRCS1(val)   bfin_write32(SPORT1_MRCS1, val)
-#define bfin_read_SPORT1_MRCS2()       bfin_read32(SPORT1_MRCS2)
-#define bfin_write_SPORT1_MRCS2(val)   bfin_write32(SPORT1_MRCS2, val)
-#define bfin_read_SPORT1_MRCS3()       bfin_read32(SPORT1_MRCS3)
-#define bfin_write_SPORT1_MRCS3(val)   bfin_write32(SPORT1_MRCS3, val)
-#define bfin_read_EBIU_AMGCTL()        bfin_read16(EBIU_AMGCTL)
-#define bfin_write_EBIU_AMGCTL(val)    bfin_write16(EBIU_AMGCTL, val)
-#define bfin_read_EBIU_AMBCTL0()       bfin_read32(EBIU_AMBCTL0)
-#define bfin_write_EBIU_AMBCTL0(val)   bfin_write32(EBIU_AMBCTL0, val)
-#define bfin_read_EBIU_AMBCTL1()       bfin_read32(EBIU_AMBCTL1)
-#define bfin_write_EBIU_AMBCTL1(val)   bfin_write32(EBIU_AMBCTL1, val)
-#define bfin_read_EBIU_SDGCTL()        bfin_read32(EBIU_SDGCTL)
-#define bfin_write_EBIU_SDGCTL(val)    bfin_write32(EBIU_SDGCTL, val)
-#define bfin_read_EBIU_SDBCTL()        bfin_read16(EBIU_SDBCTL)
-#define bfin_write_EBIU_SDBCTL(val)    bfin_write16(EBIU_SDBCTL, val)
-#define bfin_read_EBIU_SDRRC()         bfin_read16(EBIU_SDRRC)
-#define bfin_write_EBIU_SDRRC(val)     bfin_write16(EBIU_SDRRC, val)
-#define bfin_read_EBIU_SDSTAT()        bfin_read16(EBIU_SDSTAT)
-#define bfin_write_EBIU_SDSTAT(val)    bfin_write16(EBIU_SDSTAT, val)
-#define bfin_read_DMA0_NEXT_DESC_PTR() bfin_readPTR(DMA0_NEXT_DESC_PTR)
-#define bfin_write_DMA0_NEXT_DESC_PTR(val) bfin_writePTR(DMA0_NEXT_DESC_PTR, val)
-#define bfin_read_DMA0_START_ADDR()    bfin_readPTR(DMA0_START_ADDR)
-#define bfin_write_DMA0_START_ADDR(val) bfin_writePTR(DMA0_START_ADDR, val)
-#define bfin_read_DMA0_CONFIG()        bfin_read16(DMA0_CONFIG)
-#define bfin_write_DMA0_CONFIG(val)    bfin_write16(DMA0_CONFIG, val)
-#define bfin_read_DMA0_X_COUNT()       bfin_read16(DMA0_X_COUNT)
-#define bfin_write_DMA0_X_COUNT(val)   bfin_write16(DMA0_X_COUNT, val)
-#define bfin_read_DMA0_X_MODIFY()      bfin_read16(DMA0_X_MODIFY)
-#define bfin_write_DMA0_X_MODIFY(val)  bfin_write16(DMA0_X_MODIFY, val)
-#define bfin_read_DMA0_Y_COUNT()       bfin_read16(DMA0_Y_COUNT)
-#define bfin_write_DMA0_Y_COUNT(val)   bfin_write16(DMA0_Y_COUNT, val)
-#define bfin_read_DMA0_Y_MODIFY()      bfin_read16(DMA0_Y_MODIFY)
-#define bfin_write_DMA0_Y_MODIFY(val)  bfin_write16(DMA0_Y_MODIFY, val)
-#define bfin_read_DMA0_CURR_DESC_PTR() bfin_readPTR(DMA0_CURR_DESC_PTR)
-#define bfin_write_DMA0_CURR_DESC_PTR(val) bfin_writePTR(DMA0_CURR_DESC_PTR, val)
-#define bfin_read_DMA0_CURR_ADDR()     bfin_readPTR(DMA0_CURR_ADDR)
-#define bfin_write_DMA0_CURR_ADDR(val) bfin_writePTR(DMA0_CURR_ADDR, val)
-#define bfin_read_DMA0_IRQ_STATUS()    bfin_read16(DMA0_IRQ_STATUS)
-#define bfin_write_DMA0_IRQ_STATUS(val) bfin_write16(DMA0_IRQ_STATUS, val)
-#define bfin_read_DMA0_PERIPHERAL_MAP() bfin_read16(DMA0_PERIPHERAL_MAP)
-#define bfin_write_DMA0_PERIPHERAL_MAP(val) bfin_write16(DMA0_PERIPHERAL_MAP, val)
-#define bfin_read_DMA0_CURR_X_COUNT()  bfin_read16(DMA0_CURR_X_COUNT)
-#define bfin_write_DMA0_CURR_X_COUNT(val) bfin_write16(DMA0_CURR_X_COUNT, val)
-#define bfin_read_DMA0_CURR_Y_COUNT()  bfin_read16(DMA0_CURR_Y_COUNT)
-#define bfin_write_DMA0_CURR_Y_COUNT(val) bfin_write16(DMA0_CURR_Y_COUNT, val)
-#define bfin_read_DMA1_NEXT_DESC_PTR() bfin_readPTR(DMA1_NEXT_DESC_PTR)
-#define bfin_write_DMA1_NEXT_DESC_PTR(val) bfin_writePTR(DMA1_NEXT_DESC_PTR, val)
-#define bfin_read_DMA1_START_ADDR()    bfin_readPTR(DMA1_START_ADDR)
-#define bfin_write_DMA1_START_ADDR(val) bfin_writePTR(DMA1_START_ADDR, val)
-#define bfin_read_DMA1_CONFIG()        bfin_read16(DMA1_CONFIG)
-#define bfin_write_DMA1_CONFIG(val)    bfin_write16(DMA1_CONFIG, val)
-#define bfin_read_DMA1_X_COUNT()       bfin_read16(DMA1_X_COUNT)
-#define bfin_write_DMA1_X_COUNT(val)   bfin_write16(DMA1_X_COUNT, val)
-#define bfin_read_DMA1_X_MODIFY()      bfin_read16(DMA1_X_MODIFY)
-#define bfin_write_DMA1_X_MODIFY(val)  bfin_write16(DMA1_X_MODIFY, val)
-#define bfin_read_DMA1_Y_COUNT()       bfin_read16(DMA1_Y_COUNT)
-#define bfin_write_DMA1_Y_COUNT(val)   bfin_write16(DMA1_Y_COUNT, val)
-#define bfin_read_DMA1_Y_MODIFY()      bfin_read16(DMA1_Y_MODIFY)
-#define bfin_write_DMA1_Y_MODIFY(val)  bfin_write16(DMA1_Y_MODIFY, val)
-#define bfin_read_DMA1_CURR_DESC_PTR() bfin_readPTR(DMA1_CURR_DESC_PTR)
-#define bfin_write_DMA1_CURR_DESC_PTR(val) bfin_writePTR(DMA1_CURR_DESC_PTR, val)
-#define bfin_read_DMA1_CURR_ADDR()     bfin_readPTR(DMA1_CURR_ADDR)
-#define bfin_write_DMA1_CURR_ADDR(val) bfin_writePTR(DMA1_CURR_ADDR, val)
-#define bfin_read_DMA1_IRQ_STATUS()    bfin_read16(DMA1_IRQ_STATUS)
-#define bfin_write_DMA1_IRQ_STATUS(val) bfin_write16(DMA1_IRQ_STATUS, val)
-#define bfin_read_DMA1_PERIPHERAL_MAP() bfin_read16(DMA1_PERIPHERAL_MAP)
-#define bfin_write_DMA1_PERIPHERAL_MAP(val) bfin_write16(DMA1_PERIPHERAL_MAP, val)
-#define bfin_read_DMA1_CURR_X_COUNT()  bfin_read16(DMA1_CURR_X_COUNT)
-#define bfin_write_DMA1_CURR_X_COUNT(val) bfin_write16(DMA1_CURR_X_COUNT, val)
-#define bfin_read_DMA1_CURR_Y_COUNT()  bfin_read16(DMA1_CURR_Y_COUNT)
-#define bfin_write_DMA1_CURR_Y_COUNT(val) bfin_write16(DMA1_CURR_Y_COUNT, val)
-#define bfin_read_DMA2_NEXT_DESC_PTR() bfin_readPTR(DMA2_NEXT_DESC_PTR)
-#define bfin_write_DMA2_NEXT_DESC_PTR(val) bfin_writePTR(DMA2_NEXT_DESC_PTR, val)
-#define bfin_read_DMA2_START_ADDR()    bfin_readPTR(DMA2_START_ADDR)
-#define bfin_write_DMA2_START_ADDR(val) bfin_writePTR(DMA2_START_ADDR, val)
-#define bfin_read_DMA2_CONFIG()        bfin_read16(DMA2_CONFIG)
-#define bfin_write_DMA2_CONFIG(val)    bfin_write16(DMA2_CONFIG, val)
-#define bfin_read_DMA2_X_COUNT()       bfin_read16(DMA2_X_COUNT)
-#define bfin_write_DMA2_X_COUNT(val)   bfin_write16(DMA2_X_COUNT, val)
-#define bfin_read_DMA2_X_MODIFY()      bfin_read16(DMA2_X_MODIFY)
-#define bfin_write_DMA2_X_MODIFY(val)  bfin_write16(DMA2_X_MODIFY, val)
-#define bfin_read_DMA2_Y_COUNT()       bfin_read16(DMA2_Y_COUNT)
-#define bfin_write_DMA2_Y_COUNT(val)   bfin_write16(DMA2_Y_COUNT, val)
-#define bfin_read_DMA2_Y_MODIFY()      bfin_read16(DMA2_Y_MODIFY)
-#define bfin_write_DMA2_Y_MODIFY(val)  bfin_write16(DMA2_Y_MODIFY, val)
-#define bfin_read_DMA2_CURR_DESC_PTR() bfin_readPTR(DMA2_CURR_DESC_PTR)
-#define bfin_write_DMA2_CURR_DESC_PTR(val) bfin_writePTR(DMA2_CURR_DESC_PTR, val)
-#define bfin_read_DMA2_CURR_ADDR()     bfin_readPTR(DMA2_CURR_ADDR)
-#define bfin_write_DMA2_CURR_ADDR(val) bfin_writePTR(DMA2_CURR_ADDR, val)
-#define bfin_read_DMA2_IRQ_STATUS()    bfin_read16(DMA2_IRQ_STATUS)
-#define bfin_write_DMA2_IRQ_STATUS(val) bfin_write16(DMA2_IRQ_STATUS, val)
-#define bfin_read_DMA2_PERIPHERAL_MAP() bfin_read16(DMA2_PERIPHERAL_MAP)
-#define bfin_write_DMA2_PERIPHERAL_MAP(val) bfin_write16(DMA2_PERIPHERAL_MAP, val)
-#define bfin_read_DMA2_CURR_X_COUNT()  bfin_read16(DMA2_CURR_X_COUNT)
-#define bfin_write_DMA2_CURR_X_COUNT(val) bfin_write16(DMA2_CURR_X_COUNT, val)
-#define bfin_read_DMA2_CURR_Y_COUNT()  bfin_read16(DMA2_CURR_Y_COUNT)
-#define bfin_write_DMA2_CURR_Y_COUNT(val) bfin_write16(DMA2_CURR_Y_COUNT, val)
-#define bfin_read_DMA3_NEXT_DESC_PTR() bfin_readPTR(DMA3_NEXT_DESC_PTR)
-#define bfin_write_DMA3_NEXT_DESC_PTR(val) bfin_writePTR(DMA3_NEXT_DESC_PTR, val)
-#define bfin_read_DMA3_START_ADDR()    bfin_readPTR(DMA3_START_ADDR)
-#define bfin_write_DMA3_START_ADDR(val) bfin_writePTR(DMA3_START_ADDR, val)
-#define bfin_read_DMA3_CONFIG()        bfin_read16(DMA3_CONFIG)
-#define bfin_write_DMA3_CONFIG(val)    bfin_write16(DMA3_CONFIG, val)
-#define bfin_read_DMA3_X_COUNT()       bfin_read16(DMA3_X_COUNT)
-#define bfin_write_DMA3_X_COUNT(val)   bfin_write16(DMA3_X_COUNT, val)
-#define bfin_read_DMA3_X_MODIFY()      bfin_read16(DMA3_X_MODIFY)
-#define bfin_write_DMA3_X_MODIFY(val)  bfin_write16(DMA3_X_MODIFY, val)
-#define bfin_read_DMA3_Y_COUNT()       bfin_read16(DMA3_Y_COUNT)
-#define bfin_write_DMA3_Y_COUNT(val)   bfin_write16(DMA3_Y_COUNT, val)
-#define bfin_read_DMA3_Y_MODIFY()      bfin_read16(DMA3_Y_MODIFY)
-#define bfin_write_DMA3_Y_MODIFY(val)  bfin_write16(DMA3_Y_MODIFY, val)
-#define bfin_read_DMA3_CURR_DESC_PTR() bfin_readPTR(DMA3_CURR_DESC_PTR)
-#define bfin_write_DMA3_CURR_DESC_PTR(val) bfin_writePTR(DMA3_CURR_DESC_PTR, val)
-#define bfin_read_DMA3_CURR_ADDR()     bfin_readPTR(DMA3_CURR_ADDR)
-#define bfin_write_DMA3_CURR_ADDR(val) bfin_writePTR(DMA3_CURR_ADDR, val)
-#define bfin_read_DMA3_IRQ_STATUS()    bfin_read16(DMA3_IRQ_STATUS)
-#define bfin_write_DMA3_IRQ_STATUS(val) bfin_write16(DMA3_IRQ_STATUS, val)
-#define bfin_read_DMA3_PERIPHERAL_MAP() bfin_read16(DMA3_PERIPHERAL_MAP)
-#define bfin_write_DMA3_PERIPHERAL_MAP(val) bfin_write16(DMA3_PERIPHERAL_MAP, val)
-#define bfin_read_DMA3_CURR_X_COUNT()  bfin_read16(DMA3_CURR_X_COUNT)
-#define bfin_write_DMA3_CURR_X_COUNT(val) bfin_write16(DMA3_CURR_X_COUNT, val)
-#define bfin_read_DMA3_CURR_Y_COUNT()  bfin_read16(DMA3_CURR_Y_COUNT)
-#define bfin_write_DMA3_CURR_Y_COUNT(val) bfin_write16(DMA3_CURR_Y_COUNT, val)
-#define bfin_read_DMA4_NEXT_DESC_PTR() bfin_readPTR(DMA4_NEXT_DESC_PTR)
-#define bfin_write_DMA4_NEXT_DESC_PTR(val) bfin_writePTR(DMA4_NEXT_DESC_PTR, val)
-#define bfin_read_DMA4_START_ADDR()    bfin_readPTR(DMA4_START_ADDR)
-#define bfin_write_DMA4_START_ADDR(val) bfin_writePTR(DMA4_START_ADDR, val)
-#define bfin_read_DMA4_CONFIG()        bfin_read16(DMA4_CONFIG)
-#define bfin_write_DMA4_CONFIG(val)    bfin_write16(DMA4_CONFIG, val)
-#define bfin_read_DMA4_X_COUNT()       bfin_read16(DMA4_X_COUNT)
-#define bfin_write_DMA4_X_COUNT(val)   bfin_write16(DMA4_X_COUNT, val)
-#define bfin_read_DMA4_X_MODIFY()      bfin_read16(DMA4_X_MODIFY)
-#define bfin_write_DMA4_X_MODIFY(val)  bfin_write16(DMA4_X_MODIFY, val)
-#define bfin_read_DMA4_Y_COUNT()       bfin_read16(DMA4_Y_COUNT)
-#define bfin_write_DMA4_Y_COUNT(val)   bfin_write16(DMA4_Y_COUNT, val)
-#define bfin_read_DMA4_Y_MODIFY()      bfin_read16(DMA4_Y_MODIFY)
-#define bfin_write_DMA4_Y_MODIFY(val)  bfin_write16(DMA4_Y_MODIFY, val)
-#define bfin_read_DMA4_CURR_DESC_PTR() bfin_readPTR(DMA4_CURR_DESC_PTR)
-#define bfin_write_DMA4_CURR_DESC_PTR(val) bfin_writePTR(DMA4_CURR_DESC_PTR, val)
-#define bfin_read_DMA4_CURR_ADDR()     bfin_readPTR(DMA4_CURR_ADDR)
-#define bfin_write_DMA4_CURR_ADDR(val) bfin_writePTR(DMA4_CURR_ADDR, val)
-#define bfin_read_DMA4_IRQ_STATUS()    bfin_read16(DMA4_IRQ_STATUS)
-#define bfin_write_DMA4_IRQ_STATUS(val) bfin_write16(DMA4_IRQ_STATUS, val)
-#define bfin_read_DMA4_PERIPHERAL_MAP() bfin_read16(DMA4_PERIPHERAL_MAP)
-#define bfin_write_DMA4_PERIPHERAL_MAP(val) bfin_write16(DMA4_PERIPHERAL_MAP, val)
-#define bfin_read_DMA4_CURR_X_COUNT()  bfin_read16(DMA4_CURR_X_COUNT)
-#define bfin_write_DMA4_CURR_X_COUNT(val) bfin_write16(DMA4_CURR_X_COUNT, val)
-#define bfin_read_DMA4_CURR_Y_COUNT()  bfin_read16(DMA4_CURR_Y_COUNT)
-#define bfin_write_DMA4_CURR_Y_COUNT(val) bfin_write16(DMA4_CURR_Y_COUNT, val)
-#define bfin_read_DMA5_NEXT_DESC_PTR() bfin_readPTR(DMA5_NEXT_DESC_PTR)
-#define bfin_write_DMA5_NEXT_DESC_PTR(val) bfin_writePTR(DMA5_NEXT_DESC_PTR, val)
-#define bfin_read_DMA5_START_ADDR()    bfin_readPTR(DMA5_START_ADDR)
-#define bfin_write_DMA5_START_ADDR(val) bfin_writePTR(DMA5_START_ADDR, val)
-#define bfin_read_DMA5_CONFIG()        bfin_read16(DMA5_CONFIG)
-#define bfin_write_DMA5_CONFIG(val)    bfin_write16(DMA5_CONFIG, val)
-#define bfin_read_DMA5_X_COUNT()       bfin_read16(DMA5_X_COUNT)
-#define bfin_write_DMA5_X_COUNT(val)   bfin_write16(DMA5_X_COUNT, val)
-#define bfin_read_DMA5_X_MODIFY()      bfin_read16(DMA5_X_MODIFY)
-#define bfin_write_DMA5_X_MODIFY(val)  bfin_write16(DMA5_X_MODIFY, val)
-#define bfin_read_DMA5_Y_COUNT()       bfin_read16(DMA5_Y_COUNT)
-#define bfin_write_DMA5_Y_COUNT(val)   bfin_write16(DMA5_Y_COUNT, val)
-#define bfin_read_DMA5_Y_MODIFY()      bfin_read16(DMA5_Y_MODIFY)
-#define bfin_write_DMA5_Y_MODIFY(val)  bfin_write16(DMA5_Y_MODIFY, val)
-#define bfin_read_DMA5_CURR_DESC_PTR() bfin_readPTR(DMA5_CURR_DESC_PTR)
-#define bfin_write_DMA5_CURR_DESC_PTR(val) bfin_writePTR(DMA5_CURR_DESC_PTR, val)
-#define bfin_read_DMA5_CURR_ADDR()     bfin_readPTR(DMA5_CURR_ADDR)
-#define bfin_write_DMA5_CURR_ADDR(val) bfin_writePTR(DMA5_CURR_ADDR, val)
-#define bfin_read_DMA5_IRQ_STATUS()    bfin_read16(DMA5_IRQ_STATUS)
-#define bfin_write_DMA5_IRQ_STATUS(val) bfin_write16(DMA5_IRQ_STATUS, val)
-#define bfin_read_DMA5_PERIPHERAL_MAP() bfin_read16(DMA5_PERIPHERAL_MAP)
-#define bfin_write_DMA5_PERIPHERAL_MAP(val) bfin_write16(DMA5_PERIPHERAL_MAP, val)
-#define bfin_read_DMA5_CURR_X_COUNT()  bfin_read16(DMA5_CURR_X_COUNT)
-#define bfin_write_DMA5_CURR_X_COUNT(val) bfin_write16(DMA5_CURR_X_COUNT, val)
-#define bfin_read_DMA5_CURR_Y_COUNT()  bfin_read16(DMA5_CURR_Y_COUNT)
-#define bfin_write_DMA5_CURR_Y_COUNT(val) bfin_write16(DMA5_CURR_Y_COUNT, val)
-#define bfin_read_DMA6_NEXT_DESC_PTR() bfin_read32(DMA6_NEXT_DESC_PTR)
-#define bfin_write_DMA6_NEXT_DESC_PTR(val) bfin_write32(DMA6_NEXT_DESC_PTR, val)
-#define bfin_read_DMA6_START_ADDR()    bfin_readPTR(DMA6_START_ADDR)
-#define bfin_write_DMA6_START_ADDR(val) bfin_writePTR(DMA6_START_ADDR, val)
-#define bfin_read_DMA6_CONFIG()        bfin_read16(DMA6_CONFIG)
-#define bfin_write_DMA6_CONFIG(val)    bfin_write16(DMA6_CONFIG, val)
-#define bfin_read_DMA6_X_COUNT()       bfin_read16(DMA6_X_COUNT)
-#define bfin_write_DMA6_X_COUNT(val)   bfin_write16(DMA6_X_COUNT, val)
-#define bfin_read_DMA6_X_MODIFY()      bfin_read16(DMA6_X_MODIFY)
-#define bfin_write_DMA6_X_MODIFY(val)  bfin_write16(DMA6_X_MODIFY, val)
-#define bfin_read_DMA6_Y_COUNT()       bfin_read16(DMA6_Y_COUNT)
-#define bfin_write_DMA6_Y_COUNT(val)   bfin_write16(DMA6_Y_COUNT, val)
-#define bfin_read_DMA6_Y_MODIFY()      bfin_read16(DMA6_Y_MODIFY)
-#define bfin_write_DMA6_Y_MODIFY(val)  bfin_write16(DMA6_Y_MODIFY, val)
-#define bfin_read_DMA6_CURR_DESC_PTR() bfin_readPTR(DMA6_CURR_DESC_PTR)
-#define bfin_write_DMA6_CURR_DESC_PTR(val) bfin_writePTR(DMA6_CURR_DESC_PTR, val)
-#define bfin_read_DMA6_CURR_ADDR()     bfin_readPTR(DMA6_CURR_ADDR)
-#define bfin_write_DMA6_CURR_ADDR(val) bfin_writePTR(DMA6_CURR_ADDR, val)
-#define bfin_read_DMA6_IRQ_STATUS()    bfin_read16(DMA6_IRQ_STATUS)
-#define bfin_write_DMA6_IRQ_STATUS(val) bfin_write16(DMA6_IRQ_STATUS, val)
-#define bfin_read_DMA6_PERIPHERAL_MAP() bfin_read16(DMA6_PERIPHERAL_MAP)
-#define bfin_write_DMA6_PERIPHERAL_MAP(val) bfin_write16(DMA6_PERIPHERAL_MAP, val)
-#define bfin_read_DMA6_CURR_X_COUNT()  bfin_read16(DMA6_CURR_X_COUNT)
-#define bfin_write_DMA6_CURR_X_COUNT(val) bfin_write16(DMA6_CURR_X_COUNT, val)
-#define bfin_read_DMA6_CURR_Y_COUNT()  bfin_read16(DMA6_CURR_Y_COUNT)
-#define bfin_write_DMA6_CURR_Y_COUNT(val) bfin_write16(DMA6_CURR_Y_COUNT, val)
-#define bfin_read_DMA7_NEXT_DESC_PTR() bfin_readPTR(DMA7_NEXT_DESC_PTR)
-#define bfin_write_DMA7_NEXT_DESC_PTR(val) bfin_writePTR(DMA7_NEXT_DESC_PTR, val)
-#define bfin_read_DMA7_START_ADDR()    bfin_readPTR(DMA7_START_ADDR)
-#define bfin_write_DMA7_START_ADDR(val) bfin_writePTR(DMA7_START_ADDR, val)
-#define bfin_read_DMA7_CONFIG()        bfin_read16(DMA7_CONFIG)
-#define bfin_write_DMA7_CONFIG(val)    bfin_write16(DMA7_CONFIG, val)
-#define bfin_read_DMA7_X_COUNT()       bfin_read16(DMA7_X_COUNT)
-#define bfin_write_DMA7_X_COUNT(val)   bfin_write16(DMA7_X_COUNT, val)
-#define bfin_read_DMA7_X_MODIFY()      bfin_read16(DMA7_X_MODIFY)
-#define bfin_write_DMA7_X_MODIFY(val)  bfin_write16(DMA7_X_MODIFY, val)
-#define bfin_read_DMA7_Y_COUNT()       bfin_read16(DMA7_Y_COUNT)
-#define bfin_write_DMA7_Y_COUNT(val)   bfin_write16(DMA7_Y_COUNT, val)
-#define bfin_read_DMA7_Y_MODIFY()      bfin_read16(DMA7_Y_MODIFY)
-#define bfin_write_DMA7_Y_MODIFY(val)  bfin_write16(DMA7_Y_MODIFY, val)
-#define bfin_read_DMA7_CURR_DESC_PTR() bfin_readPTR(DMA7_CURR_DESC_PTR)
-#define bfin_write_DMA7_CURR_DESC_PTR(val) bfin_writePTR(DMA7_CURR_DESC_PTR, val)
-#define bfin_read_DMA7_CURR_ADDR()     bfin_readPTR(DMA7_CURR_ADDR)
-#define bfin_write_DMA7_CURR_ADDR(val) bfin_writePTR(DMA7_CURR_ADDR, val)
-#define bfin_read_DMA7_IRQ_STATUS()    bfin_read16(DMA7_IRQ_STATUS)
-#define bfin_write_DMA7_IRQ_STATUS(val) bfin_write16(DMA7_IRQ_STATUS, val)
-#define bfin_read_DMA7_PERIPHERAL_MAP() bfin_read16(DMA7_PERIPHERAL_MAP)
-#define bfin_write_DMA7_PERIPHERAL_MAP(val) bfin_write16(DMA7_PERIPHERAL_MAP, val)
-#define bfin_read_DMA7_CURR_X_COUNT()  bfin_read16(DMA7_CURR_X_COUNT)
-#define bfin_write_DMA7_CURR_X_COUNT(val) bfin_write16(DMA7_CURR_X_COUNT, val)
-#define bfin_read_DMA7_CURR_Y_COUNT()  bfin_read16(DMA7_CURR_Y_COUNT)
-#define bfin_write_DMA7_CURR_Y_COUNT(val) bfin_write16(DMA7_CURR_Y_COUNT, val)
-#define bfin_read_DMA8_NEXT_DESC_PTR() bfin_readPTR(DMA8_NEXT_DESC_PTR)
-#define bfin_write_DMA8_NEXT_DESC_PTR(val) bfin_writePTR(DMA8_NEXT_DESC_PTR, val)
-#define bfin_read_DMA8_START_ADDR()    bfin_readPTR(DMA8_START_ADDR)
-#define bfin_write_DMA8_START_ADDR(val) bfin_writePTR(DMA8_START_ADDR, val)
-#define bfin_read_DMA8_CONFIG()        bfin_read16(DMA8_CONFIG)
-#define bfin_write_DMA8_CONFIG(val)    bfin_write16(DMA8_CONFIG, val)
-#define bfin_read_DMA8_X_COUNT()       bfin_read16(DMA8_X_COUNT)
-#define bfin_write_DMA8_X_COUNT(val)   bfin_write16(DMA8_X_COUNT, val)
-#define bfin_read_DMA8_X_MODIFY()      bfin_read16(DMA8_X_MODIFY)
-#define bfin_write_DMA8_X_MODIFY(val)  bfin_write16(DMA8_X_MODIFY, val)
-#define bfin_read_DMA8_Y_COUNT()       bfin_read16(DMA8_Y_COUNT)
-#define bfin_write_DMA8_Y_COUNT(val)   bfin_write16(DMA8_Y_COUNT, val)
-#define bfin_read_DMA8_Y_MODIFY()      bfin_read16(DMA8_Y_MODIFY)
-#define bfin_write_DMA8_Y_MODIFY(val)  bfin_write16(DMA8_Y_MODIFY, val)
-#define bfin_read_DMA8_CURR_DESC_PTR() bfin_readPTR(DMA8_CURR_DESC_PTR)
-#define bfin_write_DMA8_CURR_DESC_PTR(val) bfin_writePTR(DMA8_CURR_DESC_PTR, val)
-#define bfin_read_DMA8_CURR_ADDR()     bfin_readPTR(DMA8_CURR_ADDR)
-#define bfin_write_DMA8_CURR_ADDR(val) bfin_writePTR(DMA8_CURR_ADDR, val)
-#define bfin_read_DMA8_IRQ_STATUS()    bfin_read16(DMA8_IRQ_STATUS)
-#define bfin_write_DMA8_IRQ_STATUS(val) bfin_write16(DMA8_IRQ_STATUS, val)
-#define bfin_read_DMA8_PERIPHERAL_MAP() bfin_read16(DMA8_PERIPHERAL_MAP)
-#define bfin_write_DMA8_PERIPHERAL_MAP(val) bfin_write16(DMA8_PERIPHERAL_MAP, val)
-#define bfin_read_DMA8_CURR_X_COUNT()  bfin_read16(DMA8_CURR_X_COUNT)
-#define bfin_write_DMA8_CURR_X_COUNT(val) bfin_write16(DMA8_CURR_X_COUNT, val)
-#define bfin_read_DMA8_CURR_Y_COUNT()  bfin_read16(DMA8_CURR_Y_COUNT)
-#define bfin_write_DMA8_CURR_Y_COUNT(val) bfin_write16(DMA8_CURR_Y_COUNT, val)
-#define bfin_read_DMA9_NEXT_DESC_PTR() bfin_readPTR(DMA9_NEXT_DESC_PTR)
-#define bfin_write_DMA9_NEXT_DESC_PTR(val) bfin_writePTR(DMA9_NEXT_DESC_PTR, val)
-#define bfin_read_DMA9_START_ADDR()    bfin_readPTR(DMA9_START_ADDR)
-#define bfin_write_DMA9_START_ADDR(val) bfin_writePTR(DMA9_START_ADDR, val)
-#define bfin_read_DMA9_CONFIG()        bfin_read16(DMA9_CONFIG)
-#define bfin_write_DMA9_CONFIG(val)    bfin_write16(DMA9_CONFIG, val)
-#define bfin_read_DMA9_X_COUNT()       bfin_read16(DMA9_X_COUNT)
-#define bfin_write_DMA9_X_COUNT(val)   bfin_write16(DMA9_X_COUNT, val)
-#define bfin_read_DMA9_X_MODIFY()      bfin_read16(DMA9_X_MODIFY)
-#define bfin_write_DMA9_X_MODIFY(val)  bfin_write16(DMA9_X_MODIFY, val)
-#define bfin_read_DMA9_Y_COUNT()       bfin_read16(DMA9_Y_COUNT)
-#define bfin_write_DMA9_Y_COUNT(val)   bfin_write16(DMA9_Y_COUNT, val)
-#define bfin_read_DMA9_Y_MODIFY()      bfin_read16(DMA9_Y_MODIFY)
-#define bfin_write_DMA9_Y_MODIFY(val)  bfin_write16(DMA9_Y_MODIFY, val)
-#define bfin_read_DMA9_CURR_DESC_PTR() bfin_readPTR(DMA9_CURR_DESC_PTR)
-#define bfin_write_DMA9_CURR_DESC_PTR(val) bfin_writePTR(DMA9_CURR_DESC_PTR, val)
-#define bfin_read_DMA9_CURR_ADDR()     bfin_readPTR(DMA9_CURR_ADDR)
-#define bfin_write_DMA9_CURR_ADDR(val) bfin_writePTR(DMA9_CURR_ADDR, val)
-#define bfin_read_DMA9_IRQ_STATUS()    bfin_read16(DMA9_IRQ_STATUS)
-#define bfin_write_DMA9_IRQ_STATUS(val) bfin_write16(DMA9_IRQ_STATUS, val)
-#define bfin_read_DMA9_PERIPHERAL_MAP() bfin_read16(DMA9_PERIPHERAL_MAP)
-#define bfin_write_DMA9_PERIPHERAL_MAP(val) bfin_write16(DMA9_PERIPHERAL_MAP, val)
-#define bfin_read_DMA9_CURR_X_COUNT()  bfin_read16(DMA9_CURR_X_COUNT)
-#define bfin_write_DMA9_CURR_X_COUNT(val) bfin_write16(DMA9_CURR_X_COUNT, val)
-#define bfin_read_DMA9_CURR_Y_COUNT()  bfin_read16(DMA9_CURR_Y_COUNT)
-#define bfin_write_DMA9_CURR_Y_COUNT(val) bfin_write16(DMA9_CURR_Y_COUNT, val)
-#define bfin_read_DMA10_NEXT_DESC_PTR() bfin_readPTR(DMA10_NEXT_DESC_PTR)
-#define bfin_write_DMA10_NEXT_DESC_PTR(val) bfin_writePTR(DMA10_NEXT_DESC_PTR, val)
-#define bfin_read_DMA10_START_ADDR()   bfin_readPTR(DMA10_START_ADDR)
-#define bfin_write_DMA10_START_ADDR(val) bfin_writePTR(DMA10_START_ADDR, val)
-#define bfin_read_DMA10_CONFIG()       bfin_read16(DMA10_CONFIG)
-#define bfin_write_DMA10_CONFIG(val)   bfin_write16(DMA10_CONFIG, val)
-#define bfin_read_DMA10_X_COUNT()      bfin_read16(DMA10_X_COUNT)
-#define bfin_write_DMA10_X_COUNT(val)  bfin_write16(DMA10_X_COUNT, val)
-#define bfin_read_DMA10_X_MODIFY()     bfin_read16(DMA10_X_MODIFY)
-#define bfin_write_DMA10_X_MODIFY(val) bfin_write16(DMA10_X_MODIFY, val)
-#define bfin_read_DMA10_Y_COUNT()      bfin_read16(DMA10_Y_COUNT)
-#define bfin_write_DMA10_Y_COUNT(val)  bfin_write16(DMA10_Y_COUNT, val)
-#define bfin_read_DMA10_Y_MODIFY()     bfin_read16(DMA10_Y_MODIFY)
-#define bfin_write_DMA10_Y_MODIFY(val) bfin_write16(DMA10_Y_MODIFY, val)
-#define bfin_read_DMA10_CURR_DESC_PTR() bfin_readPTR(DMA10_CURR_DESC_PTR)
-#define bfin_write_DMA10_CURR_DESC_PTR(val) bfin_writePTR(DMA10_CURR_DESC_PTR, val)
-#define bfin_read_DMA10_CURR_ADDR()    bfin_readPTR(DMA10_CURR_ADDR)
-#define bfin_write_DMA10_CURR_ADDR(val) bfin_writePTR(DMA10_CURR_ADDR, val)
-#define bfin_read_DMA10_IRQ_STATUS()   bfin_read16(DMA10_IRQ_STATUS)
-#define bfin_write_DMA10_IRQ_STATUS(val) bfin_write16(DMA10_IRQ_STATUS, val)
-#define bfin_read_DMA10_PERIPHERAL_MAP() bfin_read16(DMA10_PERIPHERAL_MAP)
-#define bfin_write_DMA10_PERIPHERAL_MAP(val) bfin_write16(DMA10_PERIPHERAL_MAP, val)
-#define bfin_read_DMA10_CURR_X_COUNT() bfin_read16(DMA10_CURR_X_COUNT)
-#define bfin_write_DMA10_CURR_X_COUNT(val) bfin_write16(DMA10_CURR_X_COUNT, val)
-#define bfin_read_DMA10_CURR_Y_COUNT() bfin_read16(DMA10_CURR_Y_COUNT)
-#define bfin_write_DMA10_CURR_Y_COUNT(val) bfin_write16(DMA10_CURR_Y_COUNT, val)
-#define bfin_read_DMA11_NEXT_DESC_PTR() bfin_readPTR(DMA11_NEXT_DESC_PTR)
-#define bfin_write_DMA11_NEXT_DESC_PTR(val) bfin_writePTR(DMA11_NEXT_DESC_PTR, val)
-#define bfin_read_DMA11_START_ADDR()   bfin_readPTR(DMA11_START_ADDR)
-#define bfin_write_DMA11_START_ADDR(val) bfin_writePTR(DMA11_START_ADDR, val)
-#define bfin_read_DMA11_CONFIG()       bfin_read16(DMA11_CONFIG)
-#define bfin_write_DMA11_CONFIG(val)   bfin_write16(DMA11_CONFIG, val)
-#define bfin_read_DMA11_X_COUNT()      bfin_read16(DMA11_X_COUNT)
-#define bfin_write_DMA11_X_COUNT(val)  bfin_write16(DMA11_X_COUNT, val)
-#define bfin_read_DMA11_X_MODIFY()     bfin_read16(DMA11_X_MODIFY)
-#define bfin_write_DMA11_X_MODIFY(val) bfin_write16(DMA11_X_MODIFY, val)
-#define bfin_read_DMA11_Y_COUNT()      bfin_read16(DMA11_Y_COUNT)
-#define bfin_write_DMA11_Y_COUNT(val)  bfin_write16(DMA11_Y_COUNT, val)
-#define bfin_read_DMA11_Y_MODIFY()     bfin_read16(DMA11_Y_MODIFY)
-#define bfin_write_DMA11_Y_MODIFY(val) bfin_write16(DMA11_Y_MODIFY, val)
-#define bfin_read_DMA11_CURR_DESC_PTR() bfin_readPTR(DMA11_CURR_DESC_PTR)
-#define bfin_write_DMA11_CURR_DESC_PTR(val) bfin_writePTR(DMA11_CURR_DESC_PTR, val)
-#define bfin_read_DMA11_CURR_ADDR()    bfin_readPTR(DMA11_CURR_ADDR)
-#define bfin_write_DMA11_CURR_ADDR(val) bfin_writePTR(DMA11_CURR_ADDR, val)
-#define bfin_read_DMA11_IRQ_STATUS()   bfin_read16(DMA11_IRQ_STATUS)
-#define bfin_write_DMA11_IRQ_STATUS(val) bfin_write16(DMA11_IRQ_STATUS, val)
-#define bfin_read_DMA11_PERIPHERAL_MAP() bfin_read16(DMA11_PERIPHERAL_MAP)
-#define bfin_write_DMA11_PERIPHERAL_MAP(val) bfin_write16(DMA11_PERIPHERAL_MAP, val)
-#define bfin_read_DMA11_CURR_X_COUNT() bfin_read16(DMA11_CURR_X_COUNT)
-#define bfin_write_DMA11_CURR_X_COUNT(val) bfin_write16(DMA11_CURR_X_COUNT, val)
-#define bfin_read_DMA11_CURR_Y_COUNT() bfin_read16(DMA11_CURR_Y_COUNT)
-#define bfin_write_DMA11_CURR_Y_COUNT(val) bfin_write16(DMA11_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S0_NEXT_DESC_PTR() bfin_readPTR(MDMA_S0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S0_START_ADDR() bfin_readPTR(MDMA_S0_START_ADDR)
-#define bfin_write_MDMA_S0_START_ADDR(val) bfin_writePTR(MDMA_S0_START_ADDR, val)
-#define bfin_read_MDMA_S0_CONFIG()     bfin_read16(MDMA_S0_CONFIG)
-#define bfin_write_MDMA_S0_CONFIG(val) bfin_write16(MDMA_S0_CONFIG, val)
-#define bfin_read_MDMA_S0_X_COUNT()    bfin_read16(MDMA_S0_X_COUNT)
-#define bfin_write_MDMA_S0_X_COUNT(val) bfin_write16(MDMA_S0_X_COUNT, val)
-#define bfin_read_MDMA_S0_X_MODIFY()   bfin_read16(MDMA_S0_X_MODIFY)
-#define bfin_write_MDMA_S0_X_MODIFY(val) bfin_write16(MDMA_S0_X_MODIFY, val)
-#define bfin_read_MDMA_S0_Y_COUNT()    bfin_read16(MDMA_S0_Y_COUNT)
-#define bfin_write_MDMA_S0_Y_COUNT(val) bfin_write16(MDMA_S0_Y_COUNT, val)
-#define bfin_read_MDMA_S0_Y_MODIFY()   bfin_read16(MDMA_S0_Y_MODIFY)
-#define bfin_write_MDMA_S0_Y_MODIFY(val) bfin_write16(MDMA_S0_Y_MODIFY, val)
-#define bfin_read_MDMA_S0_CURR_DESC_PTR() bfin_readPTR(MDMA_S0_CURR_DESC_PTR)
-#define bfin_write_MDMA_S0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S0_CURR_ADDR()  bfin_readPTR(MDMA_S0_CURR_ADDR)
-#define bfin_write_MDMA_S0_CURR_ADDR(val) bfin_writePTR(MDMA_S0_CURR_ADDR, val)
-#define bfin_read_MDMA_S0_IRQ_STATUS() bfin_read16(MDMA_S0_IRQ_STATUS)
-#define bfin_write_MDMA_S0_IRQ_STATUS(val) bfin_write16(MDMA_S0_IRQ_STATUS, val)
-#define bfin_read_MDMA_S0_PERIPHERAL_MAP() bfin_read16(MDMA_S0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S0_PERIPHERAL_MAP(val) bfin_write16(MDMA_S0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S0_CURR_X_COUNT() bfin_read16(MDMA_S0_CURR_X_COUNT)
-#define bfin_write_MDMA_S0_CURR_X_COUNT(val) bfin_write16(MDMA_S0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S0_CURR_Y_COUNT() bfin_read16(MDMA_S0_CURR_Y_COUNT)
-#define bfin_write_MDMA_S0_CURR_Y_COUNT(val) bfin_write16(MDMA_S0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D0_NEXT_DESC_PTR() bfin_readPTR(MDMA_D0_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D0_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D0_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D0_START_ADDR() bfin_readPTR(MDMA_D0_START_ADDR)
-#define bfin_write_MDMA_D0_START_ADDR(val) bfin_writePTR(MDMA_D0_START_ADDR, val)
-#define bfin_read_MDMA_D0_CONFIG()     bfin_read16(MDMA_D0_CONFIG)
-#define bfin_write_MDMA_D0_CONFIG(val) bfin_write16(MDMA_D0_CONFIG, val)
-#define bfin_read_MDMA_D0_X_COUNT()    bfin_read16(MDMA_D0_X_COUNT)
-#define bfin_write_MDMA_D0_X_COUNT(val) bfin_write16(MDMA_D0_X_COUNT, val)
-#define bfin_read_MDMA_D0_X_MODIFY()   bfin_read16(MDMA_D0_X_MODIFY)
-#define bfin_write_MDMA_D0_X_MODIFY(val) bfin_write16(MDMA_D0_X_MODIFY, val)
-#define bfin_read_MDMA_D0_Y_COUNT()    bfin_read16(MDMA_D0_Y_COUNT)
-#define bfin_write_MDMA_D0_Y_COUNT(val) bfin_write16(MDMA_D0_Y_COUNT, val)
-#define bfin_read_MDMA_D0_Y_MODIFY()   bfin_read16(MDMA_D0_Y_MODIFY)
-#define bfin_write_MDMA_D0_Y_MODIFY(val) bfin_write16(MDMA_D0_Y_MODIFY, val)
-#define bfin_read_MDMA_D0_CURR_DESC_PTR() bfin_readPTR(MDMA_D0_CURR_DESC_PTR)
-#define bfin_write_MDMA_D0_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D0_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D0_CURR_ADDR()  bfin_readPTR(MDMA_D0_CURR_ADDR)
-#define bfin_write_MDMA_D0_CURR_ADDR(val) bfin_writePTR(MDMA_D0_CURR_ADDR, val)
-#define bfin_read_MDMA_D0_IRQ_STATUS() bfin_read16(MDMA_D0_IRQ_STATUS)
-#define bfin_write_MDMA_D0_IRQ_STATUS(val) bfin_write16(MDMA_D0_IRQ_STATUS, val)
-#define bfin_read_MDMA_D0_PERIPHERAL_MAP() bfin_read16(MDMA_D0_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D0_PERIPHERAL_MAP(val) bfin_write16(MDMA_D0_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D0_CURR_X_COUNT() bfin_read16(MDMA_D0_CURR_X_COUNT)
-#define bfin_write_MDMA_D0_CURR_X_COUNT(val) bfin_write16(MDMA_D0_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D0_CURR_Y_COUNT() bfin_read16(MDMA_D0_CURR_Y_COUNT)
-#define bfin_write_MDMA_D0_CURR_Y_COUNT(val) bfin_write16(MDMA_D0_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_S1_NEXT_DESC_PTR() bfin_readPTR(MDMA_S1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_S1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_S1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_S1_START_ADDR() bfin_readPTR(MDMA_S1_START_ADDR)
-#define bfin_write_MDMA_S1_START_ADDR(val) bfin_writePTR(MDMA_S1_START_ADDR, val)
-#define bfin_read_MDMA_S1_CONFIG()     bfin_read16(MDMA_S1_CONFIG)
-#define bfin_write_MDMA_S1_CONFIG(val) bfin_write16(MDMA_S1_CONFIG, val)
-#define bfin_read_MDMA_S1_X_COUNT()    bfin_read16(MDMA_S1_X_COUNT)
-#define bfin_write_MDMA_S1_X_COUNT(val) bfin_write16(MDMA_S1_X_COUNT, val)
-#define bfin_read_MDMA_S1_X_MODIFY()   bfin_read16(MDMA_S1_X_MODIFY)
-#define bfin_write_MDMA_S1_X_MODIFY(val) bfin_write16(MDMA_S1_X_MODIFY, val)
-#define bfin_read_MDMA_S1_Y_COUNT()    bfin_read16(MDMA_S1_Y_COUNT)
-#define bfin_write_MDMA_S1_Y_COUNT(val) bfin_write16(MDMA_S1_Y_COUNT, val)
-#define bfin_read_MDMA_S1_Y_MODIFY()   bfin_read16(MDMA_S1_Y_MODIFY)
-#define bfin_write_MDMA_S1_Y_MODIFY(val) bfin_write16(MDMA_S1_Y_MODIFY, val)
-#define bfin_read_MDMA_S1_CURR_DESC_PTR() bfin_readPTR(MDMA_S1_CURR_DESC_PTR)
-#define bfin_write_MDMA_S1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_S1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_S1_CURR_ADDR()  bfin_readPTR(MDMA_S1_CURR_ADDR)
-#define bfin_write_MDMA_S1_CURR_ADDR(val) bfin_writePTR(MDMA_S1_CURR_ADDR, val)
-#define bfin_read_MDMA_S1_IRQ_STATUS() bfin_read16(MDMA_S1_IRQ_STATUS)
-#define bfin_write_MDMA_S1_IRQ_STATUS(val) bfin_write16(MDMA_S1_IRQ_STATUS, val)
-#define bfin_read_MDMA_S1_PERIPHERAL_MAP() bfin_read16(MDMA_S1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_S1_PERIPHERAL_MAP(val) bfin_write16(MDMA_S1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_S1_CURR_X_COUNT() bfin_read16(MDMA_S1_CURR_X_COUNT)
-#define bfin_write_MDMA_S1_CURR_X_COUNT(val) bfin_write16(MDMA_S1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_S1_CURR_Y_COUNT() bfin_read16(MDMA_S1_CURR_Y_COUNT)
-#define bfin_write_MDMA_S1_CURR_Y_COUNT(val) bfin_write16(MDMA_S1_CURR_Y_COUNT, val)
-#define bfin_read_MDMA_D1_NEXT_DESC_PTR() bfin_readPTR(MDMA_D1_NEXT_DESC_PTR)
-#define bfin_write_MDMA_D1_NEXT_DESC_PTR(val) bfin_writePTR(MDMA_D1_NEXT_DESC_PTR, val)
-#define bfin_read_MDMA_D1_START_ADDR() bfin_readPTR(MDMA_D1_START_ADDR)
-#define bfin_write_MDMA_D1_START_ADDR(val) bfin_writePTR(MDMA_D1_START_ADDR, val)
-#define bfin_read_MDMA_D1_CONFIG()     bfin_read16(MDMA_D1_CONFIG)
-#define bfin_write_MDMA_D1_CONFIG(val) bfin_write16(MDMA_D1_CONFIG, val)
-#define bfin_read_MDMA_D1_X_COUNT()    bfin_read16(MDMA_D1_X_COUNT)
-#define bfin_write_MDMA_D1_X_COUNT(val) bfin_write16(MDMA_D1_X_COUNT, val)
-#define bfin_read_MDMA_D1_X_MODIFY()   bfin_read16(MDMA_D1_X_MODIFY)
-#define bfin_write_MDMA_D1_X_MODIFY(val) bfin_write16(MDMA_D1_X_MODIFY, val)
-#define bfin_read_MDMA_D1_Y_COUNT()    bfin_read16(MDMA_D1_Y_COUNT)
-#define bfin_write_MDMA_D1_Y_COUNT(val) bfin_write16(MDMA_D1_Y_COUNT, val)
-#define bfin_read_MDMA_D1_Y_MODIFY()   bfin_read16(MDMA_D1_Y_MODIFY)
-#define bfin_write_MDMA_D1_Y_MODIFY(val) bfin_write16(MDMA_D1_Y_MODIFY, val)
-#define bfin_read_MDMA_D1_CURR_DESC_PTR() bfin_readPTR(MDMA_D1_CURR_DESC_PTR)
-#define bfin_write_MDMA_D1_CURR_DESC_PTR(val) bfin_writePTR(MDMA_D1_CURR_DESC_PTR, val)
-#define bfin_read_MDMA_D1_CURR_ADDR()  bfin_readPTR(MDMA_D1_CURR_ADDR)
-#define bfin_write_MDMA_D1_CURR_ADDR(val) bfin_writePTR(MDMA_D1_CURR_ADDR, val)
-#define bfin_read_MDMA_D1_IRQ_STATUS() bfin_read16(MDMA_D1_IRQ_STATUS)
-#define bfin_write_MDMA_D1_IRQ_STATUS(val) bfin_write16(MDMA_D1_IRQ_STATUS, val)
-#define bfin_read_MDMA_D1_PERIPHERAL_MAP() bfin_read16(MDMA_D1_PERIPHERAL_MAP)
-#define bfin_write_MDMA_D1_PERIPHERAL_MAP(val) bfin_write16(MDMA_D1_PERIPHERAL_MAP, val)
-#define bfin_read_MDMA_D1_CURR_X_COUNT() bfin_read16(MDMA_D1_CURR_X_COUNT)
-#define bfin_write_MDMA_D1_CURR_X_COUNT(val) bfin_write16(MDMA_D1_CURR_X_COUNT, val)
-#define bfin_read_MDMA_D1_CURR_Y_COUNT() bfin_read16(MDMA_D1_CURR_Y_COUNT)
-#define bfin_write_MDMA_D1_CURR_Y_COUNT(val) bfin_write16(MDMA_D1_CURR_Y_COUNT, val)
-#define bfin_read_PPI_CONTROL()        bfin_read16(PPI_CONTROL)
-#define bfin_write_PPI_CONTROL(val)    bfin_write16(PPI_CONTROL, val)
-#define bfin_read_PPI_STATUS()         bfin_read16(PPI_STATUS)
-#define bfin_write_PPI_STATUS(val)     bfin_write16(PPI_STATUS, val)
-#define bfin_read_PPI_COUNT()          bfin_read16(PPI_COUNT)
-#define bfin_write_PPI_COUNT(val)      bfin_write16(PPI_COUNT, val)
-#define bfin_read_PPI_DELAY()          bfin_read16(PPI_DELAY)
-#define bfin_write_PPI_DELAY(val)      bfin_write16(PPI_DELAY, val)
-#define bfin_read_PPI_FRAME()          bfin_read16(PPI_FRAME)
-#define bfin_write_PPI_FRAME(val)      bfin_write16(PPI_FRAME, val)
-#define bfin_read_TWI_CLKDIV()         bfin_read16(TWI_CLKDIV)
-#define bfin_write_TWI_CLKDIV(val)     bfin_write16(TWI_CLKDIV, val)
-#define bfin_read_TWI_CONTROL()        bfin_read16(TWI_CONTROL)
-#define bfin_write_TWI_CONTROL(val)    bfin_write16(TWI_CONTROL, val)
-#define bfin_read_TWI_SLAVE_CTL()      bfin_read16(TWI_SLAVE_CTL)
-#define bfin_write_TWI_SLAVE_CTL(val)  bfin_write16(TWI_SLAVE_CTL, val)
-#define bfin_read_TWI_SLAVE_STAT()     bfin_read16(TWI_SLAVE_STAT)
-#define bfin_write_TWI_SLAVE_STAT(val) bfin_write16(TWI_SLAVE_STAT, val)
-#define bfin_read_TWI_SLAVE_ADDR()     bfin_read16(TWI_SLAVE_ADDR)
-#define bfin_write_TWI_SLAVE_ADDR(val) bfin_write16(TWI_SLAVE_ADDR, val)
-#define bfin_read_TWI_MASTER_CTL()     bfin_read16(TWI_MASTER_CTL)
-#define bfin_write_TWI_MASTER_CTL(val) bfin_write16(TWI_MASTER_CTL, val)
-#define bfin_read_TWI_MASTER_STAT()    bfin_read16(TWI_MASTER_STAT)
-#define bfin_write_TWI_MASTER_STAT(val) bfin_write16(TWI_MASTER_STAT, val)
-#define bfin_read_TWI_MASTER_ADDR()    bfin_read16(TWI_MASTER_ADDR)
-#define bfin_write_TWI_MASTER_ADDR(val) bfin_write16(TWI_MASTER_ADDR, val)
-#define bfin_read_TWI_INT_STAT()       bfin_read16(TWI_INT_STAT)
-#define bfin_write_TWI_INT_STAT(val)   bfin_write16(TWI_INT_STAT, val)
-#define bfin_read_TWI_INT_MASK()       bfin_read16(TWI_INT_MASK)
-#define bfin_write_TWI_INT_MASK(val)   bfin_write16(TWI_INT_MASK, val)
-#define bfin_read_TWI_FIFO_CTL()       bfin_read16(TWI_FIFO_CTL)
-#define bfin_write_TWI_FIFO_CTL(val)   bfin_write16(TWI_FIFO_CTL, val)
-#define bfin_read_TWI_FIFO_STAT()      bfin_read16(TWI_FIFO_STAT)
-#define bfin_write_TWI_FIFO_STAT(val)  bfin_write16(TWI_FIFO_STAT, val)
-#define bfin_read_TWI_XMT_DATA8()      bfin_read16(TWI_XMT_DATA8)
-#define bfin_write_TWI_XMT_DATA8(val)  bfin_write16(TWI_XMT_DATA8, val)
-#define bfin_read_TWI_XMT_DATA16()     bfin_read16(TWI_XMT_DATA16)
-#define bfin_write_TWI_XMT_DATA16(val) bfin_write16(TWI_XMT_DATA16, val)
-#define bfin_read_TWI_RCV_DATA8()      bfin_read16(TWI_RCV_DATA8)
-#define bfin_write_TWI_RCV_DATA8(val)  bfin_write16(TWI_RCV_DATA8, val)
-#define bfin_read_TWI_RCV_DATA16()     bfin_read16(TWI_RCV_DATA16)
-#define bfin_write_TWI_RCV_DATA16(val) bfin_write16(TWI_RCV_DATA16, val)
-#define bfin_read_PORTGIO()            bfin_read16(PORTGIO)
-#define bfin_write_PORTGIO(val)        bfin_write16(PORTGIO, val)
-#define bfin_read_PORTGIO_CLEAR()      bfin_read16(PORTGIO_CLEAR)
-#define bfin_write_PORTGIO_CLEAR(val)  bfin_write16(PORTGIO_CLEAR, val)
-#define bfin_read_PORTGIO_SET()        bfin_read16(PORTGIO_SET)
-#define bfin_write_PORTGIO_SET(val)    bfin_write16(PORTGIO_SET, val)
-#define bfin_read_PORTGIO_TOGGLE()     bfin_read16(PORTGIO_TOGGLE)
-#define bfin_write_PORTGIO_TOGGLE(val) bfin_write16(PORTGIO_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKA()      bfin_read16(PORTGIO_MASKA)
-#define bfin_write_PORTGIO_MASKA(val)  bfin_write16(PORTGIO_MASKA, val)
-#define bfin_read_PORTGIO_MASKA_CLEAR() bfin_read16(PORTGIO_MASKA_CLEAR)
-#define bfin_write_PORTGIO_MASKA_CLEAR(val) bfin_write16(PORTGIO_MASKA_CLEAR, val)
-#define bfin_read_PORTGIO_MASKA_SET()  bfin_read16(PORTGIO_MASKA_SET)
-#define bfin_write_PORTGIO_MASKA_SET(val) bfin_write16(PORTGIO_MASKA_SET, val)
-#define bfin_read_PORTGIO_MASKA_TOGGLE() bfin_read16(PORTGIO_MASKA_TOGGLE)
-#define bfin_write_PORTGIO_MASKA_TOGGLE(val) bfin_write16(PORTGIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTGIO_MASKB()      bfin_read16(PORTGIO_MASKB)
-#define bfin_write_PORTGIO_MASKB(val)  bfin_write16(PORTGIO_MASKB, val)
-#define bfin_read_PORTGIO_MASKB_CLEAR() bfin_read16(PORTGIO_MASKB_CLEAR)
-#define bfin_write_PORTGIO_MASKB_CLEAR(val) bfin_write16(PORTGIO_MASKB_CLEAR, val)
-#define bfin_read_PORTGIO_MASKB_SET()  bfin_read16(PORTGIO_MASKB_SET)
-#define bfin_write_PORTGIO_MASKB_SET(val) bfin_write16(PORTGIO_MASKB_SET, val)
-#define bfin_read_PORTGIO_MASKB_TOGGLE() bfin_read16(PORTGIO_MASKB_TOGGLE)
-#define bfin_write_PORTGIO_MASKB_TOGGLE(val) bfin_write16(PORTGIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTGIO_DIR()        bfin_read16(PORTGIO_DIR)
-#define bfin_write_PORTGIO_DIR(val)    bfin_write16(PORTGIO_DIR, val)
-#define bfin_read_PORTGIO_POLAR()      bfin_read16(PORTGIO_POLAR)
-#define bfin_write_PORTGIO_POLAR(val)  bfin_write16(PORTGIO_POLAR, val)
-#define bfin_read_PORTGIO_EDGE()       bfin_read16(PORTGIO_EDGE)
-#define bfin_write_PORTGIO_EDGE(val)   bfin_write16(PORTGIO_EDGE, val)
-#define bfin_read_PORTGIO_BOTH()       bfin_read16(PORTGIO_BOTH)
-#define bfin_write_PORTGIO_BOTH(val)   bfin_write16(PORTGIO_BOTH, val)
-#define bfin_read_PORTGIO_INEN()       bfin_read16(PORTGIO_INEN)
-#define bfin_write_PORTGIO_INEN(val)   bfin_write16(PORTGIO_INEN, val)
-#define bfin_read_PORTHIO()            bfin_read16(PORTHIO)
-#define bfin_write_PORTHIO(val)        bfin_write16(PORTHIO, val)
-#define bfin_read_PORTHIO_CLEAR()      bfin_read16(PORTHIO_CLEAR)
-#define bfin_write_PORTHIO_CLEAR(val)  bfin_write16(PORTHIO_CLEAR, val)
-#define bfin_read_PORTHIO_SET()        bfin_read16(PORTHIO_SET)
-#define bfin_write_PORTHIO_SET(val)    bfin_write16(PORTHIO_SET, val)
-#define bfin_read_PORTHIO_TOGGLE()     bfin_read16(PORTHIO_TOGGLE)
-#define bfin_write_PORTHIO_TOGGLE(val) bfin_write16(PORTHIO_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKA()      bfin_read16(PORTHIO_MASKA)
-#define bfin_write_PORTHIO_MASKA(val)  bfin_write16(PORTHIO_MASKA, val)
-#define bfin_read_PORTHIO_MASKA_CLEAR() bfin_read16(PORTHIO_MASKA_CLEAR)
-#define bfin_write_PORTHIO_MASKA_CLEAR(val) bfin_write16(PORTHIO_MASKA_CLEAR, val)
-#define bfin_read_PORTHIO_MASKA_SET()  bfin_read16(PORTHIO_MASKA_SET)
-#define bfin_write_PORTHIO_MASKA_SET(val) bfin_write16(PORTHIO_MASKA_SET, val)
-#define bfin_read_PORTHIO_MASKA_TOGGLE() bfin_read16(PORTHIO_MASKA_TOGGLE)
-#define bfin_write_PORTHIO_MASKA_TOGGLE(val) bfin_write16(PORTHIO_MASKA_TOGGLE, val)
-#define bfin_read_PORTHIO_MASKB()      bfin_read16(PORTHIO_MASKB)
-#define bfin_write_PORTHIO_MASKB(val)  bfin_write16(PORTHIO_MASKB, val)
-#define bfin_read_PORTHIO_MASKB_CLEAR() bfin_read16(PORTHIO_MASKB_CLEAR)
-#define bfin_write_PORTHIO_MASKB_CLEAR(val) bfin_write16(PORTHIO_MASKB_CLEAR, val)
-#define bfin_read_PORTHIO_MASKB_SET()  bfin_read16(PORTHIO_MASKB_SET)
-#define bfin_write_PORTHIO_MASKB_SET(val) bfin_write16(PORTHIO_MASKB_SET, val)
-#define bfin_read_PORTHIO_MASKB_TOGGLE() bfin_read16(PORTHIO_MASKB_TOGGLE)
-#define bfin_write_PORTHIO_MASKB_TOGGLE(val) bfin_write16(PORTHIO_MASKB_TOGGLE, val)
-#define bfin_read_PORTHIO_DIR()        bfin_read16(PORTHIO_DIR)
-#define bfin_write_PORTHIO_DIR(val)    bfin_write16(PORTHIO_DIR, val)
-#define bfin_read_PORTHIO_POLAR()      bfin_read16(PORTHIO_POLAR)
-#define bfin_write_PORTHIO_POLAR(val)  bfin_write16(PORTHIO_POLAR, val)
-#define bfin_read_PORTHIO_EDGE()       bfin_read16(PORTHIO_EDGE)
-#define bfin_write_PORTHIO_EDGE(val)   bfin_write16(PORTHIO_EDGE, val)
-#define bfin_read_PORTHIO_BOTH()       bfin_read16(PORTHIO_BOTH)
-#define bfin_write_PORTHIO_BOTH(val)   bfin_write16(PORTHIO_BOTH, val)
-#define bfin_read_PORTHIO_INEN()       bfin_read16(PORTHIO_INEN)
-#define bfin_write_PORTHIO_INEN(val)   bfin_write16(PORTHIO_INEN, val)
-#define bfin_read_UART1_THR()          bfin_read16(UART1_THR)
-#define bfin_write_UART1_THR(val)      bfin_write16(UART1_THR, val)
-#define bfin_read_UART1_RBR()          bfin_read16(UART1_RBR)
-#define bfin_write_UART1_RBR(val)      bfin_write16(UART1_RBR, val)
-#define bfin_read_UART1_DLL()          bfin_read16(UART1_DLL)
-#define bfin_write_UART1_DLL(val)      bfin_write16(UART1_DLL, val)
-#define bfin_read_UART1_IER()          bfin_read16(UART1_IER)
-#define bfin_write_UART1_IER(val)      bfin_write16(UART1_IER, val)
-#define bfin_read_UART1_DLH()          bfin_read16(UART1_DLH)
-#define bfin_write_UART1_DLH(val)      bfin_write16(UART1_DLH, val)
-#define bfin_read_UART1_IIR()          bfin_read16(UART1_IIR)
-#define bfin_write_UART1_IIR(val)      bfin_write16(UART1_IIR, val)
-#define bfin_read_UART1_LCR()          bfin_read16(UART1_LCR)
-#define bfin_write_UART1_LCR(val)      bfin_write16(UART1_LCR, val)
-#define bfin_read_UART1_MCR()          bfin_read16(UART1_MCR)
-#define bfin_write_UART1_MCR(val)      bfin_write16(UART1_MCR, val)
-#define bfin_read_UART1_LSR()          bfin_read16(UART1_LSR)
-#define bfin_write_UART1_LSR(val)      bfin_write16(UART1_LSR, val)
-#define bfin_read_UART1_MSR()          bfin_read16(UART1_MSR)
-#define bfin_write_UART1_MSR(val)      bfin_write16(UART1_MSR, val)
-#define bfin_read_UART1_SCR()          bfin_read16(UART1_SCR)
-#define bfin_write_UART1_SCR(val)      bfin_write16(UART1_SCR, val)
-#define bfin_read_UART1_GCTL()         bfin_read16(UART1_GCTL)
-#define bfin_write_UART1_GCTL(val)     bfin_write16(UART1_GCTL, val)
-#define bfin_read_CAN_MC1()            bfin_read16(CAN_MC1)
-#define bfin_write_CAN_MC1(val)        bfin_write16(CAN_MC1, val)
-#define bfin_read_CAN_MD1()            bfin_read16(CAN_MD1)
-#define bfin_write_CAN_MD1(val)        bfin_write16(CAN_MD1, val)
-#define bfin_read_CAN_TRS1()           bfin_read16(CAN_TRS1)
-#define bfin_write_CAN_TRS1(val)       bfin_write16(CAN_TRS1, val)
-#define bfin_read_CAN_TRR1()           bfin_read16(CAN_TRR1)
-#define bfin_write_CAN_TRR1(val)       bfin_write16(CAN_TRR1, val)
-#define bfin_read_CAN_TA1()            bfin_read16(CAN_TA1)
-#define bfin_write_CAN_TA1(val)        bfin_write16(CAN_TA1, val)
-#define bfin_read_CAN_AA1()            bfin_read16(CAN_AA1)
-#define bfin_write_CAN_AA1(val)        bfin_write16(CAN_AA1, val)
-#define bfin_read_CAN_RMP1()           bfin_read16(CAN_RMP1)
-#define bfin_write_CAN_RMP1(val)       bfin_write16(CAN_RMP1, val)
-#define bfin_read_CAN_RML1()           bfin_read16(CAN_RML1)
-#define bfin_write_CAN_RML1(val)       bfin_write16(CAN_RML1, val)
-#define bfin_read_CAN_MBTIF1()         bfin_read16(CAN_MBTIF1)
-#define bfin_write_CAN_MBTIF1(val)     bfin_write16(CAN_MBTIF1, val)
-#define bfin_read_CAN_MBRIF1()         bfin_read16(CAN_MBRIF1)
-#define bfin_write_CAN_MBRIF1(val)     bfin_write16(CAN_MBRIF1, val)
-#define bfin_read_CAN_MBIM1()          bfin_read16(CAN_MBIM1)
-#define bfin_write_CAN_MBIM1(val)      bfin_write16(CAN_MBIM1, val)
-#define bfin_read_CAN_RFH1()           bfin_read16(CAN_RFH1)
-#define bfin_write_CAN_RFH1(val)       bfin_write16(CAN_RFH1, val)
-#define bfin_read_CAN_OPSS1()          bfin_read16(CAN_OPSS1)
-#define bfin_write_CAN_OPSS1(val)      bfin_write16(CAN_OPSS1, val)
-#define bfin_read_CAN_MC2()            bfin_read16(CAN_MC2)
-#define bfin_write_CAN_MC2(val)        bfin_write16(CAN_MC2, val)
-#define bfin_read_CAN_MD2()            bfin_read16(CAN_MD2)
-#define bfin_write_CAN_MD2(val)        bfin_write16(CAN_MD2, val)
-#define bfin_read_CAN_TRS2()           bfin_read16(CAN_TRS2)
-#define bfin_write_CAN_TRS2(val)       bfin_write16(CAN_TRS2, val)
-#define bfin_read_CAN_TRR2()           bfin_read16(CAN_TRR2)
-#define bfin_write_CAN_TRR2(val)       bfin_write16(CAN_TRR2, val)
-#define bfin_read_CAN_TA2()            bfin_read16(CAN_TA2)
-#define bfin_write_CAN_TA2(val)        bfin_write16(CAN_TA2, val)
-#define bfin_read_CAN_AA2()            bfin_read16(CAN_AA2)
-#define bfin_write_CAN_AA2(val)        bfin_write16(CAN_AA2, val)
-#define bfin_read_CAN_RMP2()           bfin_read16(CAN_RMP2)
-#define bfin_write_CAN_RMP2(val)       bfin_write16(CAN_RMP2, val)
-#define bfin_read_CAN_RML2()           bfin_read16(CAN_RML2)
-#define bfin_write_CAN_RML2(val)       bfin_write16(CAN_RML2, val)
-#define bfin_read_CAN_MBTIF2()         bfin_read16(CAN_MBTIF2)
-#define bfin_write_CAN_MBTIF2(val)     bfin_write16(CAN_MBTIF2, val)
-#define bfin_read_CAN_MBRIF2()         bfin_read16(CAN_MBRIF2)
-#define bfin_write_CAN_MBRIF2(val)     bfin_write16(CAN_MBRIF2, val)
-#define bfin_read_CAN_MBIM2()          bfin_read16(CAN_MBIM2)
-#define bfin_write_CAN_MBIM2(val)      bfin_write16(CAN_MBIM2, val)
-#define bfin_read_CAN_RFH2()           bfin_read16(CAN_RFH2)
-#define bfin_write_CAN_RFH2(val)       bfin_write16(CAN_RFH2, val)
-#define bfin_read_CAN_OPSS2()          bfin_read16(CAN_OPSS2)
-#define bfin_write_CAN_OPSS2(val)      bfin_write16(CAN_OPSS2, val)
-#define bfin_read_CAN_CLOCK()          bfin_read16(CAN_CLOCK)
-#define bfin_write_CAN_CLOCK(val)      bfin_write16(CAN_CLOCK, val)
-#define bfin_read_CAN_TIMING()         bfin_read16(CAN_TIMING)
-#define bfin_write_CAN_TIMING(val)     bfin_write16(CAN_TIMING, val)
-#define bfin_read_CAN_DEBUG()          bfin_read16(CAN_DEBUG)
-#define bfin_write_CAN_DEBUG(val)      bfin_write16(CAN_DEBUG, val)
-#define bfin_read_CAN_STATUS()         bfin_read16(CAN_STATUS)
-#define bfin_write_CAN_STATUS(val)     bfin_write16(CAN_STATUS, val)
-#define bfin_read_CAN_CEC()            bfin_read16(CAN_CEC)
-#define bfin_write_CAN_CEC(val)        bfin_write16(CAN_CEC, val)
-#define bfin_read_CAN_GIS()            bfin_read16(CAN_GIS)
-#define bfin_write_CAN_GIS(val)        bfin_write16(CAN_GIS, val)
-#define bfin_read_CAN_GIM()            bfin_read16(CAN_GIM)
-#define bfin_write_CAN_GIM(val)        bfin_write16(CAN_GIM, val)
-#define bfin_read_CAN_GIF()            bfin_read16(CAN_GIF)
-#define bfin_write_CAN_GIF(val)        bfin_write16(CAN_GIF, val)
-#define bfin_read_CAN_CONTROL()        bfin_read16(CAN_CONTROL)
-#define bfin_write_CAN_CONTROL(val)    bfin_write16(CAN_CONTROL, val)
-#define bfin_read_CAN_INTR()           bfin_read16(CAN_INTR)
-#define bfin_write_CAN_INTR(val)       bfin_write16(CAN_INTR, val)
-#define bfin_read_CAN_VERSION()        bfin_read16(CAN_VERSION)
-#define bfin_write_CAN_VERSION(val)    bfin_write16(CAN_VERSION, val)
-#define bfin_read_CAN_MBTD()           bfin_read16(CAN_MBTD)
-#define bfin_write_CAN_MBTD(val)       bfin_write16(CAN_MBTD, val)
-#define bfin_read_CAN_EWR()            bfin_read16(CAN_EWR)
-#define bfin_write_CAN_EWR(val)        bfin_write16(CAN_EWR, val)
-#define bfin_read_CAN_ESR()            bfin_read16(CAN_ESR)
-#define bfin_write_CAN_ESR(val)        bfin_write16(CAN_ESR, val)
-#define bfin_read_CAN_UCREG()          bfin_read16(CAN_UCREG)
-#define bfin_write_CAN_UCREG(val)      bfin_write16(CAN_UCREG, val)
-#define bfin_read_CAN_UCCNT()          bfin_read16(CAN_UCCNT)
-#define bfin_write_CAN_UCCNT(val)      bfin_write16(CAN_UCCNT, val)
-#define bfin_read_CAN_UCRC()           bfin_read16(CAN_UCRC)
-#define bfin_write_CAN_UCRC(val)       bfin_write16(CAN_UCRC, val)
-#define bfin_read_CAN_UCCNF()          bfin_read16(CAN_UCCNF)
-#define bfin_write_CAN_UCCNF(val)      bfin_write16(CAN_UCCNF, val)
-#define bfin_read_CAN_VERSION2()       bfin_read16(CAN_VERSION2)
-#define bfin_write_CAN_VERSION2(val)   bfin_write16(CAN_VERSION2, val)
-#define bfin_read_CAN_AM00L()          bfin_read16(CAN_AM00L)
-#define bfin_write_CAN_AM00L(val)      bfin_write16(CAN_AM00L, val)
-#define bfin_read_CAN_AM00H()          bfin_read16(CAN_AM00H)
-#define bfin_write_CAN_AM00H(val)      bfin_write16(CAN_AM00H, val)
-#define bfin_read_CAN_AM01L()          bfin_read16(CAN_AM01L)
-#define bfin_write_CAN_AM01L(val)      bfin_write16(CAN_AM01L, val)
-#define bfin_read_CAN_AM01H()          bfin_read16(CAN_AM01H)
-#define bfin_write_CAN_AM01H(val)      bfin_write16(CAN_AM01H, val)
-#define bfin_read_CAN_AM02L()          bfin_read16(CAN_AM02L)
-#define bfin_write_CAN_AM02L(val)      bfin_write16(CAN_AM02L, val)
-#define bfin_read_CAN_AM02H()          bfin_read16(CAN_AM02H)
-#define bfin_write_CAN_AM02H(val)      bfin_write16(CAN_AM02H, val)
-#define bfin_read_CAN_AM03L()          bfin_read16(CAN_AM03L)
-#define bfin_write_CAN_AM03L(val)      bfin_write16(CAN_AM03L, val)
-#define bfin_read_CAN_AM03H()          bfin_read16(CAN_AM03H)
-#define bfin_write_CAN_AM03H(val)      bfin_write16(CAN_AM03H, val)
-#define bfin_read_CAN_AM04L()          bfin_read16(CAN_AM04L)
-#define bfin_write_CAN_AM04L(val)      bfin_write16(CAN_AM04L, val)
-#define bfin_read_CAN_AM04H()          bfin_read16(CAN_AM04H)
-#define bfin_write_CAN_AM04H(val)      bfin_write16(CAN_AM04H, val)
-#define bfin_read_CAN_AM05L()          bfin_read16(CAN_AM05L)
-#define bfin_write_CAN_AM05L(val)      bfin_write16(CAN_AM05L, val)
-#define bfin_read_CAN_AM05H()          bfin_read16(CAN_AM05H)
-#define bfin_write_CAN_AM05H(val)      bfin_write16(CAN_AM05H, val)
-#define bfin_read_CAN_AM06L()          bfin_read16(CAN_AM06L)
-#define bfin_write_CAN_AM06L(val)      bfin_write16(CAN_AM06L, val)
-#define bfin_read_CAN_AM06H()          bfin_read16(CAN_AM06H)
-#define bfin_write_CAN_AM06H(val)      bfin_write16(CAN_AM06H, val)
-#define bfin_read_CAN_AM07L()          bfin_read16(CAN_AM07L)
-#define bfin_write_CAN_AM07L(val)      bfin_write16(CAN_AM07L, val)
-#define bfin_read_CAN_AM07H()          bfin_read16(CAN_AM07H)
-#define bfin_write_CAN_AM07H(val)      bfin_write16(CAN_AM07H, val)
-#define bfin_read_CAN_AM08L()          bfin_read16(CAN_AM08L)
-#define bfin_write_CAN_AM08L(val)      bfin_write16(CAN_AM08L, val)
-#define bfin_read_CAN_AM08H()          bfin_read16(CAN_AM08H)
-#define bfin_write_CAN_AM08H(val)      bfin_write16(CAN_AM08H, val)
-#define bfin_read_CAN_AM09L()          bfin_read16(CAN_AM09L)
-#define bfin_write_CAN_AM09L(val)      bfin_write16(CAN_AM09L, val)
-#define bfin_read_CAN_AM09H()          bfin_read16(CAN_AM09H)
-#define bfin_write_CAN_AM09H(val)      bfin_write16(CAN_AM09H, val)
-#define bfin_read_CAN_AM10L()          bfin_read16(CAN_AM10L)
-#define bfin_write_CAN_AM10L(val)      bfin_write16(CAN_AM10L, val)
-#define bfin_read_CAN_AM10H()          bfin_read16(CAN_AM10H)
-#define bfin_write_CAN_AM10H(val)      bfin_write16(CAN_AM10H, val)
-#define bfin_read_CAN_AM11L()          bfin_read16(CAN_AM11L)
-#define bfin_write_CAN_AM11L(val)      bfin_write16(CAN_AM11L, val)
-#define bfin_read_CAN_AM11H()          bfin_read16(CAN_AM11H)
-#define bfin_write_CAN_AM11H(val)      bfin_write16(CAN_AM11H, val)
-#define bfin_read_CAN_AM12L()          bfin_read16(CAN_AM12L)
-#define bfin_write_CAN_AM12L(val)      bfin_write16(CAN_AM12L, val)
-#define bfin_read_CAN_AM12H()          bfin_read16(CAN_AM12H)
-#define bfin_write_CAN_AM12H(val)      bfin_write16(CAN_AM12H, val)
-#define bfin_read_CAN_AM13L()          bfin_read16(CAN_AM13L)
-#define bfin_write_CAN_AM13L(val)      bfin_write16(CAN_AM13L, val)
-#define bfin_read_CAN_AM13H()          bfin_read16(CAN_AM13H)
-#define bfin_write_CAN_AM13H(val)      bfin_write16(CAN_AM13H, val)
-#define bfin_read_CAN_AM14L()          bfin_read16(CAN_AM14L)
-#define bfin_write_CAN_AM14L(val)      bfin_write16(CAN_AM14L, val)
-#define bfin_read_CAN_AM14H()          bfin_read16(CAN_AM14H)
-#define bfin_write_CAN_AM14H(val)      bfin_write16(CAN_AM14H, val)
-#define bfin_read_CAN_AM15L()          bfin_read16(CAN_AM15L)
-#define bfin_write_CAN_AM15L(val)      bfin_write16(CAN_AM15L, val)
-#define bfin_read_CAN_AM15H()          bfin_read16(CAN_AM15H)
-#define bfin_write_CAN_AM15H(val)      bfin_write16(CAN_AM15H, val)
-#define bfin_read_CAN_AM16L()          bfin_read16(CAN_AM16L)
-#define bfin_write_CAN_AM16L(val)      bfin_write16(CAN_AM16L, val)
-#define bfin_read_CAN_AM16H()          bfin_read16(CAN_AM16H)
-#define bfin_write_CAN_AM16H(val)      bfin_write16(CAN_AM16H, val)
-#define bfin_read_CAN_AM17L()          bfin_read16(CAN_AM17L)
-#define bfin_write_CAN_AM17L(val)      bfin_write16(CAN_AM17L, val)
-#define bfin_read_CAN_AM17H()          bfin_read16(CAN_AM17H)
-#define bfin_write_CAN_AM17H(val)      bfin_write16(CAN_AM17H, val)
-#define bfin_read_CAN_AM18L()          bfin_read16(CAN_AM18L)
-#define bfin_write_CAN_AM18L(val)      bfin_write16(CAN_AM18L, val)
-#define bfin_read_CAN_AM18H()          bfin_read16(CAN_AM18H)
-#define bfin_write_CAN_AM18H(val)      bfin_write16(CAN_AM18H, val)
-#define bfin_read_CAN_AM19L()          bfin_read16(CAN_AM19L)
-#define bfin_write_CAN_AM19L(val)      bfin_write16(CAN_AM19L, val)
-#define bfin_read_CAN_AM19H()          bfin_read16(CAN_AM19H)
-#define bfin_write_CAN_AM19H(val)      bfin_write16(CAN_AM19H, val)
-#define bfin_read_CAN_AM20L()          bfin_read16(CAN_AM20L)
-#define bfin_write_CAN_AM20L(val)      bfin_write16(CAN_AM20L, val)
-#define bfin_read_CAN_AM20H()          bfin_read16(CAN_AM20H)
-#define bfin_write_CAN_AM20H(val)      bfin_write16(CAN_AM20H, val)
-#define bfin_read_CAN_AM21L()          bfin_read16(CAN_AM21L)
-#define bfin_write_CAN_AM21L(val)      bfin_write16(CAN_AM21L, val)
-#define bfin_read_CAN_AM21H()          bfin_read16(CAN_AM21H)
-#define bfin_write_CAN_AM21H(val)      bfin_write16(CAN_AM21H, val)
-#define bfin_read_CAN_AM22L()          bfin_read16(CAN_AM22L)
-#define bfin_write_CAN_AM22L(val)      bfin_write16(CAN_AM22L, val)
-#define bfin_read_CAN_AM22H()          bfin_read16(CAN_AM22H)
-#define bfin_write_CAN_AM22H(val)      bfin_write16(CAN_AM22H, val)
-#define bfin_read_CAN_AM23L()          bfin_read16(CAN_AM23L)
-#define bfin_write_CAN_AM23L(val)      bfin_write16(CAN_AM23L, val)
-#define bfin_read_CAN_AM23H()          bfin_read16(CAN_AM23H)
-#define bfin_write_CAN_AM23H(val)      bfin_write16(CAN_AM23H, val)
-#define bfin_read_CAN_AM24L()          bfin_read16(CAN_AM24L)
-#define bfin_write_CAN_AM24L(val)      bfin_write16(CAN_AM24L, val)
-#define bfin_read_CAN_AM24H()          bfin_read16(CAN_AM24H)
-#define bfin_write_CAN_AM24H(val)      bfin_write16(CAN_AM24H, val)
-#define bfin_read_CAN_AM25L()          bfin_read16(CAN_AM25L)
-#define bfin_write_CAN_AM25L(val)      bfin_write16(CAN_AM25L, val)
-#define bfin_read_CAN_AM25H()          bfin_read16(CAN_AM25H)
-#define bfin_write_CAN_AM25H(val)      bfin_write16(CAN_AM25H, val)
-#define bfin_read_CAN_AM26L()          bfin_read16(CAN_AM26L)
-#define bfin_write_CAN_AM26L(val)      bfin_write16(CAN_AM26L, val)
-#define bfin_read_CAN_AM26H()          bfin_read16(CAN_AM26H)
-#define bfin_write_CAN_AM26H(val)      bfin_write16(CAN_AM26H, val)
-#define bfin_read_CAN_AM27L()          bfin_read16(CAN_AM27L)
-#define bfin_write_CAN_AM27L(val)      bfin_write16(CAN_AM27L, val)
-#define bfin_read_CAN_AM27H()          bfin_read16(CAN_AM27H)
-#define bfin_write_CAN_AM27H(val)      bfin_write16(CAN_AM27H, val)
-#define bfin_read_CAN_AM28L()          bfin_read16(CAN_AM28L)
-#define bfin_write_CAN_AM28L(val)      bfin_write16(CAN_AM28L, val)
-#define bfin_read_CAN_AM28H()          bfin_read16(CAN_AM28H)
-#define bfin_write_CAN_AM28H(val)      bfin_write16(CAN_AM28H, val)
-#define bfin_read_CAN_AM29L()          bfin_read16(CAN_AM29L)
-#define bfin_write_CAN_AM29L(val)      bfin_write16(CAN_AM29L, val)
-#define bfin_read_CAN_AM29H()          bfin_read16(CAN_AM29H)
-#define bfin_write_CAN_AM29H(val)      bfin_write16(CAN_AM29H, val)
-#define bfin_read_CAN_AM30L()          bfin_read16(CAN_AM30L)
-#define bfin_write_CAN_AM30L(val)      bfin_write16(CAN_AM30L, val)
-#define bfin_read_CAN_AM30H()          bfin_read16(CAN_AM30H)
-#define bfin_write_CAN_AM30H(val)      bfin_write16(CAN_AM30H, val)
-#define bfin_read_CAN_AM31L()          bfin_read16(CAN_AM31L)
-#define bfin_write_CAN_AM31L(val)      bfin_write16(CAN_AM31L, val)
-#define bfin_read_CAN_AM31H()          bfin_read16(CAN_AM31H)
-#define bfin_write_CAN_AM31H(val)      bfin_write16(CAN_AM31H, val)
-#define bfin_read_CAN_MB00_DATA0()     bfin_read16(CAN_MB00_DATA0)
-#define bfin_write_CAN_MB00_DATA0(val) bfin_write16(CAN_MB00_DATA0, val)
-#define bfin_read_CAN_MB00_DATA1()     bfin_read16(CAN_MB00_DATA1)
-#define bfin_write_CAN_MB00_DATA1(val) bfin_write16(CAN_MB00_DATA1, val)
-#define bfin_read_CAN_MB00_DATA2()     bfin_read16(CAN_MB00_DATA2)
-#define bfin_write_CAN_MB00_DATA2(val) bfin_write16(CAN_MB00_DATA2, val)
-#define bfin_read_CAN_MB00_DATA3()     bfin_read16(CAN_MB00_DATA3)
-#define bfin_write_CAN_MB00_DATA3(val) bfin_write16(CAN_MB00_DATA3, val)
-#define bfin_read_CAN_MB00_LENGTH()    bfin_read16(CAN_MB00_LENGTH)
-#define bfin_write_CAN_MB00_LENGTH(val) bfin_write16(CAN_MB00_LENGTH, val)
-#define bfin_read_CAN_MB00_TIMESTAMP() bfin_read16(CAN_MB00_TIMESTAMP)
-#define bfin_write_CAN_MB00_TIMESTAMP(val) bfin_write16(CAN_MB00_TIMESTAMP, val)
-#define bfin_read_CAN_MB00_ID0()       bfin_read16(CAN_MB00_ID0)
-#define bfin_write_CAN_MB00_ID0(val)   bfin_write16(CAN_MB00_ID0, val)
-#define bfin_read_CAN_MB00_ID1()       bfin_read16(CAN_MB00_ID1)
-#define bfin_write_CAN_MB00_ID1(val)   bfin_write16(CAN_MB00_ID1, val)
-#define bfin_read_CAN_MB01_DATA0()     bfin_read16(CAN_MB01_DATA0)
-#define bfin_write_CAN_MB01_DATA0(val) bfin_write16(CAN_MB01_DATA0, val)
-#define bfin_read_CAN_MB01_DATA1()     bfin_read16(CAN_MB01_DATA1)
-#define bfin_write_CAN_MB01_DATA1(val) bfin_write16(CAN_MB01_DATA1, val)
-#define bfin_read_CAN_MB01_DATA2()     bfin_read16(CAN_MB01_DATA2)
-#define bfin_write_CAN_MB01_DATA2(val) bfin_write16(CAN_MB01_DATA2, val)
-#define bfin_read_CAN_MB01_DATA3()     bfin_read16(CAN_MB01_DATA3)
-#define bfin_write_CAN_MB01_DATA3(val) bfin_write16(CAN_MB01_DATA3, val)
-#define bfin_read_CAN_MB01_LENGTH()    bfin_read16(CAN_MB01_LENGTH)
-#define bfin_write_CAN_MB01_LENGTH(val) bfin_write16(CAN_MB01_LENGTH, val)
-#define bfin_read_CAN_MB01_TIMESTAMP() bfin_read16(CAN_MB01_TIMESTAMP)
-#define bfin_write_CAN_MB01_TIMESTAMP(val) bfin_write16(CAN_MB01_TIMESTAMP, val)
-#define bfin_read_CAN_MB01_ID0()       bfin_read16(CAN_MB01_ID0)
-#define bfin_write_CAN_MB01_ID0(val)   bfin_write16(CAN_MB01_ID0, val)
-#define bfin_read_CAN_MB01_ID1()       bfin_read16(CAN_MB01_ID1)
-#define bfin_write_CAN_MB01_ID1(val)   bfin_write16(CAN_MB01_ID1, val)
-#define bfin_read_CAN_MB02_DATA0()     bfin_read16(CAN_MB02_DATA0)
-#define bfin_write_CAN_MB02_DATA0(val) bfin_write16(CAN_MB02_DATA0, val)
-#define bfin_read_CAN_MB02_DATA1()     bfin_read16(CAN_MB02_DATA1)
-#define bfin_write_CAN_MB02_DATA1(val) bfin_write16(CAN_MB02_DATA1, val)
-#define bfin_read_CAN_MB02_DATA2()     bfin_read16(CAN_MB02_DATA2)
-#define bfin_write_CAN_MB02_DATA2(val) bfin_write16(CAN_MB02_DATA2, val)
-#define bfin_read_CAN_MB02_DATA3()     bfin_read16(CAN_MB02_DATA3)
-#define bfin_write_CAN_MB02_DATA3(val) bfin_write16(CAN_MB02_DATA3, val)
-#define bfin_read_CAN_MB02_LENGTH()    bfin_read16(CAN_MB02_LENGTH)
-#define bfin_write_CAN_MB02_LENGTH(val) bfin_write16(CAN_MB02_LENGTH, val)
-#define bfin_read_CAN_MB02_TIMESTAMP() bfin_read16(CAN_MB02_TIMESTAMP)
-#define bfin_write_CAN_MB02_TIMESTAMP(val) bfin_write16(CAN_MB02_TIMESTAMP, val)
-#define bfin_read_CAN_MB02_ID0()       bfin_read16(CAN_MB02_ID0)
-#define bfin_write_CAN_MB02_ID0(val)   bfin_write16(CAN_MB02_ID0, val)
-#define bfin_read_CAN_MB02_ID1()       bfin_read16(CAN_MB02_ID1)
-#define bfin_write_CAN_MB02_ID1(val)   bfin_write16(CAN_MB02_ID1, val)
-#define bfin_read_CAN_MB03_DATA0()     bfin_read16(CAN_MB03_DATA0)
-#define bfin_write_CAN_MB03_DATA0(val) bfin_write16(CAN_MB03_DATA0, val)
-#define bfin_read_CAN_MB03_DATA1()     bfin_read16(CAN_MB03_DATA1)
-#define bfin_write_CAN_MB03_DATA1(val) bfin_write16(CAN_MB03_DATA1, val)
-#define bfin_read_CAN_MB03_DATA2()     bfin_read16(CAN_MB03_DATA2)
-#define bfin_write_CAN_MB03_DATA2(val) bfin_write16(CAN_MB03_DATA2, val)
-#define bfin_read_CAN_MB03_DATA3()     bfin_read16(CAN_MB03_DATA3)
-#define bfin_write_CAN_MB03_DATA3(val) bfin_write16(CAN_MB03_DATA3, val)
-#define bfin_read_CAN_MB03_LENGTH()    bfin_read16(CAN_MB03_LENGTH)
-#define bfin_write_CAN_MB03_LENGTH(val) bfin_write16(CAN_MB03_LENGTH, val)
-#define bfin_read_CAN_MB03_TIMESTAMP() bfin_read16(CAN_MB03_TIMESTAMP)
-#define bfin_write_CAN_MB03_TIMESTAMP(val) bfin_write16(CAN_MB03_TIMESTAMP, val)
-#define bfin_read_CAN_MB03_ID0()       bfin_read16(CAN_MB03_ID0)
-#define bfin_write_CAN_MB03_ID0(val)   bfin_write16(CAN_MB03_ID0, val)
-#define bfin_read_CAN_MB03_ID1()       bfin_read16(CAN_MB03_ID1)
-#define bfin_write_CAN_MB03_ID1(val)   bfin_write16(CAN_MB03_ID1, val)
-#define bfin_read_CAN_MB04_DATA0()     bfin_read16(CAN_MB04_DATA0)
-#define bfin_write_CAN_MB04_DATA0(val) bfin_write16(CAN_MB04_DATA0, val)
-#define bfin_read_CAN_MB04_DATA1()     bfin_read16(CAN_MB04_DATA1)
-#define bfin_write_CAN_MB04_DATA1(val) bfin_write16(CAN_MB04_DATA1, val)
-#define bfin_read_CAN_MB04_DATA2()     bfin_read16(CAN_MB04_DATA2)
-#define bfin_write_CAN_MB04_DATA2(val) bfin_write16(CAN_MB04_DATA2, val)
-#define bfin_read_CAN_MB04_DATA3()     bfin_read16(CAN_MB04_DATA3)
-#define bfin_write_CAN_MB04_DATA3(val) bfin_write16(CAN_MB04_DATA3, val)
-#define bfin_read_CAN_MB04_LENGTH()    bfin_read16(CAN_MB04_LENGTH)
-#define bfin_write_CAN_MB04_LENGTH(val) bfin_write16(CAN_MB04_LENGTH, val)
-#define bfin_read_CAN_MB04_TIMESTAMP() bfin_read16(CAN_MB04_TIMESTAMP)
-#define bfin_write_CAN_MB04_TIMESTAMP(val) bfin_write16(CAN_MB04_TIMESTAMP, val)
-#define bfin_read_CAN_MB04_ID0()       bfin_read16(CAN_MB04_ID0)
-#define bfin_write_CAN_MB04_ID0(val)   bfin_write16(CAN_MB04_ID0, val)
-#define bfin_read_CAN_MB04_ID1()       bfin_read16(CAN_MB04_ID1)
-#define bfin_write_CAN_MB04_ID1(val)   bfin_write16(CAN_MB04_ID1, val)
-#define bfin_read_CAN_MB05_DATA0()     bfin_read16(CAN_MB05_DATA0)
-#define bfin_write_CAN_MB05_DATA0(val) bfin_write16(CAN_MB05_DATA0, val)
-#define bfin_read_CAN_MB05_DATA1()     bfin_read16(CAN_MB05_DATA1)
-#define bfin_write_CAN_MB05_DATA1(val) bfin_write16(CAN_MB05_DATA1, val)
-#define bfin_read_CAN_MB05_DATA2()     bfin_read16(CAN_MB05_DATA2)
-#define bfin_write_CAN_MB05_DATA2(val) bfin_write16(CAN_MB05_DATA2, val)
-#define bfin_read_CAN_MB05_DATA3()     bfin_read16(CAN_MB05_DATA3)
-#define bfin_write_CAN_MB05_DATA3(val) bfin_write16(CAN_MB05_DATA3, val)
-#define bfin_read_CAN_MB05_LENGTH()    bfin_read16(CAN_MB05_LENGTH)
-#define bfin_write_CAN_MB05_LENGTH(val) bfin_write16(CAN_MB05_LENGTH, val)
-#define bfin_read_CAN_MB05_TIMESTAMP() bfin_read16(CAN_MB05_TIMESTAMP)
-#define bfin_write_CAN_MB05_TIMESTAMP(val) bfin_write16(CAN_MB05_TIMESTAMP, val)
-#define bfin_read_CAN_MB05_ID0()       bfin_read16(CAN_MB05_ID0)
-#define bfin_write_CAN_MB05_ID0(val)   bfin_write16(CAN_MB05_ID0, val)
-#define bfin_read_CAN_MB05_ID1()       bfin_read16(CAN_MB05_ID1)
-#define bfin_write_CAN_MB05_ID1(val)   bfin_write16(CAN_MB05_ID1, val)
-#define bfin_read_CAN_MB06_DATA0()     bfin_read16(CAN_MB06_DATA0)
-#define bfin_write_CAN_MB06_DATA0(val) bfin_write16(CAN_MB06_DATA0, val)
-#define bfin_read_CAN_MB06_DATA1()     bfin_read16(CAN_MB06_DATA1)
-#define bfin_write_CAN_MB06_DATA1(val) bfin_write16(CAN_MB06_DATA1, val)
-#define bfin_read_CAN_MB06_DATA2()     bfin_read16(CAN_MB06_DATA2)
-#define bfin_write_CAN_MB06_DATA2(val) bfin_write16(CAN_MB06_DATA2, val)
-#define bfin_read_CAN_MB06_DATA3()     bfin_read16(CAN_MB06_DATA3)
-#define bfin_write_CAN_MB06_DATA3(val) bfin_write16(CAN_MB06_DATA3, val)
-#define bfin_read_CAN_MB06_LENGTH()    bfin_read16(CAN_MB06_LENGTH)
-#define bfin_write_CAN_MB06_LENGTH(val) bfin_write16(CAN_MB06_LENGTH, val)
-#define bfin_read_CAN_MB06_TIMESTAMP() bfin_read16(CAN_MB06_TIMESTAMP)
-#define bfin_write_CAN_MB06_TIMESTAMP(val) bfin_write16(CAN_MB06_TIMESTAMP, val)
-#define bfin_read_CAN_MB06_ID0()       bfin_read16(CAN_MB06_ID0)
-#define bfin_write_CAN_MB06_ID0(val)   bfin_write16(CAN_MB06_ID0, val)
-#define bfin_read_CAN_MB06_ID1()       bfin_read16(CAN_MB06_ID1)
-#define bfin_write_CAN_MB06_ID1(val)   bfin_write16(CAN_MB06_ID1, val)
-#define bfin_read_CAN_MB07_DATA0()     bfin_read16(CAN_MB07_DATA0)
-#define bfin_write_CAN_MB07_DATA0(val) bfin_write16(CAN_MB07_DATA0, val)
-#define bfin_read_CAN_MB07_DATA1()     bfin_read16(CAN_MB07_DATA1)
-#define bfin_write_CAN_MB07_DATA1(val) bfin_write16(CAN_MB07_DATA1, val)
-#define bfin_read_CAN_MB07_DATA2()     bfin_read16(CAN_MB07_DATA2)
-#define bfin_write_CAN_MB07_DATA2(val) bfin_write16(CAN_MB07_DATA2, val)
-#define bfin_read_CAN_MB07_DATA3()     bfin_read16(CAN_MB07_DATA3)
-#define bfin_write_CAN_MB07_DATA3(val) bfin_write16(CAN_MB07_DATA3, val)
-#define bfin_read_CAN_MB07_LENGTH()    bfin_read16(CAN_MB07_LENGTH)
-#define bfin_write_CAN_MB07_LENGTH(val) bfin_write16(CAN_MB07_LENGTH, val)
-#define bfin_read_CAN_MB07_TIMESTAMP() bfin_read16(CAN_MB07_TIMESTAMP)
-#define bfin_write_CAN_MB07_TIMESTAMP(val) bfin_write16(CAN_MB07_TIMESTAMP, val)
-#define bfin_read_CAN_MB07_ID0()       bfin_read16(CAN_MB07_ID0)
-#define bfin_write_CAN_MB07_ID0(val)   bfin_write16(CAN_MB07_ID0, val)
-#define bfin_read_CAN_MB07_ID1()       bfin_read16(CAN_MB07_ID1)
-#define bfin_write_CAN_MB07_ID1(val)   bfin_write16(CAN_MB07_ID1, val)
-#define bfin_read_CAN_MB08_DATA0()     bfin_read16(CAN_MB08_DATA0)
-#define bfin_write_CAN_MB08_DATA0(val) bfin_write16(CAN_MB08_DATA0, val)
-#define bfin_read_CAN_MB08_DATA1()     bfin_read16(CAN_MB08_DATA1)
-#define bfin_write_CAN_MB08_DATA1(val) bfin_write16(CAN_MB08_DATA1, val)
-#define bfin_read_CAN_MB08_DATA2()     bfin_read16(CAN_MB08_DATA2)
-#define bfin_write_CAN_MB08_DATA2(val) bfin_write16(CAN_MB08_DATA2, val)
-#define bfin_read_CAN_MB08_DATA3()     bfin_read16(CAN_MB08_DATA3)
-#define bfin_write_CAN_MB08_DATA3(val) bfin_write16(CAN_MB08_DATA3, val)
-#define bfin_read_CAN_MB08_LENGTH()    bfin_read16(CAN_MB08_LENGTH)
-#define bfin_write_CAN_MB08_LENGTH(val) bfin_write16(CAN_MB08_LENGTH, val)
-#define bfin_read_CAN_MB08_TIMESTAMP() bfin_read16(CAN_MB08_TIMESTAMP)
-#define bfin_write_CAN_MB08_TIMESTAMP(val) bfin_write16(CAN_MB08_TIMESTAMP, val)
-#define bfin_read_CAN_MB08_ID0()       bfin_read16(CAN_MB08_ID0)
-#define bfin_write_CAN_MB08_ID0(val)   bfin_write16(CAN_MB08_ID0, val)
-#define bfin_read_CAN_MB08_ID1()       bfin_read16(CAN_MB08_ID1)
-#define bfin_write_CAN_MB08_ID1(val)   bfin_write16(CAN_MB08_ID1, val)
-#define bfin_read_CAN_MB09_DATA0()     bfin_read16(CAN_MB09_DATA0)
-#define bfin_write_CAN_MB09_DATA0(val) bfin_write16(CAN_MB09_DATA0, val)
-#define bfin_read_CAN_MB09_DATA1()     bfin_read16(CAN_MB09_DATA1)
-#define bfin_write_CAN_MB09_DATA1(val) bfin_write16(CAN_MB09_DATA1, val)
-#define bfin_read_CAN_MB09_DATA2()     bfin_read16(CAN_MB09_DATA2)
-#define bfin_write_CAN_MB09_DATA2(val) bfin_write16(CAN_MB09_DATA2, val)
-#define bfin_read_CAN_MB09_DATA3()     bfin_read16(CAN_MB09_DATA3)
-#define bfin_write_CAN_MB09_DATA3(val) bfin_write16(CAN_MB09_DATA3, val)
-#define bfin_read_CAN_MB09_LENGTH()    bfin_read16(CAN_MB09_LENGTH)
-#define bfin_write_CAN_MB09_LENGTH(val) bfin_write16(CAN_MB09_LENGTH, val)
-#define bfin_read_CAN_MB09_TIMESTAMP() bfin_read16(CAN_MB09_TIMESTAMP)
-#define bfin_write_CAN_MB09_TIMESTAMP(val) bfin_write16(CAN_MB09_TIMESTAMP, val)
-#define bfin_read_CAN_MB09_ID0()       bfin_read16(CAN_MB09_ID0)
-#define bfin_write_CAN_MB09_ID0(val)   bfin_write16(CAN_MB09_ID0, val)
-#define bfin_read_CAN_MB09_ID1()       bfin_read16(CAN_MB09_ID1)
-#define bfin_write_CAN_MB09_ID1(val)   bfin_write16(CAN_MB09_ID1, val)
-#define bfin_read_CAN_MB10_DATA0()     bfin_read16(CAN_MB10_DATA0)
-#define bfin_write_CAN_MB10_DATA0(val) bfin_write16(CAN_MB10_DATA0, val)
-#define bfin_read_CAN_MB10_DATA1()     bfin_read16(CAN_MB10_DATA1)
-#define bfin_write_CAN_MB10_DATA1(val) bfin_write16(CAN_MB10_DATA1, val)
-#define bfin_read_CAN_MB10_DATA2()     bfin_read16(CAN_MB10_DATA2)
-#define bfin_write_CAN_MB10_DATA2(val) bfin_write16(CAN_MB10_DATA2, val)
-#define bfin_read_CAN_MB10_DATA3()     bfin_read16(CAN_MB10_DATA3)
-#define bfin_write_CAN_MB10_DATA3(val) bfin_write16(CAN_MB10_DATA3, val)
-#define bfin_read_CAN_MB10_LENGTH()    bfin_read16(CAN_MB10_LENGTH)
-#define bfin_write_CAN_MB10_LENGTH(val) bfin_write16(CAN_MB10_LENGTH, val)
-#define bfin_read_CAN_MB10_TIMESTAMP() bfin_read16(CAN_MB10_TIMESTAMP)
-#define bfin_write_CAN_MB10_TIMESTAMP(val) bfin_write16(CAN_MB10_TIMESTAMP, val)
-#define bfin_read_CAN_MB10_ID0()       bfin_read16(CAN_MB10_ID0)
-#define bfin_write_CAN_MB10_ID0(val)   bfin_write16(CAN_MB10_ID0, val)
-#define bfin_read_CAN_MB10_ID1()       bfin_read16(CAN_MB10_ID1)
-#define bfin_write_CAN_MB10_ID1(val)   bfin_write16(CAN_MB10_ID1, val)
-#define bfin_read_CAN_MB11_DATA0()     bfin_read16(CAN_MB11_DATA0)
-#define bfin_write_CAN_MB11_DATA0(val) bfin_write16(CAN_MB11_DATA0, val)
-#define bfin_read_CAN_MB11_DATA1()     bfin_read16(CAN_MB11_DATA1)
-#define bfin_write_CAN_MB11_DATA1(val) bfin_write16(CAN_MB11_DATA1, val)
-#define bfin_read_CAN_MB11_DATA2()     bfin_read16(CAN_MB11_DATA2)
-#define bfin_write_CAN_MB11_DATA2(val) bfin_write16(CAN_MB11_DATA2, val)
-#define bfin_read_CAN_MB11_DATA3()     bfin_read16(CAN_MB11_DATA3)
-#define bfin_write_CAN_MB11_DATA3(val) bfin_write16(CAN_MB11_DATA3, val)
-#define bfin_read_CAN_MB11_LENGTH()    bfin_read16(CAN_MB11_LENGTH)
-#define bfin_write_CAN_MB11_LENGTH(val) bfin_write16(CAN_MB11_LENGTH, val)
-#define bfin_read_CAN_MB11_TIMESTAMP() bfin_read16(CAN_MB11_TIMESTAMP)
-#define bfin_write_CAN_MB11_TIMESTAMP(val) bfin_write16(CAN_MB11_TIMESTAMP, val)
-#define bfin_read_CAN_MB11_ID0()       bfin_read16(CAN_MB11_ID0)
-#define bfin_write_CAN_MB11_ID0(val)   bfin_write16(CAN_MB11_ID0, val)
-#define bfin_read_CAN_MB11_ID1()       bfin_read16(CAN_MB11_ID1)
-#define bfin_write_CAN_MB11_ID1(val)   bfin_write16(CAN_MB11_ID1, val)
-#define bfin_read_CAN_MB12_DATA0()     bfin_read16(CAN_MB12_DATA0)
-#define bfin_write_CAN_MB12_DATA0(val) bfin_write16(CAN_MB12_DATA0, val)
-#define bfin_read_CAN_MB12_DATA1()     bfin_read16(CAN_MB12_DATA1)
-#define bfin_write_CAN_MB12_DATA1(val) bfin_write16(CAN_MB12_DATA1, val)
-#define bfin_read_CAN_MB12_DATA2()     bfin_read16(CAN_MB12_DATA2)
-#define bfin_write_CAN_MB12_DATA2(val) bfin_write16(CAN_MB12_DATA2, val)
-#define bfin_read_CAN_MB12_DATA3()     bfin_read16(CAN_MB12_DATA3)
-#define bfin_write_CAN_MB12_DATA3(val) bfin_write16(CAN_MB12_DATA3, val)
-#define bfin_read_CAN_MB12_LENGTH()    bfin_read16(CAN_MB12_LENGTH)
-#define bfin_write_CAN_MB12_LENGTH(val) bfin_write16(CAN_MB12_LENGTH, val)
-#define bfin_read_CAN_MB12_TIMESTAMP() bfin_read16(CAN_MB12_TIMESTAMP)
-#define bfin_write_CAN_MB12_TIMESTAMP(val) bfin_write16(CAN_MB12_TIMESTAMP, val)
-#define bfin_read_CAN_MB12_ID0()       bfin_read16(CAN_MB12_ID0)
-#define bfin_write_CAN_MB12_ID0(val)   bfin_write16(CAN_MB12_ID0, val)
-#define bfin_read_CAN_MB12_ID1()       bfin_read16(CAN_MB12_ID1)
-#define bfin_write_CAN_MB12_ID1(val)   bfin_write16(CAN_MB12_ID1, val)
-#define bfin_read_CAN_MB13_DATA0()     bfin_read16(CAN_MB13_DATA0)
-#define bfin_write_CAN_MB13_DATA0(val) bfin_write16(CAN_MB13_DATA0, val)
-#define bfin_read_CAN_MB13_DATA1()     bfin_read16(CAN_MB13_DATA1)
-#define bfin_write_CAN_MB13_DATA1(val) bfin_write16(CAN_MB13_DATA1, val)
-#define bfin_read_CAN_MB13_DATA2()     bfin_read16(CAN_MB13_DATA2)
-#define bfin_write_CAN_MB13_DATA2(val) bfin_write16(CAN_MB13_DATA2, val)
-#define bfin_read_CAN_MB13_DATA3()     bfin_read16(CAN_MB13_DATA3)
-#define bfin_write_CAN_MB13_DATA3(val) bfin_write16(CAN_MB13_DATA3, val)
-#define bfin_read_CAN_MB13_LENGTH()    bfin_read16(CAN_MB13_LENGTH)
-#define bfin_write_CAN_MB13_LENGTH(val) bfin_write16(CAN_MB13_LENGTH, val)
-#define bfin_read_CAN_MB13_TIMESTAMP() bfin_read16(CAN_MB13_TIMESTAMP)
-#define bfin_write_CAN_MB13_TIMESTAMP(val) bfin_write16(CAN_MB13_TIMESTAMP, val)
-#define bfin_read_CAN_MB13_ID0()       bfin_read16(CAN_MB13_ID0)
-#define bfin_write_CAN_MB13_ID0(val)   bfin_write16(CAN_MB13_ID0, val)
-#define bfin_read_CAN_MB13_ID1()       bfin_read16(CAN_MB13_ID1)
-#define bfin_write_CAN_MB13_ID1(val)   bfin_write16(CAN_MB13_ID1, val)
-#define bfin_read_CAN_MB14_DATA0()     bfin_read16(CAN_MB14_DATA0)
-#define bfin_write_CAN_MB14_DATA0(val) bfin_write16(CAN_MB14_DATA0, val)
-#define bfin_read_CAN_MB14_DATA1()     bfin_read16(CAN_MB14_DATA1)
-#define bfin_write_CAN_MB14_DATA1(val) bfin_write16(CAN_MB14_DATA1, val)
-#define bfin_read_CAN_MB14_DATA2()     bfin_read16(CAN_MB14_DATA2)
-#define bfin_write_CAN_MB14_DATA2(val) bfin_write16(CAN_MB14_DATA2, val)
-#define bfin_read_CAN_MB14_DATA3()     bfin_read16(CAN_MB14_DATA3)
-#define bfin_write_CAN_MB14_DATA3(val) bfin_write16(CAN_MB14_DATA3, val)
-#define bfin_read_CAN_MB14_LENGTH()    bfin_read16(CAN_MB14_LENGTH)
-#define bfin_write_CAN_MB14_LENGTH(val) bfin_write16(CAN_MB14_LENGTH, val)
-#define bfin_read_CAN_MB14_TIMESTAMP() bfin_read16(CAN_MB14_TIMESTAMP)
-#define bfin_write_CAN_MB14_TIMESTAMP(val) bfin_write16(CAN_MB14_TIMESTAMP, val)
-#define bfin_read_CAN_MB14_ID0()       bfin_read16(CAN_MB14_ID0)
-#define bfin_write_CAN_MB14_ID0(val)   bfin_write16(CAN_MB14_ID0, val)
-#define bfin_read_CAN_MB14_ID1()       bfin_read16(CAN_MB14_ID1)
-#define bfin_write_CAN_MB14_ID1(val)   bfin_write16(CAN_MB14_ID1, val)
-#define bfin_read_CAN_MB15_DATA0()     bfin_read16(CAN_MB15_DATA0)
-#define bfin_write_CAN_MB15_DATA0(val) bfin_write16(CAN_MB15_DATA0, val)
-#define bfin_read_CAN_MB15_DATA1()     bfin_read16(CAN_MB15_DATA1)
-#define bfin_write_CAN_MB15_DATA1(val) bfin_write16(CAN_MB15_DATA1, val)
-#define bfin_read_CAN_MB15_DATA2()     bfin_read16(CAN_MB15_DATA2)
-#define bfin_write_CAN_MB15_DATA2(val) bfin_write16(CAN_MB15_DATA2, val)
-#define bfin_read_CAN_MB15_DATA3()     bfin_read16(CAN_MB15_DATA3)
-#define bfin_write_CAN_MB15_DATA3(val) bfin_write16(CAN_MB15_DATA3, val)
-#define bfin_read_CAN_MB15_LENGTH()    bfin_read16(CAN_MB15_LENGTH)
-#define bfin_write_CAN_MB15_LENGTH(val) bfin_write16(CAN_MB15_LENGTH, val)
-#define bfin_read_CAN_MB15_TIMESTAMP() bfin_read16(CAN_MB15_TIMESTAMP)
-#define bfin_write_CAN_MB15_TIMESTAMP(val) bfin_write16(CAN_MB15_TIMESTAMP, val)
-#define bfin_read_CAN_MB15_ID0()       bfin_read16(CAN_MB15_ID0)
-#define bfin_write_CAN_MB15_ID0(val)   bfin_write16(CAN_MB15_ID0, val)
-#define bfin_read_CAN_MB15_ID1()       bfin_read16(CAN_MB15_ID1)
-#define bfin_write_CAN_MB15_ID1(val)   bfin_write16(CAN_MB15_ID1, val)
-#define bfin_read_CAN_MB16_DATA0()     bfin_read16(CAN_MB16_DATA0)
-#define bfin_write_CAN_MB16_DATA0(val) bfin_write16(CAN_MB16_DATA0, val)
-#define bfin_read_CAN_MB16_DATA1()     bfin_read16(CAN_MB16_DATA1)
-#define bfin_write_CAN_MB16_DATA1(val) bfin_write16(CAN_MB16_DATA1, val)
-#define bfin_read_CAN_MB16_DATA2()     bfin_read16(CAN_MB16_DATA2)
-#define bfin_write_CAN_MB16_DATA2(val) bfin_write16(CAN_MB16_DATA2, val)
-#define bfin_read_CAN_MB16_DATA3()     bfin_read16(CAN_MB16_DATA3)
-#define bfin_write_CAN_MB16_DATA3(val) bfin_write16(CAN_MB16_DATA3, val)
-#define bfin_read_CAN_MB16_LENGTH()    bfin_read16(CAN_MB16_LENGTH)
-#define bfin_write_CAN_MB16_LENGTH(val) bfin_write16(CAN_MB16_LENGTH, val)
-#define bfin_read_CAN_MB16_TIMESTAMP() bfin_read16(CAN_MB16_TIMESTAMP)
-#define bfin_write_CAN_MB16_TIMESTAMP(val) bfin_write16(CAN_MB16_TIMESTAMP, val)
-#define bfin_read_CAN_MB16_ID0()       bfin_read16(CAN_MB16_ID0)
-#define bfin_write_CAN_MB16_ID0(val)   bfin_write16(CAN_MB16_ID0, val)
-#define bfin_read_CAN_MB16_ID1()       bfin_read16(CAN_MB16_ID1)
-#define bfin_write_CAN_MB16_ID1(val)   bfin_write16(CAN_MB16_ID1, val)
-#define bfin_read_CAN_MB17_DATA0()     bfin_read16(CAN_MB17_DATA0)
-#define bfin_write_CAN_MB17_DATA0(val) bfin_write16(CAN_MB17_DATA0, val)
-#define bfin_read_CAN_MB17_DATA1()     bfin_read16(CAN_MB17_DATA1)
-#define bfin_write_CAN_MB17_DATA1(val) bfin_write16(CAN_MB17_DATA1, val)
-#define bfin_read_CAN_MB17_DATA2()     bfin_read16(CAN_MB17_DATA2)
-#define bfin_write_CAN_MB17_DATA2(val) bfin_write16(CAN_MB17_DATA2, val)
-#define bfin_read_CAN_MB17_DATA3()     bfin_read16(CAN_MB17_DATA3)
-#define bfin_write_CAN_MB17_DATA3(val) bfin_write16(CAN_MB17_DATA3, val)
-#define bfin_read_CAN_MB17_LENGTH()    bfin_read16(CAN_MB17_LENGTH)
-#define bfin_write_CAN_MB17_LENGTH(val) bfin_write16(CAN_MB17_LENGTH, val)
-#define bfin_read_CAN_MB17_TIMESTAMP() bfin_read16(CAN_MB17_TIMESTAMP)
-#define bfin_write_CAN_MB17_TIMESTAMP(val) bfin_write16(CAN_MB17_TIMESTAMP, val)
-#define bfin_read_CAN_MB17_ID0()       bfin_read16(CAN_MB17_ID0)
-#define bfin_write_CAN_MB17_ID0(val)   bfin_write16(CAN_MB17_ID0, val)
-#define bfin_read_CAN_MB17_ID1()       bfin_read16(CAN_MB17_ID1)
-#define bfin_write_CAN_MB17_ID1(val)   bfin_write16(CAN_MB17_ID1, val)
-#define bfin_read_CAN_MB18_DATA0()     bfin_read16(CAN_MB18_DATA0)
-#define bfin_write_CAN_MB18_DATA0(val) bfin_write16(CAN_MB18_DATA0, val)
-#define bfin_read_CAN_MB18_DATA1()     bfin_read16(CAN_MB18_DATA1)
-#define bfin_write_CAN_MB18_DATA1(val) bfin_write16(CAN_MB18_DATA1, val)
-#define bfin_read_CAN_MB18_DATA2()     bfin_read16(CAN_MB18_DATA2)
-#define bfin_write_CAN_MB18_DATA2(val) bfin_write16(CAN_MB18_DATA2, val)
-#define bfin_read_CAN_MB18_DATA3()     bfin_read16(CAN_MB18_DATA3)
-#define bfin_write_CAN_MB18_DATA3(val) bfin_write16(CAN_MB18_DATA3, val)
-#define bfin_read_CAN_MB18_LENGTH()    bfin_read16(CAN_MB18_LENGTH)
-#define bfin_write_CAN_MB18_LENGTH(val) bfin_write16(CAN_MB18_LENGTH, val)
-#define bfin_read_CAN_MB18_TIMESTAMP() bfin_read16(CAN_MB18_TIMESTAMP)
-#define bfin_write_CAN_MB18_TIMESTAMP(val) bfin_write16(CAN_MB18_TIMESTAMP, val)
-#define bfin_read_CAN_MB18_ID0()       bfin_read16(CAN_MB18_ID0)
-#define bfin_write_CAN_MB18_ID0(val)   bfin_write16(CAN_MB18_ID0, val)
-#define bfin_read_CAN_MB18_ID1()       bfin_read16(CAN_MB18_ID1)
-#define bfin_write_CAN_MB18_ID1(val)   bfin_write16(CAN_MB18_ID1, val)
-#define bfin_read_CAN_MB19_DATA0()     bfin_read16(CAN_MB19_DATA0)
-#define bfin_write_CAN_MB19_DATA0(val) bfin_write16(CAN_MB19_DATA0, val)
-#define bfin_read_CAN_MB19_DATA1()     bfin_read16(CAN_MB19_DATA1)
-#define bfin_write_CAN_MB19_DATA1(val) bfin_write16(CAN_MB19_DATA1, val)
-#define bfin_read_CAN_MB19_DATA2()     bfin_read16(CAN_MB19_DATA2)
-#define bfin_write_CAN_MB19_DATA2(val) bfin_write16(CAN_MB19_DATA2, val)
-#define bfin_read_CAN_MB19_DATA3()     bfin_read16(CAN_MB19_DATA3)
-#define bfin_write_CAN_MB19_DATA3(val) bfin_write16(CAN_MB19_DATA3, val)
-#define bfin_read_CAN_MB19_LENGTH()    bfin_read16(CAN_MB19_LENGTH)
-#define bfin_write_CAN_MB19_LENGTH(val) bfin_write16(CAN_MB19_LENGTH, val)
-#define bfin_read_CAN_MB19_TIMESTAMP() bfin_read16(CAN_MB19_TIMESTAMP)
-#define bfin_write_CAN_MB19_TIMESTAMP(val) bfin_write16(CAN_MB19_TIMESTAMP, val)
-#define bfin_read_CAN_MB19_ID0()       bfin_read16(CAN_MB19_ID0)
-#define bfin_write_CAN_MB19_ID0(val)   bfin_write16(CAN_MB19_ID0, val)
-#define bfin_read_CAN_MB19_ID1()       bfin_read16(CAN_MB19_ID1)
-#define bfin_write_CAN_MB19_ID1(val)   bfin_write16(CAN_MB19_ID1, val)
-#define bfin_read_CAN_MB20_DATA0()     bfin_read16(CAN_MB20_DATA0)
-#define bfin_write_CAN_MB20_DATA0(val) bfin_write16(CAN_MB20_DATA0, val)
-#define bfin_read_CAN_MB20_DATA1()     bfin_read16(CAN_MB20_DATA1)
-#define bfin_write_CAN_MB20_DATA1(val) bfin_write16(CAN_MB20_DATA1, val)
-#define bfin_read_CAN_MB20_DATA2()     bfin_read16(CAN_MB20_DATA2)
-#define bfin_write_CAN_MB20_DATA2(val) bfin_write16(CAN_MB20_DATA2, val)
-#define bfin_read_CAN_MB20_DATA3()     bfin_read16(CAN_MB20_DATA3)
-#define bfin_write_CAN_MB20_DATA3(val) bfin_write16(CAN_MB20_DATA3, val)
-#define bfin_read_CAN_MB20_LENGTH()    bfin_read16(CAN_MB20_LENGTH)
-#define bfin_write_CAN_MB20_LENGTH(val) bfin_write16(CAN_MB20_LENGTH, val)
-#define bfin_read_CAN_MB20_TIMESTAMP() bfin_read16(CAN_MB20_TIMESTAMP)
-#define bfin_write_CAN_MB20_TIMESTAMP(val) bfin_write16(CAN_MB20_TIMESTAMP, val)
-#define bfin_read_CAN_MB20_ID0()       bfin_read16(CAN_MB20_ID0)
-#define bfin_write_CAN_MB20_ID0(val)   bfin_write16(CAN_MB20_ID0, val)
-#define bfin_read_CAN_MB20_ID1()       bfin_read16(CAN_MB20_ID1)
-#define bfin_write_CAN_MB20_ID1(val)   bfin_write16(CAN_MB20_ID1, val)
-#define bfin_read_CAN_MB21_DATA0()     bfin_read16(CAN_MB21_DATA0)
-#define bfin_write_CAN_MB21_DATA0(val) bfin_write16(CAN_MB21_DATA0, val)
-#define bfin_read_CAN_MB21_DATA1()     bfin_read16(CAN_MB21_DATA1)
-#define bfin_write_CAN_MB21_DATA1(val) bfin_write16(CAN_MB21_DATA1, val)
-#define bfin_read_CAN_MB21_DATA2()     bfin_read16(CAN_MB21_DATA2)
-#define bfin_write_CAN_MB21_DATA2(val) bfin_write16(CAN_MB21_DATA2, val)
-#define bfin_read_CAN_MB21_DATA3()     bfin_read16(CAN_MB21_DATA3)
-#define bfin_write_CAN_MB21_DATA3(val) bfin_write16(CAN_MB21_DATA3, val)
-#define bfin_read_CAN_MB21_LENGTH()    bfin_read16(CAN_MB21_LENGTH)
-#define bfin_write_CAN_MB21_LENGTH(val) bfin_write16(CAN_MB21_LENGTH, val)
-#define bfin_read_CAN_MB21_TIMESTAMP() bfin_read16(CAN_MB21_TIMESTAMP)
-#define bfin_write_CAN_MB21_TIMESTAMP(val) bfin_write16(CAN_MB21_TIMESTAMP, val)
-#define bfin_read_CAN_MB21_ID0()       bfin_read16(CAN_MB21_ID0)
-#define bfin_write_CAN_MB21_ID0(val)   bfin_write16(CAN_MB21_ID0, val)
-#define bfin_read_CAN_MB21_ID1()       bfin_read16(CAN_MB21_ID1)
-#define bfin_write_CAN_MB21_ID1(val)   bfin_write16(CAN_MB21_ID1, val)
-#define bfin_read_CAN_MB22_DATA0()     bfin_read16(CAN_MB22_DATA0)
-#define bfin_write_CAN_MB22_DATA0(val) bfin_write16(CAN_MB22_DATA0, val)
-#define bfin_read_CAN_MB22_DATA1()     bfin_read16(CAN_MB22_DATA1)
-#define bfin_write_CAN_MB22_DATA1(val) bfin_write16(CAN_MB22_DATA1, val)
-#define bfin_read_CAN_MB22_DATA2()     bfin_read16(CAN_MB22_DATA2)
-#define bfin_write_CAN_MB22_DATA2(val) bfin_write16(CAN_MB22_DATA2, val)
-#define bfin_read_CAN_MB22_DATA3()     bfin_read16(CAN_MB22_DATA3)
-#define bfin_write_CAN_MB22_DATA3(val) bfin_write16(CAN_MB22_DATA3, val)
-#define bfin_read_CAN_MB22_LENGTH()    bfin_read16(CAN_MB22_LENGTH)
-#define bfin_write_CAN_MB22_LENGTH(val) bfin_write16(CAN_MB22_LENGTH, val)
-#define bfin_read_CAN_MB22_TIMESTAMP() bfin_read16(CAN_MB22_TIMESTAMP)
-#define bfin_write_CAN_MB22_TIMESTAMP(val) bfin_write16(CAN_MB22_TIMESTAMP, val)
-#define bfin_read_CAN_MB22_ID0()       bfin_read16(CAN_MB22_ID0)
-#define bfin_write_CAN_MB22_ID0(val)   bfin_write16(CAN_MB22_ID0, val)
-#define bfin_read_CAN_MB22_ID1()       bfin_read16(CAN_MB22_ID1)
-#define bfin_write_CAN_MB22_ID1(val)   bfin_write16(CAN_MB22_ID1, val)
-#define bfin_read_CAN_MB23_DATA0()     bfin_read16(CAN_MB23_DATA0)
-#define bfin_write_CAN_MB23_DATA0(val) bfin_write16(CAN_MB23_DATA0, val)
-#define bfin_read_CAN_MB23_DATA1()     bfin_read16(CAN_MB23_DATA1)
-#define bfin_write_CAN_MB23_DATA1(val) bfin_write16(CAN_MB23_DATA1, val)
-#define bfin_read_CAN_MB23_DATA2()     bfin_read16(CAN_MB23_DATA2)
-#define bfin_write_CAN_MB23_DATA2(val) bfin_write16(CAN_MB23_DATA2, val)
-#define bfin_read_CAN_MB23_DATA3()     bfin_read16(CAN_MB23_DATA3)
-#define bfin_write_CAN_MB23_DATA3(val) bfin_write16(CAN_MB23_DATA3, val)
-#define bfin_read_CAN_MB23_LENGTH()    bfin_read16(CAN_MB23_LENGTH)
-#define bfin_write_CAN_MB23_LENGTH(val) bfin_write16(CAN_MB23_LENGTH, val)
-#define bfin_read_CAN_MB23_TIMESTAMP() bfin_read16(CAN_MB23_TIMESTAMP)
-#define bfin_write_CAN_MB23_TIMESTAMP(val) bfin_write16(CAN_MB23_TIMESTAMP, val)
-#define bfin_read_CAN_MB23_ID0()       bfin_read16(CAN_MB23_ID0)
-#define bfin_write_CAN_MB23_ID0(val)   bfin_write16(CAN_MB23_ID0, val)
-#define bfin_read_CAN_MB23_ID1()       bfin_read16(CAN_MB23_ID1)
-#define bfin_write_CAN_MB23_ID1(val)   bfin_write16(CAN_MB23_ID1, val)
-#define bfin_read_CAN_MB24_DATA0()     bfin_read16(CAN_MB24_DATA0)
-#define bfin_write_CAN_MB24_DATA0(val) bfin_write16(CAN_MB24_DATA0, val)
-#define bfin_read_CAN_MB24_DATA1()     bfin_read16(CAN_MB24_DATA1)
-#define bfin_write_CAN_MB24_DATA1(val) bfin_write16(CAN_MB24_DATA1, val)
-#define bfin_read_CAN_MB24_DATA2()     bfin_read16(CAN_MB24_DATA2)
-#define bfin_write_CAN_MB24_DATA2(val) bfin_write16(CAN_MB24_DATA2, val)
-#define bfin_read_CAN_MB24_DATA3()     bfin_read16(CAN_MB24_DATA3)
-#define bfin_write_CAN_MB24_DATA3(val) bfin_write16(CAN_MB24_DATA3, val)
-#define bfin_read_CAN_MB24_LENGTH()    bfin_read16(CAN_MB24_LENGTH)
-#define bfin_write_CAN_MB24_LENGTH(val) bfin_write16(CAN_MB24_LENGTH, val)
-#define bfin_read_CAN_MB24_TIMESTAMP() bfin_read16(CAN_MB24_TIMESTAMP)
-#define bfin_write_CAN_MB24_TIMESTAMP(val) bfin_write16(CAN_MB24_TIMESTAMP, val)
-#define bfin_read_CAN_MB24_ID0()       bfin_read16(CAN_MB24_ID0)
-#define bfin_write_CAN_MB24_ID0(val)   bfin_write16(CAN_MB24_ID0, val)
-#define bfin_read_CAN_MB24_ID1()       bfin_read16(CAN_MB24_ID1)
-#define bfin_write_CAN_MB24_ID1(val)   bfin_write16(CAN_MB24_ID1, val)
-#define bfin_read_CAN_MB25_DATA0()     bfin_read16(CAN_MB25_DATA0)
-#define bfin_write_CAN_MB25_DATA0(val) bfin_write16(CAN_MB25_DATA0, val)
-#define bfin_read_CAN_MB25_DATA1()     bfin_read16(CAN_MB25_DATA1)
-#define bfin_write_CAN_MB25_DATA1(val) bfin_write16(CAN_MB25_DATA1, val)
-#define bfin_read_CAN_MB25_DATA2()     bfin_read16(CAN_MB25_DATA2)
-#define bfin_write_CAN_MB25_DATA2(val) bfin_write16(CAN_MB25_DATA2, val)
-#define bfin_read_CAN_MB25_DATA3()     bfin_read16(CAN_MB25_DATA3)
-#define bfin_write_CAN_MB25_DATA3(val) bfin_write16(CAN_MB25_DATA3, val)
-#define bfin_read_CAN_MB25_LENGTH()    bfin_read16(CAN_MB25_LENGTH)
-#define bfin_write_CAN_MB25_LENGTH(val) bfin_write16(CAN_MB25_LENGTH, val)
-#define bfin_read_CAN_MB25_TIMESTAMP() bfin_read16(CAN_MB25_TIMESTAMP)
-#define bfin_write_CAN_MB25_TIMESTAMP(val) bfin_write16(CAN_MB25_TIMESTAMP, val)
-#define bfin_read_CAN_MB25_ID0()       bfin_read16(CAN_MB25_ID0)
-#define bfin_write_CAN_MB25_ID0(val)   bfin_write16(CAN_MB25_ID0, val)
-#define bfin_read_CAN_MB25_ID1()       bfin_read16(CAN_MB25_ID1)
-#define bfin_write_CAN_MB25_ID1(val)   bfin_write16(CAN_MB25_ID1, val)
-#define bfin_read_CAN_MB26_DATA0()     bfin_read16(CAN_MB26_DATA0)
-#define bfin_write_CAN_MB26_DATA0(val) bfin_write16(CAN_MB26_DATA0, val)
-#define bfin_read_CAN_MB26_DATA1()     bfin_read16(CAN_MB26_DATA1)
-#define bfin_write_CAN_MB26_DATA1(val) bfin_write16(CAN_MB26_DATA1, val)
-#define bfin_read_CAN_MB26_DATA2()     bfin_read16(CAN_MB26_DATA2)
-#define bfin_write_CAN_MB26_DATA2(val) bfin_write16(CAN_MB26_DATA2, val)
-#define bfin_read_CAN_MB26_DATA3()     bfin_read16(CAN_MB26_DATA3)
-#define bfin_write_CAN_MB26_DATA3(val) bfin_write16(CAN_MB26_DATA3, val)
-#define bfin_read_CAN_MB26_LENGTH()    bfin_read16(CAN_MB26_LENGTH)
-#define bfin_write_CAN_MB26_LENGTH(val) bfin_write16(CAN_MB26_LENGTH, val)
-#define bfin_read_CAN_MB26_TIMESTAMP() bfin_read16(CAN_MB26_TIMESTAMP)
-#define bfin_write_CAN_MB26_TIMESTAMP(val) bfin_write16(CAN_MB26_TIMESTAMP, val)
-#define bfin_read_CAN_MB26_ID0()       bfin_read16(CAN_MB26_ID0)
-#define bfin_write_CAN_MB26_ID0(val)   bfin_write16(CAN_MB26_ID0, val)
-#define bfin_read_CAN_MB26_ID1()       bfin_read16(CAN_MB26_ID1)
-#define bfin_write_CAN_MB26_ID1(val)   bfin_write16(CAN_MB26_ID1, val)
-#define bfin_read_CAN_MB27_DATA0()     bfin_read16(CAN_MB27_DATA0)
-#define bfin_write_CAN_MB27_DATA0(val) bfin_write16(CAN_MB27_DATA0, val)
-#define bfin_read_CAN_MB27_DATA1()     bfin_read16(CAN_MB27_DATA1)
-#define bfin_write_CAN_MB27_DATA1(val) bfin_write16(CAN_MB27_DATA1, val)
-#define bfin_read_CAN_MB27_DATA2()     bfin_read16(CAN_MB27_DATA2)
-#define bfin_write_CAN_MB27_DATA2(val) bfin_write16(CAN_MB27_DATA2, val)
-#define bfin_read_CAN_MB27_DATA3()     bfin_read16(CAN_MB27_DATA3)
-#define bfin_write_CAN_MB27_DATA3(val) bfin_write16(CAN_MB27_DATA3, val)
-#define bfin_read_CAN_MB27_LENGTH()    bfin_read16(CAN_MB27_LENGTH)
-#define bfin_write_CAN_MB27_LENGTH(val) bfin_write16(CAN_MB27_LENGTH, val)
-#define bfin_read_CAN_MB27_TIMESTAMP() bfin_read16(CAN_MB27_TIMESTAMP)
-#define bfin_write_CAN_MB27_TIMESTAMP(val) bfin_write16(CAN_MB27_TIMESTAMP, val)
-#define bfin_read_CAN_MB27_ID0()       bfin_read16(CAN_MB27_ID0)
-#define bfin_write_CAN_MB27_ID0(val)   bfin_write16(CAN_MB27_ID0, val)
-#define bfin_read_CAN_MB27_ID1()       bfin_read16(CAN_MB27_ID1)
-#define bfin_write_CAN_MB27_ID1(val)   bfin_write16(CAN_MB27_ID1, val)
-#define bfin_read_CAN_MB28_DATA0()     bfin_read16(CAN_MB28_DATA0)
-#define bfin_write_CAN_MB28_DATA0(val) bfin_write16(CAN_MB28_DATA0, val)
-#define bfin_read_CAN_MB28_DATA1()     bfin_read16(CAN_MB28_DATA1)
-#define bfin_write_CAN_MB28_DATA1(val) bfin_write16(CAN_MB28_DATA1, val)
-#define bfin_read_CAN_MB28_DATA2()     bfin_read16(CAN_MB28_DATA2)
-#define bfin_write_CAN_MB28_DATA2(val) bfin_write16(CAN_MB28_DATA2, val)
-#define bfin_read_CAN_MB28_DATA3()     bfin_read16(CAN_MB28_DATA3)
-#define bfin_write_CAN_MB28_DATA3(val) bfin_write16(CAN_MB28_DATA3, val)
-#define bfin_read_CAN_MB28_LENGTH()    bfin_read16(CAN_MB28_LENGTH)
-#define bfin_write_CAN_MB28_LENGTH(val) bfin_write16(CAN_MB28_LENGTH, val)
-#define bfin_read_CAN_MB28_TIMESTAMP() bfin_read16(CAN_MB28_TIMESTAMP)
-#define bfin_write_CAN_MB28_TIMESTAMP(val) bfin_write16(CAN_MB28_TIMESTAMP, val)
-#define bfin_read_CAN_MB28_ID0()       bfin_read16(CAN_MB28_ID0)
-#define bfin_write_CAN_MB28_ID0(val)   bfin_write16(CAN_MB28_ID0, val)
-#define bfin_read_CAN_MB28_ID1()       bfin_read16(CAN_MB28_ID1)
-#define bfin_write_CAN_MB28_ID1(val)   bfin_write16(CAN_MB28_ID1, val)
-#define bfin_read_CAN_MB29_DATA0()     bfin_read16(CAN_MB29_DATA0)
-#define bfin_write_CAN_MB29_DATA0(val) bfin_write16(CAN_MB29_DATA0, val)
-#define bfin_read_CAN_MB29_DATA1()     bfin_read16(CAN_MB29_DATA1)
-#define bfin_write_CAN_MB29_DATA1(val) bfin_write16(CAN_MB29_DATA1, val)
-#define bfin_read_CAN_MB29_DATA2()     bfin_read16(CAN_MB29_DATA2)
-#define bfin_write_CAN_MB29_DATA2(val) bfin_write16(CAN_MB29_DATA2, val)
-#define bfin_read_CAN_MB29_DATA3()     bfin_read16(CAN_MB29_DATA3)
-#define bfin_write_CAN_MB29_DATA3(val) bfin_write16(CAN_MB29_DATA3, val)
-#define bfin_read_CAN_MB29_LENGTH()    bfin_read16(CAN_MB29_LENGTH)
-#define bfin_write_CAN_MB29_LENGTH(val) bfin_write16(CAN_MB29_LENGTH, val)
-#define bfin_read_CAN_MB29_TIMESTAMP() bfin_read16(CAN_MB29_TIMESTAMP)
-#define bfin_write_CAN_MB29_TIMESTAMP(val) bfin_write16(CAN_MB29_TIMESTAMP, val)
-#define bfin_read_CAN_MB29_ID0()       bfin_read16(CAN_MB29_ID0)
-#define bfin_write_CAN_MB29_ID0(val)   bfin_write16(CAN_MB29_ID0, val)
-#define bfin_read_CAN_MB29_ID1()       bfin_read16(CAN_MB29_ID1)
-#define bfin_write_CAN_MB29_ID1(val)   bfin_write16(CAN_MB29_ID1, val)
-#define bfin_read_CAN_MB30_DATA0()     bfin_read16(CAN_MB30_DATA0)
-#define bfin_write_CAN_MB30_DATA0(val) bfin_write16(CAN_MB30_DATA0, val)
-#define bfin_read_CAN_MB30_DATA1()     bfin_read16(CAN_MB30_DATA1)
-#define bfin_write_CAN_MB30_DATA1(val) bfin_write16(CAN_MB30_DATA1, val)
-#define bfin_read_CAN_MB30_DATA2()     bfin_read16(CAN_MB30_DATA2)
-#define bfin_write_CAN_MB30_DATA2(val) bfin_write16(CAN_MB30_DATA2, val)
-#define bfin_read_CAN_MB30_DATA3()     bfin_read16(CAN_MB30_DATA3)
-#define bfin_write_CAN_MB30_DATA3(val) bfin_write16(CAN_MB30_DATA3, val)
-#define bfin_read_CAN_MB30_LENGTH()    bfin_read16(CAN_MB30_LENGTH)
-#define bfin_write_CAN_MB30_LENGTH(val) bfin_write16(CAN_MB30_LENGTH, val)
-#define bfin_read_CAN_MB30_TIMESTAMP() bfin_read16(CAN_MB30_TIMESTAMP)
-#define bfin_write_CAN_MB30_TIMESTAMP(val) bfin_write16(CAN_MB30_TIMESTAMP, val)
-#define bfin_read_CAN_MB30_ID0()       bfin_read16(CAN_MB30_ID0)
-#define bfin_write_CAN_MB30_ID0(val)   bfin_write16(CAN_MB30_ID0, val)
-#define bfin_read_CAN_MB30_ID1()       bfin_read16(CAN_MB30_ID1)
-#define bfin_write_CAN_MB30_ID1(val)   bfin_write16(CAN_MB30_ID1, val)
-#define bfin_read_CAN_MB31_DATA0()     bfin_read16(CAN_MB31_DATA0)
-#define bfin_write_CAN_MB31_DATA0(val) bfin_write16(CAN_MB31_DATA0, val)
-#define bfin_read_CAN_MB31_DATA1()     bfin_read16(CAN_MB31_DATA1)
-#define bfin_write_CAN_MB31_DATA1(val) bfin_write16(CAN_MB31_DATA1, val)
-#define bfin_read_CAN_MB31_DATA2()     bfin_read16(CAN_MB31_DATA2)
-#define bfin_write_CAN_MB31_DATA2(val) bfin_write16(CAN_MB31_DATA2, val)
-#define bfin_read_CAN_MB31_DATA3()     bfin_read16(CAN_MB31_DATA3)
-#define bfin_write_CAN_MB31_DATA3(val) bfin_write16(CAN_MB31_DATA3, val)
-#define bfin_read_CAN_MB31_LENGTH()    bfin_read16(CAN_MB31_LENGTH)
-#define bfin_write_CAN_MB31_LENGTH(val) bfin_write16(CAN_MB31_LENGTH, val)
-#define bfin_read_CAN_MB31_TIMESTAMP() bfin_read16(CAN_MB31_TIMESTAMP)
-#define bfin_write_CAN_MB31_TIMESTAMP(val) bfin_write16(CAN_MB31_TIMESTAMP, val)
-#define bfin_read_CAN_MB31_ID0()       bfin_read16(CAN_MB31_ID0)
-#define bfin_write_CAN_MB31_ID0(val)   bfin_write16(CAN_MB31_ID0, val)
-#define bfin_read_CAN_MB31_ID1()       bfin_read16(CAN_MB31_ID1)
-#define bfin_write_CAN_MB31_ID1(val)   bfin_write16(CAN_MB31_ID1, val)
-#define bfin_read_PORTF_FER()          bfin_read16(PORTF_FER)
-#define bfin_write_PORTF_FER(val)      bfin_write16(PORTF_FER, val)
-#define bfin_read_PORTG_FER()          bfin_read16(PORTG_FER)
-#define bfin_write_PORTG_FER(val)      bfin_write16(PORTG_FER, val)
-#define bfin_read_PORTH_FER()          bfin_read16(PORTH_FER)
-#define bfin_write_PORTH_FER(val)      bfin_write16(PORTH_FER, val)
-#define bfin_read_PORT_MUX()           bfin_read16(PORT_MUX)
-#define bfin_write_PORT_MUX(val)       bfin_write16(PORT_MUX, val)
-#define bfin_read_HMDMA0_CONTROL()     bfin_read16(HMDMA0_CONTROL)
-#define bfin_write_HMDMA0_CONTROL(val) bfin_write16(HMDMA0_CONTROL, val)
-#define bfin_read_HMDMA0_ECINIT()      bfin_read16(HMDMA0_ECINIT)
-#define bfin_write_HMDMA0_ECINIT(val)  bfin_write16(HMDMA0_ECINIT, val)
-#define bfin_read_HMDMA0_BCINIT()      bfin_read16(HMDMA0_BCINIT)
-#define bfin_write_HMDMA0_BCINIT(val)  bfin_write16(HMDMA0_BCINIT, val)
-#define bfin_read_HMDMA0_ECURGENT()    bfin_read16(HMDMA0_ECURGENT)
-#define bfin_write_HMDMA0_ECURGENT(val) bfin_write16(HMDMA0_ECURGENT, val)
-#define bfin_read_HMDMA0_ECOVERFLOW()  bfin_read16(HMDMA0_ECOVERFLOW)
-#define bfin_write_HMDMA0_ECOVERFLOW(val) bfin_write16(HMDMA0_ECOVERFLOW, val)
-#define bfin_read_HMDMA0_ECOUNT()      bfin_read16(HMDMA0_ECOUNT)
-#define bfin_write_HMDMA0_ECOUNT(val)  bfin_write16(HMDMA0_ECOUNT, val)
-#define bfin_read_HMDMA0_BCOUNT()      bfin_read16(HMDMA0_BCOUNT)
-#define bfin_write_HMDMA0_BCOUNT(val)  bfin_write16(HMDMA0_BCOUNT, val)
-#define bfin_read_HMDMA1_CONTROL()     bfin_read16(HMDMA1_CONTROL)
-#define bfin_write_HMDMA1_CONTROL(val) bfin_write16(HMDMA1_CONTROL, val)
-#define bfin_read_HMDMA1_ECINIT()      bfin_read16(HMDMA1_ECINIT)
-#define bfin_write_HMDMA1_ECINIT(val)  bfin_write16(HMDMA1_ECINIT, val)
-#define bfin_read_HMDMA1_BCINIT()      bfin_read16(HMDMA1_BCINIT)
-#define bfin_write_HMDMA1_BCINIT(val)  bfin_write16(HMDMA1_BCINIT, val)
-#define bfin_read_HMDMA1_ECURGENT()    bfin_read16(HMDMA1_ECURGENT)
-#define bfin_write_HMDMA1_ECURGENT(val) bfin_write16(HMDMA1_ECURGENT, val)
-#define bfin_read_HMDMA1_ECOVERFLOW()  bfin_read16(HMDMA1_ECOVERFLOW)
-#define bfin_write_HMDMA1_ECOVERFLOW(val) bfin_write16(HMDMA1_ECOVERFLOW, val)
-#define bfin_read_HMDMA1_ECOUNT()      bfin_read16(HMDMA1_ECOUNT)
-#define bfin_write_HMDMA1_ECOUNT(val)  bfin_write16(HMDMA1_ECOUNT, val)
-#define bfin_read_HMDMA1_BCOUNT()      bfin_read16(HMDMA1_BCOUNT)
-#define bfin_write_HMDMA1_BCOUNT(val)  bfin_write16(HMDMA1_BCOUNT, val)
-#define bfin_read_CHIPID()             bfin_read32(CHIPID)
-#define bfin_write_CHIPID(val)         bfin_write32(CHIPID, val)
-#define bfin_read_DMA_TC_CNT()         bfin_read16(DMA_TC_CNT)
-#define bfin_write_DMA_TC_CNT(val)     bfin_write16(DMA_TC_CNT, val)
-#define bfin_read_DMA_TC_PER()         bfin_read16(DMA_TC_PER)
-#define bfin_write_DMA_TC_PER(val)     bfin_write16(DMA_TC_PER, val)
-
-#endif /* __BFIN_CDEF_ADSP_BF534_proc__ */

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