u-boot.lds 2.8 KB

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  1. /*
  2. * U-Boot - u-boot.lds.S
  3. *
  4. * Copyright (c) 2005-2010 Analog Device Inc.
  5. *
  6. * (C) Copyright 2000-2004
  7. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  8. *
  9. * SPDX-License-Identifier: GPL-2.0+
  10. */
  11. #include <config.h>
  12. #include <asm/blackfin.h>
  13. #undef ALIGN
  14. #undef ENTRY
  15. #ifndef LDS_BOARD_TEXT
  16. # define LDS_BOARD_TEXT
  17. #endif
  18. /* If we don't actually load anything into L1 data, this will avoid
  19. * a syntax error. If we do actually load something into L1 data,
  20. * we'll get a linker memory load error (which is what we'd want).
  21. * This is here in the first place so we can quickly test building
  22. * for different CPU's which may lack non-cache L1 data.
  23. */
  24. #ifndef L1_DATA_A_SRAM
  25. # define L1_DATA_A_SRAM 0
  26. # define L1_DATA_A_SRAM_SIZE 0
  27. #endif
  28. #ifndef L1_DATA_B_SRAM
  29. # define L1_DATA_B_SRAM L1_DATA_A_SRAM
  30. # define L1_DATA_B_SRAM_SIZE L1_DATA_A_SRAM_SIZE
  31. #endif
  32. /* The 0xC offset is so we don't clobber the tiny LDR jump block. */
  33. #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
  34. # define L1_CODE_ORIGIN L1_INST_SRAM
  35. #else
  36. # define L1_CODE_ORIGIN L1_INST_SRAM + 0xC
  37. #endif
  38. OUTPUT_ARCH(bfin)
  39. MEMORY
  40. {
  41. #if CONFIG_MEM_SIZE
  42. ram : ORIGIN = CONFIG_SYS_MONITOR_BASE, LENGTH = CONFIG_SYS_MONITOR_LEN
  43. # define ram_code ram
  44. # define ram_data ram
  45. #else
  46. # define ram_code l1_code
  47. # define ram_data l1_data
  48. #endif
  49. l1_code : ORIGIN = L1_CODE_ORIGIN, LENGTH = L1_INST_SRAM_SIZE
  50. l1_data : ORIGIN = L1_DATA_B_SRAM, LENGTH = L1_DATA_B_SRAM_SIZE
  51. }
  52. ENTRY(_start)
  53. SECTIONS
  54. {
  55. .text.pre :
  56. {
  57. arch/blackfin/cpu/start.o (.text .text.*)
  58. LDS_BOARD_TEXT
  59. } >ram_code
  60. .text.init :
  61. {
  62. arch/blackfin/cpu/initcode.o (.text .text.*)
  63. } >ram_code
  64. __initcode_lma = LOADADDR(.text.init);
  65. __initcode_len = SIZEOF(.text.init);
  66. .text :
  67. {
  68. *(.text .text.*)
  69. } >ram_code
  70. .rodata :
  71. {
  72. . = ALIGN(4);
  73. *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*)))
  74. . = ALIGN(4);
  75. } >ram_data
  76. .data :
  77. {
  78. . = ALIGN(4);
  79. *(.data .data.*)
  80. *(.data1)
  81. *(.sdata)
  82. *(.sdata2)
  83. *(.dynamic)
  84. CONSTRUCTORS
  85. } >ram_data
  86. .u_boot_list : {
  87. KEEP(*(SORT(.u_boot_list*)));
  88. } >ram_data
  89. .text_l1 :
  90. {
  91. . = ALIGN(4);
  92. __stext_l1 = .;
  93. *(.l1.text)
  94. . = ALIGN(4);
  95. __etext_l1 = .;
  96. } >l1_code AT>ram_code
  97. __text_l1_lma = LOADADDR(.text_l1);
  98. __text_l1_len = SIZEOF(.text_l1);
  99. ASSERT (__text_l1_len <= L1_INST_SRAM_SIZE, "L1 text overflow!")
  100. .data_l1 :
  101. {
  102. . = ALIGN(4);
  103. __sdata_l1 = .;
  104. *(.l1.data)
  105. *(.l1.bss)
  106. . = ALIGN(4);
  107. __edata_l1 = .;
  108. } >l1_data AT>ram_data
  109. __data_l1_lma = LOADADDR(.data_l1);
  110. __data_l1_len = SIZEOF(.data_l1);
  111. ASSERT (__data_l1_len <= L1_DATA_B_SRAM_SIZE, "L1 data overflow!")
  112. .bss :
  113. {
  114. . = ALIGN(4);
  115. *(.sbss) *(.scommon)
  116. *(.dynbss)
  117. *(.bss .bss.*)
  118. *(COMMON)
  119. . = ALIGN(4);
  120. } >ram_data
  121. __bss_end = .;
  122. __bss_start = ADDR(.bss);
  123. __bss_len = SIZEOF(.bss);
  124. __init_end = .;
  125. }