cplb.h 4.2 KB

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  1. /*
  2. * cplb.h - defines for managing CPLB tables
  3. *
  4. * Copyright (c) 2002-2007 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #ifndef __ASM_BLACKFIN_CPLB_H__
  9. #define __ASM_BLACKFIN_CPLB_H__
  10. #include <asm/mach-common/bits/mpu.h>
  11. #define CPLB_ENABLE_ICACHE_P 0
  12. #define CPLB_ENABLE_DCACHE_P 1
  13. #define CPLB_ENABLE_DCACHE2_P 2
  14. #define CPLB_ENABLE_CPLBS_P 3 /* Deprecated! */
  15. #define CPLB_ENABLE_ICPLBS_P 4
  16. #define CPLB_ENABLE_DCPLBS_P 5
  17. #define CPLB_ENABLE_ICACHE (1<<CPLB_ENABLE_ICACHE_P)
  18. #define CPLB_ENABLE_DCACHE (1<<CPLB_ENABLE_DCACHE_P)
  19. #define CPLB_ENABLE_DCACHE2 (1<<CPLB_ENABLE_DCACHE2_P)
  20. #define CPLB_ENABLE_CPLBS (1<<CPLB_ENABLE_CPLBS_P)
  21. #define CPLB_ENABLE_ICPLBS (1<<CPLB_ENABLE_ICPLBS_P)
  22. #define CPLB_ENABLE_DCPLBS (1<<CPLB_ENABLE_DCPLBS_P)
  23. #define CPLB_ENABLE_ANY_CPLBS CPLB_ENABLE_CPLBS | \
  24. CPLB_ENABLE_ICPLBS | \
  25. CPLB_ENABLE_DCPLBS
  26. #define CPLB_RELOADED 0x0000
  27. #define CPLB_NO_UNLOCKED 0x0001
  28. #define CPLB_NO_ADDR_MATCH 0x0002
  29. #define CPLB_PROT_VIOL 0x0003
  30. #define CPLB_DEF_CACHE CPLB_L1_CHBL | CPLB_WT
  31. #define CPLB_CACHE_ENABLED CPLB_L1_CHBL | CPLB_DIRTY
  32. #define CPLB_ALL_ACCESS CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR
  33. #define CPLB_I_PAGE_MGMT CPLB_LOCK | CPLB_VALID
  34. #define CPLB_D_PAGE_MGMT CPLB_LOCK | CPLB_ALL_ACCESS | CPLB_VALID
  35. #define CPLB_DNOCACHE CPLB_ALL_ACCESS | CPLB_VALID
  36. #define CPLB_DDOCACHE CPLB_DNOCACHE | CPLB_DEF_CACHE
  37. #define CPLB_INOCACHE CPLB_USER_RD | CPLB_VALID
  38. #define CPLB_IDOCACHE CPLB_INOCACHE | CPLB_L1_CHBL
  39. /* Data Attibutes*/
  40. #if defined(__ADSPBF60x__)
  41. #define SDRAM_IGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | \
  42. CPLB_USER_RD | CPLB_VALID)
  43. #else
  44. #define SDRAM_IGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | \
  45. CPLB_USER_RD | CPLB_VALID)
  46. #endif
  47. #define SDRAM_IKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  48. #define L1_IMEMORY (PAGE_SIZE_1MB | CPLB_USER_RD | CPLB_VALID | CPLB_LOCK)
  49. #define SDRAM_INON_CHBL (PAGE_SIZE_4MB | CPLB_USER_RD | CPLB_VALID)
  50. #if ANOMALY_05000158
  51. # define ANOMALY_05000158_WORKAROUND 0x200
  52. #else
  53. # define ANOMALY_05000158_WORKAROUND 0
  54. #endif
  55. #ifdef CONFIG_DCACHE_WB /*Write Back Policy */
  56. #if defined(__ADSPBF60x__)
  57. #define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_DIRTY | \
  58. CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
  59. CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  60. #else
  61. #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_DIRTY | \
  62. CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | \
  63. CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  64. #endif
  65. #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_USER_RD | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  66. #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_USER_RD | CPLB_USER_WR | CPLB_DIRTY | CPLB_SUPV_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
  67. #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  68. #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_DIRTY | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  69. #else /*Write Through */
  70. #if defined(__ADSPBF60x__)
  71. #define SDRAM_DGENERIC (PAGE_SIZE_16MB | CPLB_L1_CHBL | CPLB_WT | \
  72. CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
  73. CPLB_USER_WR | CPLB_VALID | \
  74. ANOMALY_05000158_WORKAROUND)
  75. #else
  76. #define SDRAM_DGENERIC (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | \
  77. CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_RD | \
  78. CPLB_USER_WR | CPLB_VALID | \
  79. ANOMALY_05000158_WORKAROUND)
  80. #endif
  81. #define SDRAM_DNON_CHBL (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_USER_RD | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  82. #define SDRAM_DKERNEL (PAGE_SIZE_4MB | CPLB_L1_CHBL | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | CPLB_LOCK | ANOMALY_05000158_WORKAROUND)
  83. #define L1_DMEMORY (PAGE_SIZE_4MB | CPLB_SUPV_WR | CPLB_USER_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  84. #define SDRAM_EBIU (PAGE_SIZE_4MB | CPLB_WT | CPLB_L1_AOW | CPLB_USER_RD | CPLB_USER_WR | CPLB_SUPV_WR | CPLB_VALID | ANOMALY_05000158_WORKAROUND)
  85. #endif
  86. #endif /* _CPLB_H */