reset.c 2.6 KB

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  1. /*
  2. * reset.c - logic for resetting the cpu
  3. *
  4. * Copyright (c) 2005-2008 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <asm/blackfin.h>
  11. #include <asm/mach-common/bits/bootrom.h>
  12. #include "cpu.h"
  13. /* A system soft reset makes external memory unusable so force
  14. * this function into L1. We use the compiler ssync here rather
  15. * than SSYNC() because it's safe (no interrupts and such) and
  16. * we save some L1. We do not need to force sanity in the SYSCR
  17. * register as the BMODE selection bit is cleared by the soft
  18. * reset while the Core B bit (on dual core parts) is cleared by
  19. * the core reset.
  20. */
  21. __attribute__ ((__l1_text__, __noreturn__))
  22. static void bfin_reset(void)
  23. {
  24. #ifdef SWRST
  25. /* Wait for completion of "system" events such as cache line
  26. * line fills so that we avoid infinite stalls later on as
  27. * much as possible. This code is in L1, so it won't trigger
  28. * any such event after this point in time.
  29. */
  30. __builtin_bfin_ssync();
  31. /* Initiate System software reset. */
  32. bfin_write_SWRST(0x7);
  33. /* Due to the way reset is handled in the hardware, we need
  34. * to delay for 10 SCLKS. The only reliable way to do this is
  35. * to calculate the CCLK/SCLK ratio and multiply 10. For now,
  36. * we'll assume worse case which is a 1:15 ratio.
  37. */
  38. asm(
  39. "LSETUP (1f, 1f) LC0 = %0\n"
  40. "1: nop;"
  41. :
  42. : "a" (15 * 10)
  43. : "LC0", "LB0", "LT0"
  44. );
  45. /* Clear System software reset */
  46. bfin_write_SWRST(0);
  47. /* The BF526 ROM will crash during reset */
  48. #if defined(__ADSPBF522__) || defined(__ADSPBF524__) || defined(__ADSPBF526__)
  49. /* Seems to be fixed with newer parts though ... */
  50. if (__SILICON_REVISION__ < 1 && bfin_revid() < 1)
  51. bfin_read_SWRST();
  52. #endif
  53. /* Wait for the SWRST write to complete. Cannot rely on SSYNC
  54. * though as the System state is all reset now.
  55. */
  56. asm(
  57. "LSETUP (1f, 1f) LC1 = %0\n"
  58. "1: nop;"
  59. :
  60. : "a" (15 * 1)
  61. : "LC1", "LB1", "LT1"
  62. );
  63. #endif
  64. while (1)
  65. #if defined(__ADSPBF60x__)
  66. bfin_write_RCU0_CTL(0x1);
  67. #else
  68. /* Issue core reset */
  69. asm("raise 1");
  70. #endif
  71. }
  72. /* We need to trampoline ourselves up into L1 since our linker
  73. * does not have relaxtion support and will only generate a
  74. * PC relative call with a 25 bit immediate. This is not enough
  75. * to get us from the top of SDRAM into L1.
  76. */
  77. int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[])
  78. {
  79. if (board_reset)
  80. board_reset();
  81. if (ANOMALY_05000353 || ANOMALY_05000386)
  82. while (1)
  83. asm("jump (%0);" : : "a" (bfin_reset));
  84. else
  85. bfrom_SoftReset((void *)(L1_SRAM_SCRATCH_END - 20));
  86. return 0;
  87. }