config-pre.h 3.2 KB

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  1. /*
  2. * config-pre.h - common defines for Blackfin boards in config.h
  3. *
  4. * Copyright (c) 2007-2009 Analog Devices Inc.
  5. *
  6. * Licensed under the GPL-2 or later.
  7. */
  8. #ifndef __ASM_BLACKFIN_CONFIG_PRE_H__
  9. #define __ASM_BLACKFIN_CONFIG_PRE_H__
  10. /* Bootmode defines -- your config needs to select this via CONFIG_BFIN_BOOT_MODE.
  11. * Depending on your cpu, some of these may not be valid, check your HRM.
  12. * The actual values here are meaningless as long as they're unique.
  13. */
  14. #define BFIN_BOOT_BYPASS 1 /* bypass bootrom */
  15. #define BFIN_BOOT_PARA 2 /* boot ldr out of parallel flash */
  16. #define BFIN_BOOT_SPI_MASTER 3 /* boot ldr out of serial flash */
  17. #define BFIN_BOOT_SPI_SLAVE 4 /* boot ldr as spi slave */
  18. #define BFIN_BOOT_TWI_MASTER 5 /* boot ldr over twi device */
  19. #define BFIN_BOOT_TWI_SLAVE 6 /* boot ldr over twi slave */
  20. #define BFIN_BOOT_UART 7 /* boot ldr over uart */
  21. #define BFIN_BOOT_IDLE 8 /* do nothing, just idle */
  22. #define BFIN_BOOT_FIFO 9 /* boot ldr out of FIFO */
  23. #define BFIN_BOOT_MEM 10 /* boot ldr out of memory (warmboot) */
  24. #define BFIN_BOOT_16HOST_DMA 11 /* boot ldr from 16-bit host dma */
  25. #define BFIN_BOOT_8HOST_DMA 12 /* boot ldr from 8-bit host dma */
  26. #define BFIN_BOOT_NAND 13 /* boot ldr from nand flash */
  27. #define BFIN_BOOT_RSI_MASTER 14 /* boot ldr from rsi */
  28. #define BFIN_BOOT_LP_SLAVE 15 /* boot ldr from link port */
  29. #ifndef __ASSEMBLY__
  30. static inline const char *get_bfin_boot_mode(int bfin_boot)
  31. {
  32. switch (bfin_boot) {
  33. case BFIN_BOOT_BYPASS: return "bypass";
  34. case BFIN_BOOT_PARA: return "parallel flash";
  35. case BFIN_BOOT_SPI_MASTER: return "spi flash";
  36. case BFIN_BOOT_SPI_SLAVE: return "spi slave";
  37. case BFIN_BOOT_TWI_MASTER: return "i2c flash";
  38. case BFIN_BOOT_TWI_SLAVE: return "i2c slave";
  39. case BFIN_BOOT_UART: return "uart";
  40. case BFIN_BOOT_IDLE: return "idle";
  41. case BFIN_BOOT_FIFO: return "fifo";
  42. case BFIN_BOOT_MEM: return "memory";
  43. case BFIN_BOOT_16HOST_DMA: return "16bit dma";
  44. case BFIN_BOOT_8HOST_DMA: return "8bit dma";
  45. case BFIN_BOOT_NAND: return "nand flash";
  46. case BFIN_BOOT_RSI_MASTER: return "rsi master";
  47. case BFIN_BOOT_LP_SLAVE: return "link port slave";
  48. default: return "INVALID";
  49. }
  50. }
  51. #endif
  52. /* Most bootroms allow for EVT1 redirection */
  53. #if ((defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__)) \
  54. && __SILICON_REVISION__ < 3) || defined(__ADSPBF561__)
  55. # undef CONFIG_BFIN_BOOTROM_USES_EVT1
  56. #else
  57. # define CONFIG_BFIN_BOOTROM_USES_EVT1
  58. #endif
  59. /* Define the default SPI CS used when booting out of SPI */
  60. #if defined(__ADSPBF531__) || defined(__ADSPBF532__) || defined(__ADSPBF533__) || \
  61. defined(__ADSPBF538__) || defined(__ADSPBF539__) || defined(__ADSPBF561__) || \
  62. defined(__ADSPBF51x__)
  63. # define BFIN_BOOT_SPI_SSEL 2
  64. #else
  65. # define BFIN_BOOT_SPI_SSEL 1
  66. #endif
  67. /* Define to get a GPIO CS with the Blackfin SPI controller */
  68. #define MAX_CTRL_CS 8
  69. /* There is no Blackfin/NetBSD port */
  70. #undef CONFIG_BOOTM_NETBSD
  71. /* We rarely use interrupts, so favor throughput over latency */
  72. #define CONFIG_BFIN_INS_LOWOVERHEAD
  73. #endif