initcode.c 27 KB

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  1. /*
  2. * initcode.c - Initialize the processor. This is usually entails things
  3. * like external memory, voltage regulators, etc... Note that this file
  4. * cannot make any function calls as it may be executed all by itself by
  5. * the Blackfin's bootrom in LDR format.
  6. *
  7. * Copyright (c) 2004-2011 Analog Devices Inc.
  8. *
  9. * Licensed under the GPL-2 or later.
  10. */
  11. #define BFIN_IN_INITCODE
  12. #include <config.h>
  13. #include <asm/blackfin.h>
  14. #include <asm/mach-common/bits/watchdog.h>
  15. #include <asm/mach-common/bits/bootrom.h>
  16. #include <asm/mach-common/bits/core.h>
  17. #include <asm/serial.h>
  18. #ifndef __ADSPBF60x__
  19. #include <asm/mach-common/bits/ebiu.h>
  20. #include <asm/mach-common/bits/pll.h>
  21. #else /* __ADSPBF60x__ */
  22. #include <asm/mach-common/bits/cgu.h>
  23. #define CONFIG_BFIN_GET_DCLK_M \
  24. ((CONFIG_CLKIN_HZ*CONFIG_VCO_MULT)/(CONFIG_DCLK_DIV*1000000))
  25. #ifndef CONFIG_DMC_DDRCFG
  26. #if ((CONFIG_BFIN_GET_DCLK_M != 125) && \
  27. (CONFIG_BFIN_GET_DCLK_M != 133) && \
  28. (CONFIG_BFIN_GET_DCLK_M != 150) && \
  29. (CONFIG_BFIN_GET_DCLK_M != 166) && \
  30. (CONFIG_BFIN_GET_DCLK_M != 200) && \
  31. (CONFIG_BFIN_GET_DCLK_M != 225) && \
  32. (CONFIG_BFIN_GET_DCLK_M != 250))
  33. #error "DDR2 CLK must be in (125, 133, 150, 166, 200, 225, 250)MHz"
  34. #endif
  35. #endif
  36. /* DMC control bits */
  37. #define SRREQ 0x8
  38. /* DMC status bits */
  39. #define IDLE 0x1
  40. #define MEMINITDONE 0x4
  41. #define SRACK 0x8
  42. #define PDACK 0x10
  43. #define DPDACK 0x20
  44. #define DLLCALDONE 0x2000
  45. #define PENDREF 0xF0000
  46. #define PHYRDPHASE 0xF00000
  47. #define PHYRDPHASE_OFFSET 20
  48. /* DMC DLL control bits */
  49. #define DLLCALRDCNT 0xFF
  50. #define DATACYC_OFFSET 8
  51. struct ddr_config {
  52. u32 ddr_clk;
  53. u32 dmc_ddrctl;
  54. u32 dmc_ddrcfg;
  55. u32 dmc_ddrtr0;
  56. u32 dmc_ddrtr1;
  57. u32 dmc_ddrtr2;
  58. u32 dmc_ddrmr;
  59. u32 dmc_ddrmr1;
  60. };
  61. static struct ddr_config ddr_config_table[] = {
  62. [0] = {
  63. .ddr_clk = 125, /* 125MHz */
  64. .dmc_ddrctl = 0x00000904,
  65. .dmc_ddrcfg = 0x00000422,
  66. .dmc_ddrtr0 = 0x20705212,
  67. .dmc_ddrtr1 = 0x201003CF,
  68. .dmc_ddrtr2 = 0x00320107,
  69. .dmc_ddrmr = 0x00000422,
  70. .dmc_ddrmr1 = 0x4,
  71. },
  72. [1] = {
  73. .ddr_clk = 133, /* 133MHz */
  74. .dmc_ddrctl = 0x00000904,
  75. .dmc_ddrcfg = 0x00000422,
  76. .dmc_ddrtr0 = 0x20806313,
  77. .dmc_ddrtr1 = 0x2013040D,
  78. .dmc_ddrtr2 = 0x00320108,
  79. .dmc_ddrmr = 0x00000632,
  80. .dmc_ddrmr1 = 0x4,
  81. },
  82. [2] = {
  83. .ddr_clk = 150, /* 150MHz */
  84. .dmc_ddrctl = 0x00000904,
  85. .dmc_ddrcfg = 0x00000422,
  86. .dmc_ddrtr0 = 0x20A07323,
  87. .dmc_ddrtr1 = 0x20160492,
  88. .dmc_ddrtr2 = 0x00320209,
  89. .dmc_ddrmr = 0x00000632,
  90. .dmc_ddrmr1 = 0x4,
  91. },
  92. [3] = {
  93. .ddr_clk = 166, /* 166MHz */
  94. .dmc_ddrctl = 0x00000904,
  95. .dmc_ddrcfg = 0x00000422,
  96. .dmc_ddrtr0 = 0x20A07323,
  97. .dmc_ddrtr1 = 0x2016050E,
  98. .dmc_ddrtr2 = 0x00320209,
  99. .dmc_ddrmr = 0x00000632,
  100. .dmc_ddrmr1 = 0x4,
  101. },
  102. [4] = {
  103. .ddr_clk = 200, /* 200MHz */
  104. .dmc_ddrctl = 0x00000904,
  105. .dmc_ddrcfg = 0x00000422,
  106. .dmc_ddrtr0 = 0x20a07323,
  107. .dmc_ddrtr1 = 0x2016050f,
  108. .dmc_ddrtr2 = 0x00320509,
  109. .dmc_ddrmr = 0x00000632,
  110. .dmc_ddrmr1 = 0x4,
  111. },
  112. [5] = {
  113. .ddr_clk = 225, /* 225MHz */
  114. .dmc_ddrctl = 0x00000904,
  115. .dmc_ddrcfg = 0x00000422,
  116. .dmc_ddrtr0 = 0x20E0A424,
  117. .dmc_ddrtr1 = 0x302006DB,
  118. .dmc_ddrtr2 = 0x0032020D,
  119. .dmc_ddrmr = 0x00000842,
  120. .dmc_ddrmr1 = 0x4,
  121. },
  122. [6] = {
  123. .ddr_clk = 250, /* 250MHz */
  124. .dmc_ddrctl = 0x00000904,
  125. .dmc_ddrcfg = 0x00000422,
  126. .dmc_ddrtr0 = 0x20E0A424,
  127. .dmc_ddrtr1 = 0x3020079E,
  128. .dmc_ddrtr2 = 0x0032050D,
  129. .dmc_ddrmr = 0x00000842,
  130. .dmc_ddrmr1 = 0x4,
  131. },
  132. };
  133. #endif /* __ADSPBF60x__ */
  134. __attribute__((always_inline))
  135. static inline void serial_init(void)
  136. {
  137. #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
  138. # ifdef BFIN_BOOT_UART_USE_RTS
  139. # define BFIN_UART_USE_RTS 1
  140. # else
  141. # define BFIN_UART_USE_RTS 0
  142. # endif
  143. if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
  144. uint32_t uart_base = UART_BASE;
  145. size_t i;
  146. /* force RTS rather than relying on auto RTS */
  147. #if BFIN_UART_HW_VER < 4
  148. bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) | FCPOL);
  149. #else
  150. bfin_write32(&pUART->control, bfin_read32(&pUART->control) |
  151. FCPOL);
  152. #endif
  153. /* Wait for the line to clear up. We cannot rely on UART
  154. * registers as none of them reflect the status of the RSR.
  155. * Instead, we'll sleep for ~10 bit times at 9600 baud.
  156. * We can precalc things here by assuming boot values for
  157. * PLL rather than loading registers and calculating.
  158. * baud = SCLK / (16 ^ (1 - EDBO) * Divisor)
  159. * EDB0 = 0
  160. * Divisor = (SCLK / baud) / 16
  161. * SCLK = baud * 16 * Divisor
  162. * SCLK = (0x14 * CONFIG_CLKIN_HZ) / 5
  163. * CCLK = (16 * Divisor * 5) * (9600 / 10)
  164. * In reality, this will probably be just about 1 second delay,
  165. * so assuming 9600 baud is OK (both as a very low and too high
  166. * speed as this will buffer things enough).
  167. */
  168. #define _NUMBITS (10) /* how many bits to delay */
  169. #define _LOWBAUD (9600) /* low baud rate */
  170. #define _SCLK ((0x14 * CONFIG_CLKIN_HZ) / 5) /* SCLK based on PLL */
  171. #define _DIVISOR ((_SCLK / _LOWBAUD) / 16) /* UART DLL/DLH */
  172. #define _NUMINS (3) /* how many instructions in loop */
  173. #define _CCLK (((16 * _DIVISOR * 5) * (_LOWBAUD / _NUMBITS)) / _NUMINS)
  174. i = _CCLK;
  175. while (i--)
  176. asm volatile("" : : : "memory");
  177. }
  178. #endif
  179. #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS
  180. if (BFIN_DEBUG_EARLY_SERIAL) {
  181. serial_early_init(UART_BASE);
  182. serial_early_set_baud(UART_BASE, CONFIG_BAUDRATE);
  183. }
  184. #endif
  185. }
  186. __attribute__((always_inline))
  187. static inline void serial_deinit(void)
  188. {
  189. #if defined(__ADSPBF54x__) || defined(__ADSPBF60x__)
  190. uint32_t uart_base = UART_BASE;
  191. if (BFIN_UART_USE_RTS && CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
  192. /* clear forced RTS rather than relying on auto RTS */
  193. #if BFIN_UART_HW_VER < 4
  194. bfin_write16(&pUART->mcr, bfin_read16(&pUART->mcr) & ~FCPOL);
  195. #else
  196. bfin_write32(&pUART->control, bfin_read32(&pUART->control) &
  197. ~FCPOL);
  198. #endif
  199. }
  200. #endif
  201. }
  202. __attribute__((always_inline))
  203. static inline void serial_putc(char c)
  204. {
  205. uint32_t uart_base = UART_BASE;
  206. if (!BFIN_DEBUG_EARLY_SERIAL)
  207. return;
  208. if (c == '\n')
  209. serial_putc('\r');
  210. bfin_write(&pUART->thr, c);
  211. while (!(_lsr_read(pUART) & TEMT))
  212. continue;
  213. }
  214. #include "initcode.h"
  215. __attribute__((always_inline)) static inline void
  216. program_nmi_handler(void)
  217. {
  218. u32 tmp1, tmp2;
  219. /* Older bootroms don't create a dummy NMI handler,
  220. * so make one ourselves ASAP in case it fires.
  221. */
  222. if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS && !ANOMALY_05000219)
  223. return;
  224. asm volatile (
  225. "%0 = RETS;" /* Save current RETS */
  226. "CALL 1f;" /* Figure out current PC */
  227. "RTN;" /* The simple NMI handler */
  228. "1:"
  229. "%1 = RETS;" /* Load addr of NMI handler */
  230. "RETS = %0;" /* Restore RETS */
  231. "[%2] = %1;" /* Write NMI handler */
  232. : "=d"(tmp1), "=d"(tmp2)
  233. : "ab"(EVT2)
  234. );
  235. }
  236. /* Max SCLK can be 133MHz ... dividing that by (2*4) gives
  237. * us a freq of 16MHz for SPI which should generally be
  238. * slow enough for the slow reads the bootrom uses.
  239. */
  240. #if !defined(CONFIG_SPI_FLASH_SLOW_READ) && \
  241. ((defined(__ADSPBF52x__) && __SILICON_REVISION__ >= 2) || \
  242. (defined(__ADSPBF54x__) && __SILICON_REVISION__ >= 1))
  243. # define BOOTROM_SUPPORTS_SPI_FAST_READ 1
  244. #else
  245. # define BOOTROM_SUPPORTS_SPI_FAST_READ 0
  246. #endif
  247. #ifndef CONFIG_SPI_BAUD_INITBLOCK
  248. # define CONFIG_SPI_BAUD_INITBLOCK (BOOTROM_SUPPORTS_SPI_FAST_READ ? 2 : 4)
  249. #endif
  250. #ifdef SPI0_BAUD
  251. # define bfin_write_SPI_BAUD bfin_write_SPI0_BAUD
  252. #endif
  253. #ifdef __ADSPBF60x__
  254. #ifndef CONFIG_CGU_CTL_VAL
  255. # define CONFIG_CGU_CTL_VAL ((CONFIG_VCO_MULT << 8) | CONFIG_CLKIN_HALF)
  256. #endif
  257. #ifndef CONFIG_CGU_DIV_VAL
  258. # define CONFIG_CGU_DIV_VAL \
  259. ((CONFIG_CCLK_DIV << CSEL_P) | \
  260. (CONFIG_SCLK0_DIV << S0SEL_P) | \
  261. (CONFIG_SCLK_DIV << SYSSEL_P) | \
  262. (CONFIG_SCLK1_DIV << S1SEL_P) | \
  263. (CONFIG_DCLK_DIV << DSEL_P) | \
  264. (CONFIG_OCLK_DIV << OSEL_P))
  265. #endif
  266. #else /* __ADSPBF60x__ */
  267. /* PLL_DIV defines */
  268. #ifndef CONFIG_PLL_DIV_VAL
  269. # if (CONFIG_CCLK_DIV == 1)
  270. # define CONFIG_CCLK_ACT_DIV CCLK_DIV1
  271. # elif (CONFIG_CCLK_DIV == 2)
  272. # define CONFIG_CCLK_ACT_DIV CCLK_DIV2
  273. # elif (CONFIG_CCLK_DIV == 4)
  274. # define CONFIG_CCLK_ACT_DIV CCLK_DIV4
  275. # elif (CONFIG_CCLK_DIV == 8)
  276. # define CONFIG_CCLK_ACT_DIV CCLK_DIV8
  277. # else
  278. # define CONFIG_CCLK_ACT_DIV CONFIG_CCLK_DIV_not_defined_properly
  279. # endif
  280. # define CONFIG_PLL_DIV_VAL (CONFIG_CCLK_ACT_DIV | CONFIG_SCLK_DIV)
  281. #endif
  282. #ifndef CONFIG_PLL_LOCKCNT_VAL
  283. # define CONFIG_PLL_LOCKCNT_VAL 0x0300
  284. #endif
  285. #ifndef CONFIG_PLL_CTL_VAL
  286. # define CONFIG_PLL_CTL_VAL (SPORT_HYST | (CONFIG_VCO_MULT << 9) | CONFIG_CLKIN_HALF)
  287. #endif
  288. /* Make sure our voltage value is sane so we don't blow up! */
  289. #ifndef CONFIG_VR_CTL_VAL
  290. # define BFIN_CCLK ((CONFIG_CLKIN_HZ * CONFIG_VCO_MULT) / CONFIG_CCLK_DIV)
  291. # if defined(__ADSPBF533__) || defined(__ADSPBF532__) || defined(__ADSPBF531__)
  292. # define CCLK_VLEV_120 400000000
  293. # define CCLK_VLEV_125 533000000
  294. # elif defined(__ADSPBF537__) || defined(__ADSPBF536__) || defined(__ADSPBF534__)
  295. # define CCLK_VLEV_120 401000000
  296. # define CCLK_VLEV_125 401000000
  297. # elif defined(__ADSPBF561__)
  298. # define CCLK_VLEV_120 300000000
  299. # define CCLK_VLEV_125 501000000
  300. # endif
  301. # if BFIN_CCLK < CCLK_VLEV_120
  302. # define CONFIG_VR_CTL_VLEV VLEV_120
  303. # elif BFIN_CCLK < CCLK_VLEV_125
  304. # define CONFIG_VR_CTL_VLEV VLEV_125
  305. # else
  306. # define CONFIG_VR_CTL_VLEV VLEV_130
  307. # endif
  308. # if defined(__ADSPBF52x__) /* TBD; use default */
  309. # undef CONFIG_VR_CTL_VLEV
  310. # define CONFIG_VR_CTL_VLEV VLEV_110
  311. # elif defined(__ADSPBF54x__) /* TBD; use default */
  312. # undef CONFIG_VR_CTL_VLEV
  313. # define CONFIG_VR_CTL_VLEV VLEV_120
  314. # elif defined(__ADSPBF538__) || defined(__ADSPBF539__) /* TBD; use default */
  315. # undef CONFIG_VR_CTL_VLEV
  316. # define CONFIG_VR_CTL_VLEV VLEV_125
  317. # endif
  318. # ifdef CONFIG_BFIN_MAC
  319. # define CONFIG_VR_CTL_CLKBUF CLKBUFOE
  320. # else
  321. # define CONFIG_VR_CTL_CLKBUF 0
  322. # endif
  323. # if defined(__ADSPBF52x__)
  324. # define CONFIG_VR_CTL_FREQ FREQ_1000
  325. # else
  326. # define CONFIG_VR_CTL_FREQ (GAIN_20 | FREQ_1000)
  327. # endif
  328. # define CONFIG_VR_CTL_VAL (CONFIG_VR_CTL_CLKBUF | CONFIG_VR_CTL_VLEV | CONFIG_VR_CTL_FREQ)
  329. #endif
  330. /* some parts do not have an on-chip voltage regulator */
  331. #if defined(__ADSPBF51x__)
  332. # define CONFIG_HAS_VR 0
  333. # undef CONFIG_VR_CTL_VAL
  334. # define CONFIG_VR_CTL_VAL 0
  335. #else
  336. # define CONFIG_HAS_VR 1
  337. #endif
  338. #if CONFIG_MEM_SIZE
  339. #ifndef EBIU_RSTCTL
  340. /* Blackfin with SDRAM */
  341. #ifndef CONFIG_EBIU_SDBCTL_VAL
  342. # if CONFIG_MEM_SIZE == 16
  343. # define CONFIG_EBSZ_VAL EBSZ_16
  344. # elif CONFIG_MEM_SIZE == 32
  345. # define CONFIG_EBSZ_VAL EBSZ_32
  346. # elif CONFIG_MEM_SIZE == 64
  347. # define CONFIG_EBSZ_VAL EBSZ_64
  348. # elif CONFIG_MEM_SIZE == 128
  349. # define CONFIG_EBSZ_VAL EBSZ_128
  350. # elif CONFIG_MEM_SIZE == 256
  351. # define CONFIG_EBSZ_VAL EBSZ_256
  352. # elif CONFIG_MEM_SIZE == 512
  353. # define CONFIG_EBSZ_VAL EBSZ_512
  354. # else
  355. # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_SIZE
  356. # endif
  357. # if CONFIG_MEM_ADD_WDTH == 8
  358. # define CONFIG_EBCAW_VAL EBCAW_8
  359. # elif CONFIG_MEM_ADD_WDTH == 9
  360. # define CONFIG_EBCAW_VAL EBCAW_9
  361. # elif CONFIG_MEM_ADD_WDTH == 10
  362. # define CONFIG_EBCAW_VAL EBCAW_10
  363. # elif CONFIG_MEM_ADD_WDTH == 11
  364. # define CONFIG_EBCAW_VAL EBCAW_11
  365. # else
  366. # error You need to define CONFIG_EBIU_SDBCTL_VAL or CONFIG_MEM_ADD_WDTH
  367. # endif
  368. # define CONFIG_EBIU_SDBCTL_VAL (CONFIG_EBCAW_VAL | CONFIG_EBSZ_VAL | EBE)
  369. #endif
  370. #endif
  371. #endif
  372. /* Conflicting Column Address Widths Causes SDRAM Errors:
  373. * EB2CAW and EB3CAW must be the same
  374. */
  375. #if ANOMALY_05000362
  376. # if ((CONFIG_EBIU_SDBCTL_VAL & 0x30000000) >> 8) != (CONFIG_EBIU_SDBCTL_VAL & 0x00300000)
  377. # error "Anomaly 05000362: EB2CAW and EB3CAW must be the same"
  378. # endif
  379. #endif
  380. #endif /* __ADSPBF60x__ */
  381. __attribute__((always_inline)) static inline void
  382. program_early_devices(ADI_BOOT_DATA *bs, uint *sdivB, uint *divB, uint *vcoB)
  383. {
  384. serial_putc('a');
  385. /* Save the clock pieces that are used in baud rate calculation */
  386. if (BFIN_DEBUG_EARLY_SERIAL || CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
  387. serial_putc('b');
  388. #ifdef __ADSPBF60x__
  389. *sdivB = bfin_read_CGU_DIV();
  390. *sdivB = ((*sdivB >> 8) & 0x1f) * ((*sdivB >> 5) & 0x7);
  391. *vcoB = (bfin_read_CGU_CTL() >> 8) & 0x7f;
  392. #else
  393. *sdivB = bfin_read_PLL_DIV() & 0xf;
  394. *vcoB = (bfin_read_PLL_CTL() >> 9) & 0x3f;
  395. #endif
  396. *divB = serial_early_get_div();
  397. serial_putc('c');
  398. }
  399. serial_putc('d');
  400. #ifdef CONFIG_HW_WATCHDOG
  401. # ifndef CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE
  402. # define CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE 20000
  403. # endif
  404. /* Program the watchdog with an initial timeout of ~20 seconds.
  405. * Hopefully that should be long enough to load the u-boot LDR
  406. * (from wherever) and then the common u-boot code can take over.
  407. * In bypass mode, the start.S would have already set a much lower
  408. * timeout, so don't clobber that.
  409. */
  410. if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS) {
  411. serial_putc('e');
  412. #ifdef __ADSPBF60x__
  413. /* Reset system event controller */
  414. bfin_write_SEC_GCTL(0x2);
  415. bfin_write_SEC_CCTL(0x2);
  416. SSYNC();
  417. /* Enable fault event input and system reset action in fault
  418. * controller. Route watchdog timeout event to fault interface.
  419. */
  420. bfin_write_SEC_FCTL(0xc1);
  421. /* Enable watchdog interrupt source */
  422. bfin_write_SEC_SCTL(2, bfin_read_SEC_SCTL(2) | 0x6);
  423. SSYNC();
  424. /* Enable system event controller */
  425. bfin_write_SEC_GCTL(0x1);
  426. bfin_write_SEC_CCTL(0x1);
  427. SSYNC();
  428. #endif
  429. bfin_write_WDOG_CTL(WDDIS);
  430. SSYNC();
  431. bfin_write_WDOG_CNT(MSEC_TO_SCLK(CONFIG_HW_WATCHDOG_TIMEOUT_INITCODE));
  432. #if CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_UART
  433. bfin_write_WDOG_CTL(WDEN);
  434. #endif
  435. serial_putc('f');
  436. }
  437. #endif
  438. serial_putc('g');
  439. /* Blackfin bootroms use the SPI slow read opcode instead of the SPI
  440. * fast read, so we need to slow down the SPI clock a lot more during
  441. * boot. Once we switch over to u-boot's SPI flash driver, we'll
  442. * increase the speed appropriately.
  443. */
  444. #ifdef SPI_BAUD
  445. if (CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_SPI_MASTER) {
  446. serial_putc('h');
  447. if (BOOTROM_SUPPORTS_SPI_FAST_READ && CONFIG_SPI_BAUD_INITBLOCK < 4)
  448. bs->dFlags |= BFLAG_FASTREAD;
  449. bfin_write_SPI_BAUD(CONFIG_SPI_BAUD_INITBLOCK);
  450. serial_putc('i');
  451. }
  452. #endif
  453. serial_putc('j');
  454. }
  455. __attribute__((always_inline)) static inline bool
  456. maybe_self_refresh(ADI_BOOT_DATA *bs)
  457. {
  458. serial_putc('a');
  459. if (!CONFIG_MEM_SIZE)
  460. return false;
  461. #ifdef __ADSPBF60x__
  462. /* resume from hibernate, return false let ddr initialize */
  463. if ((bfin_read32(DPM0_STAT) & 0xF0) == 0x50) {
  464. serial_putc('b');
  465. return false;
  466. }
  467. #else /* __ADSPBF60x__ */
  468. /* If external memory is enabled, put it into self refresh first. */
  469. #if defined(EBIU_RSTCTL)
  470. if (bfin_read_EBIU_RSTCTL() & DDR_SRESET) {
  471. serial_putc('b');
  472. bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | SRREQ);
  473. return true;
  474. }
  475. #elif defined(EBIU_SDGCTL)
  476. if (bfin_read_EBIU_SDBCTL() & EBE) {
  477. serial_putc('b');
  478. bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() | SRFS);
  479. return true;
  480. }
  481. #endif
  482. #endif /* __ADSPBF60x__ */
  483. serial_putc('c');
  484. return false;
  485. }
  486. __attribute__((always_inline)) static inline u16
  487. program_clocks(ADI_BOOT_DATA *bs, bool put_into_srfs)
  488. {
  489. u16 vr_ctl = 0;
  490. serial_putc('a');
  491. #ifdef __ADSPBF60x__
  492. if (bfin_read_DMC0_STAT() & MEMINITDONE) {
  493. bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() | SRREQ);
  494. SSYNC();
  495. while (!(bfin_read_DMC0_STAT() & SRACK))
  496. continue;
  497. }
  498. /* Don't set the same value of MSEL and DF to CGU_CTL */
  499. if ((bfin_read_CGU_CTL() & (MSEL_MASK | DF_MASK))
  500. != CONFIG_CGU_CTL_VAL) {
  501. bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL);
  502. bfin_write_CGU_CTL(CONFIG_CGU_CTL_VAL);
  503. while ((bfin_read_CGU_STAT() & (CLKSALGN | PLLBP)) ||
  504. !(bfin_read_CGU_STAT() & PLLLK))
  505. continue;
  506. }
  507. bfin_write_CGU_DIV(CONFIG_CGU_DIV_VAL | UPDT);
  508. while (bfin_read_CGU_STAT() & CLKSALGN)
  509. continue;
  510. if (bfin_read_DMC0_STAT() & MEMINITDONE) {
  511. bfin_write_DMC0_CTL(bfin_read_DMC0_CTL() & ~SRREQ);
  512. SSYNC();
  513. while (bfin_read_DMC0_STAT() & SRACK)
  514. continue;
  515. }
  516. #else /* __ADSPBF60x__ */
  517. vr_ctl = bfin_read_VR_CTL();
  518. serial_putc('b');
  519. /* If we're entering self refresh, make sure it has happened. */
  520. if (put_into_srfs)
  521. #if defined(EBIU_RSTCTL)
  522. while (!(bfin_read_EBIU_RSTCTL() & SRACK))
  523. continue;
  524. #elif defined(EBIU_SDGCTL)
  525. while (!(bfin_read_EBIU_SDSTAT() & SDSRA))
  526. continue;
  527. #else
  528. ;
  529. #endif
  530. serial_putc('c');
  531. /* With newer bootroms, we use the helper function to set up
  532. * the memory controller. Older bootroms lacks such helpers
  533. * so we do it ourselves.
  534. */
  535. if (!ANOMALY_05000386) {
  536. serial_putc('d');
  537. /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
  538. ADI_SYSCTRL_VALUES memory_settings;
  539. uint32_t actions = SYSCTRL_WRITE | SYSCTRL_PLLCTL | SYSCTRL_LOCKCNT;
  540. if (!ANOMALY_05000440)
  541. actions |= SYSCTRL_PLLDIV;
  542. if (CONFIG_HAS_VR) {
  543. actions |= SYSCTRL_VRCTL;
  544. if (CONFIG_VR_CTL_VAL & FREQ_MASK)
  545. actions |= SYSCTRL_INTVOLTAGE;
  546. else
  547. actions |= SYSCTRL_EXTVOLTAGE;
  548. memory_settings.uwVrCtl = CONFIG_VR_CTL_VAL;
  549. } else
  550. actions |= SYSCTRL_EXTVOLTAGE;
  551. memory_settings.uwPllCtl = CONFIG_PLL_CTL_VAL;
  552. memory_settings.uwPllDiv = CONFIG_PLL_DIV_VAL;
  553. memory_settings.uwPllLockCnt = CONFIG_PLL_LOCKCNT_VAL;
  554. #if ANOMALY_05000432
  555. bfin_write_SIC_IWR1(0);
  556. #endif
  557. serial_putc('e');
  558. bfrom_SysControl(actions, &memory_settings, NULL);
  559. serial_putc('f');
  560. if (ANOMALY_05000440)
  561. bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
  562. #if ANOMALY_05000432
  563. bfin_write_SIC_IWR1(-1);
  564. #endif
  565. #if ANOMALY_05000171
  566. bfin_write_SICA_IWR0(-1);
  567. bfin_write_SICA_IWR1(-1);
  568. #endif
  569. serial_putc('g');
  570. } else {
  571. serial_putc('h');
  572. /* Disable all peripheral wakeups except for the PLL event. */
  573. #ifdef SIC_IWR0
  574. bfin_write_SIC_IWR0(1);
  575. bfin_write_SIC_IWR1(0);
  576. # ifdef SIC_IWR2
  577. bfin_write_SIC_IWR2(0);
  578. # endif
  579. #elif defined(SICA_IWR0)
  580. bfin_write_SICA_IWR0(1);
  581. bfin_write_SICA_IWR1(0);
  582. #elif defined(SIC_IWR)
  583. bfin_write_SIC_IWR(1);
  584. #endif
  585. serial_putc('i');
  586. /* Always programming PLL_LOCKCNT avoids Anomaly 05000430 */
  587. bfin_write_PLL_LOCKCNT(CONFIG_PLL_LOCKCNT_VAL);
  588. serial_putc('j');
  589. /* Only reprogram when needed to avoid triggering unnecessary
  590. * PLL relock sequences.
  591. */
  592. if (vr_ctl != CONFIG_VR_CTL_VAL) {
  593. serial_putc('?');
  594. bfin_write_VR_CTL(CONFIG_VR_CTL_VAL);
  595. asm("idle;");
  596. serial_putc('!');
  597. }
  598. serial_putc('k');
  599. bfin_write_PLL_DIV(CONFIG_PLL_DIV_VAL);
  600. serial_putc('l');
  601. /* Only reprogram when needed to avoid triggering unnecessary
  602. * PLL relock sequences.
  603. */
  604. if (ANOMALY_05000242 || bfin_read_PLL_CTL() != CONFIG_PLL_CTL_VAL) {
  605. serial_putc('?');
  606. bfin_write_PLL_CTL(CONFIG_PLL_CTL_VAL);
  607. asm("idle;");
  608. serial_putc('!');
  609. }
  610. serial_putc('m');
  611. /* Restore all peripheral wakeups. */
  612. #ifdef SIC_IWR0
  613. bfin_write_SIC_IWR0(-1);
  614. bfin_write_SIC_IWR1(-1);
  615. # ifdef SIC_IWR2
  616. bfin_write_SIC_IWR2(-1);
  617. # endif
  618. #elif defined(SICA_IWR0)
  619. bfin_write_SICA_IWR0(-1);
  620. bfin_write_SICA_IWR1(-1);
  621. #elif defined(SIC_IWR)
  622. bfin_write_SIC_IWR(-1);
  623. #endif
  624. serial_putc('n');
  625. }
  626. #endif /* __ADSPBF60x__ */
  627. serial_putc('o');
  628. return vr_ctl;
  629. }
  630. __attribute__((always_inline)) static inline void
  631. update_serial_clocks(ADI_BOOT_DATA *bs, uint sdivB, uint divB, uint vcoB)
  632. {
  633. /* Since we've changed the SCLK above, we may need to update
  634. * the UART divisors (UART baud rates are based on SCLK).
  635. * Do the division by hand as there are no native instructions
  636. * for dividing which means we'd generate a libgcc reference.
  637. */
  638. unsigned int sdivR, vcoR;
  639. unsigned int dividend;
  640. unsigned int divisor;
  641. unsigned int quotient;
  642. serial_putc('a');
  643. if (BFIN_DEBUG_EARLY_SERIAL ||
  644. CONFIG_BFIN_BOOT_MODE == BFIN_BOOT_UART) {
  645. #ifdef __ADSPBF60x__
  646. sdivR = bfin_read_CGU_DIV();
  647. sdivR = ((sdivR >> 8) & 0x1f) * ((sdivR >> 5) & 0x7);
  648. vcoR = (bfin_read_CGU_CTL() >> 8) & 0x7f;
  649. #else
  650. sdivR = bfin_read_PLL_DIV() & 0xf;
  651. vcoR = (bfin_read_PLL_CTL() >> 9) & 0x3f;
  652. #endif
  653. dividend = sdivB * divB * vcoR;
  654. divisor = vcoB * sdivR;
  655. quotient = early_division(dividend, divisor);
  656. serial_early_put_div(quotient - ANOMALY_05000230);
  657. }
  658. serial_putc('c');
  659. }
  660. __attribute__((always_inline)) static inline void
  661. program_memory_controller(ADI_BOOT_DATA *bs, bool put_into_srfs)
  662. {
  663. serial_putc('a');
  664. if (!CONFIG_MEM_SIZE)
  665. return;
  666. serial_putc('b');
  667. #ifdef __ADSPBF60x__
  668. int dlldatacycle;
  669. int dll_ctl;
  670. int i = 0;
  671. if (CONFIG_BFIN_GET_DCLK_M == 125)
  672. i = 0;
  673. else if (CONFIG_BFIN_GET_DCLK_M == 133)
  674. i = 1;
  675. else if (CONFIG_BFIN_GET_DCLK_M == 150)
  676. i = 2;
  677. else if (CONFIG_BFIN_GET_DCLK_M == 166)
  678. i = 3;
  679. else if (CONFIG_BFIN_GET_DCLK_M == 200)
  680. i = 4;
  681. else if (CONFIG_BFIN_GET_DCLK_M == 225)
  682. i = 5;
  683. else if (CONFIG_BFIN_GET_DCLK_M == 250)
  684. i = 6;
  685. #if 0
  686. for (i = 0; i < ARRAY_SIZE(ddr_config_table); i++)
  687. if (CONFIG_BFIN_GET_DCLK_M == ddr_config_table[i].ddr_clk)
  688. break;
  689. #endif
  690. #ifndef CONFIG_DMC_DDRCFG
  691. bfin_write_DMC0_CFG(ddr_config_table[i].dmc_ddrcfg);
  692. #else
  693. bfin_write_DMC0_CFG(CONFIG_DMC_DDRCFG);
  694. #endif
  695. #ifndef CONFIG_DMC_DDRTR0
  696. bfin_write_DMC0_TR0(ddr_config_table[i].dmc_ddrtr0);
  697. #else
  698. bfin_write_DMC0_TR0(CONFIG_DMC_DDRTR0);
  699. #endif
  700. #ifndef CONFIG_DMC_DDRTR1
  701. bfin_write_DMC0_TR1(ddr_config_table[i].dmc_ddrtr1);
  702. #else
  703. bfin_write_DMC0_TR1(CONFIG_DMC_DDRTR1);
  704. #endif
  705. #ifndef CONFIG_DMC_DDRTR2
  706. bfin_write_DMC0_TR2(ddr_config_table[i].dmc_ddrtr2);
  707. #else
  708. bfin_write_DMC0_TR2(CONFIG_DMC_DDRTR2);
  709. #endif
  710. #ifndef CONFIG_DMC_DDRMR
  711. bfin_write_DMC0_MR(ddr_config_table[i].dmc_ddrmr);
  712. #else
  713. bfin_write_DMC0_MR(CONFIG_DMC_DDRMR);
  714. #endif
  715. #ifndef CONFIG_DMC_DDREMR1
  716. bfin_write_DMC0_EMR1(ddr_config_table[i].dmc_ddrmr1);
  717. #else
  718. bfin_write_DMC0_EMR1(CONFIG_DMC_DDREMR1);
  719. #endif
  720. #ifndef CONFIG_DMC_DDRCTL
  721. bfin_write_DMC0_CTL(ddr_config_table[i].dmc_ddrctl);
  722. #else
  723. bfin_write_DMC0_CTL(CONFIG_DMC_DDRCTL);
  724. #endif
  725. SSYNC();
  726. while (!(bfin_read_DMC0_STAT() & MEMINITDONE))
  727. continue;
  728. dlldatacycle = (bfin_read_DMC0_STAT() & PHYRDPHASE) >>
  729. PHYRDPHASE_OFFSET;
  730. dll_ctl = bfin_read_DMC0_DLLCTL();
  731. dll_ctl &= 0x0ff;
  732. bfin_write_DMC0_DLLCTL(dll_ctl | (dlldatacycle << DATACYC_OFFSET));
  733. SSYNC();
  734. while (!(bfin_read_DMC0_STAT() & DLLCALDONE))
  735. continue;
  736. serial_putc('!');
  737. #else /* __ADSPBF60x__ */
  738. /* Program the external memory controller before we come out of
  739. * self-refresh. This only works with our SDRAM controller.
  740. */
  741. #ifdef EBIU_SDGCTL
  742. # ifdef CONFIG_EBIU_SDRRC_VAL
  743. bfin_write_EBIU_SDRRC(CONFIG_EBIU_SDRRC_VAL);
  744. # endif
  745. # ifdef CONFIG_EBIU_SDBCTL_VAL
  746. bfin_write_EBIU_SDBCTL(CONFIG_EBIU_SDBCTL_VAL);
  747. # endif
  748. # ifdef CONFIG_EBIU_SDGCTL_VAL
  749. bfin_write_EBIU_SDGCTL(CONFIG_EBIU_SDGCTL_VAL);
  750. # endif
  751. #endif
  752. serial_putc('c');
  753. /* Now that we've reprogrammed, take things out of self refresh. */
  754. if (put_into_srfs)
  755. #if defined(EBIU_RSTCTL)
  756. bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() & ~(SRREQ));
  757. #elif defined(EBIU_SDGCTL)
  758. bfin_write_EBIU_SDGCTL(bfin_read_EBIU_SDGCTL() & ~(SRFS));
  759. #endif
  760. serial_putc('d');
  761. /* Our DDR controller sucks and cannot be programmed while in
  762. * self-refresh. So we have to pull it out before programming.
  763. */
  764. #ifdef EBIU_RSTCTL
  765. # ifdef CONFIG_EBIU_RSTCTL_VAL
  766. bfin_write_EBIU_RSTCTL(bfin_read_EBIU_RSTCTL() | 0x1 /*DDRSRESET*/ | CONFIG_EBIU_RSTCTL_VAL);
  767. # endif
  768. # ifdef CONFIG_EBIU_DDRCTL0_VAL
  769. bfin_write_EBIU_DDRCTL0(CONFIG_EBIU_DDRCTL0_VAL);
  770. # endif
  771. # ifdef CONFIG_EBIU_DDRCTL1_VAL
  772. bfin_write_EBIU_DDRCTL1(CONFIG_EBIU_DDRCTL1_VAL);
  773. # endif
  774. # ifdef CONFIG_EBIU_DDRCTL2_VAL
  775. bfin_write_EBIU_DDRCTL2(CONFIG_EBIU_DDRCTL2_VAL);
  776. # endif
  777. # ifdef CONFIG_EBIU_DDRCTL3_VAL
  778. /* default is disable, so don't need to force this */
  779. bfin_write_EBIU_DDRCTL3(CONFIG_EBIU_DDRCTL3_VAL);
  780. # endif
  781. # ifdef CONFIG_EBIU_DDRQUE_VAL
  782. bfin_write_EBIU_DDRQUE(bfin_read_EBIU_DDRQUE() | CONFIG_EBIU_DDRQUE_VAL);
  783. # endif
  784. #endif
  785. #endif /* __ADSPBF60x__ */
  786. serial_putc('e');
  787. }
  788. __attribute__((always_inline)) static inline void
  789. check_hibernation(ADI_BOOT_DATA *bs, u16 vr_ctl, bool put_into_srfs)
  790. {
  791. serial_putc('a');
  792. if (!CONFIG_MEM_SIZE)
  793. return;
  794. serial_putc('b');
  795. #ifdef __ADSPBF60x__
  796. if (bfin_read32(DPM0_RESTORE0) != 0) {
  797. uint32_t reg = bfin_read_DMC0_CTL();
  798. reg &= ~0x8;
  799. bfin_write_DMC0_CTL(reg);
  800. while ((bfin_read_DMC0_STAT() & 0x8))
  801. continue;
  802. while (!(bfin_read_DMC0_STAT() & 0x1))
  803. continue;
  804. serial_putc('z');
  805. uint32_t *hibernate_magic =
  806. (uint32_t *)bfin_read32(DPM0_RESTORE4);
  807. SSYNC(); /* make sure memory controller is done */
  808. if (hibernate_magic[0] == 0xDEADBEEF) {
  809. serial_putc('c');
  810. SSYNC();
  811. bfin_write_EVT15(hibernate_magic[1]);
  812. bfin_write_IMASK(EVT_IVG15);
  813. __asm__ __volatile__ (
  814. /* load reti early to avoid anomaly 281 */
  815. "reti = %2;"
  816. /* clear hibernate magic */
  817. "[%0] = %1;"
  818. /* load stack pointer */
  819. "SP = [%0 + 8];"
  820. /* lower ourselves from reset ivg to ivg15 */
  821. "raise 15;"
  822. "nop;nop;nop;"
  823. "rti;"
  824. :
  825. : "p"(hibernate_magic),
  826. "d"(0x2000 /* jump.s 0 */),
  827. "d"(0xffa00000)
  828. );
  829. }
  830. }
  831. #else
  832. /* Are we coming out of hibernate (suspend to memory) ?
  833. * The memory layout is:
  834. * 0x0: hibernate magic for anomaly 307 (0xDEADBEEF)
  835. * 0x4: return address
  836. * 0x8: stack pointer
  837. *
  838. * SCKELOW is unreliable on older parts (anomaly 307)
  839. */
  840. if (ANOMALY_05000307 || vr_ctl & 0x8000) {
  841. uint32_t *hibernate_magic = 0;
  842. SSYNC();
  843. /* cppcheck-suppress nullPointer */
  844. if (hibernate_magic[0] == 0xDEADBEEF) {
  845. serial_putc('c');
  846. bfin_write_EVT15(hibernate_magic[1]);
  847. bfin_write_IMASK(EVT_IVG15);
  848. __asm__ __volatile__ (
  849. /* load reti early to avoid anomaly 281 */
  850. "reti = %0;"
  851. /* clear hibernate magic */
  852. "[%0] = %1;"
  853. /* load stack pointer */
  854. "SP = [%0 + 8];"
  855. /* lower ourselves from reset ivg to ivg15 */
  856. "raise 15;"
  857. "rti;"
  858. :
  859. : "p"(hibernate_magic), "d"(0x2000 /* jump.s 0 */)
  860. );
  861. }
  862. serial_putc('d');
  863. }
  864. #endif
  865. serial_putc('e');
  866. }
  867. BOOTROM_CALLED_FUNC_ATTR
  868. void initcode(ADI_BOOT_DATA *bs)
  869. {
  870. ADI_BOOT_DATA bootstruct_scratch;
  871. /* Setup NMI handler before anything else */
  872. program_nmi_handler();
  873. serial_init();
  874. serial_putc('A');
  875. /* If the bootstruct is NULL, then it's because we're loading
  876. * dynamically and not via LDR (bootrom). So set the struct to
  877. * some scratch space.
  878. */
  879. if (!bs)
  880. bs = &bootstruct_scratch;
  881. serial_putc('B');
  882. bool put_into_srfs = maybe_self_refresh(bs);
  883. serial_putc('C');
  884. uint sdivB, divB, vcoB;
  885. program_early_devices(bs, &sdivB, &divB, &vcoB);
  886. serial_putc('D');
  887. u16 vr_ctl = program_clocks(bs, put_into_srfs);
  888. serial_putc('E');
  889. update_serial_clocks(bs, sdivB, divB, vcoB);
  890. serial_putc('F');
  891. program_memory_controller(bs, put_into_srfs);
  892. serial_putc('G');
  893. check_hibernation(bs, vr_ctl, put_into_srfs);
  894. serial_putc('H');
  895. program_async_controller(bs);
  896. #ifdef CONFIG_BFIN_BOOTROM_USES_EVT1
  897. serial_putc('I');
  898. /* Tell the bootrom where our entry point is so that it knows
  899. * where to jump to when finishing processing the LDR. This
  900. * allows us to avoid small jump blocks in the LDR, and also
  901. * works around anomaly 05000389 (init address in external
  902. * memory causes bootrom to trigger external addressing IVHW).
  903. */
  904. if (CONFIG_BFIN_BOOT_MODE != BFIN_BOOT_BYPASS)
  905. bfin_write_EVT1(CONFIG_SYS_MONITOR_BASE);
  906. #endif
  907. serial_putc('>');
  908. serial_putc('\n');
  909. serial_deinit();
  910. }