anomaly.h 6.6 KB

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  1. /*
  2. * DO NOT EDIT THIS FILE
  3. * This file is under version control at
  4. * svn://sources.blackfin.uclinux.org/toolchain/trunk/proc-defs/header-frags/
  5. * and can be replaced with that version at any time
  6. * DO NOT EDIT THIS FILE
  7. *
  8. * Copyright 2004-2011 Analog Devices Inc.
  9. * Licensed under the ADI BSD license.
  10. * https://docs.blackfin.uclinux.org/doku.php?id=adi_bsd
  11. */
  12. /* This file should be up to date with:
  13. * - Revision F, 05/23/2011; ADSP-BF512/BF514/BF516/BF518 Blackfin Processor Anomaly List
  14. */
  15. #if __SILICON_REVISION__ < 0
  16. # error will not work on BF518 silicon version
  17. #endif
  18. #ifndef _MACH_ANOMALY_H_
  19. #define _MACH_ANOMALY_H_
  20. /* Multi-Issue Instruction with dsp32shiftimm in slot1 and P-reg Store in slot2 Not Supported */
  21. #define ANOMALY_05000074 (1)
  22. /* DMA_RUN Bit Is Not Valid after a Peripheral Receive Channel DMA Stops */
  23. #define ANOMALY_05000119 (1)
  24. /* Rx.H Cannot Be Used to Access 16-bit System MMR Registers */
  25. #define ANOMALY_05000122 (1)
  26. /* False Hardware Error from an Access in the Shadow of a Conditional Branch */
  27. #define ANOMALY_05000245 (1)
  28. /* Incorrect Timer Pulse Width in Single-Shot PWM_OUT Mode with External Clock */
  29. #define ANOMALY_05000254 (1)
  30. /* Sensitivity To Noise with Slow Input Edge Rates on External SPORT TX and RX Clocks */
  31. #define ANOMALY_05000265 (1)
  32. /* False Hardware Errors Caused by Fetches at the Boundary of Reserved Memory */
  33. #define ANOMALY_05000310 (1)
  34. /* PPI Underflow Error Goes Undetected in ITU-R 656 Mode */
  35. #define ANOMALY_05000366 (1)
  36. /* Lockbox SESR Firmware Does Not Save/Restore Full Context */
  37. #define ANOMALY_05000405 (1)
  38. /* Lockbox Firmware Memory Cleanup Routine Does not Clear Registers */
  39. #define ANOMALY_05000408 (1)
  40. /* Speculative Fetches Can Cause Undesired External FIFO Operations */
  41. #define ANOMALY_05000416 (1)
  42. /* TWI Fall Time (Tof) May Violate the Minimum I2C Specification */
  43. #define ANOMALY_05000421 (1)
  44. /* TWI Input Capacitance (Ci) May Violate the Maximum I2C Specification */
  45. #define ANOMALY_05000422 (1)
  46. /* Speculative Fetches of Indirect-Pointer Instructions Can Cause False Hardware Errors */
  47. #define ANOMALY_05000426 (1)
  48. /* Software System Reset Corrupts PLL_LOCKCNT Register */
  49. #define ANOMALY_05000430 (__SILICON_REVISION__ < 1)
  50. /* Incorrect Use of Stack in Lockbox Firmware During Authentication */
  51. #define ANOMALY_05000431 (1)
  52. /* SW Breakpoints Ignored Upon Return From Lockbox Authentication */
  53. #define ANOMALY_05000434 (1)
  54. /* Certain SIC Registers are not Reset After Soft or Core Double Fault Reset */
  55. #define ANOMALY_05000435 (__SILICON_REVISION__ < 1)
  56. /* PORTx_DRIVE and PORTx_HYSTERESIS Registers Read Back Incorrect Values */
  57. #define ANOMALY_05000438 (__SILICON_REVISION__ < 1)
  58. /* Preboot Cannot be Used to Alter the PLL_DIV Register */
  59. #define ANOMALY_05000439 (__SILICON_REVISION__ < 1)
  60. /* bfrom_SysControl() Cannot be Used to Write the PLL_DIV Register */
  61. #define ANOMALY_05000440 (__SILICON_REVISION__ < 1)
  62. /* IFLUSH Instruction at End of Hardware Loop Causes Infinite Stall */
  63. #define ANOMALY_05000443 (1)
  64. /* Incorrect L1 Instruction Bank B Memory Map Location */
  65. #define ANOMALY_05000444 (__SILICON_REVISION__ < 1)
  66. /* Incorrect Default Hysteresis Setting for RESET, NMI, and BMODE Signals */
  67. #define ANOMALY_05000452 (__SILICON_REVISION__ < 1)
  68. /* PWM_TRIPB Signal Not Available on PG10 */
  69. #define ANOMALY_05000453 (__SILICON_REVISION__ < 1)
  70. /* PPI_FS3 is Driven One Half Cycle Later Than PPI Data */
  71. #define ANOMALY_05000455 (__SILICON_REVISION__ < 1)
  72. /* False Hardware Error when RETI Points to Invalid Memory */
  73. #define ANOMALY_05000461 (1)
  74. /* Synchronization Problem at Startup May Cause SPORT Transmit Channels to Misalign */
  75. #define ANOMALY_05000462 (__SILICON_REVISION__ < 2)
  76. /* Incorrect Default MSEL Value in PLL_CTL */
  77. #define ANOMALY_05000472 (__SILICON_REVISION__ < 2)
  78. /* Interrupted SPORT Receive Data Register Read Results In Underflow when SLEN > 15 */
  79. #define ANOMALY_05000473 (1)
  80. /* TESTSET Instruction Cannot Be Interrupted */
  81. #define ANOMALY_05000477 (1)
  82. /* Reads of ITEST_COMMAND and ITEST_DATA Registers Cause Cache Corruption */
  83. #define ANOMALY_05000481 (1)
  84. /* PLL Latches Incorrect Settings During Reset */
  85. #define ANOMALY_05000482 (__SILICON_REVISION__ < 2)
  86. /* PLL_CTL Change Using bfrom_SysControl() Can Result in Processor Overclocking */
  87. #define ANOMALY_05000485 (__SILICON_REVISION__ < 2)
  88. /* SPI Master Boot Can Fail Under Certain Conditions */
  89. #define ANOMALY_05000490 (1)
  90. /* Instruction Memory Stalls Can Cause IFLUSH to Fail */
  91. #define ANOMALY_05000491 (1)
  92. /* EXCPT Instruction May Be Lost If NMI Happens Simultaneously */
  93. #define ANOMALY_05000494 (1)
  94. /* CNT_COMMAND Functionality Depends on CNT_IMASK Configuration */
  95. #define ANOMALY_05000498 (1)
  96. /* RXS Bit in SPI_STAT May Become Stuck In RX DMA Modes */
  97. #define ANOMALY_05000501 (1)
  98. /* Anomalies that don't exist on this proc */
  99. #define ANOMALY_05000099 (0)
  100. #define ANOMALY_05000120 (0)
  101. #define ANOMALY_05000125 (0)
  102. #define ANOMALY_05000149 (0)
  103. #define ANOMALY_05000158 (0)
  104. #define ANOMALY_05000171 (0)
  105. #define ANOMALY_05000179 (0)
  106. #define ANOMALY_05000182 (0)
  107. #define ANOMALY_05000183 (0)
  108. #define ANOMALY_05000189 (0)
  109. #define ANOMALY_05000198 (0)
  110. #define ANOMALY_05000202 (0)
  111. #define ANOMALY_05000215 (0)
  112. #define ANOMALY_05000219 (0)
  113. #define ANOMALY_05000220 (0)
  114. #define ANOMALY_05000227 (0)
  115. #define ANOMALY_05000230 (0)
  116. #define ANOMALY_05000231 (0)
  117. #define ANOMALY_05000233 (0)
  118. #define ANOMALY_05000234 (0)
  119. #define ANOMALY_05000242 (0)
  120. #define ANOMALY_05000244 (0)
  121. #define ANOMALY_05000248 (0)
  122. #define ANOMALY_05000250 (0)
  123. #define ANOMALY_05000257 (0)
  124. #define ANOMALY_05000261 (0)
  125. #define ANOMALY_05000263 (0)
  126. #define ANOMALY_05000266 (0)
  127. #define ANOMALY_05000273 (0)
  128. #define ANOMALY_05000274 (0)
  129. #define ANOMALY_05000278 (0)
  130. #define ANOMALY_05000281 (0)
  131. #define ANOMALY_05000283 (0)
  132. #define ANOMALY_05000285 (0)
  133. #define ANOMALY_05000287 (0)
  134. #define ANOMALY_05000301 (0)
  135. #define ANOMALY_05000305 (0)
  136. #define ANOMALY_05000307 (0)
  137. #define ANOMALY_05000311 (0)
  138. #define ANOMALY_05000312 (0)
  139. #define ANOMALY_05000315 (0)
  140. #define ANOMALY_05000323 (0)
  141. #define ANOMALY_05000353 (0)
  142. #define ANOMALY_05000357 (0)
  143. #define ANOMALY_05000362 (1)
  144. #define ANOMALY_05000363 (0)
  145. #define ANOMALY_05000364 (0)
  146. #define ANOMALY_05000371 (0)
  147. #define ANOMALY_05000380 (0)
  148. #define ANOMALY_05000383 (0)
  149. #define ANOMALY_05000386 (0)
  150. #define ANOMALY_05000389 (0)
  151. #define ANOMALY_05000400 (0)
  152. #define ANOMALY_05000402 (0)
  153. #define ANOMALY_05000412 (0)
  154. #define ANOMALY_05000432 (0)
  155. #define ANOMALY_05000447 (0)
  156. #define ANOMALY_05000448 (0)
  157. #define ANOMALY_05000456 (0)
  158. #define ANOMALY_05000450 (0)
  159. #define ANOMALY_05000465 (0)
  160. #define ANOMALY_05000467 (0)
  161. #define ANOMALY_05000474 (0)
  162. #define ANOMALY_05000475 (0)
  163. #define ANOMALY_05000480 (0)
  164. #endif