BF531_def.h 24 KB

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  1. /* DO NOT EDIT THIS FILE
  2. * Automatically generated by generate-def-headers.xsl
  3. * DO NOT EDIT THIS FILE
  4. */
  5. #ifndef __BFIN_DEF_ADSP_BF531_proc__
  6. #define __BFIN_DEF_ADSP_BF531_proc__
  7. #include "../mach-common/ADSP-EDN-core_def.h"
  8. #define MDMAFLX0_DMACNFG_D 0xFFC00E08
  9. #define MDMAFLX0_XCOUNT_D 0xFFC00E10
  10. #define MDMAFLX0_XMODIFY_D 0xFFC00E14
  11. #define MDMAFLX0_YCOUNT_D 0xFFC00E18
  12. #define MDMAFLX0_YMODIFY_D 0xFFC00E1C
  13. #define MDMAFLX0_IRQSTAT_D 0xFFC00E28
  14. #define MDMAFLX0_PMAP_D 0xFFC00E2C
  15. #define MDMAFLX0_CURXCOUNT_D 0xFFC00E30
  16. #define MDMAFLX0_CURYCOUNT_D 0xFFC00E38
  17. #define MDMAFLX0_DMACNFG_S 0xFFC00E48
  18. #define MDMAFLX0_XCOUNT_S 0xFFC00E50
  19. #define MDMAFLX0_XMODIFY_S 0xFFC00E54
  20. #define MDMAFLX0_YCOUNT_S 0xFFC00E58
  21. #define MDMAFLX0_YMODIFY_S 0xFFC00E5C
  22. #define MDMAFLX0_IRQSTAT_S 0xFFC00E68
  23. #define MDMAFLX0_PMAP_S 0xFFC00E6C
  24. #define MDMAFLX0_CURXCOUNT_S 0xFFC00E70
  25. #define MDMAFLX0_CURYCOUNT_S 0xFFC00E78
  26. #define MDMAFLX1_DMACNFG_D 0xFFC00E88
  27. #define MDMAFLX1_XCOUNT_D 0xFFC00E90
  28. #define MDMAFLX1_XMODIFY_D 0xFFC00E94
  29. #define MDMAFLX1_YCOUNT_D 0xFFC00E98
  30. #define MDMAFLX1_YMODIFY_D 0xFFC00E9C
  31. #define MDMAFLX1_IRQSTAT_D 0xFFC00EA8
  32. #define MDMAFLX1_PMAP_D 0xFFC00EAC
  33. #define MDMAFLX1_CURXCOUNT_D 0xFFC00EB0
  34. #define MDMAFLX1_CURYCOUNT_D 0xFFC00EB8
  35. #define MDMAFLX1_DMACNFG_S 0xFFC00EC8
  36. #define MDMAFLX1_XCOUNT_S 0xFFC00ED0
  37. #define MDMAFLX1_XMODIFY_S 0xFFC00ED4
  38. #define MDMAFLX1_YCOUNT_S 0xFFC00ED8
  39. #define MDMAFLX1_YMODIFY_S 0xFFC00EDC
  40. #define MDMAFLX1_IRQSTAT_S 0xFFC00EE8
  41. #define MDMAFLX1_PMAP_S 0xFFC00EEC
  42. #define MDMAFLX1_CURXCOUNT_S 0xFFC00EF0
  43. #define MDMAFLX1_CURYCOUNT_S 0xFFC00EF8
  44. #define DMAFLX0_DMACNFG 0xFFC00C08
  45. #define DMAFLX0_XCOUNT 0xFFC00C10
  46. #define DMAFLX0_XMODIFY 0xFFC00C14
  47. #define DMAFLX0_YCOUNT 0xFFC00C18
  48. #define DMAFLX0_YMODIFY 0xFFC00C1C
  49. #define DMAFLX0_IRQSTAT 0xFFC00C28
  50. #define DMAFLX0_PMAP 0xFFC00C2C
  51. #define DMAFLX0_CURXCOUNT 0xFFC00C30
  52. #define DMAFLX0_CURYCOUNT 0xFFC00C38
  53. #define DMAFLX1_DMACNFG 0xFFC00C48
  54. #define DMAFLX1_XCOUNT 0xFFC00C50
  55. #define DMAFLX1_XMODIFY 0xFFC00C54
  56. #define DMAFLX1_YCOUNT 0xFFC00C58
  57. #define DMAFLX1_YMODIFY 0xFFC00C5C
  58. #define DMAFLX1_IRQSTAT 0xFFC00C68
  59. #define DMAFLX1_PMAP 0xFFC00C6C
  60. #define DMAFLX1_CURXCOUNT 0xFFC00C70
  61. #define DMAFLX1_CURYCOUNT 0xFFC00C78
  62. #define DMAFLX2_DMACNFG 0xFFC00C88
  63. #define DMAFLX2_XCOUNT 0xFFC00C90
  64. #define DMAFLX2_XMODIFY 0xFFC00C94
  65. #define DMAFLX2_YCOUNT 0xFFC00C98
  66. #define DMAFLX2_YMODIFY 0xFFC00C9C
  67. #define DMAFLX2_IRQSTAT 0xFFC00CA8
  68. #define DMAFLX2_PMAP 0xFFC00CAC
  69. #define DMAFLX2_CURXCOUNT 0xFFC00CB0
  70. #define DMAFLX2_CURYCOUNT 0xFFC00CB8
  71. #define DMAFLX3_DMACNFG 0xFFC00CC8
  72. #define DMAFLX3_XCOUNT 0xFFC00CD0
  73. #define DMAFLX3_XMODIFY 0xFFC00CD4
  74. #define DMAFLX3_YCOUNT 0xFFC00CD8
  75. #define DMAFLX3_YMODIFY 0xFFC00CDC
  76. #define DMAFLX3_IRQSTAT 0xFFC00CE8
  77. #define DMAFLX3_PMAP 0xFFC00CEC
  78. #define DMAFLX3_CURXCOUNT 0xFFC00CF0
  79. #define DMAFLX3_CURYCOUNT 0xFFC00CF8
  80. #define DMAFLX4_DMACNFG 0xFFC00D08
  81. #define DMAFLX4_XCOUNT 0xFFC00D10
  82. #define DMAFLX4_XMODIFY 0xFFC00D14
  83. #define DMAFLX4_YCOUNT 0xFFC00D18
  84. #define DMAFLX4_YMODIFY 0xFFC00D1C
  85. #define DMAFLX4_IRQSTAT 0xFFC00D28
  86. #define DMAFLX4_PMAP 0xFFC00D2C
  87. #define DMAFLX4_CURXCOUNT 0xFFC00D30
  88. #define DMAFLX4_CURYCOUNT 0xFFC00D38
  89. #define DMAFLX5_DMACNFG 0xFFC00D48
  90. #define DMAFLX5_XCOUNT 0xFFC00D50
  91. #define DMAFLX5_XMODIFY 0xFFC00D54
  92. #define DMAFLX5_YCOUNT 0xFFC00D58
  93. #define DMAFLX5_YMODIFY 0xFFC00D5C
  94. #define DMAFLX5_IRQSTAT 0xFFC00D68
  95. #define DMAFLX5_PMAP 0xFFC00D6C
  96. #define DMAFLX5_CURXCOUNT 0xFFC00D70
  97. #define DMAFLX5_CURYCOUNT 0xFFC00D78
  98. #define DMAFLX6_DMACNFG 0xFFC00D88
  99. #define DMAFLX6_XCOUNT 0xFFC00D90
  100. #define DMAFLX6_XMODIFY 0xFFC00D94
  101. #define DMAFLX6_YCOUNT 0xFFC00D98
  102. #define DMAFLX6_YMODIFY 0xFFC00D9C
  103. #define DMAFLX6_IRQSTAT 0xFFC00DA8
  104. #define DMAFLX6_PMAP 0xFFC00DAC
  105. #define DMAFLX6_CURXCOUNT 0xFFC00DB0
  106. #define DMAFLX6_CURYCOUNT 0xFFC00DB8
  107. #define DMAFLX7_DMACNFG 0xFFC00DC8
  108. #define DMAFLX7_XCOUNT 0xFFC00DD0
  109. #define DMAFLX7_XMODIFY 0xFFC00DD4
  110. #define DMAFLX7_YCOUNT 0xFFC00DD8
  111. #define DMAFLX7_YMODIFY 0xFFC00DDC
  112. #define DMAFLX7_IRQSTAT 0xFFC00DE8
  113. #define DMAFLX7_PMAP 0xFFC00DEC
  114. #define DMAFLX7_CURXCOUNT 0xFFC00DF0
  115. #define DMAFLX7_CURYCOUNT 0xFFC00DF8
  116. #define TIMER0_CONFIG 0xFFC00600
  117. #define TIMER0_COUNTER 0xFFC00604
  118. #define TIMER0_PERIOD 0xFFC00608
  119. #define TIMER0_WIDTH 0xFFC0060C
  120. #define TIMER1_CONFIG 0xFFC00610
  121. #define TIMER1_COUNTER 0xFFC00614
  122. #define TIMER1_PERIOD 0xFFC00618
  123. #define TIMER1_WIDTH 0xFFC0061C
  124. #define TIMER2_CONFIG 0xFFC00620
  125. #define TIMER2_COUNTER 0xFFC00624
  126. #define TIMER2_PERIOD 0xFFC00628
  127. #define TIMER2_WIDTH 0xFFC0062C
  128. #define TIMER_ENABLE 0xFFC00640
  129. #define TIMER_DISABLE 0xFFC00644
  130. #define TIMER_STATUS 0xFFC00648
  131. #define SIC_RVECT 0xFFC00108 /* Interrupt Reset Vector Address Register */
  132. #define SIC_IMASK 0xFFC0010C /* Interrupt Mask Register */
  133. #define SIC_IAR0 0xFFC00110 /* Interrupt Assignment Register 0 */
  134. #define SIC_IAR1 0xFFC00114 /* Interrupt Assignment Register 1 */
  135. #define SIC_IAR2 0xFFC00118 /* Interrupt Assignment Register 2 */
  136. #define SIC_IAR3 0xFFC0011C /* Interrupt Assignment Register 3 */
  137. #define SIC_ISR 0xFFC00120 /* Interrupt Status Register */
  138. #define SIC_IWR 0xFFC00124 /* Interrupt Wakeup Register */
  139. #define UART_THR 0xFFC00400 /* Transmit Holding */
  140. #define UART_DLL 0xFFC00400 /* Divisor Latch Low Byte */
  141. #define UART_DLH 0xFFC00404 /* Divisor Latch High Byte */
  142. #define UART_IER 0xFFC00404
  143. #define UART_IIR 0xFFC00408
  144. #define UART_LCR 0xFFC0040C
  145. #define UART_MCR 0xFFC00410
  146. #define UART_LSR 0xFFC00414
  147. #define UART_SCR 0xFFC0041C
  148. #define UART_RBR 0xFFC00400 /* Receive Buffer */
  149. #define UART0_RBR UART_RBR
  150. #define UART_GCTL 0xFFC00424
  151. #define SPT0_TX_CONFIG0 0xFFC00800
  152. #define SPT0_TX_CONFIG1 0xFFC00804
  153. #define SPT0_RX_CONFIG0 0xFFC00820
  154. #define SPT0_RX_CONFIG1 0xFFC00824
  155. #define SPT0_TX 0xFFC00810
  156. #define SPT0_RX 0xFFC00818
  157. #define SPT0_TSCLKDIV 0xFFC00808
  158. #define SPT0_RSCLKDIV 0xFFC00828
  159. #define SPT0_TFSDIV 0xFFC0080C
  160. #define SPT0_RFSDIV 0xFFC0082C
  161. #define SPT0_STAT 0xFFC00830
  162. #define SPT0_MTCS0 0xFFC00840
  163. #define SPT0_MTCS1 0xFFC00844
  164. #define SPT0_MTCS2 0xFFC00848
  165. #define SPT0_MTCS3 0xFFC0084C
  166. #define SPT0_MRCS0 0xFFC00850
  167. #define SPT0_MRCS1 0xFFC00854
  168. #define SPT0_MRCS2 0xFFC00858
  169. #define SPT0_MRCS3 0xFFC0085C
  170. #define SPT0_MCMC1 0xFFC00838
  171. #define SPT0_MCMC2 0xFFC0083C
  172. #define SPT0_CHNL 0xFFC00834
  173. #define SPT1_TX_CONFIG0 0xFFC00900
  174. #define SPT1_TX_CONFIG1 0xFFC00904
  175. #define SPT1_RX_CONFIG0 0xFFC00920
  176. #define SPT1_RX_CONFIG1 0xFFC00924
  177. #define SPT1_TX 0xFFC00910
  178. #define SPT1_RX 0xFFC00918
  179. #define SPT1_TSCLKDIV 0xFFC00908
  180. #define SPT1_RSCLKDIV 0xFFC00928
  181. #define SPT1_TFSDIV 0xFFC0090C
  182. #define SPT1_RFSDIV 0xFFC0092C
  183. #define SPT1_STAT 0xFFC00930
  184. #define SPT1_MTCS0 0xFFC00940
  185. #define SPT1_MTCS1 0xFFC00944
  186. #define SPT1_MTCS2 0xFFC00948
  187. #define SPT1_MTCS3 0xFFC0094C
  188. #define SPT1_MRCS0 0xFFC00950
  189. #define SPT1_MRCS1 0xFFC00954
  190. #define SPT1_MRCS2 0xFFC00958
  191. #define SPT1_MRCS3 0xFFC0095C
  192. #define SPT1_MCMC1 0xFFC00938
  193. #define SPT1_MCMC2 0xFFC0093C
  194. #define SPT1_CHNL 0xFFC00934
  195. #define PPI_CONTROL 0xFFC01000
  196. #define PPI_STATUS 0xFFC01004
  197. #define PPI_DELAY 0xFFC0100C
  198. #define PPI_COUNT 0xFFC01008
  199. #define PPI_FRAME 0xFFC01010
  200. #define PLL_CTL 0xFFC00000 /* PLL Control register (16-bit) */
  201. #define PLL_DIV 0xFFC00004 /* PLL Divide Register (16-bit) */
  202. #define VR_CTL 0xFFC00008 /* Voltage Regulator Control Register (16-bit) */
  203. #define PLL_STAT 0xFFC0000C /* PLL Status register (16-bit) */
  204. #define PLL_LOCKCNT 0xFFC00010 /* PLL Lock Count register (16-bit) */
  205. #define SWRST 0xFFC00100 /* Software Reset Register (16-bit) */
  206. #define SYSCR 0xFFC00104 /* System Configuration register */
  207. #define CHIPID 0xFFC00014
  208. #define WDOG_CTL 0xFFC00200 /* Watchdog Control Register */
  209. #define WDOG_CNT 0xFFC00204 /* Watchdog Count Register */
  210. #define WDOG_STAT 0xFFC00208 /* Watchdog Status Register */
  211. #define RTC_STAT 0xFFC00300
  212. #define RTC_ICTL 0xFFC00304
  213. #define RTC_ISTAT 0xFFC00308
  214. #define RTC_SWCNT 0xFFC0030C
  215. #define RTC_ALARM 0xFFC00310
  216. #define RTC_PREN 0xFFC00314
  217. #define SPI_CTL 0xFFC00500
  218. #define SPI_FLG 0xFFC00504
  219. #define SPI_STAT 0xFFC00508
  220. #define SPI_TDBR 0xFFC0050C
  221. #define SPI_RDBR 0xFFC00510
  222. #define SPI_BAUD 0xFFC00514
  223. #define SPI_SHADOW 0xFFC00518
  224. #define FIO_FLAG_D 0xFFC00700
  225. #define FIO_FLAG_C 0xFFC00704
  226. #define FIO_FLAG_S 0xFFC00708
  227. #define FIO_FLAG_T 0xFFC0070C
  228. #define FIO_MASKA_D 0xFFC00710
  229. #define FIO_MASKA_C 0xFFC00714
  230. #define FIO_MASKA_S 0xFFC00718
  231. #define FIO_MASKA_T 0xFFC0071C
  232. #define FIO_MASKB_D 0xFFC00720
  233. #define FIO_MASKB_C 0xFFC00724
  234. #define FIO_MASKB_S 0xFFC00728
  235. #define FIO_MASKB_T 0xFFC0072C
  236. #define FIO_DIR 0xFFC00730
  237. #define FIO_POLAR 0xFFC00734
  238. #define FIO_EDGE 0xFFC00738
  239. #define FIO_BOTH 0xFFC0073C
  240. #define FIO_INEN 0xFFC00740
  241. #define SPORT0_TCR1 0xFFC00800 /* SPORT0 Transmit Configuration 1 Register */
  242. #define SPORT0_TCR2 0xFFC00804 /* SPORT0 Transmit Configuration 2 Register */
  243. #define SPORT0_TCLKDIV 0xFFC00808 /* SPORT0 Transmit Clock Divider */
  244. #define SPORT0_TFSDIV 0xFFC0080C /* SPORT0 Transmit Frame Sync Divider */
  245. #define SPORT0_TX 0xFFC00810 /* SPORT0 TX Data Register */
  246. #define SPORT0_RX 0xFFC00818 /* SPORT0 RX Data Register */
  247. #define SPORT0_RCR1 0xFFC00820 /* SPORT0 Transmit Configuration 1 Register */
  248. #define SPORT0_RCR2 0xFFC00824 /* SPORT0 Transmit Configuration 2 Register */
  249. #define SPORT0_RCLKDIV 0xFFC00828 /* SPORT0 Receive Clock Divider */
  250. #define SPORT0_RFSDIV 0xFFC0082C /* SPORT0 Receive Frame Sync Divider */
  251. #define SPORT0_STAT 0xFFC00830 /* SPORT0 Status Register */
  252. #define SPORT0_CHNL 0xFFC00834 /* SPORT0 Current Channel Register */
  253. #define SPORT0_MCMC1 0xFFC00838 /* SPORT0 Multi-Channel Configuration Register 1 */
  254. #define SPORT0_MCMC2 0xFFC0083C /* SPORT0 Multi-Channel Configuration Register 2 */
  255. #define SPORT1_TCR1 0xFFC00900 /* SPORT1 Transmit Configuration 1 Register */
  256. #define SPORT1_TCR2 0xFFC00904 /* SPORT1 Transmit Configuration 2 Register */
  257. #define SPORT1_TCLKDIV 0xFFC00908 /* SPORT1 Transmit Clock Divider */
  258. #define SPORT1_TFSDIV 0xFFC0090C /* SPORT1 Transmit Frame Sync Divider */
  259. #define SPORT1_TX 0xFFC00910 /* SPORT1 TX Data Register */
  260. #define SPORT1_RX 0xFFC00918 /* SPORT1 RX Data Register */
  261. #define SPORT1_RCR1 0xFFC00920 /* SPORT1 Transmit Configuration 1 Register */
  262. #define SPORT1_RCR2 0xFFC00924 /* SPORT1 Transmit Configuration 2 Register */
  263. #define SPORT1_RCLKDIV 0xFFC00928 /* SPORT1 Receive Clock Divider */
  264. #define SPORT1_RFSDIV 0xFFC0092C /* SPORT1 Receive Frame Sync Divider */
  265. #define SPORT1_STAT 0xFFC00930 /* SPORT1 Status Register */
  266. #define SPORT1_CHNL 0xFFC00934 /* SPORT1 Current Channel Register */
  267. #define SPORT1_MCMC1 0xFFC00938 /* SPORT1 Multi-Channel Configuration Register 1 */
  268. #define SPORT1_MCMC2 0xFFC0093C /* SPORT1 Multi-Channel Configuration Register 2 */
  269. #define DMA0_NEXT_DESC_PTR 0xFFC00C00
  270. #define DMA0_START_ADDR 0xFFC00C04
  271. #define DMA0_CONFIG 0xFFC00C08 /* DMA Channel 0 Configuration Register */
  272. #define DMA0_X_COUNT 0xFFC00C10
  273. #define DMA0_X_MODIFY 0xFFC00C14
  274. #define DMA0_Y_COUNT 0xFFC00C18
  275. #define DMA0_Y_MODIFY 0xFFC00C1C
  276. #define DMA0_CURR_DESC_PTR 0xFFC00C20
  277. #define DMA0_CURR_ADDR 0xFFC00C24
  278. #define DMA0_IRQ_STATUS 0xFFC00C28
  279. #define DMA0_PERIPHERAL_MAP 0xFFC00C2C
  280. #define DMA0_CURR_X_COUNT 0xFFC00C30
  281. #define DMA0_CURR_Y_COUNT 0xFFC00C38
  282. #define DMA1_NEXT_DESC_PTR 0xFFC00C40
  283. #define DMA1_START_ADDR 0xFFC00C44
  284. #define DMA1_CONFIG 0xFFC00C48 /* DMA Channel 1 Configuration Register */
  285. #define DMA1_X_COUNT 0xFFC00C50
  286. #define DMA1_X_MODIFY 0xFFC00C54
  287. #define DMA1_Y_COUNT 0xFFC00C58
  288. #define DMA1_Y_MODIFY 0xFFC00C5C
  289. #define DMA1_CURR_DESC_PTR 0xFFC00C60
  290. #define DMA1_CURR_ADDR 0xFFC00C64
  291. #define DMA1_IRQ_STATUS 0xFFC00C68
  292. #define DMA1_PERIPHERAL_MAP 0xFFC00C6C
  293. #define DMA1_CURR_X_COUNT 0xFFC00C70
  294. #define DMA1_CURR_Y_COUNT 0xFFC00C78
  295. #define DMA2_NEXT_DESC_PTR 0xFFC00C80
  296. #define DMA2_START_ADDR 0xFFC00C84
  297. #define DMA2_CONFIG 0xFFC00C88 /* DMA Channel 2 Configuration Register */
  298. #define DMA2_X_COUNT 0xFFC00C90
  299. #define DMA2_X_MODIFY 0xFFC00C94
  300. #define DMA2_Y_COUNT 0xFFC00C98
  301. #define DMA2_Y_MODIFY 0xFFC00C9C
  302. #define DMA2_CURR_DESC_PTR 0xFFC00CA0
  303. #define DMA2_CURR_ADDR 0xFFC00CA4
  304. #define DMA2_IRQ_STATUS 0xFFC00CA8
  305. #define DMA2_PERIPHERAL_MAP 0xFFC00CAC
  306. #define DMA2_CURR_X_COUNT 0xFFC00CB0
  307. #define DMA2_CURR_Y_COUNT 0xFFC00CB8
  308. #define DMA3_NEXT_DESC_PTR 0xFFC00CC0
  309. #define DMA3_START_ADDR 0xFFC00CC4
  310. #define DMA3_CONFIG 0xFFC00CC8 /* DMA Channel 3 Configuration Register */
  311. #define DMA3_X_COUNT 0xFFC00CD0
  312. #define DMA3_X_MODIFY 0xFFC00CD4
  313. #define DMA3_Y_COUNT 0xFFC00CD8
  314. #define DMA3_Y_MODIFY 0xFFC00CDC
  315. #define DMA3_CURR_DESC_PTR 0xFFC00CE0
  316. #define DMA3_CURR_ADDR 0xFFC00CE4
  317. #define DMA3_IRQ_STATUS 0xFFC00CE8
  318. #define DMA3_PERIPHERAL_MAP 0xFFC00CEC
  319. #define DMA3_CURR_X_COUNT 0xFFC00CF0
  320. #define DMA3_CURR_Y_COUNT 0xFFC00CF8
  321. #define DMA4_NEXT_DESC_PTR 0xFFC00D00
  322. #define DMA4_START_ADDR 0xFFC00D04
  323. #define DMA4_CONFIG 0xFFC00D08 /* DMA Channel 4 Configuration Register */
  324. #define DMA4_X_COUNT 0xFFC00D10
  325. #define DMA4_X_MODIFY 0xFFC00D14
  326. #define DMA4_Y_COUNT 0xFFC00D18
  327. #define DMA4_Y_MODIFY 0xFFC00D1C
  328. #define DMA4_CURR_DESC_PTR 0xFFC00D20
  329. #define DMA4_CURR_ADDR 0xFFC00D24
  330. #define DMA4_IRQ_STATUS 0xFFC00D28
  331. #define DMA4_PERIPHERAL_MAP 0xFFC00D2C
  332. #define DMA4_CURR_X_COUNT 0xFFC00D30
  333. #define DMA4_CURR_Y_COUNT 0xFFC00D38
  334. #define DMA5_NEXT_DESC_PTR 0xFFC00D40
  335. #define DMA5_START_ADDR 0xFFC00D44
  336. #define DMA5_CONFIG 0xFFC00D48 /* DMA Channel 5 Configuration Register */
  337. #define DMA5_X_COUNT 0xFFC00D50
  338. #define DMA5_X_MODIFY 0xFFC00D54
  339. #define DMA5_Y_COUNT 0xFFC00D58
  340. #define DMA5_Y_MODIFY 0xFFC00D5C
  341. #define DMA5_CURR_DESC_PTR 0xFFC00D60
  342. #define DMA5_CURR_ADDR 0xFFC00D64
  343. #define DMA5_IRQ_STATUS 0xFFC00D68
  344. #define DMA5_PERIPHERAL_MAP 0xFFC00D6C
  345. #define DMA5_CURR_X_COUNT 0xFFC00D70
  346. #define DMA5_CURR_Y_COUNT 0xFFC00D78
  347. #define DMA6_NEXT_DESC_PTR 0xFFC00D80
  348. #define DMA6_START_ADDR 0xFFC00D84
  349. #define DMA6_CONFIG 0xFFC00D88 /* DMA Channel 6 Configuration Register */
  350. #define DMA6_X_COUNT 0xFFC00D90
  351. #define DMA6_X_MODIFY 0xFFC00D94
  352. #define DMA6_Y_COUNT 0xFFC00D98
  353. #define DMA6_Y_MODIFY 0xFFC00D9C
  354. #define DMA6_CURR_DESC_PTR 0xFFC00DA0
  355. #define DMA6_CURR_ADDR 0xFFC00DA4
  356. #define DMA6_IRQ_STATUS 0xFFC00DA8
  357. #define DMA6_PERIPHERAL_MAP 0xFFC00DAC
  358. #define DMA6_CURR_X_COUNT 0xFFC00DB0
  359. #define DMA6_CURR_Y_COUNT 0xFFC00DB8
  360. #define DMA7_NEXT_DESC_PTR 0xFFC00DC0
  361. #define DMA7_START_ADDR 0xFFC00DC4
  362. #define DMA7_CONFIG 0xFFC00DC8 /* DMA Channel 7 Configuration Register */
  363. #define DMA7_X_COUNT 0xFFC00DD0
  364. #define DMA7_X_MODIFY 0xFFC00DD4
  365. #define DMA7_Y_COUNT 0xFFC00DD8
  366. #define DMA7_Y_MODIFY 0xFFC00DDC
  367. #define DMA7_CURR_DESC_PTR 0xFFC00DE0
  368. #define DMA7_CURR_ADDR 0xFFC00DE4
  369. #define DMA7_IRQ_STATUS 0xFFC00DE8
  370. #define DMA7_PERIPHERAL_MAP 0xFFC00DEC
  371. #define DMA7_CURR_X_COUNT 0xFFC00DF0
  372. #define DMA7_CURR_Y_COUNT 0xFFC00DF8
  373. #define MDMA_D0_NEXT_DESC_PTR 0xFFC00E00
  374. #define MDMA_D0_START_ADDR 0xFFC00E04
  375. #define MDMA_D0_CONFIG 0xFFC00E08
  376. #define MDMA_D0_X_COUNT 0xFFC00E10
  377. #define MDMA_D0_X_MODIFY 0xFFC00E14
  378. #define MDMA_D0_Y_COUNT 0xFFC00E18
  379. #define MDMA_D0_Y_MODIFY 0xFFC00E1C
  380. #define MDMA_D0_CURR_DESC_PTR 0xFFC00E20
  381. #define MDMA_D0_CURR_ADDR 0xFFC00E24
  382. #define MDMA_D0_IRQ_STATUS 0xFFC00E28
  383. #define MDMA_D0_PERIPHERAL_MAP 0xFFC00E2C
  384. #define MDMA_D0_CURR_X_COUNT 0xFFC00E30
  385. #define MDMA_D0_CURR_Y_COUNT 0xFFC00E38
  386. #define MDMA_S0_NEXT_DESC_PTR 0xFFC00E40
  387. #define MDMA_S0_START_ADDR 0xFFC00E44
  388. #define MDMA_S0_CONFIG 0xFFC00E48
  389. #define MDMA_S0_X_COUNT 0xFFC00E50
  390. #define MDMA_S0_X_MODIFY 0xFFC00E54
  391. #define MDMA_S0_Y_COUNT 0xFFC00E58
  392. #define MDMA_S0_Y_MODIFY 0xFFC00E5C
  393. #define MDMA_S0_CURR_DESC_PTR 0xFFC00E60
  394. #define MDMA_S0_CURR_ADDR 0xFFC00E64
  395. #define MDMA_S0_IRQ_STATUS 0xFFC00E68
  396. #define MDMA_S0_PERIPHERAL_MAP 0xFFC00E6C
  397. #define MDMA_S0_CURR_X_COUNT 0xFFC00E70
  398. #define MDMA_S0_CURR_Y_COUNT 0xFFC00E78
  399. #define MDMA_D1_NEXT_DESC_PTR 0xFFC00E80
  400. #define MDMA_D1_START_ADDR 0xFFC00E84
  401. #define MDMA_D1_CONFIG 0xFFC00E88 /* MemDMA Stream 1 Destination Configuration Register */
  402. #define MDMA_D1_X_COUNT 0xFFC00E90
  403. #define MDMA_D1_X_MODIFY 0xFFC00E94
  404. #define MDMA_D1_Y_COUNT 0xFFC00E98
  405. #define MDMA_D1_Y_MODIFY 0xFFC00E9C
  406. #define MDMA_D1_CURR_DESC_PTR 0xFFC00EA0
  407. #define MDMA_D1_CURR_ADDR 0xFFC00EA4
  408. #define MDMA_D1_IRQ_STATUS 0xFFC00EA8
  409. #define MDMA_D1_PERIPHERAL_MAP 0xFFC00EAC
  410. #define MDMA_D1_CURR_X_COUNT 0xFFC00EB0
  411. #define MDMA_D1_CURR_Y_COUNT 0xFFC00EB8
  412. #define MDMA_S1_NEXT_DESC_PTR 0xFFC00EC0
  413. #define MDMA_S1_START_ADDR 0xFFC00EC4
  414. #define MDMA_S1_CONFIG 0xFFC00EC8
  415. #define MDMA_S1_X_COUNT 0xFFC00ED0
  416. #define MDMA_S1_X_MODIFY 0xFFC00ED4
  417. #define MDMA_S1_Y_COUNT 0xFFC00ED8
  418. #define MDMA_S1_Y_MODIFY 0xFFC00EDC
  419. #define MDMA_S1_CURR_DESC_PTR 0xFFC00EE0
  420. #define MDMA_S1_CURR_ADDR 0xFFC00EE4
  421. #define MDMA_S1_IRQ_STATUS 0xFFC00EE8
  422. #define MDMA_S1_PERIPHERAL_MAP 0xFFC00EEC
  423. #define MDMA_S1_CURR_X_COUNT 0xFFC00EF0
  424. #define MDMA_S1_CURR_Y_COUNT 0xFFC00EF8
  425. #define EBIU_AMGCTL 0xFFC00A00
  426. #define EBIU_AMBCTL0 0xFFC00A04
  427. #define EBIU_AMBCTL1 0xFFC00A08
  428. #define EBIU_SDGCTL 0xFFC00A10
  429. #define EBIU_SDBCTL 0xFFC00A14
  430. #define EBIU_SDRRC 0xFFC00A18
  431. #define EBIU_SDSTAT 0xFFC00A1C
  432. #define DMA_TC_CNT 0xFFC00B0C
  433. #define DMA_TC_PER 0xFFC00B10
  434. #ifndef __BFIN_DEF_ADSP_BF533_proc__
  435. #define L1_INST_SRAM 0xFFA08000 /* 0xFFA08000 -> 0xFFA0BFFF Instruction Bank A SRAM */
  436. #define L1_INST_SRAM_SIZE (0xFFA0BFFF - 0xFFA08000 + 1)
  437. #define L1_INST_SRAM_END (L1_INST_SRAM + L1_INST_SRAM_SIZE)
  438. #endif
  439. #endif /* __BFIN_DEF_ADSP_BF531_proc__ */